Method for manufacturing display substrate, display substrate and display device

Abstract

The present disclosure provides a display substrate manufacturing method, a display substrate and a display device. The display substrate comprises a display area and a peripheral area. The display substrate comprises a substrate, a wiring functional layer arranged on one side of the substrate, the wiring functional layer comprising a metal wiring and a binding terminal connected to the metal wiring, the binding terminal comprising a first binding terminal, a second binding terminal and a third binding terminal, the first binding terminal and the second binding terminal being located in the display area, and the third binding terminal being located in the peripheral area; a first passivation layer arranged on a side of the wiring functional layer away from the substrate; and a light shielding layer arranged on a side of the first passivation layer away from the substrate, a normal projection of the light shielding layer on the substrate and a normal projection of the binding terminal on the substrate not overlapping, and a normal projection of the light shielding layer on the substrate covering a normal projection of the metal wiring on the substrate in the display area. The technical scheme of the present disclosure can improve the contrast of the display device.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a method for preparing a display substrate, a display substrate, and a display device. Background Technology

[0002] Micro / Mini-LED display technology, as a new generation of display technology, has advantages such as high brightness, high luminous efficiency, and low power consumption.

[0003] Currently, the metal traces in LED display substrates are made of highly reflective metal materials and run through the display area. When the ambient light is strong, these metal traces will exhibit strong reflection, thus affecting the contrast of the LED display substrate. Summary of the Invention

[0004] This disclosure provides a method for preparing a display substrate, a display substrate, and a display device to improve display contrast.

[0005] This disclosure provides a display substrate, including a display area and a peripheral area located around the display area, the display substrate comprising:

[0006] Substrate;

[0007] A wiring functional layer is disposed on one side of the substrate. The wiring functional layer includes metal traces and bonding terminals connected to the metal traces. The bonding terminals include a first bonding terminal, a second bonding terminal, and a third bonding terminal. The first bonding terminal is used to bond an LED chip, the second bonding terminal is used to bond a driver chip, the driver chip is used to drive the LED chip to emit light, and the third bonding terminal is used to bond a flexible circuit board. The first bonding terminal and the second bonding terminal are located in the display area, and the third bonding terminal is located in the peripheral area.

[0008] A first passivation layer is disposed on the side of the wiring functional layer opposite to the substrate; and...

[0009] A light-shielding layer is disposed on the side of the first passivation layer away from the substrate. The orthographic projection of the light-shielding layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate. In the display area, the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the metal trace on the substrate.

[0010] In one alternative implementation, within the display area, the orthographic projection of the light-shielding layer on the substrate completely coincides with the orthographic projection of the metal trace on the substrate.

[0011] In one optional implementation, the wiring functional layer includes: a first metal layer, an insulating layer, and a second metal layer stacked together, wherein the first metal layer is disposed close to the substrate.

[0012] The metal trace includes a first metal trace located on the first metal layer and a second metal trace located on the second metal layer. The bonding terminal is located on the second metal layer and is interconnected with the second metal trace. The second metal trace and the first metal trace are connected through a via disposed on the insulating layer.

[0013] In one alternative implementation, the second metal layer is a copper layer, and a transparent electrode layer is further disposed between the first passivation layer and the second metal layer, wherein the orthographic projection of the transparent electrode layer on the substrate covers the orthographic projection of the third bonding terminal on the substrate.

[0014] In one alternative implementation, the second metal layer includes a copper layer and a copper-nickel alloy layer disposed on the side of the copper layer facing away from the substrate, and the thickness of the first passivation layer is greater than or equal to 8000 angstroms.

[0015] In one alternative implementation, the orthographic projection of the copper-nickel alloy layer on the substrate overlaps the orthographic projection of the copper layer on the substrate.

[0016] In one alternative implementation, a first planarization layer is further provided on the side of the light-shielding layer opposite to the substrate, wherein the orthographic projection of the first planarization layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate, and the orthographic projection of the first passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

[0017] In one alternative implementation, the material of the light-shielding layer is an organic black material.

[0018] In one alternative implementation, a second planarization layer is further provided between the light-shielding layer and the first passivation layer, wherein the orthographic projection of the second planarization layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate, and the orthographic projection of the first passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

[0019] In one alternative implementation, a second passivation layer is further disposed between the light-shielding layer and the second planarization layer, wherein the orthographic projection of the second passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

[0020] In one alternative implementation, the material of the light-shielding layer is carbon black.

[0021] In one alternative implementation, the insulating layer includes a third passivation layer, a third planarization layer, and a fourth passivation layer stacked on the side of the first metal layer facing away from the substrate, wherein the third passivation layer is disposed close to the first metal layer.

[0022] In one optional implementation, an electroplating functional layer is further disposed between the substrate and the first metal layer, wherein the orthographic projection of the electroplating functional layer on the substrate completely coincides with the orthographic projection of the first metal layer on the substrate.

[0023] In one optional implementation, the display area includes a plurality of pixel units arranged in an array, and the first metal trace includes:

[0024] At least one first sub-trace extending along the pixel column direction within the display area, the first sub-trace having a first linewidth along the pixel row direction; and,

[0025] At least one second sub-trace extending along the pixel column direction within the display area, the second sub-trace having a second line width along the pixel row direction, the second line width being smaller than the first line width.

[0026] In one alternative implementation, a second sub-trace adjacent to the first sub-trace along the pixel row direction has a first spacing with the first sub-trace, the first spacing being greater than three times the first line width.

[0027] In one alternative implementation, the orthographic projection of the first bonding terminal on the substrate is located within the orthographic projection range of the first sub-trace on the substrate.

[0028] This disclosure provides a display device, which includes any of the display substrates described in the present invention.

[0029] This disclosure provides a method for fabricating a display substrate, the display substrate including a display area and a peripheral area located around the display area, the fabrication method comprising:

[0030] Provide substrates;

[0031] A wiring functional layer is formed on one side of the substrate. The wiring functional layer includes metal traces and bonding terminals connected to the metal traces. The bonding terminals include a first bonding terminal, a second bonding terminal, and a third bonding terminal. The first bonding terminal is used to bond an LED chip, the second bonding terminal is used to bond a driver chip, the driver chip is used to drive the LED chip to emit light, and the third bonding terminal is used to bond a flexible circuit board. The first bonding terminal and the second bonding terminal are located in the display area, and the third bonding terminal is located in the peripheral area.

[0032] A first passivation layer and a light-shielding layer are sequentially formed on the side of the wiring functional layer away from the substrate. The orthographic projection of the light-shielding layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate. In the display area, the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the metal wiring on the substrate.

[0033] In one optional implementation, the step of sequentially forming a first passivation layer and a light-shielding layer on the side of the wiring functional layer opposite to the substrate includes:

[0034] A passivation material film is formed on the side of the wiring functional layer opposite to the substrate.

[0035] Using a first patterning process, the light-shielding layer is formed on the side of the passivation material film facing away from the substrate.

[0036] Using a second patterning process, a first planarization layer is formed on the side of the light-shielding layer opposite to the substrate, wherein the orthographic projection of the first planarization layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate; and,

[0037] Using the first planarization layer as a mask, the passivation material film is etched to form the first passivation layer. The orthographic projection of the first passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

[0038] In one optional implementation, the step of sequentially forming a first passivation layer and a light-shielding layer on the side of the wiring functional layer opposite to the substrate includes:

[0039] A passivation material film is formed on the side of the wiring functional layer opposite to the substrate.

[0040] A third patterning process is used to form a second planarization layer on the side of the passivation material film away from the substrate, wherein the orthographic projection of the second planarization layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

[0041] Using a fourth patterning process, the light-shielding layer is formed on the side of the second planarization layer opposite to the substrate; and,

[0042] Using the second planarization layer as a mask, the passivation material film is etched to form the first passivation layer. The orthographic projection of the first passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

[0043] In one alternative implementation, prior to the step of forming the light-shielding layer on the side of the second planarization layer opposite to the substrate, the method further includes:

[0044] Using a fifth patterning process, a second passivation layer is formed on the side of the second planarization layer opposite to the substrate, and the orthographic projection of the second passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

[0045] The step of forming the light-shielding layer on the side of the second planarization layer opposite to the substrate includes:

[0046] The light-shielding layer is formed on the side of the second passivation layer away from the substrate.

[0047] In one alternative implementation, the step of forming a wiring functional layer on one side of the substrate includes:

[0048] A first metal layer, a third passivation layer, a third planarization layer, a fourth passivation layer, and a second metal layer are sequentially formed on one side of the substrate. The metal traces include a first metal trace located on the first metal layer and a second metal trace located on the second metal layer. The bonding terminal is located on the second metal layer and is interconnected with the second metal trace. The second metal trace and the first metal trace are connected through vias provided on the insulating layer.

[0049] The step of forming the third planarization layer includes:

[0050] Using a sixth patterning process, a fourth planarization layer is formed on the side of the third passivation layer opposite to the substrate; and,

[0051] Using a seventh patterning process, a fifth planarization layer is formed on the side of the fourth planarization layer opposite to the substrate, and the fourth and fifth planarization layers constitute the third planarization layer.

[0052] Compared with the prior art, this disclosure includes the following advantages:

[0053] This disclosure provides a method for fabricating a display substrate, a display substrate, and a display device. The display substrate includes a display area and a peripheral area. The display substrate includes: a substrate; a wiring functional layer disposed on one side of the substrate, the wiring functional layer including metal traces and bonding terminals connected to the metal traces, the bonding terminals including a first bonding terminal, a second bonding terminal, and a third bonding terminal, the first and second bonding terminals being located in the display area, and the third bonding terminal being located in the peripheral area; a first passivation layer disposed on the side of the wiring functional layer facing away from the substrate; and a light-shielding layer disposed on the side of the first passivation layer facing away from the substrate, wherein the orthographic projection of the light-shielding layer on the substrate does not overlap with the orthographic projection of the bonding terminals on the substrate, and within the display area, the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the metal traces on the substrate. This disclosure can improve the contrast of the display device. By providing a light-shielding layer on the side of the wiring functional layer facing away from the substrate, and ensuring that the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the metal traces on the substrate, this disclosure avoids light reflection from the metal traces, thereby improving the contrast of the display device.

[0054] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0056] Figure 1 A schematic diagram of a planar structure of a display substrate provided in an embodiment of this disclosure is shown;

[0057] Figure 2 A cross-sectional structural schematic diagram of the first type of display substrate provided in this embodiment is shown;

[0058] Figure 3 This diagram illustrates a planar structure of a routing function layer according to an embodiment of the present disclosure.

[0059] Figure 4 A schematic diagram of a planar structure of a light-shielding layer provided in an embodiment of this disclosure is shown;

[0060] Figure 5 This diagram illustrates a connection structure of a routing function layer according to an embodiment of the present disclosure.

[0061] Figure 6 A schematic diagram of the planar structure of the first metal layer and the second metal layer provided in an embodiment of this disclosure is shown;

[0062] Figure 7 A cross-sectional structural schematic diagram of a second type of display substrate provided in an embodiment of this disclosure is shown;

[0063] Figure 8 Scanning electron microscope images of first passivation layers of different thicknesses provided in embodiments of this disclosure in a second type of display substrate are shown.

[0064] Figure 9 The present disclosure provides a parameter comparison of several light-shielding layer materials according to embodiments;

[0065] Figure 10 A cross-sectional structural schematic diagram of a third type of display substrate provided in an embodiment of this disclosure is shown;

[0066] Figure 11 An image showing no residual light-shielding layer provided in an embodiment of this disclosure is shown;

[0067] Figure 12 An image showing a residual light-shielding layer provided in an embodiment of this disclosure is shown;

[0068] Figure 13 A schematic diagram of the structure of a display device provided in an embodiment of this disclosure is shown;

[0069] Figure 14 A flowchart illustrating the steps of a method for fabricating a display substrate according to an embodiment of this disclosure is shown;

[0070] Figure 15 This illustration shows a process flow diagram of the fabrication process of a first passivation layer in a display substrate according to an embodiment of the present disclosure;

[0071] Figure 16 A process flow diagram of the fabrication process of a third planarization layer in a display substrate provided in an embodiment of this disclosure is shown;

[0072] Figure 17a A process flow diagram of a display substrate fabrication process provided in an embodiment of this disclosure is shown;

[0073] Figure 17b A process flow diagram of a display substrate fabrication process provided in an embodiment of this disclosure is shown;

[0074] Figure 17c A flowchart illustrating the fabrication process of a display substrate according to an embodiment of this disclosure is shown. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0076] One embodiment of this disclosure provides a display substrate, with reference to... Figure 1 A schematic diagram of a planar structure of a display substrate provided in this embodiment is shown. The display substrate includes a display area AA and a peripheral area BB located around the display area AA.

[0077] Reference Figure 2 , Figure 7 and Figure 10 The diagram shows a cross-sectional structure of several display substrates provided in this embodiment. The display substrate includes: a substrate 21; a wiring functional layer 22 disposed on one side of the substrate 21; a first passivation layer 23 disposed on the side of the wiring functional layer 22 opposite to the substrate 21; and a light-shielding layer 24 disposed on the side of the first passivation layer 23 opposite to the substrate 21.

[0078] Reference Figure 3 A schematic diagram of a planar structure of a routing functional layer is shown. This routing functional layer 22 includes metal traces 31 and bonding terminals connected to the metal traces 31. The bonding terminals include a first bonding terminal 32, a second bonding terminal 33, and a third bonding terminal 34 (e.g., ...). Figure 1 As shown, the first bonding terminal 32 is used to bond the LED chip, the second bonding terminal 33 is used to bond the driver chip, the driver chip is used to drive the LED chip to emit light, and the third bonding terminal 34 is used to bond the flexible circuit board. The first bonding terminal 32 and the second bonding terminal 33 are located in the display area AA, and the third bonding terminal 34 is located in the peripheral area BB.

[0079] Reference Figure 4 A schematic diagram of a planar structure for a light-shielding layer is shown. (Combined with...) Figure 3 and Figure 4 The orthographic projection of the light-shielding layer 24 on the substrate 21 does not overlap with the orthographic projection of the bonding terminal on the substrate 21. Within the display area AA, the orthographic projection of the light-shielding layer 24 on the substrate 21 covers the orthographic projection of the metal trace 31 on the substrate 21.

[0080] Reference Figures 2 to 4The light-shielding layer 24 has opening areas at corresponding positions to the first bonding terminal 32, the second bonding terminal 33 and the third bonding terminal 34 to facilitate subsequent bonding processes.

[0081] Reference Figure 1 The display area AA may include multiple pixel units, and each pixel unit may be divided into a transparent area TR and a non-transparent area. The first bonding terminal 32 and the second bonding terminal 33 may be located within the non-transparent area of ​​each pixel unit, such as... Figure 3 and Figure 5 As shown. Among them, Figure 3 This diagram shows a planar structure of the wiring functional layer within a single pixel unit. Figure 5 The diagram shows the connection structure of the routing functional layer corresponding to multiple pixel units.

[0082] Reference Figure 3 The first bonding terminal 32 can be multiple, such as the positive terminal of the red LED chip, the negative terminal of the red LED chip, the positive terminal of the green LED chip, the negative terminal of the green LED chip, the positive terminal of the blue LED chip, and the negative terminal of the blue LED chip.

[0083] like Figure 3 and Figure 5 As shown, the metal trace 31 may include a scan signal supply line VCC1, a data signal line Data, a reference signal line GND, a first voltage signal line VGB, a second voltage signal line VR, and a scan signal line VCC2, etc.

[0084] It should be noted that, as Figure 5 As shown, at least one scan signal line VCC2 in the metal trace 31 is electrically connected to at least one scan signal supply line VCC1, so that the scan signal supply line VCC1 can transmit the scan signal received from the flexible circuit board to the scan signal line VCC2 of the corresponding row connected thereto. Figure 5 This embodiment only illustrates one possible arrangement of the metal traces 31, and does not limit the connection positions between different traces.

[0085] Reference Figure 1 The surrounding area BB may include the pad area SA and the fan-out area located between the pad area SA and the display area AA. The third bonding terminal 34 is located within the pad area SA.

[0086] In this embodiment, the substrate 21 may include a glass substrate or a flexible substrate, and may also include alignment marks disposed on one side of the substrate, and may also include a buffer layer or other film layer. This embodiment does not limit these features.

[0087] The routing functional layer 22 can be a single-layer structure or a multi-layer structure, such as including multiple metal layers and an insulating layer disposed between two adjacent metal layers. This embodiment does not limit the specific layer structure of the routing functional layer 22. Subsequent embodiments will describe the structure of a routing functional layer 22 in detail.

[0088] The material of the first passivation layer 23 may include inorganic materials such as silicon oxide and silicon nitride, and this embodiment does not limit this. By setting the first passivation layer 23, oxidation of the metal traces 31 in the trace functional layer 22 can be prevented, ensuring the performance stability of the display substrate. At the same time, it can also prevent the light-shielding layer 24 from remaining on the surface of the trace functional layer 22.

[0089] The material of the light-shielding layer 24 can be carbon black or inorganic black, etc., and this embodiment does not limit it.

[0090] In this embodiment, the LED chip is an active light-emitting device. A driver chip is used to drive the LED chip to emit light, which can make a larger display substrate and achieve a larger driving current.

[0091] The display substrate provided in this embodiment provides a light-shielding layer 24 on the side of the wiring functional layer 22 away from the substrate 21, and the orthogonal projection of the light-shielding layer 24 on the substrate 21 covers the orthogonal projection of the metal wiring 31 on the substrate 21, thereby preventing the metal wiring 31 from reflecting light and improving the contrast of the display device.

[0092] To improve the light transmittance of the display area AA, in one optional implementation, the orthographic projection of the light-shielding layer 24 onto the substrate 21 and the orthographic projection of the metal trace 31 onto the substrate 21 can completely coincide within the display area AA. In this way, the light-shielding layer 24 can completely cover the metal trace 31, preventing it from reflecting ambient light, while simultaneously increasing the area of ​​the transparent region TR, thereby improving the light transmittance of the display area AA.

[0093] In one alternative implementation, the substrate 21 can be a flexible substrate, with a bendable area provided between the display area AA and the pad area SA. This allows the peripheral area BB to be bent to the back of the display area AA. When multiple display substrates are spliced ​​together to form a display panel, the gap between adjacent display substrates can be reduced because the peripheral area BB is located on the back of the display substrate, thereby improving the overall display effect of the display panel.

[0094] In a specific implementation, if the peripheral area BB is located on the back of the display area AA, or can be bent to the back of the display area AA, the orthographic projection of the light-shielding layer 24 on the substrate 21 can be non-overlapping with the peripheral area BB. If the peripheral area BB is located on the front of the display area AA, or cannot be bent to the back of the display area AA, the orthographic projection of the light-shielding layer 24 on the substrate 21 within the peripheral area BB can cover the orthographic projection of the metal trace 31 on the substrate 21.

[0095] In one alternative implementation, refer to Figure 2 , Figure 7 and Figure 10 The wiring functional layer 22 may include: a first metal layer 221, an insulating layer and a second metal layer 222 stacked together, wherein the first metal layer 221 is disposed close to the substrate 21.

[0096] In this implementation, refer to Figure 6 The metal trace 31 may include a first metal trace located on the first metal layer 221 and a second metal trace located on the second metal layer 222. The bonding terminal is located on the second metal layer 222 and is interconnected with the second metal trace. The second metal trace and the first metal trace are connected through a via provided on the insulating layer.

[0097] In one alternative implementation, the display area AA comprises multiple pixel units arranged in an array, as shown in the figure. Figure 6 The first metal trace may include at least one first sub-trace (e.g., a reference signal line GND) extending along the pixel column direction within the display area AA, the first sub-trace having a first line width S1 along the pixel row direction.

[0098] Wherein, the pixel column direction is the column direction of the pixel units arranged in the array, and the pixel row direction is the row direction of the pixel units arranged in the array.

[0099] Reference Figure 6 The first metal trace may further include at least one second sub-trace (e.g., a first voltage signal line VGB, a second voltage signal line VR, a data signal line Data, a scan signal supply line VCC1, etc.) extending along the pixel column direction within the display area AA. The second sub-trace has a second linewidth S2 along the pixel row direction, and the second linewidth S2 is smaller than the first linewidth S1. When there are multiple second sub-traces, they may have different second linewidths S2 along the pixel row direction (e.g., including at least one second sub-trace with a linewidth of S21, at least one second sub-trace with a linewidth of S22, ..., at least one second sub-trace with a linewidth of S2n), but all of these second linewidths S2 are smaller than the first linewidth S1.

[0100] Reference Figure 6A first spacing S3 exists between a second sub-trace adjacent to the first sub-trace (e.g., a reference signal line GND) along the pixel row direction and the first sub-trace (e.g., a reference signal line GND), wherein the first spacing S3 is greater than three times the first line width S1, i.e., S3>3S1.

[0101] In some examples, refer to Figure 6 The orthographic projection of the first bonding terminal 32 on the substrate 21 is located within the orthographic projection range of the first sub-trace (e.g., the reference signal line GND) on the substrate 21.

[0102] Reference Figure 6 The first metal trace located on the first metal layer 221 may include: a scan signal supply line VCC1, a data signal line Data, a reference signal line GND, a first voltage signal line VGB, and a second voltage signal line VR. The second metal trace located on the second metal layer 222 may include a scan signal line VCC2, and may also include leads connecting bonding terminals to the aforementioned signal lines. Additionally, the first bonding terminal 32, the second bonding terminal 33, and the third bonding terminal 34 may also be located on the second metal layer 222.

[0103] The material of the first metal layer 221 may include a metal film layer such as a copper layer, a molybdenum layer, or an aluminum layer; this embodiment does not limit the material. The material of the second metal layer 222 may include a metal film layer such as a copper layer, a molybdenum layer, or an aluminum layer; this embodiment does not limit the material.

[0104] like Figure 2 , Figure 7 and Figure 10 As shown, the insulating layer disposed between the first metal layer 221 and the second metal layer 222 may include a third passivation layer 223, a third planarization layer 224 and a fourth passivation layer 225 stacked on the side of the first metal layer 221 away from the substrate 21, with the third passivation layer 223 disposed close to the first metal layer 221.

[0105] The material of the third passivation layer 223 may include inorganic materials such as silicon oxide and silicon nitride, and this embodiment is not limited thereto. The material of the fourth passivation layer 225 may include inorganic materials such as silicon oxide and silicon nitride, and this embodiment is not limited thereto. The material of the third planarization layer 224 may be, for example, an organic material such as polyacrylic resin, and this embodiment is not limited thereto.

[0106] By providing a third passivation layer 223 between the third planarization layer 224 and the first metal layer 221, the oxidation of the first metal layer 221 by oxygen released from the third planarization layer 224 in subsequent processes can be prevented. By providing a fourth passivation layer 225 between the third planarization layer 224 and the second metal layer 222, the oxidation of the second metal layer 222 by oxygen released from the third planarization layer 224 in subsequent processes can be prevented.

[0107] In one alternative implementation, such as Figure 2 and Figure 10 As shown, the second metal layer 222 can be a copper layer. In order to prevent the third bonding terminal 34 of the surrounding area BB from oxidizing, a transparent electrode layer 25 can also be provided between the first passivation layer 23 and the second metal layer 222. The orthogonal projection of the transparent electrode layer 25 on the substrate 21 covers the orthogonal projection of the third bonding terminal 34 on the substrate 21.

[0108] The transparent electrode layer 25 can be made of conductive and oxidation-resistant materials such as indium tin oxide, and this embodiment is not limited to this. By providing a transparent electrode layer 25 on the third bonding terminal 34, oxidation of the third bonding terminal 34 can be prevented.

[0109] In another alternative implementation, refer to Figure 7 The second metal layer 222 may include a copper layer and a copper-nickel alloy layer disposed on the side of the copper layer facing away from the substrate 21. By providing a copper-nickel alloy layer on the surface of the copper layer, oxidation of the third bonding terminal 34 in the surrounding area BB can be prevented.

[0110] The orthogonal projection of the copper-nickel alloy layer onto the substrate 21 can be the orthogonal projection of the copper layer onto the substrate 21.

[0111] In this implementation, because copper-nickel alloy has high strength, corrosion resistance, and hardness, covering the entire surface of the copper layer with a copper-nickel alloy layer can prevent the copper layer from oxidizing and the bonding terminals from oxidizing. Thus, there is no need to set a transparent electrode layer on the surface of the third bonding terminal 34, thereby reducing a masking process, simplifying the process steps, improving yield, and reducing costs.

[0112] In this implementation, a molybdenum layer or a molybdenum-niobium alloy layer can be disposed between the fourth passivation layer 225 in the insulating layer and the second metal layer 222, which can improve the bonding strength between the second metal layer 222 and the fourth passivation layer 225 in the insulating layer.

[0113] The thickness of the molybdenum-niobium alloy layer can be, for example, 300 angstroms, the thickness of the copper layer can be, for example, 6000 angstroms, and the thickness of the copper-nickel alloy layer can be, for example, 500 angstroms.

[0114] The inventors, through scanning electron microscopy analysis, discovered that in this implementation, due to the faster etching rate of the copper layer in the second metal layer 222, the etched copper layer is recessed relative to the copper-nickel alloy layer. Figure 8 As shown, this leads to a risk of cracking during the subsequent fabrication of the first passivation layer 23, especially when the thickness of the first passivation layer 23 is relatively thin, the risk of cracking increases. Figure 8 As shown in b in the figure.

[0115] To reduce the risk of fracture in the first passivation layer 23, the thickness of the first passivation layer 23 can be greater than or equal to 8000 angstroms, such as... Figure 8 As shown in 'a'.

[0116] Reference Figure 2 and Figure 7 A first planarization layer 26 may also be provided on the side of the light-shielding layer 24 away from the substrate 21. The orthographic projection of the first planarization layer 26 on the substrate 21 does not overlap with the orthographic projection of the bonding terminal on the substrate 21. The orthographic projection of the first passivation layer 23 on the substrate 21 does not overlap with the orthographic projection of the bonding terminal on the substrate 21.

[0117] The material of the first planarization layer 26 can be, for example, an organic material such as polyacrylic resin, but this embodiment does not limit it.

[0118] To prevent oxidation of the bonding terminals during storage before the bonding process, the first passivation layer 23 and the corresponding position of the bonding terminals can be etched separately during the manufacturing process of the display substrate. Instead, the first passivation layer 23 can be etched using a patterned first planarization layer 26 as a mask before the bonding process, so that the orthographic projection of the first passivation layer 23 on the substrate 21 does not overlap with the orthographic projection of the bonding terminals on the substrate 21. The bonding process can then be performed.

[0119] To further reduce the coupling capacitance formed between the light-shielding layer 24 and the second metal layer 222, refer to Figure 10 A second planarization layer 101 may also be provided between the light-shielding layer 24 and the first passivation layer 23. The orthographic projection of the second planarization layer 101 on the substrate 21 does not overlap with the orthographic projection of the bonding terminal on the substrate 21, and the orthographic projection of the first passivation layer 23 on the substrate 21 does not overlap with the orthographic projection of the bonding terminal on the substrate 21.

[0120] The material of the second planarization layer 101 can be, for example, an organic material such as polyacrylic resin, but this embodiment does not limit it.

[0121] By providing a second planarization layer 101 between the light-shielding layer 24 and the first passivation layer 23, the distance between the light-shielding layer 24 and the second metal layer 222 is increased, thereby reducing the negative impact of the coupling capacitance between the light-shielding layer 24 and the second metal layer 222.

[0122] To prevent oxidation of the bonding terminals during storage before the bonding process, the first passivation layer 23 and the corresponding position of the bonding terminals can be etched separately in the manufacturing process of the display substrate. Instead, the first passivation layer 23 can be etched using the second planarization layer 101 as a mask before the bonding process, so that the orthographic projection of the first passivation layer 23 on the substrate 21 does not overlap with the orthographic projection of the bonding terminals on the substrate 21. The bonding process is then performed.

[0123] The inventors discovered that the material of the light-shielding layer 24 has a small contact angle on the hydrophilic surface (-OH interface), which allows for the formation of better patterns, such as... Figure 11 As shown; on substrates with poor hydrophilicity, the contact angle is large, and residues are prone to appear. The residues are particles visible under a scanning electron microscope, such as... Figure 12 As shown, the residue is unrelated to the exposure and development processes. The interface of the second planarization layer 101 is made of polyacrylic acid resin, which is a hydrophobic material, and the material of the light-shielding layer 24 is prone to residue on its surface. Residue in the light-shielding layer 24 may have two consequences: firstly, residue in the transparent area will seriously affect the transmittance of the transparent area; secondly, residue in the bonding area may lead to poor bonding.

[0124] To avoid any residue from the light-shielding layer 24, refer to Figure 10 A second passivation layer 102 may also be provided between the light-shielding layer 24 and the second planarization layer 101. The orthographic projection of the second passivation layer 102 on the substrate 21 does not overlap with the orthographic projection of the bonding terminal on the substrate 21.

[0125] The material of the second passivation layer 102 may include inorganic materials such as silicon oxide and silicon nitride, but this embodiment does not limit this.

[0126] By providing a second passivation layer 102 between the light-shielding layer 24 and the second planarization layer 101, it is possible to prevent the light-shielding layer 24 from remaining on the second planarization layer 101.

[0127] exist Figure 2 and Figure 7 In the display substrate shown, since the light-shielding layer 24 and the second metal layer 222 are close together, in order to avoid the formation of a coupling capacitor between the light-shielding layer 24 and the second metal layer 222, the material of the light-shielding layer 24 can be an organic black material.

[0128] Reference Figure 9Columns b and c in the table show the parameters of two organic black materials. Because the dielectric constants of organic black materials are relatively low, at 3.7 and 3.5 respectively, they are used to fabricate... Figure 2 and Figure 7 The light-shielding layer 24 in the middle can reduce the coupling capacitance formed between the light-shielding layer 24 and the second metal layer 222, and avoid the influence of the light-shielding layer 24 on the load of the second metal layer 222. In practical applications, since the resolution of the c-column organic black material in the exposure process (~5μm) is better than that of the b-column material (>9μm), the c-column organic black material can be selected to make the light-shielding layer 24, which can improve the control accuracy of the exposure process.

[0129] exist Figure 10 In the display substrate shown, the material of the light-shielding layer 24 can be carbon black.

[0130] Reference Figure 9 Column 'a' in the table represents the parameters of a type of carbon black material. The dielectric constant (15) of carbon black material is higher than that of organic black materials (3.7 and 3.5), but because... Figure 10 A second planarization layer 101 is provided between the light-shielding layer 24 and the second metal layer 222, which increases the distance between the light-shielding layer 24 and the second metal layer 222. Therefore, the material of the light-shielding layer 24 can be carbon black material with a slightly higher dielectric constant, which can also avoid the influence of the coupling capacitance between the light-shielding layer 24 and the second metal layer 222, and avoid the influence of the light-shielding layer 24 on the load of the second metal layer 222.

[0131] It should be noted that, Figure 10 The light-shielding layer 24 can also be made of organic black material, which can further reduce the coupling capacitance. However, since the resolution (~0 μm) of the a-column carbon black material is better than that of the organic black material in the exposure process, choosing the a-column carbon black material to make the light-shielding layer 24 can improve the control accuracy of the exposure process.

[0132] In a specific implementation, the thickness of the light-shielding layer 24 can be determined based on the optical density value of the specific material and the designed transmittance value of the light-shielding layer 24. This embodiment does not limit this.

[0133] The thickness of the light-shielding layer 24 will be explained below, taking the example that the transmittance of the light-shielding layer 24 is less than or equal to 1%.

[0134] Figure 9 The optical density (OD) value of the material in column a is 4.0 / μm. In order to make the transmittance of the light-shielding layer 24 of the material in column a less than or equal to 1%, the thickness of the light-shielding layer 24 can be greater than or equal to 0.5μm.

[0135] Figure 9The optical density (OD) value of the material in column b is 2.0 / μm. In order to make the transmittance of the light-shielding layer 24 of the material in column b less than or equal to 1%, the thickness of the light-shielding layer 24 can be greater than or equal to 1.0μm.

[0136] Figure 9 The optical density (OD) value of the material in column c is 2.6 / μm. In order to make the transmittance of the light-shielding layer 24 of the material in column c less than or equal to 1%, the thickness of the light-shielding layer 24 can be greater than or equal to 0.77μm.

[0137] In one alternative implementation, refer to Figure 2 , Figure 7 and Figure 10 An electroplating functional layer 27 may also be provided between the substrate 21 and the first metal layer 221. The orthographic projection of the electroplating functional layer 27 on the substrate 21 completely coincides with the orthographic projection of the first metal layer 221 on the substrate 21. The electroplating functional layer 27 is used to improve the bonding strength between the first metal layer 221 and the substrate 21.

[0138] The material of the electroplated functional layer 27 can be, for example, molybdenum or a molybdenum-niobium alloy, but this embodiment does not limit it.

[0139] Another embodiment of this disclosure also provides a display device, which may include a display substrate as described in any embodiment.

[0140] It should be noted that the display device in this embodiment can be any product or component with 2D or 3D display function, such as a display panel, electronic paper, mobile phone, tablet computer, television, laptop computer, digital photo frame, or navigator.

[0141] In a specific implementation, the display device may include multiple display substrates as described in any embodiment. For example... Figure 13 As shown, multiple display substrates can be fixed together by cabinet locks and vertical beams. Multiple display substrates can be seamlessly spliced ​​vertically, meaning there are no horizontal seams, resulting in a brighter and more transparent visual effect.

[0142] In this embodiment, the display device can be applied to outdoor transparent displays. Because the LED chips are made of inorganic materials, they offer better reliability in outdoor or semi-outdoor environments.

[0143] The pixels in the display substrate can be arranged in a rectangular array, with uniform light transmission area, thereby improving the visual effect.

[0144] The display device provided in this embodiment can use 100-micron-level LED chips / wiring to achieve a transmittance of >70% and a wide viewing angle of >160°C. It employs an active driving scheme for precise light control, excellent low-grayscale performance, and low power consumption. High pixel density allows for shorter viewing distances and more detailed image quality. It is lightweight and thin, easy to assemble and disassemble, and can be infinitely spliced. Wireless signal transmission provides good scalability and ease of maintenance. The pixel pitch can be 3mm, the viewing distance is >8 meters, the transmittance reaches 85%, and the brightness reaches 2000 nits (before calibration).

[0145] Another embodiment of this disclosure also provides a method for fabricating a display substrate, the display substrate including a display area and a peripheral area located around the display area, referring to... Figure 14 The preparation method includes:

[0146] Step 1401: Provide a substrate.

[0147] Step 1402: A wiring functional layer is formed on one side of the substrate. The wiring functional layer includes metal wiring and bonding terminals connected to the metal wiring. The bonding terminals include a first bonding terminal, a second bonding terminal and a third bonding terminal. The first bonding terminal is used to bond LED chips, the second bonding terminal is used to bond driver chips, the driver chips are used to drive LED chips to emit light, and the third bonding terminal is used to bond flexible circuit boards. The first bonding terminal and the second bonding terminal are located in the display area, and the third bonding terminal is located in the peripheral area.

[0148] Step 1403: A first passivation layer and a light-shielding layer are sequentially formed on the side of the wiring functional layer away from the substrate. The orthographic projection of the light-shielding layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate. In the display area, the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the metal wiring on the substrate.

[0149] The display substrate described in any of the above embodiments can be prepared using the preparation method provided in this embodiment.

[0150] In one alternative implementation, step 1403 may specifically include:

[0151] A passivation material film is formed on the side of the wiring functional layer that is away from the substrate.

[0152] Using the first patterning process, a light-shielding layer is formed on the side of the passivation material thin film facing away from the substrate.

[0153] Using a second patterning process, a first planarization layer is formed on the side of the light-shielding layer facing away from the substrate, wherein the orthographic projection of the first planarization layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate; and,

[0154] Using the first planarization layer as a mask, the passivation material film is etched to form the first passivation layer. The orthographic projection of the first passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

[0155] In this implementation, to prevent oxidation of the bonding terminals during storage before the bonding process, refer to... Figure 15 During the fabrication of the display backplane, the first passivation layer 23 can be left unetched. When the bonding process is required, the patterned first planarization layer 26 is used as a mask to etch the first passivation layer 23, and then the bonding process is performed.

[0156] In another alternative implementation, step 1403 may specifically include:

[0157] A passivation material film is formed on the side of the wiring functional layer that is away from the substrate.

[0158] A third patterning process is used to form a second planarization layer on the side of the passivation material film away from the substrate. The orthographic projection of the second planarization layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

[0159] Using a fourth patterning process, a light-shielding layer is formed on the side of the second planarization layer opposite to the substrate; and,

[0160] Using the second planarization layer as a mask, the passivation material film is etched to form the first passivation layer. The orthographic projection of the first passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

[0161] In this implementation, to prevent oxidation of the bonding terminals during storage before the bonding process, the first passivation layer can be left unetched during the display backplane fabrication process. When the bonding process is required, the patterned second planarization layer is used as a mask to etch the first passivation layer, and then the bonding process is performed.

[0162] In this implementation, before the step of forming a light-shielding layer on the side of the second planarization layer away from the substrate, the following step may be included: using a fifth patterning process, forming a second passivation layer on the side of the second planarization layer away from the substrate, wherein the orthographic projection of the second passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate. Accordingly, the step of forming a light-shielding layer on the side of the second planarization layer away from the substrate may include: forming a light-shielding layer on the side of the second passivation layer away from the substrate.

[0163] In one alternative implementation, step 1402 may specifically include:

[0164] A first metal layer, a third passivation layer, a third planarization layer, a fourth passivation layer, and a second metal layer are sequentially formed on one side of the substrate. The metal traces include a first metal trace located on the first metal layer and a second metal trace located on the second metal layer. The bonding terminal is located on the second metal layer and is interconnected with the second metal trace. The second metal trace and the first metal trace are connected through vias disposed on the insulating layer.

[0165] The step of forming the third planarization layer may include:

[0166] A sixth patterning process is used to form a fourth planarization layer on the side of the third passivation layer away from the substrate; and a seventh patterning process is used to form a fifth planarization layer on the side of the fourth planarization layer away from the substrate, wherein the fourth planarization layer and the fifth planarization layer constitute the third planarization layer.

[0167] Reference Figure 16 The third flattening layer 224 is formed by two patterning processes, which can reduce the difficulty of the process and improve the accuracy of process control.

[0168] The patterning process in this embodiment may include at least one of the following steps: film deposition, exposure and development, etching, and photoresist removal. The film deposition process may be one of magnetron sputtering, thermal evaporation, electron beam evaporation, or electroplating. The etching process may be dry etching or wet etching. Specific patterning steps can be designed according to the material and film structure; this embodiment does not limit their application.

[0169] Reference Figures 17a to 17c A process flow diagram for fabricating the first display substrate is shown. Specifically, it may include the following steps:

[0170] Provide a substrate 21, such as Figure 17a As shown in 'a';

[0171] A thin film of electroplated functional material is formed on the substrate 21, such as Figure 17a As shown in b;

[0172] Forming a PR adhesive mask, such as Figure 17a As shown in c;

[0173] Electroplated copper layer, such as Figure 17a As shown in d;

[0174] Peel off the PR adhesive to form the first metal layer 221, as shown below. Figure 17a As shown in e;

[0175] Using the first metal layer 221 as a mask, the electroplated functional layer 27 is etched, as shown below. Figure 17a or Figure 17b As shown in f;

[0176] Forming a third passivation layer 223, such as Figure 17b As shown in g;

[0177] The third planarization layer 224 is formed using the sixth and seventh patterning processes, respectively. Figure 17b As shown in h;

[0178] Forming a fourth passivation layer 225, such as Figure 17b As shown in i;

[0179] Forming a second metal layer 222, such as Figure 17b or Figure 17c As shown in j;

[0180] Forming a transparent electrode layer 25 and a passivation material thin film, such as Figure 17c As shown in k in the figure;

[0181] Using the first patterning process, a light-shielding layer 24 is formed, such as... Figure 17c As shown in m;

[0182] A second patterning process is used to form a second planarization layer 26, and using the second planarization layer 26 as a mask, a passivation material thin film is etched to form a first passivation layer 23, such as... Figure 17c As shown in n; obtain as Figure 2 The display substrate shown.

[0183] This embodiment provides a method for fabricating a display substrate, a display substrate, and a display device. The display substrate includes a display area and a peripheral area surrounding the display area. The display substrate includes: a substrate; a wiring functional layer disposed on one side of the substrate, the wiring functional layer including metal traces and bonding terminals connected to the metal traces, the bonding terminals including a first bonding terminal, a second bonding terminal, and a third bonding terminal, the first bonding terminal for bonding an LED chip, the second bonding terminal for bonding a driver chip, the driver chip for driving the LED chip to emit light, and the third bonding terminal for bonding a flexible circuit board; the first and second bonding terminals are located in the display area, and the third bonding terminal is located in the peripheral area; a first passivation layer disposed on the side of the wiring functional layer facing away from the substrate; and a light-shielding layer disposed on the side of the first passivation layer facing away from the substrate, the orthographic projection of the light-shielding layer on the substrate not overlapping the orthographic projection of the bonding terminals on the substrate, and within the display area, the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the metal traces on the substrate. The present technical solution provides a light-shielding layer on the side of the wiring functional layer away from the substrate, and the orthogonal projection of the light-shielding layer on the substrate covers the orthogonal projection of the metal wiring on the substrate, thereby avoiding the metal wiring from reflecting light and improving the contrast of the display device.

[0184] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0185] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0186] The foregoing has provided a detailed description of a method for preparing a display substrate, the display substrate itself, and the display device provided by this disclosure. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. Furthermore, those skilled in the art will recognize that, based on the ideas of this disclosure, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this disclosure. The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a specific feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Additionally, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0187] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0188] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This disclosure can be implemented by means of hardware comprising a plurality of different elements and by means of a suitably programmed computer. In a unit claim enumerating a plurality of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0189] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A display substrate, characterized in that, The display substrate includes a display area and a peripheral area surrounding the display area. Substrate; A wiring functional layer is disposed on one side of the substrate. The wiring functional layer includes metal traces and bonding terminals connected to the metal traces. The bonding terminals include a first bonding terminal, a second bonding terminal, and a third bonding terminal. The first bonding terminal is used to bond an LED chip, the second bonding terminal is used to bond a driver chip, the driver chip is used to drive the LED chip to emit light, and the third bonding terminal is used to bond a flexible circuit board. The first bonding terminal and the second bonding terminal are located in the display area, and the third bonding terminal is located in the peripheral area. A first passivation layer is disposed on the side of the wiring functional layer opposite to the substrate; and... A light-shielding layer is disposed on the side of the first passivation layer away from the substrate. The orthographic projection of the light-shielding layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate. In the display area, the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the metal trace on the substrate. The light-shielding layer has an opening area at a position corresponding to the first bonding terminal, the second bonding terminal, and the third bonding terminal; the opening area is used for the bonding process.

2. The display substrate according to claim 1, characterized in that, Within the display area, the orthographic projection of the light-shielding layer on the substrate completely coincides with the orthographic projection of the metal trace on the substrate.

3. The display substrate according to claim 1, characterized in that, The wiring functional layer includes: a first metal layer, an insulating layer, and a second metal layer stacked together, wherein the first metal layer is disposed close to the substrate. The metal trace includes a first metal trace located on the first metal layer and a second metal trace located on the second metal layer. The bonding terminal is located on the second metal layer and is interconnected with the second metal trace. The second metal trace and the first metal trace are connected through a via disposed on the insulating layer.

4. The display substrate according to claim 3, characterized in that, The second metal layer is a copper layer. A transparent electrode layer is also disposed between the first passivation layer and the second metal layer. The orthogonal projection of the transparent electrode layer on the substrate covers the orthogonal projection of the third bonding terminal on the substrate.

5. The display substrate according to claim 3, characterized in that, The second metal layer includes a copper layer and a copper-nickel alloy layer disposed on the side of the copper layer facing away from the substrate, and the thickness of the first passivation layer is greater than or equal to 8000 angstroms.

6. The display substrate according to claim 5, characterized in that, The orthogonal projection of the copper-nickel alloy layer on the substrate covers the orthogonal projection of the copper layer on the substrate.

7. The display substrate according to any one of claims 4 to 6, characterized in that, A first planarization layer is also provided on the side of the light-shielding layer away from the substrate. The orthographic projection of the first planarization layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate. The orthographic projection of the first passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

8. The display substrate according to claim 7, characterized in that, The material of the light-shielding layer is organic black material.

9. The display substrate according to any one of claims 4 to 6, characterized in that, A second planarization layer is further disposed between the light-shielding layer and the first passivation layer. The orthographic projection of the second planarization layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate, and the orthographic projection of the first passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

10. The display substrate according to claim 9, characterized in that, A second passivation layer is also provided between the light-shielding layer and the second planarization layer, and the orthographic projection of the second passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

11. The display substrate according to claim 9, characterized in that, The material of the light-shielding layer is carbon black.

12. The display substrate according to any one of claims 3 to 6, characterized in that, The insulating layer includes a third passivation layer, a third planarization layer, and a fourth passivation layer stacked on the side of the first metal layer away from the substrate, wherein the third passivation layer is disposed close to the first metal layer.

13. The display substrate according to any one of claims 3 to 6, characterized in that, An electroplating functional layer is further disposed between the substrate and the first metal layer, and the orthographic projection of the electroplating functional layer on the substrate completely coincides with the orthographic projection of the first metal layer on the substrate.

14. The display substrate according to any one of claims 3 to 6, characterized in that, The display area includes multiple pixel units arranged in an array, and the first metal trace includes: At least one first sub-trace extending along the pixel column direction within the display area, the first sub-trace having a first linewidth along the pixel row direction; and, At least one second sub-trace extending along the pixel column direction within the display area, the second sub-trace having a second line width along the pixel row direction, the second line width being smaller than the first line width.

15. The display substrate according to claim 14, characterized in that, The second sub-trace adjacent to the first sub-trace along the pixel row direction has a first spacing with the first sub-trace, the first spacing being greater than three times the first line width.

16. The display substrate according to claim 14, characterized in that, The orthographic projection of the first bonding terminal on the substrate is located within the orthographic projection range of the first sub-trace on the substrate.

17. A display device, characterized in that, The display device includes the display substrate according to any one of claims 1 to 16.

18. A method for preparing a display substrate, characterized in that, The display substrate includes a display area and a peripheral area located around the display area, and the fabrication method includes: Provide substrates; A wiring functional layer is formed on one side of the substrate. The wiring functional layer includes metal traces and bonding terminals connected to the metal traces. The bonding terminals include a first bonding terminal, a second bonding terminal, and a third bonding terminal. The first bonding terminal is used to bond an LED chip, the second bonding terminal is used to bond a driver chip, the driver chip is used to drive the LED chip to emit light, and the third bonding terminal is used to bond a flexible circuit board. The first bonding terminal and the second bonding terminal are located in the display area, and the third bonding terminal is located in the peripheral area. A first passivation layer and a light-shielding layer are sequentially formed on the side of the wiring functional layer away from the substrate. The orthographic projection of the light-shielding layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate. In the display area, the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the metal wiring on the substrate. The light-shielding layer has an opening area at a position corresponding to the first bonding terminal, the second bonding terminal, and the third bonding terminal; the opening area is used for the bonding process.

19. The preparation method according to claim 18, characterized in that, The step of sequentially forming a first passivation layer and a light-shielding layer on the side of the wiring functional layer opposite to the substrate includes: A passivation material film is formed on the side of the wiring functional layer opposite to the substrate. The light-shielding layer is formed on the side of the passivation material film facing away from the substrate using a first patterning process; Using a second patterning process, a first planarization layer is formed on the side of the light-shielding layer opposite to the substrate, wherein the orthographic projection of the first planarization layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate; and, Using the first planarization layer as a mask, the passivation material film is etched to form the first passivation layer. The orthographic projection of the first passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

20. The preparation method according to claim 18, characterized in that, The step of sequentially forming a first passivation layer and a light-shielding layer on the side of the wiring functional layer opposite to the substrate includes: A passivation material film is formed on the side of the wiring functional layer opposite to the substrate. A third patterning process is used to form a second planarization layer on the side of the passivation material film away from the substrate, wherein the orthographic projection of the second planarization layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate. Using a fourth patterning process, the light-shielding layer is formed on the side of the second planarization layer opposite to the substrate; and, Using the second planarization layer as a mask, the passivation material film is etched to form the first passivation layer. The orthographic projection of the first passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate.

21. The preparation method according to claim 20, characterized in that, Before the step of forming the light-shielding layer on the side of the second planarization layer opposite to the substrate, the method further includes: Using a fifth patterning process, a second passivation layer is formed on the side of the second planarization layer opposite to the substrate, and the orthographic projection of the second passivation layer on the substrate does not overlap with the orthographic projection of the bonding terminal on the substrate. The step of forming the light-shielding layer on the side of the second planarization layer opposite to the substrate includes: The light-shielding layer is formed on the side of the second passivation layer away from the substrate.

22. The preparation method according to any one of claims 18 to 21, characterized in that, The step of forming a wiring functional layer on one side of the substrate includes: A first metal layer, a third passivation layer, a third planarization layer, a fourth passivation layer, and a second metal layer are sequentially formed on one side of the substrate. The metal traces include a first metal trace located on the first metal layer and a second metal trace located on the second metal layer. The bonding terminal is located on the second metal layer and is interconnected with the second metal trace. The second metal trace and the first metal trace are connected through a via disposed on the insulating layer. The step of forming the third planarization layer includes: Using a sixth patterning process, a fourth planarization layer is formed on the side of the third passivation layer opposite to the substrate; and, Using a seventh patterning process, a fifth planarization layer is formed on the side of the fourth planarization layer opposite to the substrate, and the fourth and fifth planarization layers constitute the third planarization layer.

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