Display substrate, manufacturing method thereof and display device

Abstract

This disclosure provides a display substrate and its manufacturing method, as well as a display device, comprising: a substrate having a wiring area; at least one wiring layer located on the substrate, each wiring layer including multiple first wirings and second wirings spaced apart by different patterning processes in the wiring area, at least some of the first wirings and second wirings being arranged adjacent to each other, and the distance between adjacent first wirings and second wirings being less than 2µm.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a method for manufacturing the same, and a display device. Background Technology

[0002] With the rapid development of smartphones, there is a growing demand not only for aesthetically pleasing designs but also for a superior visual experience. Major manufacturers have begun increasing screen-to-body ratios, making full-screen displays a new competitive advantage. As full-screen displays evolve, the demand for improved performance and functionality also grows. Under-display cameras, without compromising a high screen-to-body ratio, can deliver a more immersive visual and user experience. Summary of the Invention

[0003] On one hand, embodiments of this disclosure provide a display substrate, including:

[0004] The base has a wiring area;

[0005] At least one routing layer is located on the substrate. The routing layer includes multiple first and second traces spaced apart by different patterning processes in the routing area. At least some of the first and second traces are arranged adjacent to each other, and the distance between adjacent first and second traces is less than 2 μm.

[0006] Optionally, in the display substrate provided in the embodiments of this disclosure, the first trace and the second trace of at least one of the trace layers are alternately arranged.

[0007] Optionally, the display substrate provided in the embodiments of this disclosure includes a display area and a border area. The display area includes a first display area and a second display area, wherein the light transmittance of the first display area is greater than that of the second display area.

[0008] The first display area includes a plurality of sub-pixels arranged in an array. Each sub-pixel includes a light-emitting device and a pixel circuit. The pixel circuit is located in the border area adjacent to the first display area. Alternatively, the second display area has a transition area adjacent to the first display area, and the pixel circuit is located in the transition area. Or, the pixel circuit is distributed in the second display area.

[0009] The wiring area is at least partially located in the first display area, and the wiring layer is located between the anode of the light-emitting device and the pixel circuit;

[0010] The first trace is used to electrically connect the corresponding light-emitting device and the pixel circuit, and the second trace is used to electrically connect the corresponding light-emitting device and the pixel circuit.

[0011] Optionally, in the display substrate provided in the embodiments of this disclosure, the material of the first trace is p-ITO, and the material of the second trace is a-ITO; wherein, the grain size of the p-ITO is larger than that of the a-ITO, the grain boundaries of the p-ITO are fewer than those of the a-ITO, and the resistance of the p-ITO is less than that of the a-ITO.

[0012] Optionally, in the display substrate provided in the embodiments of this disclosure, the material of the first trace is a-ITO, and the material of the second trace includes at least one of doped a-Si, IZO, and IGZO.

[0013] Optionally, in the display substrate provided in the embodiments of this disclosure, the material of the first trace is a-ITO, and the second trace includes a first sub-trace disposed on the substrate and a second sub-trace disposed on the side of the first sub-trace away from the substrate. The patterns of the first sub-trace and the second sub-trace are consistent and substantially overlap. The material of the first sub-trace is a-ITO, and the material of the second sub-trace includes at least one of doped a-Si, IZO, and IGZO.

[0014] Optionally, the display substrate provided in the embodiments of this disclosure further includes a planarization layer located on the side of the wiring layer away from the substrate. The planarization layer has a first via at the position corresponding to each of the first wiring and the second wiring. The anode of the light-emitting device is electrically connected to the first wiring and the second wiring through the corresponding first via.

[0015] Optionally, the display substrate provided in the embodiments of this disclosure includes a display area and a border area, the display area includes multiple signal lines, and the border area includes the wiring area;

[0016] The first trace is used to electrically connect the corresponding signal line, and the second trace is used to electrically connect the corresponding signal line.

[0017] Optionally, the display substrate provided in the embodiments of this disclosure includes a gate metal layer and a source / drain metal layer sequentially formed on the substrate, and the wiring layer is located on the gate metal layer and / or the source / drain metal layer.

[0018] Optionally, in the display substrate provided in the embodiments of this disclosure, the distance between the first trace and the second trace arranged adjacent to each other is 0.15um-0.35um, the line width of the first trace is less than or equal to 2um, and the line width of the second trace is less than or equal to 2um.

[0019] Optionally, in the display substrate provided in the embodiments of this disclosure, the number of wiring layers is multiple, and each wiring layer is insulated from the others.

[0020] Optionally, in the display substrate provided in the embodiments of this disclosure, the orthographic projections of each of the wiring layers on the substrate are independently distributed.

[0021] On the other hand, this disclosure also provides a method for manufacturing a display substrate, including:

[0022] Provide a substrate; the substrate has a routing area;

[0023] At least one routing layer is formed in the routing area of ​​the substrate, and different patterning processes are used to pattern first and second routing lines that are spaced apart in the routing area corresponding to each routing layer; wherein at least a portion of the first and second routing lines are arranged adjacent to each other, and the distance between the adjacent first and second routing lines is less than 2 μm.

[0024] Optionally, in the manufacturing method provided in the embodiments of this disclosure, different patterning processes are used to pattern the first and second traces that are spaced apart in the trace area corresponding to each trace layer, specifically including:

[0025] A first conductive layer is deposited in the wiring area of ​​the substrate;

[0026] The first conductive layer is annealed.

[0027] After annealing, the first conductive layer is coated with a first photoresist on the side opposite to the substrate, and the first photoresist is exposed and developed to form a patterned first photoresist layer.

[0028] Using the first photoresist layer as a mask, the first etch material is used to etch the annealed first conductive layer, forming multiple first traces spaced apart on the annealed first conductive layer;

[0029] A second conductive layer is deposited on the side of the plurality of first traces away from the substrate, and the material of the second conductive layer is the same as the material of the first conductive layer before annealing;

[0030] A second photoresist is coated on the side of the second conductive layer away from the substrate, and the second photoresist is exposed and developed to form a region where the second photoresist is completely removed in the region corresponding to the first trace, and a region where the second photoresist is retained in the region between adjacent first traces, so as to form a patterned second photoresist layer.

[0031] Using the second photoresist layer as a mask, the second etching material is used to etch the second conductive layer, forming a second trace between each adjacent first trace.

[0032] Optionally, in the manufacturing method provided in the embodiments of this disclosure, different patterning processes are used to pattern the first and second traces that are spaced apart in the trace area corresponding to each trace layer, specifically including:

[0033] A first conductive layer is deposited in the wiring area of ​​the substrate;

[0034] A first photoresist is coated on the side of the first conductive layer away from the substrate, and the first photoresist is exposed and developed to form a patterned first photoresist layer.

[0035] Using the first photoresist layer as a mask, the first conductive layer is etched with a second etching material to form multiple first traces spaced apart on the first conductive layer;

[0036] The first conductive layer on which the plurality of first traces are formed is subjected to annealing treatment;

[0037] A second conductive layer is deposited on the side of the annealed first conductive layer away from the substrate, and the material of the second conductive layer is different from the material of the annealed first conductive layer.

[0038] A second photoresist is coated on the side of the second conductive layer away from the substrate, and the second photoresist is exposed and developed to form a region where the second photoresist is completely removed in the region corresponding to the first trace, and a region where the second photoresist is retained in the region between adjacent first traces, so as to form a patterned second photoresist layer.

[0039] Using the second photoresist layer as a mask, the second etching material is used to etch the second conductive layer, forming a second trace between each adjacent first trace.

[0040] Optionally, in the manufacturing method provided in the embodiments of this disclosure, the display substrate includes a display area and a border area. The display area includes a first display area and a second display area, and the light transmittance of the first display area is greater than that of the second display area. The first display area includes a plurality of sub-pixels arranged in an array. Each sub-pixel includes a light-emitting device and a pixel circuit. The pixel circuit is located in the border area adjacent to the first display area. Alternatively, the second display area has a transition area adjacent to the first display area, and the pixel circuit is located in the transition area. Or, the pixel circuit is distributed within the second display area. The wiring area is at least partially located in the first display area, and the wiring layer is located between the anode of the light-emitting device and the pixel circuit. The first wiring is used to electrically connect the corresponding light-emitting device and the pixel circuit, and the second wiring is used to electrically connect the corresponding anode of the light-emitting device and the pixel circuit.

[0041] The material of the first conductive layer after annealing is p-ITO, and the material of the second conductive layer is a-ITO; wherein, the p-ITO is annealed at high temperature, the a-ITO is annealed at room temperature, the grain size of the p-ITO is larger than that of the a-ITO, the grain boundaries of the p-ITO are fewer than those of the a-ITO, and the resistance of the p-ITO is less than that of the a-ITO.

[0042] Optionally, in the manufacturing method provided in the embodiments of this disclosure, a display area and a border area are included. The display area includes multiple signal lines, and the border area includes the wiring area. The first wiring is used to electrically connect the corresponding signal lines, and the second wiring is used to electrically connect the corresponding signal lines.

[0043] The material of the second conductive layer is the same metallic material as the material of the first conductive layer before annealing.

[0044] Optionally, in the manufacturing method provided in the embodiments of this disclosure, different patterning processes are used to pattern the first and second traces that are spaced apart in the trace area corresponding to each trace layer, specifically including:

[0045] A first conductive layer is deposited in the wiring area of ​​the substrate;

[0046] A first photoresist is coated on the side of the first conductive layer away from the substrate, and the first photoresist is exposed and developed to form a patterned first photoresist layer.

[0047] Using the first photoresist layer as a mask, the first conductive layer is etched with a second etching material to form multiple first traces spaced apart on the first conductive layer;

[0048] A second conductive layer is deposited on the side of the first conductive layer on which the plurality of first traces are formed, away from the substrate, and the material of the second conductive layer is different from that of the first conductive layer.

[0049] A second photoresist is coated on the side of the second conductive layer away from the substrate, and the second photoresist is exposed and developed to form a region where the second photoresist is completely removed in the region corresponding to the first trace, and a region where the second photoresist is retained in the region between adjacent first traces, so as to form a patterned second photoresist layer.

[0050] Using the second photoresist layer as a mask, the second conductive layer is etched with the first etching material to form a second trace between each adjacent first trace; the second etching material is different from the first etching material.

[0051] Optionally, in the manufacturing method provided in the embodiments of this disclosure, different patterning processes are used to pattern the first and second traces that are spaced apart in the trace area corresponding to each trace layer, specifically including:

[0052] A first conductive layer is deposited in the wiring area of ​​the substrate;

[0053] A second conductive layer is deposited on the side of the first conductive layer opposite to the substrate; the material of the second conductive layer is different from the material of the first conductive layer.

[0054] A first photoresist is coated on the side of the second conductive layer away from the substrate, and the first photoresist is exposed and developed to form alternating areas where the first photoresist is completely removed and areas where the first photoresist is retained, thereby forming a patterned first photoresist layer.

[0055] Using the first photoresist layer as a mask, the second conductive layer is etched with the first etching material to form multiple second sub-traces spaced apart on the second conductive layer;

[0056] A second photoresist is deposited on the side of the second conductive layer on which the plurality of second sub-lines are formed, away from the substrate, and the second photoresist is exposed and developed. A second photoresist completely removed area is formed in the area corresponding to the second sub-lines, and a second photoresist retained area is formed in the area corresponding to adjacent second sub-lines. The second photoresist retained area and the second sub-lines have a preset gap to form a patterned second photoresist layer.

[0057] Using the second photoresist layer as a mask, the first conductive layer is etched with a second etching material to form a first trace located between each adjacent second sub-trace, and a first sub-trace located below the second sub-trace. The first sub-trace and the second sub-trace constitute the second trace. The second etching material is different from the first etching material.

[0058] Optionally, in the manufacturing method provided in the embodiments of this disclosure, the display substrate includes a display area and a border area. The display area includes a first display area and a second display area, and the light transmittance of the first display area is greater than that of the second display area. The first display area includes a plurality of sub-pixels arranged in an array. Each sub-pixel includes a light-emitting device and a pixel circuit. The pixel circuit is located in the border area adjacent to the first display area. Alternatively, the second display area has a transition area adjacent to the first display area, and the pixel circuit is located in the transition area. Or, the pixel circuit is distributed within the second display area. The wiring area is at least partially located in the first display area, and the wiring layer is located between the anode of the light-emitting device and the pixel circuit. The first wiring is used to electrically connect the anode of the corresponding light-emitting device and the pixel circuit, and the second wiring is used to electrically connect the corresponding light-emitting device and the pixel circuit.

[0059] The first conductive layer is made of a-ITO, and the second conductive layer is made of at least one of doped a-Si, IZO, and IGZO.

[0060] Optionally, in the manufacturing method provided in the embodiments of this disclosure, the display substrate includes a display area and a border area, the display area includes multiple signal lines, and the border area includes the wiring area; the first wiring is used to electrically connect to the corresponding signal lines, and the second wiring is used to electrically connect to the corresponding signal lines; wherein...

[0061] The materials of the first conductive layer and the second conductive layer are different metallic materials.

[0062] Optionally, the manufacturing method provided in the embodiments of this disclosure further includes:

[0063] A planarization layer is deposited on the side of the wiring layer opposite to the substrate;

[0064] The planarization layer is patterned to form first vias corresponding to the first trace and the second trace, respectively.

[0065] Multiple anodes are formed on the side of the planar layer where the first via is formed, away from the substrate, and each anode is electrically connected to the first trace or the second trace through the corresponding first via.

[0066] Optionally, in the above-described fabrication method provided in the embodiments of this disclosure, the first etching material includes nitric acid.

[0067] Optionally, in the above-described fabrication method provided in the embodiments of this disclosure, the second etching material includes oxalic acid.

[0068] On the other hand, embodiments of this disclosure also provide a display device, including the display substrate described in any of the above claims. Attached Figure Description

[0069] Figure 1 This is a top view of a display substrate provided in an embodiment of the present disclosure;

[0070] Figure 2 This is a schematic diagram of the line width and spacing of the wiring layer fabricated using photoresist technology in related technologies.

[0071] Figure 3 This is a schematic diagram of the structure of a display substrate provided in related technologies;

[0072] Figure 4 This is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure;

[0073] Figure 5 This is a schematic diagram of the structure of another display substrate provided in an embodiment of the present disclosure;

[0074] Figure 6 This is a schematic diagram of the structure of another display substrate provided in an embodiment of the present disclosure;

[0075] Figure 7 A top view of another display substrate provided in an embodiment of this disclosure;

[0076] Figure 8 This is a schematic diagram of the structure of another display substrate provided in an embodiment of the present disclosure;

[0077] Figure 9 This is a schematic diagram of the structure of another display substrate provided in an embodiment of the present disclosure;

[0078] Figure 10 A top view schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0079] Figure 11 This is a top view of the first and second traces in the prior art;

[0080] Figure 12 This is a schematic diagram of the structure of the first and second traces provided in an embodiment of the present disclosure;

[0081] Figure 13 for Figure 12Top view of the first and second routing lines shown;

[0082] Figure 14A A schematic diagram of the structure of the first and second traces provided in the prior art;

[0083] Figure 14B for Figure 14A A schematic diagram of the territory;

[0084] Figure 15A This is a schematic diagram of the structure of the first and second traces provided in an embodiment of the present disclosure;

[0085] Figure 15B for Figure 15A A schematic diagram of the territory;

[0086] Figure 16 A schematic flowchart illustrating a method for manufacturing a display substrate according to an embodiment of this disclosure;

[0087] Figures 17A-17H To make Figure 4 The diagram shows a cross-sectional view of the display substrate after each step is performed.

[0088] Figures 18A-18G To make Figure 5 The diagram shows a cross-sectional view of the display substrate after each step is performed.

[0089] Figures 19A-19G To make Figure 6 The diagram shows a cross-sectional view of the display substrate after each step. Detailed Implementation

[0090] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0091] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "comprising" or "including," and similar terms as used in this disclosure, mean that an element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0092] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0093] In related technologies, such as Figure 1 As shown, under-display camera technology typically sets up a first display area AA1 and a second display area AA2 within the display area AA. The second display area AA2 occupies the majority of the display area, while the first display area AA1 occupies a smaller portion. The first display area AA1 is where the under-display camera is placed. An under-display camera means that the front-facing camera is located below the screen but does not affect the screen's display function. When the front-facing camera is not in use, the screen above the camera can still display images normally. Therefore, from an appearance perspective, there are no camera holes, truly achieving a full-screen display effect. However, in current under-display camera designs, the pixel circuitry of the first display area AA1 is placed in the bezel area BB above the first display area AA1 or in the second display area AA2 adjacent to the first display area AA1. Taking the pixel circuitry in the bezel area BB above the first display area AA1 as an example, the pixel circuitry is connected to the light-emitting devices within the first display area AA1 via ITO traces 100, thereby transmitting the surrounding pixel signals to the under-display camera area. Figure 2 As shown, Figure 2 This diagram illustrates the routing of ITO traces within the same layer. ITO traces are formed using a photoresist exposure, development, and etching process. Due to the minimum exposure distance and minimum exposure linewidth requirements of photoresist, ITO traces within the same layer have minimum linewidth and spacing. Currently, the general limits in manufacturing are approximately 2µm (and above) for both width and space, thus restricting the number of ITO traces within the same layer. When there are many light-emitting devices in the first display area AA1 (under-display camera area), multi-layer ITO traces are required, such as... Figure 3 As shown, Figure 3Taking the connection of pixel circuit and light-emitting device using 4-layer ITO traces as an example, the 4-layer ITO traces are shown as 10, 20, 30 and 40 respectively. Each layer of ITO requires an organic layer (planarization layer) to cover it, that is, four planarization layers (50, 60, 70 and 80) are required. The four planarization layers (50, 60, 70 and 80) need to be patterned to form vias corresponding to the anode 90 of the light-emitting device. The number of masks required for this patterning is large, resulting in long process time and high cost, which makes it difficult to apply to actual mass production.

[0094] To address the problem in existing technologies where the number of ITO traces on the same layer is limited, necessitating the use of multi-layer ITO traces, resulting in a large number of masks and high costs, this disclosure provides a display substrate, such as... Figures 4-6 As shown, it includes:

[0095] Base 1, with a routing area, Figures 4-6 Only the wiring area is shown in the diagram;

[0096] At least one routing layer 2 is located on the substrate 1. The routing layer 2 includes multiple first routing lines 21 and second routing lines 22 arranged at intervals using different patterning processes in the routing area. At least some of the first routing lines 21 and second routing lines 22 are arranged adjacent to each other, and the distance d between the adjacent first routing lines 21 and second routing lines 22 is less than 2um.

[0097] The display substrate provided in this embodiment uses different patterning processes to obtain spaced first traces 21 and second traces 22 on the same trace layer. In this way, the first traces 21 and second traces 22 formed by the two patterning processes can be wired on the same layer (i.e., the first traces 21 and second traces 22 are made on the same film layer), thereby reducing the distance between traces. The distance between adjacent first traces 21 and second traces can be less than 2µm, allowing more traces to be laid in the same wiring space. Therefore, for the same number of traces, this disclosure can reduce the number of trace layers, thereby reducing the number of planarization layers above the trace layers, thus reducing the number of patterning masks, reducing manufacturing costs, shortening the investment time, and also achieving a narrower bezel.

[0098] In specific implementation, in the display substrate provided in the embodiments of this disclosure, such as Figures 4-6 As shown, at least one routing layer 2 ( Figures 4-6The first trace 21 and the second trace 22 of the wiring layer 2 are shown to be alternately arranged. In this way, the first trace 21 with intervals can be formed on the substrate 1 by a single patterning process, and then the second trace 22 can be formed between each adjacent first trace 21 by a second patterning process. This allows more traces to be arranged in the same wiring layer (i.e., more first traces 21 and second traces 22 to be made in the same film layer).

[0099] In specific implementation, in the display substrate provided in the embodiments of this disclosure, such as Figure 1 and Figure 7 As shown, it includes a display area AA and a border area BB. The display area AA includes a first display area AA1 and a second display area AA2. The light transmittance of the first display area AA1 is greater than that of the second display area AA2.

[0100] The first display area AA1 includes multiple sub-pixels (not shown) arranged in an array. Each sub-pixel includes a light-emitting device and a pixel circuit (not shown), such as... Figure 1 As shown, the pixel circuit can be located within the border area BB adjacent to the first display area AA1, or, as... Figure 7 As shown, the second display area AA2 has a transition area CC adjacent to the first display area AA1. The pixel circuit can be located in the transition area CC, or the pixel circuit can be distributed in the second display area AA2.

[0101] like Figure 1 and Figure 7 As shown, Figure 4 The routing area shown is at least partially located in the first display area AA1; as Figure 8 As shown, the wiring layer 2 is located between the anode 3 of the light-emitting device and the pixel circuit 4, and the wiring layer 2 and the pixel circuit 4 are electrically connected; the pixel circuit 4 may be, but is not limited to, a 7T1C structure including 7 transistors and a capacitor, and the pixel circuit 4 includes a gate line layer and a source / drain electrode layer, and the wiring layer 2 and the gate line layer and / or source / drain electrode layer of the pixel circuit 4 are electrically connected.

[0102] like Figure 8 As shown, the first trace 21 is used to electrically connect the anode 3 of the corresponding light-emitting device and the pixel circuit 4, and the second trace 22 is used to electrically connect the anode 3 of the corresponding light-emitting device and the pixel circuit 4.

[0103] In specific implementation, in the display substrate provided in the embodiments of this disclosure, such as Figure 8 As shown, it also includes a first planarization layer 5 located between the pixel circuit 4 and the wiring layer 2. The first planarization layer 5 has a plurality of vias 51 corresponding to the first wiring 21 and a plurality of vias 52 corresponding to the second wiring 22. It also includes a second planarization layer 6 located between the wiring layer 2 and the anode 3. The second planarization layer 6 has a plurality of vias 61 corresponding to the anode 3.

[0104] The first trace 21 is electrically connected to the pixel circuit 4 through the corresponding via 51, the second trace 22 is electrically connected to the pixel circuit 4 through the corresponding via 52, and each anode 3 is electrically connected to the first trace 21 and the second trace 22 through the corresponding via 61.

[0105] In specific implementations, indium tin oxide (ITO) materials can be classified into crystalline and amorphous types: crystalline ITO (hereinafter referred to as "p-ITO") and amorphous ITO (hereinafter referred to as "a-ITO"). p-ITO and a-ITO can be etched using different etching materials to form corresponding traces. Therefore, in the display substrate provided in the embodiments of this disclosure, such as... Figure 4 As shown, the material of the first trace 21 can be p-ITO, and the material of the second trace 22 can be a-ITO; wherein, the grain size of p-ITO is larger than that of a-ITO, the grain boundaries of p-ITO are fewer than those of a-ITO, and the resistivity of p-ITO is less than that of a-ITO. Specifically, a-ITO is obtained by annealing ITO material at room temperature, and p-ITO is obtained by annealing a-ITO at a high temperature. The high-temperature annealing temperature can be 160℃-200℃, for example, 160℃, 170℃, 180℃, 190℃, or 200℃; the room-temperature annealing temperature can be 50℃-70℃, for example, 50℃, 60℃, or 70℃. Since p-ITO can be obtained by annealing a-ITO at a high temperature (e.g., 180℃), this disclosure can be applied to substrate 1. A layer of a-ITO is deposited, etched, and then the etched a-ITO is subjected to high-temperature annealing to form a first trace 21 made of p-ITO. Then, another layer of a-ITO is deposited on top of the first trace 21 to create a second trace 22. Since a-ITO and p-ITO use different etching materials, when etching the a-ITO above the first trace 21, the first trace 21 is not etched, thus allowing the formation of a second trace 22 made of a-ITO between the first traces 21. Therefore, this embodiment of the present disclosure can obtain spaced first traces 21 and second traces 22 on the same trace layer using different patterning processes. This allows the first traces 21 and second traces 22 formed by the two patterning processes to be routed on the same layer, enabling more traces to be routed in the same wiring space, reducing the number of patterns (masks), lowering manufacturing costs, shortening the investment time, and achieving narrower bezels.

[0106] In specific implementation, in the display substrate provided in the embodiments of this disclosure, such as Figure 5As shown, the material of the first trace 21 can be a-ITO, and the material of the second trace 22 can include at least one of doped a-Si, IZO, and IGZO. Thus, in this embodiment of the present disclosure, an a-ITO layer can be deposited on the substrate 1, and the a-ITO can be etched to form the first trace 21 made of a-ITO. Then, a film layer made of doped a-Si, IZO, or IGZO is deposited on the first trace 21 to fabricate the second trace 22. Since the etching materials used for a-ITO and doped a-Si, IZO, and IGZO are different, when the doped a-Si, IZO, or IGZO above the first trace 21 is etched, the first trace 21 made of a-ITO will not be etched, thereby forming the second trace 22 made of doped a-Si, IZO, or IGZO between the first traces 21. Therefore, in this embodiment of the present disclosure, first traces 21 and second traces 22 are spaced apart on the same trace layer through different patterning processes. In this way, the first traces 21 and second traces 22 formed by the two patterning processes can be routed on the same layer, so that more lines can be routed in the same routing space, reducing the number of pattern masks, reducing manufacturing costs, shortening investment time, and also achieving narrower bezels.

[0107] In specific implementation, in the display substrate provided in the embodiments of this disclosure, such as Figure 6As shown, the material of the first trace 21 can be a-ITO, and the second trace 22 includes a first sub-trace 221 disposed on the substrate 1 and a second sub-trace 222 disposed on the side of the first sub-trace 221 away from the substrate 1. The patterns of the first sub-trace 221 and the second sub-trace 222 are consistent and substantially overlap. The material of the first sub-trace 221 can be a-ITO, and the material of the second sub-trace 222 can include at least one of doped a-Si, IZO, and IGZO. This allows for the deposition of an a-ITO film on substrate 1, followed by the deposition of a doped a-Si, IZO, or IGZO film (e.g., doped a-Si) film on top of the a-ITO film. The doped a-Si film is etched first. Since the etching materials used for a-ITO and doped a-Si are different, the a-ITO film below is not etched when the doped a-Si film is etched. This allows for the formation of a second sub-line 222 made of doped a-Si above the a-ITO film. Then, the a-ITO film is etched using an etching material different from that used for doping a-Si, forming a first sub-line 221 below the second sub-line 222 and a first line 21 between adjacent first sub-lines 221. Therefore, in this embodiment of the present disclosure, first traces 21 and second traces 22 are spaced apart on the same trace layer through different patterning processes. In this way, the first traces 21 and second traces 22 formed by the two patterning processes can be routed on the same layer, so that more lines can be routed in the same routing space, reducing the number of pattern masks, reducing manufacturing costs, shortening investment time, and also achieving narrower bezels.

[0108] It should be noted that, Figures 4-6 The distance d between adjacent first trace 21 and second trace 22, as well as the line width of the first trace 21 and second trace 22, are only schematic illustrations and do not represent actual dimensions.

[0109] It should be noted that, Figure 8 This illustration uses a single routing layer 2 as an example. However, in practice, when a single routing layer cannot accommodate a large number of traces, the number of routing layers 2 can be two or more, with insulation between each layer. For example, as... Figure 9 As shown, Figure 9Taking a two-layer wiring layer 2 as an example, a first planarization layer 5 is provided between the first wiring layer 2 and the pixel circuit 4 (drain), a third planarization layer 7 is provided between the first wiring layer 2 and the second wiring layer 2, and a second planarization layer 6 is provided between the second wiring layer 2 and the anode 3. The first trace 21 and the second trace 22 in the first wiring layer 2 are electrically connected to the pixel circuit 4 through vias penetrating the first planarization layer 5, respectively. The first trace 21 and the second trace 22 in the second wiring layer 2 are electrically connected to the pixel circuit 4 through vias penetrating the third planarization layer 7 and the first planarization layer 5, respectively. Part of the anode 3 is electrically connected to the first trace 21 and the second trace 22 in the first wiring layer 2 through vias penetrating the second planarization layer 6 and the third planarization layer 7, respectively. Another part of the anode 3 is electrically connected to the first trace 21 and the second trace 22 in the second wiring layer 2 through vias penetrating the second planarization layer 6, respectively. This embodiment of the present disclosure Figure 12 The wiring method and existing technology Figure 3 Compared to the routing method shown, more traces can be arranged on the same routing layer in this embodiment of the present disclosure, that is, more traces can be arranged in the same routing space. Therefore, for the same number of traces, this disclosure can reduce the number of routing layers, which can reduce the number of flat layers above the routing layers, thereby reducing the number of masks in the pattern, reducing manufacturing costs, shortening investment time, and also achieving a narrower bezel.

[0110] It should be noted that, Figure 12 The illustration is based on a 2-layer routing layer 2. When more routing layers 2 are used, a planarization layer is set above each routing layer 2. The first routing layer 21 and the second routing layer 22 of each subsequent layer are electrically connected to the pixel circuit through vias that penetrate the corresponding planarization layer. The anode 3 is electrically connected to the first routing layer 21 and the second routing layer 22 through vias that penetrate the corresponding planarization layer.

[0111] In specific implementation, in the display substrate provided in the embodiments of this disclosure, such as Figure 9 As shown, the orthographic projections of each routing layer 2 on the substrate 1 can be distributed independently, which facilitates fabrication.

[0112] In specific implementation, in the display substrate provided in the embodiments of this disclosure, Figures 4-6 The wiring area shown applies not only to the under-display camera area but also to the fan-shaped area (the fan-shaped area is used to connect the signal lines of the display area AA, such as data lines, to an external driver chip for signal transmission), such as... Figure 10 As shown, the display substrate includes a display area AA and a bezel area BB. The display area AA includes multiple signal lines (e.g., data lines S1, S2, S3, etc.), and the bezel area BB includes... Figures 4-6 The routing area shown (this routing area is the sector area DD);

[0113] The first trace 21 is used to electrically connect the corresponding signal lines (e.g., data lines S1, S2...Sn), and the second trace 22 is used to electrically connect the corresponding signal lines (e.g., data lines Sn, S(n+1)...).

[0114] In specific implementation, in the display substrate provided in the embodiments of this disclosure, such as Figure 10 As shown, the first wiring layer 2 includes a gate metal layer and a source / drain metal layer sequentially formed on the substrate 1, and the wiring layer 2 can be located on the gate metal layer and / or the source / drain metal layer. Thus, by simply changing the original pattern when forming the gate metal layer or the source / drain metal layer, the pattern of the first wiring layer 2 and the gate metal layer or the source / drain metal layer can be formed in a single patterning process, eliminating the need for a separate process to fabricate the first wiring layer 2. This simplifies the fabrication process, saves production costs, and improves production efficiency.

[0115] In specific implementation, in the display substrate provided in the embodiments of this disclosure, such as Figures 4-6 As shown, the distance d between adjacent first traces 21 and second traces 22 can be 0.15um-0.35um, and further can be 0.18um, 0.2um, 0.25um, or 0.3um. The linewidths of the first traces 21 and second traces 22 can be adjusted according to actual needs, and further, the linewidth of the first trace 21 can be less than or equal to 2um, and the linewidth of the second trace 22 can be less than or equal to 2um. This allows for more traces to be arranged on the same wiring layer, thereby reducing the number of masks, lowering costs, shortening investment time, and achieving narrower bezels. Taking a 200um wiring space as an example, in existing technologies using photoresist processes, the width and spacing of the traces are 2um / 2um, respectively. Figure 11 As shown, Figure 11 This is a top view of a routing layer in the prior art, where only 50 traces (21' and 22') can be arranged in one layer; however, the solution of this disclosure can further reduce the line width / spacing, such as... Figure 12 and Figure 13 As shown, Figure 12 This is a cross-sectional schematic diagram of a single wiring layer in this disclosure. Figure 13 for Figure 12 The top view diagram shows that, taking the line width of the first trace 21 and the second trace 22 as 1.9um and the distance d between adjacent first trace 21 and second trace 22 as 0.35um, then 89 traces can be arranged in a 200um wiring space, thereby reducing the number of wiring layers, saving the number of masks in the flat layer, and reducing costs.

[0116] Furthermore, in areas where the required number of traces is met, the linewidths of the first trace 21 and / or the second trace 22 can be set to different widths in different areas. Some of the first traces 21 and / or the second trace 22 have linewidths less than or equal to 2µm, while some have linewidths greater than 2µm. This is to adjust the resistance and load of the first traces 21 and / or the second traces.

[0117] Furthermore, in specific implementation, such as Figures 14A-15B As shown, Figure 14A This is a schematic cross-sectional view of a two-layer wiring fabrication process using photoresist in existing technology. Figure 14B for Figure 14A A schematic diagram of the layout. Figure 15A This is a cross-sectional schematic diagram of the two wiring layers fabricated using photoresist technology in this disclosure. Figure 15B for Figure 15A The layout diagram shows that the line widths of the first trace 21 and the second trace 22, as well as the spacing between the first trace 21 and the second trace 22, in this embodiment can be made smaller than in the prior art. Therefore, when the same number of traces is made in this embodiment and the prior art, this embodiment can arrange more traces in the same wiring space (the same wiring layer). For example, this embodiment only needs one wiring layer to arrange all the traces, while the number of traces arranged in the same wiring layer in the prior art is less than that in this embodiment, so at least two wiring layers are required. Therefore, this embodiment can reduce the number of wiring layers, save the number of masks on the flat layer, and reduce costs.

[0118] Based on the same inventive concept, this disclosure also provides a method for manufacturing any of the above-mentioned display substrates, such as... Figure 16 As shown, it includes:

[0119] S1601, Provides a substrate; the substrate has a wiring area;

[0120] S1602. At least one routing layer is formed in the routing area of ​​the substrate, and different patterning processes are used to pattern the routing area corresponding to each routing layer to obtain a first routing line and a second routing line that are spaced apart; wherein at least a portion of the first routing lines and the second routing lines are arranged adjacent to each other, and the distance between the adjacent first routing lines and the second routing lines is less than 2um.

[0121] The following is about Figure 4 The manufacturing method of the display substrate shown is described in detail, and may specifically include the following steps:

[0122] (1) Deposit a first conductive layer 2' in the wiring area of ​​substrate 1, such as Figure 17A As shown; when Figure 4When the wiring area shown is located in the under-display camera area, the material of the first conductive layer 2' is a transparent conductive material, such as a-ITO; when Figure 4 When the trace area shown is located in the fan-shaped area of ​​the border area, the material of the first conductive layer 2' is a metallic material, such as Ag, Al, etc.

[0123] (2) Figure 17B As shown, a first photoresist is coated on the side of the first conductive layer 2' away from the substrate 1, and the first photoresist is exposed and developed to form a patterned first photoresist layer. Using the first photoresist layer as a mask, a second etching material (e.g., oxalic acid) is used to etch the first conductive layer 2' (e.g., a-ITO) to form multiple first traces 21 (before annealing) spaced apart on the first conductive layer 2'.

[0124] (3) Annealing is performed on the first conductive layer 2', which forms multiple first traces 21, such as... Figure 17C As shown, multiple first traces 21 (after annealing) are obtained.

[0125] (4) A second conductive layer 2” is deposited on the side of the annealed first conductive layer away from the substrate 1. The material of the second conductive layer 2” is different from the material of the annealed first conductive layer 2’, such as Figure 17D As shown. For example, the material of the first conductive layer 2' after annealing is p-ITO, and the material of the second conductive layer 2” is a-ITO.

[0126] (5) A second photoresist is coated on the side of the second conductive layer 2” away from the substrate 1, and the second photoresist is exposed and developed. A region where the second photoresist is completely removed is formed in the area corresponding to the first trace 21, and a region where the second photoresist is retained is formed in the area between adjacent first traces 21, so as to form a patterned second photoresist layer. Then, using the second photoresist layer as a mask, the second conductive layer 2” (a-ITO) is etched using a second etching material (e.g., oxalic acid), and a second trace 22 is formed between each adjacent first trace 21, such as... Figure 17E As shown. Specifically, since the first trace 21 is made of annealed material (e.g., p-ITO), while the material of the second conductive layer 2” is a-ITO, and since the etching materials of a-ITO and p-ITO are different, when the second conductive layer 2” is etched with the second etching material, the annealed first trace 21 will not be etched.

[0127] (6) Figure 17F As shown, a planarization layer 6 is deposited on the side of the routing layer 2 facing away from the substrate 1; the planarization layer 6 is patterned to form first vias 61 corresponding to the first routing line 21 and the second routing line 22, respectively, as shown. Figure 17GAs shown; a plurality of anodes 3 are formed on the side of the planar layer 6 opposite to the substrate 1 where the first via 61 is formed. Each anode 3 is electrically connected to the first trace 21 or the second trace 22 through the corresponding first via 61, such as... Figure 17H As shown.

[0128] It should be noted that the above-mentioned products obtained using steps (1)-(6) Figure 4 The display substrate shown is formed by etching the first conductive layer 2' (e.g., a-ITO) with a second etching material (nitric acid) followed by annealing. Alternatively, the first conductive layer 2' can be annealed first, and then a first photoresist can be coated on the side of the annealed first conductive layer (p-ITO) away from the substrate 1. The first photoresist is then exposed and developed to form a patterned first photoresist layer. Next, using the first photoresist layer as a mask, the annealed first conductive layer (p-ITO) is etched with a first etching material (oxalic acid) to form multiple spaced first traces 21 (p-ITO) on the annealed first conductive layer. Then, the multiple first traces 21 are etched... 1. A second conductive layer (a-ITO) is deposited on the side away from the substrate. The material of the second conductive layer (a-ITO) is the same as that of the first conductive layer (a-ITO) before annealing. Then, a second photoresist is coated on the side of the second conductive layer away from the substrate, and the second photoresist is exposed and developed to form a region where the second photoresist is completely removed in the area corresponding to the first trace, and a region where the second photoresist is retained in the area between adjacent first traces to form a patterned second photoresist layer. Then, using the second photoresist layer as a mask, the second conductive layer (a-ITO) is etched with a second etching material (oxalic acid) to form second traces between each adjacent first trace.

[0129] In specific implementation, in the above-described display substrate manufacturing method provided in the embodiments of this disclosure, such as Figure 1 and Figure 7 As shown, the display substrate may include a display area AA and a border area BB. The display area AA includes a first display area AA1 and a second display area AA2. The light transmittance of the first display area AA1 is greater than that of the second display area AA2. The first display area AA1 includes a plurality of sub-pixels (not shown) arranged in an array. Each sub-pixel includes a light-emitting device and a pixel circuit (not shown), such as... Figure 1 As shown, the pixel circuit can be located within the border area BB adjacent to the first display area AA1, or, as... Figure 7 As shown, the second display area AA2 has a transition area CC adjacent to the first display area AA1. The pixel circuits can be located within the transition area CC, or the pixel circuits can be distributed within the second display area AA2; as shown. Figure 1 and Figure 7 As shown, Figure 4 The routing area shown is at least partially located in the first display area AA1; as Figure 8As shown, the wiring layer 2 is located between the anode 3 of the light-emitting device and the pixel circuit 4; the first wiring 21 is used to electrically connect the anode and pixel circuit of the corresponding light-emitting device, and the second wiring 22 is used to electrically connect the anode and pixel circuit of the corresponding light-emitting device; wherein,

[0130] use Figures 17A-17H The steps shown are used to obtain Figure 4 The display substrate shown has a first conductive layer 2' made of p-ITO after annealing, and a second conductive layer 2" made of a-ITO. The p-ITO is annealed at high temperature, while the a-ITO is annealed at room temperature. The p-ITO grains are larger than the a-ITO grains, the p-ITO grain boundaries are fewer than the a-ITO grain boundaries, and the p-ITO resistance is lower than the a-ITO resistance. Specifically, p-ITO can be obtained by annealing a-ITO at high temperature.

[0131] In specific implementation, in the above-described display substrate manufacturing method provided in the embodiments of this disclosure, such as Figure 10 As shown, it includes a display area AA and a border area BB. The display area AA includes multiple signal lines (e.g., data lines S1, S2...Sn), and the border area BB includes... Figure 4 The routing area shown (this routing area is the sector area DD);

[0132] The first trace 21 is used to electrically connect the corresponding signal lines (e.g., data lines S1, S2...Sn), and the second trace 22 is used to electrically connect the corresponding signal lines (e.g., data lines Sn, S(n+1)...).

[0133] use Figures 17A-17H The steps shown are used to obtain Figure 4 The material of the second conductive layer 2” and the material of the first conductive layer 2’ before annealing can be the same metal material in the display substrate shown. By selecting metal materials etched with different etching materials before and after annealing, the first and second traces can be fabricated, thereby forming alternating first and second traces on the same trace layer.

[0134] The following is about Figure 5 The manufacturing method of the display substrate shown is described in detail, and may specifically include the following steps:

[0135] (1) Deposit a first conductive layer 2' in the wiring area of ​​substrate 1, such as Figure 18A As shown; when Figure 5 When the wiring area shown is located in the under-display camera area, the material of the first conductive layer 2' is a transparent conductive material, such as a-ITO; when Figure 5 When the trace area shown is located in the fan-shaped area of ​​the border area, the material of the first conductive layer 2' is a metallic material, such as Ag, Al, etc.

[0136] (2) A first photoresist is coated on the side of the first conductive layer 2' facing away from the substrate 1, and the first photoresist is exposed and developed to form a patterned first photoresist layer 10, such as... Figure 18B As shown.

[0137] (3) Using the first photoresist layer 10 as a mask, the first conductive layer 2' (a-ITO) is etched with a second etching material (e.g., oxalic acid) to form multiple spaced first traces 21 in the first conductive layer 2', such as... Figure 18C As shown.

[0138] (4) A second conductive layer 2” is deposited on the side of the first conductive layer 2’ with multiple first traces 21 facing away from the substrate 1. The material of the second conductive layer 2” is different from that of the first conductive layer 2’, such as Figure 18D As shown. For example, the material of the first conductive layer 2' is a-ITO, and the material of the second conductive layer 2" is doped a-Si.

[0139] (5) A second photoresist is coated on the side of the second conductive layer 2” facing away from the substrate 1, and the second photoresist is exposed and developed. A region where the second photoresist is completely removed is formed in the area corresponding to the first trace 21, and a region where the second photoresist is retained is formed in the area between adjacent first traces 21, so as to form a patterned second photoresist layer 20, such as... Figure 18E As shown.

[0140] (6) Next, using the second photoresist layer 20 as a mask, the second conductive layer 2" (a-ITO) is etched with a first etching material (e.g., nitric acid) to form second traces 22 between adjacent first traces 21. The second etching material (oxalic acid) is different from the first etching material (nitric acid), such as... Figure 18F As shown.

[0141] (7) Next, a planarization layer 6 is deposited on the side of the routing layer 2 facing away from the substrate 1. The planarization layer 6 is patterned to form first vias 61 corresponding to the first routing line 21 and the second routing line 22, respectively. Multiple anodes 3 are formed on the side of the planarization layer 6 with the first vias 61 facing away from the substrate 1. Each anode 3 is electrically connected to the first routing line 21 or the second routing line 22 through the corresponding first via 61, such as... Figure 18G As shown.

[0142] The following is about Figure 6 The manufacturing method of the display substrate shown is described in detail, and may specifically include the following steps:

[0143] (1) Deposit a first conductive layer 2' in the wiring area of ​​substrate 1, such as Figure 19A As shown; when Figure 6 When the wiring area shown is located in the under-display camera area, the material of the first conductive layer 2' is a transparent conductive material, such as a-ITO; when Figure 6 When the trace area shown is located in the fan-shaped area of ​​the border area, the material of the first conductive layer 2' is a metallic material, such as Ag, Al, etc.

[0144] (2) A second conductive layer 2” is deposited on the side of the first conductive layer 2’ away from the substrate 1; the material of the second conductive layer 2” (e.g., a-Si) is different from the material of the first conductive layer 2’ (a-ITO), such as Figure 19B As shown.

[0145] (3) A first photoresist is coated on the side of the second conductive layer 2” away from the substrate 1, and the first photoresist is exposed and developed to form alternating areas where the first photoresist is completely removed and areas where the first photoresist is retained, thereby forming a patterned first photoresist layer 10, such as... Figure 19C As shown.

[0146] (4) Using the first photoresist layer 10 as a mask, the second conductive layer 2”” is etched with a first etching material (e.g., nitric acid) to form multiple second sub-traces 222 spaced apart in the second conductive layer 2”, such as Figure 19D As shown.

[0147] (5) A second photoresist is deposited on the side of the second conductive layer 2” with multiple second sub-lines 222 facing away from the substrate 1, and the second photoresist is exposed and developed. A region where the second photoresist is completely removed is formed in the area corresponding to the second sub-lines 222, and a region where the second photoresist is retained is formed in the area between adjacent second sub-lines 222. A preset gap exists between the region where the second photoresist is retained and the second sub-lines 222, so as to form a patterned second photoresist layer 20, such as... Figure 19E As shown.

[0148] (6) Using the second photoresist layer 20 as a mask, the first conductive layer 2' (a-ITO) is etched with a second etching material (e.g., oxalic acid). The second etching material (e.g., oxalic acid) is different from the first etching material (e.g., nitric acid). This forms a first trace 21 located between each adjacent second sub-trace 222, and a first sub-trace 221 located below the second sub-trace 222. The first sub-trace 221 and the second sub-trace 222 constitute the second trace 22. Figure 19F As shown.

[0149] (7) Next, a planarization layer 6 is deposited on the side of the routing layer 2 facing away from the substrate 1. The planarization layer 6 is patterned to form first vias 61 corresponding to the first routing line 21 and the second routing line 22, respectively. Multiple anodes 3 are formed on the side of the planarization layer 6 with the first vias 61 facing away from the substrate 1. Each anode 3 is electrically connected to the first routing line 21 or the second routing line 22 through the corresponding first via 61, such as... Figure 19G As shown.

[0150] In specific implementation, in the above-described display substrate manufacturing method provided in the embodiments of this disclosure, such as Figure 1 and Figure 7 As shown, the display substrate may include a display area AA and a border area BB. The display area AA includes a first display area AA1 and a second display area AA2. The light transmittance of the first display area AA1 is greater than that of the second display area AA2. The first display area AA1 includes a plurality of sub-pixels (not shown) arranged in an array. Each sub-pixel includes a light-emitting device and a pixel circuit (not shown), such as... Figure 1 As shown, the pixel circuit can be located within the border area BB adjacent to the first display area AA1, or, as... Figure 7 As shown, the second display area AA2 has a transition area CC adjacent to the first display area AA1. The pixel circuits can be located within the transition area CC, or the pixel circuits can be distributed within the second display area AA2; as shown. Figure 1 and Figure 7 As shown, Figure 4 The routing area shown is at least partially located in the first display area AA1; as Figure 8 As shown, the wiring layer 2 is located between the anode 3 of the light-emitting device and the pixel circuit 4; the first wiring 21 is used to electrically connect the anode and pixel circuit of the corresponding light-emitting device, and the second wiring 22 is used to electrically connect the anode and pixel circuit of the corresponding light-emitting device; wherein,

[0151] use Figures 18A-18G The steps shown are used to obtain Figure 5 The display substrate shown, and the one using Figures 19A-19G The steps shown are used to obtain Figure 6 The display substrate shown has a first conductive layer 2' made of a-ITO, and a second conductive layer 2" made of at least one of doped a-Si, IZO, and IGZO. Specifically, a-ITO can be etched with nitric acid, and a-Si, IZO, and IGZO can be etched with oxalic acid.

[0152] In specific implementation, in the above-described display substrate manufacturing method provided in the embodiments of this disclosure, such as Figure 10 As shown, it includes a display area AA and a border area BB. The display area AA includes multiple signal lines (e.g., data lines S1, S2...Sn), and the border area BB includes... Figure 4 The routing area shown (this routing area is the sector area DD);

[0153] The first trace 21 is used to electrically connect the corresponding signal lines (e.g., data lines S1, S2...Sn), and the second trace 22 is used to electrically connect the corresponding signal lines (e.g., data lines Sn, S(n+1)...).

[0154] use Figures 18A-18G The steps shown are used to obtain Figure 5 The display substrate shown, and the one using Figures 19A-19G The steps shown are used to obtain Figure 6 The display substrate shown can be made of different metal materials, specifically the first conductive layer 2' and the second conductive layer 2''. This allows for the selection of metal materials that can be etched using different etching materials to fabricate the first and second traces, thereby enabling the formation of alternating first and second traces on the same trace layer.

[0155] It should be noted that the first etching material is not limited to the nitric acid provided in the embodiments of this disclosure, and the second etching material is not limited to the oxalic acid provided in the embodiments of this disclosure, as long as the first etching material and the second etching material can respectively etch the first conductive layer and the second conductive layer.

[0156] It should be noted that wet etching can be used when using the first etching material and dry etching can be used when using the second etching material; or dry etching can be used when using the first etching material and wet etching can be used when using the second etching material.

[0157] It should be noted that the etching of the first conductive layer and the second conductive layer provided in the embodiments of this disclosure can be carried out using two different etching gases, and the etching processes do not affect each other; alternatively, dry etching and wet etching processes can be used to etch the two layers separately, so as to achieve the purpose of wiring the two layers on the same layer, but the etching of each other does not affect each other.

[0158] It should be noted that, in this disclosure, the shape of the first display area AA1 can be... Figure 1 and Figure 7 The circle shown can also be a rectangle, ellipse, polygon, or other shapes; the specific design can be tailored to actual needs and is not limited here. The second display area AA2 can be as follows... Figure 1 and Figure 7 The area shown is the periphery of the first display area AA1; it can also surround part of the first display area AA1, for example, the left, lower and right sides of the first display area AA1, while the upper boundary of the first display area AA1 coincides with the upper boundary of the second display area AA2.

[0159] Optionally, in the display substrate provided in the embodiments of this disclosure, such as Figure 1 and Figure 7 As shown, the first display area AA1 is configured to mount a photosensitive device, such as a camera module. Since only light-emitting devices exist in the first display area AA1 in this disclosure, a larger light-transmitting area can be provided, which helps to accommodate larger-sized camera modules.

[0160] Based on the same inventive concept, this disclosure also provides a display device, including the above-described display substrate.

[0161] In specific implementations, the aforementioned display device further includes a photosensitive device (e.g., a camera module), which is disposed in the first display area of ​​the display substrate. Optionally, the photosensitive device can be a camera module. The display device can be an electroluminescent display device or a photoluminescent display device. If the display device is an electroluminescent display device, it can be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device is a photoluminescent display device, it can be a quantum dot photoluminescent display device.

[0162] The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Other essential components of the display device are readily understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention. Furthermore, since the principle by which this display device solves the problem is similar to that of the display substrate described above, the implementation of this display device can refer to the embodiments of the display substrate described above, and repeated details will not be elaborated upon.

[0163] This disclosure provides a display substrate and its manufacturing method, as well as a display device. By employing different patterning processes, first and second traces are obtained at intervals on the same trace layer. In this way, the first and second traces formed by the two patterning processes can be wired on the same layer, thereby reducing the distance between the traces. This allows the distance between adjacent first and second traces to be less than 2µm, enabling more traces to be wired in the same wiring space. Therefore, for the same number of traces, this disclosure can reduce the number of trace layers, thereby reducing the number of planarization layers above the trace layers, thus reducing the number of patterning masks, lowering manufacturing costs, shortening investment time, and achieving narrower bezels.

[0164] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0165] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display substrate, wherein, include: The base has a wiring area; At least one routing layer is located on the substrate. The at least one routing layer includes multiple first and second routing lines spaced apart by different patterning processes in the routing area. At least some of the first and second routing lines are arranged adjacent to each other, and the distance between adjacent first and second routing lines is less than 2 μm. Wherein, the material of the first trace is p-ITO, and the material of the second trace is a-ITO; wherein, the grain size of the p-ITO is larger than that of the a-ITO, the grain boundaries of the p-ITO are fewer than those of the a-ITO, and the resistance of the p-ITO is less than that of the a-ITO. Alternatively, the material of the first trace is a-ITO, and the material of the second trace includes at least one of doped a-Si, IZO, and IGZO. Alternatively, the material of the first trace is a-ITO, and the second trace includes a first sub-trace disposed on the substrate and a second sub-trace disposed on the side of the first sub-trace away from the substrate. The patterns of the first sub-trace and the second sub-trace are consistent and substantially overlap. The material of the first sub-trace is a-ITO, and the material of the second sub-trace includes at least one of doped a-Si, IZO, and IGZO.

2. The display substrate as claimed in claim 1, wherein, The first trace and the second trace of at least one of the trace layers are arranged alternately at intervals.

3. The display substrate as described in claim 1, wherein, It includes a display area and a border area. The display area includes a first display area and a second display area. The light transmittance of the first display area is greater than that of the second display area. The first display area includes a plurality of sub-pixels arranged in an array. Each sub-pixel includes a light-emitting device and a pixel circuit. The pixel circuit is located in the border area adjacent to the first display area. Alternatively, the second display area has a transition area adjacent to the first display area, and the pixel circuit is located in the transition area. Or, the pixel circuit is distributed in the second display area. The wiring area is at least partially located in the first display area, and the wiring layer is located between the anode of the light-emitting device and the pixel circuit; The first trace is used to electrically connect the corresponding light-emitting device and the pixel circuit, and the second trace is used to electrically connect the corresponding light-emitting device and the pixel circuit.

4. The display substrate as described in claim 3, wherein, It also includes a planarization layer located on the side of the wiring layer opposite to the substrate, wherein the planarization layer has a first via at the position corresponding to each of the first wiring and the second wiring, and the anode of the light-emitting device is electrically connected to the first wiring and the second wiring through the corresponding first via.

5. The display substrate as claimed in claim 1, wherein, It includes a display area and a border area, wherein the display area includes multiple signal lines and the border area includes the wiring area; The first trace is used to electrically connect the corresponding signal line, and the second trace is used to electrically connect the corresponding signal line.

6. The display substrate as claimed in claim 5, wherein, It includes a gate metal layer and a source / drain metal layer sequentially formed on the substrate, and the wiring layer is located on the gate metal layer and / or the source / drain metal layer.

7. The display substrate as claimed in claim 1, wherein, The distance between the first and second traces that are set adjacently is 0.15um-0.35um, the line width of the first trace is less than or equal to 2um, and the line width of the second trace is less than or equal to 2um.

8. The display substrate as claimed in claim 1, wherein, The number of wiring layers is multiple, and each wiring layer is insulated from the others.

9. The display substrate as claimed in claim 8, wherein, Each of the aforementioned wiring layers has its orthographic projection on the substrate distributed independently.

10. A method for manufacturing a display substrate, wherein, include: Provide a base; The substrate has a wiring area; At least one routing layer is formed in the routing area of ​​the substrate, and different patterning processes are used to pattern first and second routing lines that are spaced apart in the routing area corresponding to each routing layer; wherein at least a portion of the first and second routing lines are arranged adjacent to each other, and the distance between the adjacent first and second routing lines is less than 2 μm. Wherein, the material of the first trace is p-ITO, and the material of the second trace is a-ITO; wherein, the grain size of the p-ITO is larger than that of the a-ITO, the grain boundaries of the p-ITO are fewer than those of the a-ITO, and the resistance of the p-ITO is less than that of the a-ITO. Alternatively, the material of the first trace is a-ITO, and the material of the second trace includes at least one of doped a-Si, IZO, and IGZO. Alternatively, the material of the first trace is a-ITO, and the second trace includes a first sub-trace disposed on the substrate and a second sub-trace disposed on the side of the first sub-trace away from the substrate. The patterns of the first sub-trace and the second sub-trace are consistent and substantially overlap. The material of the first sub-trace is a-ITO, and the material of the second sub-trace includes at least one of doped a-Si, IZO, and IGZO.

11. The manufacturing method as described in claim 10, wherein, Using different patterning techniques, patterning is performed in the routing area corresponding to each routing layer to obtain spaced first and second routing traces, specifically including: A first conductive layer is deposited in the wiring area of ​​the substrate; The first conductive layer is annealed. After annealing, the first conductive layer is coated with a first photoresist on the side opposite to the substrate, and the first photoresist is exposed and developed to form a patterned first photoresist layer. Using the first photoresist layer as a mask, the first etch material is used to etch the annealed first conductive layer, forming multiple first traces spaced apart on the annealed first conductive layer; A second conductive layer is deposited on the side of the plurality of first traces away from the substrate, and the material of the second conductive layer is the same as the material of the first conductive layer before annealing; A second photoresist is coated on the side of the second conductive layer away from the substrate, and the second photoresist is exposed and developed to form a region where the second photoresist is completely removed in the region corresponding to the first trace, and a region where the second photoresist is retained in the region between adjacent first traces, so as to form a patterned second photoresist layer. Using the second photoresist layer as a mask, the second conductive layer is etched with the second etching material to form a second trace between each adjacent first trace.

12. The manufacturing method as described in claim 10, wherein, Using different patterning techniques, patterning is performed in the routing area corresponding to each routing layer to obtain spaced first and second routing traces, specifically including: A first conductive layer is deposited in the wiring area of ​​the substrate; A first photoresist is coated on the side of the first conductive layer away from the substrate, and the first photoresist is exposed and developed to form a patterned first photoresist layer. Using the first photoresist layer as a mask, the first conductive layer is etched with a second etching material to form multiple first traces spaced apart on the first conductive layer; The first conductive layer on which the plurality of first traces are formed is subjected to annealing treatment; A second conductive layer is deposited on the side of the annealed first conductive layer away from the substrate, and the material of the second conductive layer is different from the material of the annealed first conductive layer. A second photoresist is coated on the side of the second conductive layer away from the substrate, and the second photoresist is exposed and developed to form a region where the second photoresist is completely removed in the region corresponding to the first trace, and a region where the second photoresist is retained in the region between adjacent first traces, so as to form a patterned second photoresist layer. Using the second photoresist layer as a mask, the second etching material is used to etch the second conductive layer, forming a second trace between each adjacent first trace.

13. The manufacturing method as described in claim 11 or 12, wherein, The display substrate includes a display area and a border area. The display area includes a first display area and a second display area, wherein the light transmittance of the first display area is greater than that of the second display area. The first display area includes a plurality of sub-pixels arranged in an array. Each sub-pixel includes a light-emitting device and a pixel circuit. The pixel circuit is located in the border area adjacent to the first display area. Alternatively, the second display area has a transition area adjacent to the first display area, and the pixel circuit is located in the transition area. Or, the pixel circuit is distributed within the second display area. The wiring area is at least partially located in the first display area, and the wiring layer is located between the anode of the light-emitting device and the pixel circuit. The first wiring is used to electrically connect the corresponding light-emitting device and the pixel circuit, and the second wiring is used to electrically connect the corresponding light-emitting device and the pixel circuit. The material of the first conductive layer after annealing is p-ITO, and the material of the second conductive layer is a-ITO; wherein, the p-ITO is annealed at high temperature, the a-ITO is annealed at room temperature, the grain size of the p-ITO is larger than that of the a-ITO, the grain boundaries of the p-ITO are fewer than those of the a-ITO, and the resistance of the p-ITO is less than that of the a-ITO.

14. The manufacturing method as described in claim 11 or 12, wherein, It includes a display area and a border area. The display area includes multiple signal lines, and the border area includes the wiring area. The first wiring is used to electrically connect the corresponding signal lines, and the second wiring is used to electrically connect the corresponding signal lines. The material of the second conductive layer is the same metallic material as the material of the first conductive layer before annealing.

15. The manufacturing method as described in claim 10, wherein, Using different patterning techniques, patterning is performed in the routing area corresponding to each routing layer to obtain spaced first and second routing traces, specifically including: A first conductive layer is deposited in the wiring area of ​​the substrate; A first photoresist is coated on the side of the first conductive layer away from the substrate, and the first photoresist is exposed and developed to form a patterned first photoresist layer. Using the first photoresist layer as a mask, the first conductive layer is etched with a second etching material to form multiple first traces spaced apart on the first conductive layer; A second conductive layer is deposited on the side of the first conductive layer on which the plurality of first traces are formed, away from the substrate, and the material of the second conductive layer is different from that of the first conductive layer. A second photoresist is coated on the side of the second conductive layer away from the substrate, and the second photoresist is exposed and developed to form a region where the second photoresist is completely removed in the region corresponding to the first trace, and a region where the second photoresist is retained in the region between adjacent first traces, so as to form a patterned second photoresist layer. Using the second photoresist layer as a mask, the second conductive layer is etched with the first etching material to form a second trace between each adjacent first trace; the second etching material is different from the first etching material.

16. The manufacturing method as described in claim 10, wherein, Using different patterning techniques, patterning is performed in the routing area corresponding to each routing layer to obtain spaced first and second routing traces, specifically including: A first conductive layer is deposited in the wiring area of ​​the substrate; A second conductive layer is deposited on the side of the first conductive layer opposite to the substrate; the material of the second conductive layer is different from the material of the first conductive layer. A first photoresist is coated on the side of the second conductive layer away from the substrate, and the first photoresist is exposed and developed to form alternating areas where the first photoresist is completely removed and areas where the first photoresist is retained, thereby forming a patterned first photoresist layer. Using the first photoresist layer as a mask, the second conductive layer is etched with the first etching material to form multiple second sub-traces spaced apart on the second conductive layer; A second photoresist is deposited on the side of the second conductive layer on which the plurality of second sub-lines are formed, away from the substrate, and the second photoresist is exposed and developed. A second photoresist completely removed area is formed in the area corresponding to the second sub-lines, and a second photoresist retained area is formed in the area corresponding to adjacent second sub-lines. The second photoresist retained area and the second sub-lines have a preset gap to form a patterned second photoresist layer. Using the second photoresist layer as a mask, the first conductive layer is etched with a second etching material to form a first trace located between each adjacent second sub-trace, and a first sub-trace located below the second sub-trace. The first sub-trace and the second sub-trace constitute the second trace. The second etching material is different from the first etching material.

17. The manufacturing method as described in claim 15 or 16, wherein, The display substrate includes a display area and a border area. The display area includes a first display area and a second display area, wherein the light transmittance of the first display area is greater than that of the second display area. The first display area includes a plurality of sub-pixels arranged in an array. Each sub-pixel includes a light-emitting device and a pixel circuit. The pixel circuit is located in the border area adjacent to the first display area. Alternatively, the second display area has a transition area adjacent to the first display area, and the pixel circuit is located in the transition area. Or, the pixel circuit is distributed within the second display area. The wiring area is at least partially located in the first display area, and the wiring layer is located between the anode of the light-emitting device and the pixel circuit. The first wiring is used to electrically connect the corresponding light-emitting device and the pixel circuit, and the second wiring is used to electrically connect the corresponding light-emitting device and the pixel circuit. The first conductive layer is made of a-ITO, and the second conductive layer is made of at least one of doped a-Si, IZO, and IGZO.

18. The manufacturing method as described in claim 15 or 16, wherein, The display substrate includes a display area and a bezel area. The display area includes multiple signal lines, and the bezel area includes the wiring area. The first wiring is used to electrically connect to the corresponding signal lines, and the second wiring is used to electrically connect to the corresponding signal lines. The materials of the first conductive layer and the second conductive layer are different metallic materials.

19. The manufacturing method as described in claim 17, wherein, Also includes: A planarization layer is deposited on the side of the wiring layer opposite to the substrate; The planarization layer is patterned to form first vias corresponding to the first trace and the second trace, respectively. Multiple anodes are formed on the side of the planar layer where the first via is formed, away from the substrate, and each anode is electrically connected to the first trace or the second trace through the corresponding first via.

20. The manufacturing method according to any one of claims 11, 15, and 16, wherein, The first etching material includes nitric acid.

21. The manufacturing method as described in claim 11, 12, 15, or 16, wherein, The second etching material includes oxalic acid.

22. A display device, wherein, Includes the display substrate as described in any one of claims 1-9.

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