Self-assembled monolayers formed on quantum devices

Abstract

Devices, methods, and / or computer-implemented methods are provided to facilitate the formation of self-assembled monolayers on quantum devices. According to embodiments, the device may include qubits formed on a substrate. The device may further include a self-assembled monolayer formed on the qubits.

Description

Technical Field

[0001] This subject matter discloses self-assembled monolayers formed on integrated circuits and methods thereof. More specifically, this subject matter discloses self-assembled monolayers formed on quantum devices and methods thereof. Summary of the Invention

[0002] The following overview is presented to provide a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements, or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, devices and / or methods (e.g., computer-implemented methods) are described to facilitate the formation of a self-assembled monolayer on a quantum device.

[0003] According to an embodiment, a device may include a qubit formed on a substrate. The device may further include a self-assembled monolayer formed on the qubit. An advantage of such a device is that it can contribute to at least one of improved coherence time and / or improved lifetime of the qubit.

[0004] In some embodiments, the self-assembled monolayer is formed on at least one of the qubit or the substrate to prevent oxidation of at least one of the qubit or the substrate. An advantage of such a device is that it can contribute to at least one of improved coherence time and / or improved lifetime of the qubit.

[0005] According to one embodiment, a method may include removing one or more oxide layers from a qubit formed on a substrate. The method may further include depositing a self-assembled monolayer on the qubit. An advantage of this method is that it can be implemented to assist in at least one of improved coherence time and / or improved lifetime of the qubit.

[0006] In some embodiments, the above method may further include removing at least one oxide layer from at least one of the qubit or the substrate and depositing the self-assembled monolayer on at least one of the qubit or the substrate to prevent oxidation of at least one of the qubit or the substrate. An advantage of this method is that it can be implemented to assist in at least one of improved coherence time and / or improved lifetime of the qubit.

[0007] According to one embodiment, a device may include one or more superconducting components formed on a substrate. The device may further include a self-assembled monolayer formed on the one or more superconducting components. An advantage of such a device is that it can contribute to at least one of improved coherence time and / or improved lifetime of the one or more superconducting components.

[0008] In some embodiments, the self-assembled monolayer is formed on at least one of the one or more superconducting components or the substrate to prevent oxidation of at least one of the one or more superconducting components or the substrate. An advantage of this device is that it can contribute to at least one of improved coherence time and / or improved lifetime of the one or more superconducting components.

[0009] According to one embodiment, a method may include removing one or more oxide layers from one or more superconducting components formed on a substrate. The method may further include depositing a self-assembled monolayer on the one or more superconducting components. An advantage of this method is that it can be implemented to promote at least one of improved coherence time and / or improved lifetime of the one or more superconducting components.

[0010] In some embodiments, the above method may further include removing at least one oxide layer from at least one of the one or more superconducting components or the substrate and depositing the self-assembled monolayer on at least one of the one or more superconducting components or the substrate using at least one of a solution-based self-assembled monolayer deposition method or a vapor-phase-based self-assembled monolayer deposition method. The advantage of this method is that it can be implemented to promote at least one of improved coherence time and / or improved lifetime of these superconducting components.

[0011] According to an embodiment, the device may include qubits formed on a substrate of a bump-bonded device. The device may further include a self-assembled monolayer formed on the qubits. An advantage of such a device is that it can contribute to at least one of improved coherence time and / or improved lifetime of the qubits.

[0012] In some embodiments, the self-assembled monolayer is formed on at least one of the qubit or the substrate to prevent oxidation of at least one of the qubit or the substrate. An advantage of such a device is that it can contribute to at least one of improved coherence time and / or improved lifetime of the qubit. Attached Figure Description

[0013] This patent or application document contains at least one color drawing. A copy of this patent or application disclosure with color drawings will be provided by the office upon request and payment of the necessary fees.

[0014] Figure 1A A cross-sectional side view of an example, non-limiting device according to one or more embodiments described herein is shown, which may include one or more oxide layers on a substrate and / or on one or more superconducting components formed on the substrate.

[0015] Figure 1BThis illustrates the process after removing one or more oxide layers from one or more surfaces, according to one or more embodiments described herein. Figure 1A A cross-sectional side view of an example non-restrictive device.

[0016] Figure 1C This demonstrates the formation of one or more self-assembled monolayers on one or more surfaces of one or more superconducting components and / or the substrate. Figure 1B A cross-sectional side view of an example non-restrictive device.

[0017] Figure 2 This demonstrates the formation of one or more self-assembled monolayers on one or more surfaces of the one or more superconducting components and / or the substrate. Figure 1B A cross-sectional side view of an example non-restrictive device.

[0018] Figure 3A A cross-sectional side view of an example non-limiting device according to one or more embodiments described herein is shown. The device may include a bump bonding device having one or more oxide layers on one or more substrates and / or on one or more superconducting components formed on the one or more substrates.

[0019] Figure 3B This demonstrates one or more superconducting components formed on one or more substrates according to one or more embodiments described herein and / or one or more self-assembled monolayers formed on one or more surfaces of one or more substrates. Figure 3A Example of a non-restrictive device: a cross-sectional side view.

[0020] Figure 4 The diagram illustrates an example non-limiting method for promoting H-termination of a silicon (Si) substrate surface and forming one or more self-assembled monolayers on the surface, according to one or more embodiments described herein.

[0021] Figure 5 A flowchart is shown illustrating an exemplary, non-limiting method for facilitating the formation of a self-assembled monolayer on a quantum device according to one or more embodiments described herein.

[0022] Figure 6A , Figure 6B and Figure 6C A diagram is shown illustrating exemplary, non-limiting information, including experimental data from an implementation of a quantum device comprising a self-assembled monolayer formed on the quantum device, according to one or more embodiments described herein.

[0023] Figure 7AThe diagram illustrates examples of non-limiting information regarding experimental data from an embodiment of a quantum device including an H-terminated surface, which may be included after the removal of the oxide layer, according to one or more embodiments described herein.

[0024] Figure 7B A diagram illustrating example non-limiting information that may include experimental data from an embodiment of a quantum device comprising a self-assembled monolayer formed on the quantum device, according to one or more embodiments described herein.

[0025] Figure 7C The illustration shows exemplary, non-limiting information according to one or more embodiments described herein, which may include experimental data from an embodiment of a quantum device comprising a self-assembled monolayer formed on the quantum device.

[0026] Figure 8 A flowchart is shown of an exemplary, non-limiting computer implementation of a method that can facilitate the formation of a self-assembled monolayer on a quantum device according to one or more embodiments described herein.

[0027] Figure 9 A flowchart is shown of an exemplary, non-limiting computer implementation of a method that can facilitate the formation of a self-assembled monolayer on a quantum device according to one or more embodiments described herein.

[0028] Figure 10 A block diagram is shown that illustrates an exemplary, non-limiting operating environment that can facilitate one or more embodiments described herein. Detailed Implementation

[0029] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being limited by any express or implied information presented in the preceding background or overview or detailed description sections.

[0030] One or more embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals are used throughout to refer to the same elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced without these specific details in various circumstances. It should be noted that the drawings provided with this application are for illustrative purposes only, and therefore, the drawings are not drawn to scale.

[0031] Quantum processors based on superconducting qubits (qubits) can consist of aluminum (Al), alumina (Al₂O₃), and Josephson junctions of aluminum (Al) stacks (Al / Al₂O₃ / Al stacks). In some implementations, they are connected to one or more superconducting components, such as niobium (Nb) resonators deposited on a high-resistivity substrate (e.g., silicon (Si)). With appropriate device architecture and design, the lifetime of the wavefunction in qubits has been increased to several hundred microseconds in recent years, but further increases in lifetime have not yet been achieved. The wavefunction itself oscillates at approximately 5 GHz (approximately 5 GHz) radio frequency (RF). At this frequency, the absorption of RF photons within the oxides formed on the substrate and / or one or more superconducting components during device fabrication and long-term exposure to the atmosphere can significantly affect the lifetime of the qubit.

[0032] Experiments have shown that silicon dioxide (SiO2) formed on the surface of a silicon (Si) substrate, and niobium monoxide (NbO), niobium dioxide (NbO2), and / or niobium pentoxide (Nb2O5) formed on niobium (Nb) resonator lines, exhibit strong absorption in the RF state. While oxides (e.g., silicon dioxide (SiO2)) on the silicon (Si) substrate can be removed by treatment with a diluted hydrogen fluoride (HF) etchant (diluted HF etchant) to remove oxides and H-terminal surfaces, niobium oxides such as niobium pentoxide (Nb2O5), niobium dioxide (NbO2), and / or niobium monoxide (NbO) can also be removed by this etching, but rapidly regrow in the ambient atmosphere.

[0033] The problem with existing quantum devices (e.g., quantum processors, quantum chips, superconducting circuits integrated on a substrate, quantum bump-bonded devices, etc.) and / or manufacturing processes that facilitate the fabrication of such quantum devices is that they do not provide for the removal of such oxide from the quantum device, nor do they prevent such oxide from reforming on the quantum device (e.g., by exposure to air during manufacturing). Given that the aforementioned prior art (e.g., quantum devices and / or manufacturing processes) fails to provide for the removal of such oxide from the surface of the quantum device and prevent such oxide from reforming on the quantum device, this disclosure can be implemented as a solution to this problem in the form of devices and / or methods (e.g., computer-implemented methods) that can provide one or more self-assembled monolayers formed on one or more superconducting components (e.g., qubits, resonators, capacitors, etc.) of the quantum device (e.g., quantum chips, devices including qubit bump bonding, superconducting circuits including qubits integrated on a substrate, etc.). An advantage of such devices and / or methods is that they can assist in at least one of improved coherence time and / or improved lifetime of the one or more superconducting components (e.g., qubits).

[0034] In some embodiments, one or more self-assembled monolayers may be formed on one or more superconducting components (e.g., qubits, resonators, capacitors, etc.) of a quantum device (e.g., a quantum chip, a device including qubit bumps, a superconducting circuit including qubits integrated on a substrate, etc.) and on a substrate in which the one or more superconducting components are formed (e.g., integrated). An advantage of such devices and / or methods is that they can assist in at least one of improved coherence time and / or improved lifetime of the one or more superconducting components (e.g., qubits).

[0035] Figure 1A-5 , Figure 8 and / or Figure 9 Exemplary, non-limiting multi-step manufacturing sequences are shown that can be implemented to manufacture one or more embodiments of the present disclosure as described herein and / or illustrated in the accompanying drawings. For example, they can be implemented... Figure 1A-1C The non-limiting multi-step manufacturing sequence shown is for manufacturing device 100c, wherein device 100c may include semiconductor and superconducting devices comprising one or more components (e.g., silicon (Si) substrate, (multiple) superconducting components, qubits, resonators, capacitors, etc.) having one or more self-assembled monolayers formed thereon. In another example, it may be implemented Figure 1A , Figure 1B and Figure 2 The non-limiting multi-step manufacturing sequence shown is for manufacturing apparatus 200, wherein apparatus 200 may include examples and non-limiting alternative embodiments of apparatus 100c. In another example, Figure 1A , 1B The non-limiting multi-step manufacturing sequence shown in 3A and 3B can be implemented to manufacture devices 300a and / or 300b, wherein device 300a may include exemplary, non-limiting alternative embodiments of device 100b and / or device 300b may include exemplary, non-limiting alternative embodiments of device 100c and / or device 200. For example, it can be implemented Figure 1A , 1B The non-limiting multi-step manufacturing sequence shown in 3A and 3B to manufacture device 300a and / or device 300b, wherein such device(s) may include bump-bonded devices, the bump-bonded devices comprising superconducting components (e.g., qubits, resonators, capacitors, etc.) having one or more self-assembled monolayers formed thereon and one or more semiconductor components (e.g., silicon (Si) substrates).

[0036] In one example, devices 100c, 200, 300a, and / or 300b can be implemented in a quantum computing device (e.g., a quantum processor, a quantum computer, etc.), wherein such a device may include one or more superconducting components that can be implemented in such a quantum computing device. For example, devices 100c, 200, 300a, and / or 300 can be implemented in a quantum computing device (e.g., a quantum processor, a quantum computer, etc.), wherein such a device may include one or more qubits and / or resonators (e.g., bus resonators, transmission resonators, etc.) that can be implemented in such a quantum computing device.

[0037] See below for reference. Figures 1A to 5 , Figure 8 and / or Figure 9 The fabrication of the various embodiments of this subject matter disclosed herein (e.g., devices 100c, 200, 300a and / or 300b) as described herein and / or illustrated in the accompanying drawings may include a multi-step sequence of steps, such as photolithography and / or chemical processing steps, which facilitate the incremental creation of electronic-based systems, devices, components and / or circuits in semiconductor and superconducting devices (e.g., integrated circuits). For example, various embodiments of this disclosure described herein and / or shown in the figures (e.g., devices 100c, 200, 300a and / or 300b) can be manufactured using techniques including, but not limited to: photolithography, microlithography, nanolithography, nanoimprint lithography, photomask techniques, patterning techniques, photoresist techniques (e.g., positive photoresist, negative photoresist, hybrid photoresist, etc.), etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, etc.), evaporation techniques, sputtering techniques, plasma ashing techniques, heat treatment (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, etc.), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical mechanical planarization (CMP), back polishing techniques and / or another technique for manufacturing integrated circuits.

[0038] See below for reference. Figures 1A to 5 , Figure 8 and / or Figure 9As described, various materials can be used to manufacture the various embodiments of the subject matter disclosed herein and / or illustrated in the figures (e.g., devices 100c, 200, 300a, and / or 300b). For example, the various embodiments of the subject matter disclosed herein and / or illustrated in the figures (e.g., devices 100c, 200, 300a, and / or 300b) can be manufactured using one or more different material classes, including but not limited to: conductive materials, semiconductor materials, superconducting materials, dielectric materials, polymer materials, organic materials, inorganic materials, nonconducting materials, and / or another material that can be used in conjunction with one or more of the techniques described above for manufacturing integrated circuits.

[0039] It will be understood that when an element that is a layer (also called a film), region, and / or substrate is referred to as being "on" or "above" another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intermediate elements present. It should also be understood that when an element is referred to as being "below" or "under" another element, it may be directly below or under the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly below" or "directly under" another element, there are no intermediate elements present. It should also be understood that when an element is referred to as being "coupled" to another element, it may describe one or more different types of coupling, including but not limited to chemical coupling, communication coupling, electrical coupling, physical coupling, operational coupling, optical coupling, thermal coupling, and / or another type of coupling.

[0040] Figure 1A A cross-sectional side view of an exemplary non-limiting device 100a is shown according to one or more embodiments described herein, the device including one or more oxide layers on a substrate and / or on one or more superconducting components formed on the substrate. Such one or more superconducting components may be formed on the substrate of device 100a, as described below.

[0041] Device 100a may include a substrate 102. Substrate 102 may include any material having semiconductor properties, including but not limited to: silicon (Si), sapphire (e.g., aluminum oxide (Al₂O₃)), silicon-germanium (SiGe), silicon-germanium-carbon (SiGeC), silicon carbide (SiC), germanium (Ge) alloys, III / V compound semiconductors, II / VI compound semiconductors, and / or another material. In some embodiments, substrate 102 may include layered semiconductors, including but not limited to: silicon / silicon-germanium (Si / SiGe), silicon / silicon carbide (Si / SiC), silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI), and / or another layered semiconductor. In an example, substrate 102 may include a silicon (Si) substrate.

[0042] Device 100a may further include one or more superconducting components 104 that can be formed on substrate 102. Such superconducting components 104 may be formed on substrate 102 using one or more photolithography, patterning, photoresist, and / or material deposition techniques as defined above (e.g., photolithography patterning processes, evaporation techniques, sputtering techniques, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), etc.). Multiple superconducting components 104 may be formed on substrate 102 using superconducting materials (e.g., niobium (Nb)) and / or another superconducting material. Multiple superconducting components 104 may be formed on substrate 102 to generate, for example, one or more qubits, one or more components of qubits, and / or one or more components of superconducting circuits that may be coupled to the multiple qubits, such as one or more wires, electrodes, capacitors, resonators (e.g., bus resonators, transmission resonators, etc.), tuning gates, and / or another superconducting component.

[0043] In one example, device 100a may include a qubit device, wherein substrate 102 may include a silicon (Si) substrate on which niobium (Nb) superconducting components 104 are formed. In this example, one or more of the surfaces of device 100a may be oxidized by exposure to air (e.g., during processing). For example, a first oxide layer 106 comprising, for example, silicon dioxide (SiO2) may be formed on one or more surfaces of substrate 102 by exposure to air. In another example, a second oxide layer 108 comprising, for example, niobium monoxide (NbO), niobium dioxide (NbO2), and / or niobium pentoxide (Nb2O5) may be formed on one or more surfaces of one or more superconducting components 104 by exposure to air. See below for further details. Figure 1B The first oxide layer 106 and / or the second oxide layer 108 can be removed using an etching process.

[0044] Figure 1B The following diagram illustrates the process after removing one or more oxide layers from one or more surfaces, according to one or more embodiments described herein. Figure 1A A cross-sectional side view of an exemplary non-limiting device 100a. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0045] Device 100b may include exemplary, non-limiting alternative embodiments of device 100a after one or more oxide layers have been removed from one or more surfaces of device 100a. For example, a first oxide layer 106 and / or a second oxide layer 108 may be removed from one or more surfaces of substrate 102 and / or one or more superconducting components 104, respectively. Figure 1B As shown. For example, the first oxide layer 106 may include silicon dioxide (SiO2) that can be removed from one or more surfaces (e.g., top surfaces) of a substrate 102 including a silicon (Si) substrate. In another example, the second oxide layer 108 may include niobium monoxide (NbO), niobium dioxide (NbO2), niobium pentoxide (Nb2O5), and / or other low oxides that can be removed from one or more surfaces (e.g., one or more top surfaces) of one or more superconducting components 104 including one or more niobium (Nb) superconducting components (e.g., one or more niobium (Nb) resonators).

[0046] In the above examples, an etching process can be used to remove the first oxide layer 106 and / or the second oxide layer 108 from such surfaces of such components. For example, the first oxide layer 106 and / or the second oxide layer 108 can be removed from one or more surfaces of the substrate 102 and / or the superconducting component 104 using a diluted etchant, such as a diluted hydrogen fluoride (HF) etchant (diluted HF etchant), which includes a non-aqueous diluted HF etchant having trifluoroacetic acid (CF3CO2H) and / or another diluted etchant. In one example, the first oxide layer 106 and / or the second oxide layer 108 can be removed from one or more surfaces of the substrate 102 and / or one or more superconducting components 104 using a diluted etchant solution (e.g., an aqueous hydrogen fluoride (HF) solution), which includes dilutions, for example, ranging from about 1 percent (%) to about 10% of an aqueous hydrogen fluoride (HF) solution. In another example, the first oxide layer 106 and / or the second oxide layer 108 can be removed from one or more surfaces of the substrate 102 and / or one or more superconducting components 104 using a wet etch solution containing ammonium fluoride (NH4F) as a buffer. In these embodiments, the substrate 102 can then be rinsed with deionized water to remove physically absorbed fluoride.

[0047] Removing the first oxide layer 106 and / or the second oxide layer 108 from one or more surfaces of the substrate 102 and / or the superconducting component 104 using a diluted etchant (e.g., a non-aqueous diluted HF etchant containing trifluoroacetic acid (CF3CO2H) or the like) can also hydrogen-terminate the surface of the substrate 102 (e.g., as shown in the image). Figure 1B(As depicted by the symbol of three “H” letters above substrate 102). For example, in an embodiment where substrate 102 comprises a silicon (Si) substrate, removing the first oxide layer 106 from the surface (e.g., top surface) of substrate 102 using such a diluted etchant as defined above can produce an H-terminated silicon (Si) surface, which is a chemically passivated silicon (Si) surface of substrate 102 having silicon (Si) atoms covalently bonded to hydrogen (H) atoms.

[0048] In one example, the second oxide layer 108 on one or more surfaces of one or more superconducting components 104 can be removed using aqueous hydrogen fluoride (HF) and / or buffered etching containing ammonium fluoride (NH4F) at different concentrations as described above. In another example, the second oxide layer 108 on one or more surfaces of superconducting components 104 can be removed by performing a dry etching process in a vacuum chamber using a fluorinated gas including but not limited to carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), and / or another fluorinated gas. In another example, the first oxide layer 106 and / or the second oxide layer 108 on one or more surfaces of the substrate 102 and / or one or more superconducting components 104 can be removed using a combination of the wet etching process described above for removing the first oxide layer 106 (e.g., silicon dioxide (SiO2)) from one or more surfaces of the substrate 102 and a vacuum chamber annealing process at high temperature for removing the second oxide layer 108 (e.g., niobium dioxide (NbO2), niobium pentoxide (Nb2O5), and / or other low oxides) from one or more surfaces of one or more superconducting components 104. For example, temperatures ranging from about 250 degrees Celsius (°C) to about 400°C can be used during the vacuum chamber annealing process. In some embodiments, temperatures of at least 250°C and / or above 400°C can be used during the vacuum chamber annealing process to remove the second oxide layer 108 (e.g., niobium dioxide (NbO2), niobium pentoxide (Nb2O5), and / or other low oxides) from this or these surfaces of one or more superconducting components 104.

[0049] Although the first oxide layer 106 and / or the second oxide layer 108 can be removed from one or more surfaces of the substrate 102 and / or the superconducting component 104 using a diluted etchant as described above (e.g., a non-aqueous diluted HF etchant containing trifluoroacetic acid (CF3CO2H), etc.), the second oxide layer 108, which may include one or more niobium oxides (e.g., niobium monoxide (NbO), niobium dioxide (NbO2), niobium pentoxide (Nb2O5), and / or other low oxides), can be rapidly regrowed in an ambient atmosphere. For example, Figure 1BThe second oxide layer 108 shown may include a new oxide layer (e.g., niobium monoxide (NbO), niobium dioxide (NbO2), niobium pentoxide (Nb2O5), and / or other low oxides) that has been rapidly grown on one or more superconducting components 104 after a similar oxide layer has been removed from device 100a using, for example, a diluted etchant as described above. To prevent re-oxidation of one or more surfaces (e.g., H-terminated surfaces) of the superconducting components 104 and / or substrate 102, such surfaces may be reacted with one or more reactive organic compounds to form one or more self-assembled monolayers (also referred to as self-assembled monolayers, self-confined monolayers, etc.) on such surfaces, as described below. Figure 1C As stated above.

[0050] Figure 1C This demonstrates the formation of one or more self-assembled monolayers on one or more surfaces of one or more superconducting components and / or substrates. Figure 1B A cross-sectional side view of an example non-limiting device 100b. For the sake of brevity, repeated descriptions of similar elements and / or processes used in other embodiments described herein are omitted.

[0051] Device 100c may include example, non-limiting alternative embodiments of device 100b after one or more self-assembled monolayers have been formed on one or more surfaces of substrate 102 and / or superconducting component 104. For example, device 100c may include example, non-limiting alternative embodiments of device 100b after one or more self-assembled monolayers have been formed on one or more surfaces of substrate 102 and / or superconducting component 104 using a vapor-phase-based self-assembled monolayer deposition process as described below.

[0052] To prevent re-oxidation of one or more H-terminated surfaces of substrate 102 (e.g., silicon hydride (Si) surfaces) and / or one or more surfaces of superconducting component 104 (e.g., one or more niobium (Nb) superconducting components), these surfaces may be reacted with reactive organic compounds to form one or more self-assembled monolayers (also referred to as self-confined monolayers) on these surfaces via covalent bonding. Forming self-assembled monolayers on such surfaces also removes all dangling bonds that would otherwise be carriers for re-oxidation under ambient conditions, and stabilizes and / or encapsulates (e.g., seals) such surfaces to prevent the regrowth of one or more of the aforementioned oxides. It should be understood that such self-assembled monolayers possess properties including, but not limited to: strong silicon-carbon (Si-C) bonds that do not dissociate below 300 degrees Celsius (°C); non-hydrolytic or oxidized under ambient conditions; and / or hydrophobic.

[0053] As described below, in embodiments where substrate 102 comprises a silicon (Si) substrate and one or more superconducting components 104 comprise one or more niobium (Nb) superconducting components, such a self-assembled monolayer can be attached to one or more surfaces of substrate 102 (e.g., one or more silicon (Si) surfaces) and / or one or more superconducting components 104 (e.g., including surfaces containing niobium oxide remaining after etching) using solution-based deposition processes and / or vapor phase deposition processes (also known as vapor phase deposition processes). The specific chemical properties of each of these one or more surfaces (e.g., silicon (Si) or niobium (Nb)) enable the self-assembled monolayer to react with the appropriate surface.

[0054] In one example, one or more etched surfaces of the substrate 102 of device 100b (e.g., including a surface of hydride silicon) and / or the superconducting component 104 (e.g., including a surface of niobium oxide) may be reacted with one or more reactive organic compounds at moderate temperatures (e.g., ranging from about 120°C to about 200°C) to form a covalently bonded self-assembled monolayer on this or these surfaces. In another example, one or more etched surfaces of the substrate 102 of device 100b (e.g., including a surface of hydride silicon) and / or one or more superconducting components 104 (e.g., including one or more surfaces of niobium oxide) may be reacted with one or more reactive organic compounds using ultraviolet radiation to form a covalently bonded self-assembled monolayer on such surfaces. According to one or more embodiments disclosed in this subject matter, the one or more reactive organic compounds described herein may include, but are not limited to, alkynes (e.g., 1-yne), alkenes (e.g., 1-enes), alcohols, thiols, and / or another reactive organic compound.

[0055] The chain length of such reactive organic compounds as defined above can vary from, for example, 1 to 18 carbon (C) atoms. Of the reactive organic compounds defined above, only thiols can react with surfaces having silicon (Si) hydride (e.g., one or more H-terminated surfaces of substrate 102) and surfaces having niobium oxide that can be retained after etching (e.g., surfaces of one or more superconducting components 104 having niobium monoxide (NbO), niobium dioxide (NbO2), niobium pentoxide (Nb2O5), and / or other low oxides). Other reactive organic compounds defined above (e.g., alkynes, alkenes, and alcohols) can only react with surfaces having silicon (Si) hydride to form a self-assembled monolayer having silicon-carbon (Si-C) or silicon-oxygen (Si-O) bonds between the surface and a long-chain hydrocarbon. The solvents defined above can have boiling points higher than the heating temperature used for bonding and can be inert to both the surface and the reactive organic compound used for self-assembly.

[0056] like Figure 1CAs shown, in embodiments where substrate 102 comprises a silicon (Si) substrate and superconducting component 104 comprises a niobium (Nb) superconducting component, the formation of one or more self-assembled monolayers on one or more surfaces of substrate 102 (e.g., a silicon (Si) surface) and / or superconducting component 104 (e.g., including a surface containing niobium oxide remaining after etching) can be achieved using a vapor deposition process (e.g., a vapor-based self-assembled monolayer deposition process). For example, a vapor 110 containing perfluorodecene (PFD) can be applied to one or more surfaces of substrate 102 and / or superconducting component 104 of device 100b to promote the formation of long-chain reactive organic compounds (in... Figure 1C The Chinese character is represented as R. f In such Figure 1C Self-assembly on one or more surfaces of the device 100c depicted herein. For example, in order to form such a self-assembled monolayer, the device 100b having the etched surfaces of the substrate 102 and / or the superconducting component 104 can be immediately transferred (e.g., after etching as described above) to a vacuum chamber and exposed to the vapor 110 of one or more reactive organic materials as defined above while the substrate 102 is heated at a moderately high temperature (e.g., a temperature in the range of about 100°C to about 180°C).

[0057] Figure 2 This demonstrates the formation of one or more self-assembled monolayers on one or more surfaces of the one or more superconducting components and / or the substrate. Figure 1B A cross-sectional side view of an example non-limiting device 100b. For the sake of brevity, repeated descriptions of similar elements and / or processes used in other embodiments described herein are omitted.

[0058] Device 200 may include example, non-limiting alternative embodiments of device 100b after one or more self-assembled monolayers have been formed on one or more surfaces of substrate 102 and / or superconducting component 104. For example, device 200 may include example, non-limiting alternative embodiments of device 100b after one or more self-assembled monolayers have been formed on one or more surfaces of substrate 102 and / or superconducting component 104 using a solution-based self-assembled monolayer deposition process as described below.

[0059] Based on the removal of the first oxide layer 106 and / or the second oxide layer 108 from device 100b as described above, followed by rinsing and drying device 100b under a nitrogen (N) flow, device 100b may be immersed in a solution 202 containing one or more reactive organic compounds as defined above in a solvent. Based on this immersion of device 100b in solution 202, device 100b may be heated at a moderately high temperature in the range of about 100°C to about 140°C under a nitrogen (N) atmosphere to complete the reaction of the organic compound (in... Figure 2 The Chinese character is represented as R.f Covalent bonds are formed between the device 100b and the etched surface of the device, thereby forming on the Figure 2 Device 200 is shown in the figure.

[0060] Figure 3A A cross-sectional side view of an example non-limiting device 300 according to one or more embodiments described herein is shown. The device may include a bump-bonded device having one or more oxide layers formed on one or more substrates and / or on one or more superconducting components. For brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0061] After further developing device 100a into a bump-bonded device and removing one or more oxide layers from device 300a, device 300a may include example, non-limiting alternative embodiments of device 100a and / or device 100b. For example, device 300a may include devices 100a further developed into a bump-bonded device using a bump bonding process (e.g., flip-chip process) to bond two substrates 102 to bumps 302 (e.g., solder bumps). Figure 3A Examples, non-limiting alternative embodiments, are shown below, in which a vapor etchant is further applied to device 300a to remove one or more oxide layers (e.g., silicon dioxide (SiO2), niobium monoxide (NbO), niobium dioxide (NbO2), niobium pentoxide (Nb2O5), etc.) from device 300a.

[0062] The substrate 102 of device 300a may include a silicon (Si) substrate having one or more superconducting components 104 formed thereon. Figure 3A and 3B (not shown in the image), wherein one or more such superconducting components 104 may be referenced as described above. Figure 1A The aforementioned layer is formed on the substrate 102 prior to the bump bonding process using bump 302 to bond the substrate 102. One or more surfaces of the substrate 102 and / or the superconducting component 104 may respectively have a first oxide layer 106 and / or a second oxide layer 108 (in... Figure 3A and 3B (Not shown in the image), the first oxide layer and / or the second oxide layer are formed by exposing this or these surfaces to air, as referenced above. Figure 1A As described. Figure 3AAs shown, vapor etchant 304 may be applied to device 300a to remove the first oxide layer 106 and / or the second oxide layer 108. For example, vapor etchant 304 may include vapor hydrogen fluoride (HF) etchant, which may be applied to device 300a such that it penetrates the space between substrate 102 and / or bump 302, which may be inaccessible by solution deposition.

[0063] Figure 3B This demonstrates the formation of one or more self-assembled monolayers on one or more surfaces of the one or more superconducting components formed on one or more substrates, according to one or more embodiments described herein. Figure 3A A cross-sectional side view of an example non-limiting device 300a. For the sake of brevity, repeated descriptions of similar elements and / or processes used in other embodiments described herein are omitted.

[0064] Device 300b may include one or more self-assembled monolayers formed on one or more surfaces of substrate 102 and / or superconducting component 104. Figure 3B (Not shown in the image) An example, non-limiting alternative embodiment of device 300a. In this example, device 300b may include an example, non-limiting alternative embodiment of device 300a after forming one or more self-assembled monolayers on one or more surfaces of substrate 102 and / or superconducting component 104 using a vapor-phase-based self-assembly monolayer deposition process. For example, vapor 110 containing perfluorodecene (PFD) can be used as... Figure 3B The surfaces of the substrate 102 and / or the superconducting component 104 of the device 300b are shown to facilitate the self-assembly of long-chain reactive organic compounds on such surfaces of the device 300b, as described above. Figure 1C For example, to form such a self-assembled monolayer, when the substrate 102 is heated at a moderately high temperature (e.g., from about 100°C to about 180°C), the device 300a having the etched surfaces of the substrate 102 and / or the superconducting component 104 can be immediately transferred (e.g., after etching as described above) to a vacuum chamber and exposed to the vapor 110 of one or more reactive organic materials as defined above. In these examples, the vapor 110 (e.g., vapor PFD) can be applied to the device 300b such that it penetrates the space between the substrate 102 and / or the bumps 302, which may be inaccessible via solution deposition.

[0065] Figure 4A diagram illustrates an example non-limiting method 400 for facilitating H-termination of a silicon (Si) substrate surface and forming one or more self-assembled monolayers on that surface, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0066] Figure 4 The method 400 shown may include a method for H-termining the silicon (Si) surface of a substrate 102 comprising a silicon (Si) substrate. For example, method 400 may include using a diluted HF etchant to H-terminate the silicon (Si) surface of a substrate 102 comprising a silicon (Si) substrate, as referenced above. Figure 1A and 1B As stated above.

[0067] Figure 4 The method 400 shown may further include a method of attaching a self-assembled monolayer to the H-terminated silicon (Si) surface of the substrate 102 (e.g., after etching as described above). For example, method 400 may include using the method described above. Figure 1C and 3B The vapor-phase-based self-assembled monolayer deposition process (e.g., using vapor 110) attaches a self-assembled monolayer (e.g., a self-assembled fluorinated olefin, perfluorodecene (PFD), etc.) to the H-terminated silicon (Si) surface of substrate 102 (e.g., after etching as described above).

[0068] Figure 5 A flowchart of an example non-limiting method 500 for facilitating the formation of a self-assembled monolayer on a quantum device according to one or more embodiments described herein is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0069] In 502, method 500 may include starting with a qubit substrate patterned with oxidized silicon (Si) and niobium (Nb). For example, in 502, method 500 may include starting with a device, such as those described above. Figure 1A and 3A The described device 100a and / or device 300a, wherein one or more such devices may include a substrate 102 (e.g., a silicon (Si) substrate) and / or one or more superconducting components 104 (e.g., niobium (Nb) superconducting components) having a first oxide layer 106 (e.g., silicon dioxide (SiO2)) and / or a second oxide layer 108 (e.g., niobium monoxide (NbO), niobium dioxide (NbO2), niobium pentoxide (Nb2O5), and / or other low oxides) respectively formed thereon.

[0070] In method 504, method 500 may include treatment with an etchant to remove (various) oxides, for example, by using a non-aqueous diluted HF etchant having trifluoroacetic acid (CF3CO2H). For example, as referenced above. Figure 1A , Figure 1B and Figure 3A The device 100a and / or device 300a may be treated with a non-aqueous diluted HF etchant containing trifluoroacetic acid (CF3CO2H) to remove the first oxide layer 106 and / or the second oxide layer 108 from one or more surfaces of such device, and / or to H-cap the silicon (Si) surface of the substrate 102.

[0071] In 506a, method 500 may include depositing a self-assembled monolayer (SAM) onto an H-terminated silicon (Si) surface via solution deposition. For example, as referenced above. Figure 2 One or more self-assembled monolayers may be formed (e.g., deposited, assembled, grown, etc.) on one or more surfaces of device 100b using, for example, a solution-based self-assembly monolayer deposition process (e.g., a solution 202 containing one or more of the reactive organic compounds as defined above in a solvent).

[0072] In 506b, method 500 may include depositing a self-assembled monolayer (SAM) onto an H-terminated silicon (Si) surface via vapor deposition. For example, as referenced above. Figure 1B , 1C As described in 3A and 3B, a self-assembly monolayer deposition process based on the gas phase (e.g., vapor 110, including, for example, PFD, as described above) can be used. Figure 1C One or more self-assembled monolayers are formed (e.g., deposited, assembled, grown, etc.) on device 100b and / or device 300a using one or more defined reactive organic materials, etc.

[0073] In 508a, method 500 may include repeating the process on a niobium (Nb) surface using a thiol-based self-assembled monolayer (SAM). For example, refer to... Figure 2 In 508a, method 500 may include repeating the deposition steps of 506a, wherein a thiol-based self-assembled monolayer may be deposited (e.g., formed, assembled, grown, etc.) on one or more surfaces of one or more superconducting components 104 including niobium (Nb) superconducting components using, for example, a solution-based self-assembly monolayer deposition method (e.g., a solution 202 containing one or more reactive organic compounds as defined above in a solvent).

[0074] In 508b, method 500 may include repeating the process on a niobium (Nb) surface using a thiol-based self-assembled monolayer (SAM). For example, refer to... Figure 1C and 3BIn 508b, method 500 may include repeating the deposition steps of 506b, wherein a self-assembling monolayer deposition process based on the gas phase (e.g., vapor 110, including, for example, PFD, referred above) may be used. Figure 1C One or more of the defined reactive organic materials will be used to deposit (e.g., form, assemble, grow, etc.) a thiol-based self-assembled monolayer on one or more surfaces of one or more superconducting components 104, including niobium (Nb) superconducting components.

[0075] At 510, method 500 may include performing final processing of the qubit chip, wherein a self-assembled monolayer (SAM) coating prevents re-oxidation of the silicon (Si) and niobium (Nb) surfaces. For example, at 510, method 500 may include performing final processing, such as, for example, packaging of the qubit chip, which may include, for example, the above-mentioned... Figure 1C , 2 The devices 100c, 200 and / or 300b described in 3B.

[0076] Figure 6A , 6B Figures 6C and 6D illustrate examples of non-limiting information 600a, 600b, 600c according to one or more embodiments described herein, which may include experimental data from an implementation of a quantum device comprising a self-assembled monolayer formed on the quantum device. For brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0077] Information 600a, 600b, 600c may include X-ray photoelectron spectroscopy that displays experimental data from an implementation of a quantum device comprising a self-assembled monolayer formed on the quantum device according to one or more embodiments described herein.

[0078] Figure 6A The information described in 600a depicts silicon oxide (Si) as curve 602a, and the rapid reduction of oxygen (O1s core energy level) and H-terminated silicon (Si) after etching with diluted HF or trifluoroacetic acid is depicted as curve 604a.

[0079] Figure 6B Information 600b shown includes a spectrum depicting the intensity reduction of the oxygen O1s signal, which indicates the removal of silicon dioxide (SiO2) from a silicon (Si) substrate using various oxide removal processes as shown in graphs 604b, 606b, 608b, and 610b. Figure 6B The curve 602b shown represents the intensity of the oxygen O1s signal obtained from the inserted silicon (Si) substrate. Figure 6BThe curve 604b shown indicates a decrease in the intensity of the oxygen O1s signal obtained from a silicon (Si) substrate after treatment with trifluoroacetic acid (TFA). Figure 6B The curve 606b shown indicates the decrease in the intensity of the oxygen O1s signal obtained from the silicon (Si) substrate after treatment with an HF solution containing 10% (10%) HF in water (H2O). Figure 6B The curve 608b shown indicates a decrease in the intensity of the oxygen O1s signal obtained from the silicon (Si) substrate after treatment with HF vapor. Figure 6B The curve 610b shown in the figure represents the decrease in the intensity of the oxygen O1s signal obtained from the silicon (Si) substrate after treatment with HF vapor followed by annealing at 400°C.

[0080] Figure 6C The information described in 600c includes a spectrum depicting the silicon Si 2p core level of silicon oxide (Si), showing the chemical shift core level composition associated with silicon dioxide (SiO2) at a binding energy of 104 electron volts (eV) (as shown in curve 602c), and the same silicon Si 2p core level after etching and deposition of perfluorodecene SAM (as shown in curve 604c), which shows that the oxide has been removed and does not grow back after exposure to air.

[0081] Figure 7A A diagram is shown of example non-limiting information 700a according to one or more embodiments described herein, which may include experimental data from implementations of quantum devices including H-terminated surfaces after removal of the oxide layer. For brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0082] Information 700a may include ultraviolet photoelectron spectra as shown in graph 702a, which illustrates experimental data for an embodiment of a quantum device according to one or more embodiments described herein, comprising an H-terminated silicon (Si) surface formed by removing silicon dioxide (SiO2) using a non-aqueous diluted HF etchant containing trifluoroacetic acid (CF3CO2H).

[0083] Figure 7B An example, non-limiting illustration of information 700b is shown according to one or more embodiments described herein, which may include experimental data from an implementation of a quantum device comprising a self-assembled monolayer formed on the quantum device. For brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0084] Information 700b may include ultraviolet photoelectron spectroscopy displaying experimental data from a realization of a quantum device comprising a self-assembled monolayer formed on the quantum device according to one or more embodiments described herein. Information 700b may include the ultraviolet photoelectron spectrum of a silicon (Si) surface coated with a perfluorodecene (PFD) self-assembled monolayer (e.g., a coated silicon (Si) surface of substrate 102). The molecular structure of the PFD is shown in the altered spectrum. The spectra shown in Figures 702b and 704b are with light of different polarizations ( Figure 7B The P-pol and S-pol samples are collected, and the differences reveal the ordering of self-assembled monolayers (SAMs) on the silicon (Si) surface.

[0085] Figure 7C A diagram illustrating an example, non-limiting information 700c, according to one or more embodiments described herein, may include experimental data from an implementation of a quantum device comprising a self-assembled monolayer formed on the quantum device. For brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0086] Information 700c may include X-ray photoelectron spectroscopy showing experimental data from an implementation of a quantum device comprising a self-assembled monolayer formed on the quantum device according to one or more embodiments described herein. Information 700c may include X-ray photoelectron spectroscopy of a silicon (Si) surface coated with a perfluorodecene (PFD) self-assembled monolayer (e.g., a coated silicon (Si) surface of substrate 102). Figure 7C The curve 702c shown represents the X-ray photoelectron spectrum of a self-assembled monolayer of perfluorodecene (PFD) coated on a silicon (Si) surface (e.g., the coated silicon (Si) surface of substrate 102), which has been treated with trifluoroacetic acid (TFA) for 3 minutes prior to the PFD treatment for 60 minutes. Figure 7C The curve 704c shown represents the X-ray photoelectron spectrum of a self-assembled monolayer of perfluorodecene (PFD) coated on a silicon (Si) surface (e.g., the coated silicon (Si) surface of substrate 102), which has been treated with trifluoroacetic acid (TFA) for 8 minutes prior to the PFD treatment for 60 minutes. Figure 7C The F1s core energy level depicted further indicates that the PFD self-assembles a monolayer.

[0087] Figure 8 A flowchart of an exemplary, non-limiting computer-implemented method 800, according to one or more embodiments described herein, which can facilitate the formation of a self-assembled monolayer on a quantum device, is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0088] In 802, the computer-implemented method 800 may include removing one or more oxide layers from qubits formed on a substrate. See, for example... Figure 1A , 1B In 3A, at 802, the computer-implemented method 800 may include using wet etchant and / or dry etchant processes (e.g., non-aqueous diluted HF etchant with trifluoroacetic acid (CF3CO2H), aqueous hydrogen fluoride (HF) of varying concentrations, buffered etch containing ammonium fluoride (NH4F), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), etc.) to remove a first oxide layer 106 (e.g., silicon dioxide (SiO2)) and / or a second oxide layer 108 (e.g., niobium dioxide (NbO2), niobium pentoxide (Nb2O5), and / or other low oxides) from one or more surfaces of device 100a and / or device 300a. In this example, the substrate 102 and / or superconducting component 104 of device 100a and / or device 300a may constitute qubits.

[0089] In 804, the computer-implemented method 800 may include depositing a self-assembled monolayer on the qubit. See, for example. Figure 1C , 2 At 804, and 3B, the computer-implemented method 800 may include depositing one or more self-assembled monolayers on one or more surfaces of device 100b and / or device 300a using a solution-based self-assembly monolayer deposition process (e.g., using solution 202) or a vapor-phase-based self-assembly monolayer deposition process (e.g., using vapor 110). In this example, the substrate 102 and / or superconducting component 104 of device 100b and / or device 300a may constitute qubits.

[0090] Figure 9 A flowchart of an exemplary, non-limiting computer-implemented method 900, according to one or more embodiments described herein, which can facilitate the formation of a self-assembled monolayer on a quantum device, is shown. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0091] In 902, the computer-implemented method 900 may include removing one or more oxide layers from one or more superconducting components formed on a substrate. See, for example... Figure 1A , Figure 1B and Figure 3AIn 902, the computer-implemented method 900 may include using wet etchant and / or dry etchant processes (e.g., non-aqueous dilute HF etchant with trifluoroacetic acid (CF3CO2H), aqueous hydrogen fluoride (HF) of varying concentrations, buffer etchant containing ammonium fluoride (NH4F), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), etc.) to remove a first oxide layer 106 (e.g., silicon dioxide (SiO2)) and / or a second oxide layer 108 (e.g., niobium dioxide (NbO2), niobium pentoxide (Nb2O5), and / or other low oxides) from one or more surfaces of a superconducting component 104 formed on a substrate 102 of device 100a and / or device 300a.

[0092] In 904, the computer-implemented method 900 may include depositing a self-assembled monolayer on the one or more superconducting components. See, for example. Figure 1C , Figure 2 and Figure 3B At 904, the computer-implemented method 900 may include depositing one or more self-assembled monolayers on one or more surfaces of the superconducting component 104 of device 100b and / or device 300a using a solution-based self-assembly monolayer deposition process (e.g., using solution 202) or a vapor-phase-based self-assembly monolayer deposition process (e.g., using vapor 110).

[0093] Devices 100c, 200, and / or 300b can be associated with different technologies. For example, devices 100c, 200, and / or 300b can be associated with semiconductor and / or superconductor device technology, semiconductor and / or superconductor device fabrication technology, quantum computing device technology, quantum computing device fabrication technology, oxide removal technology, self-assembled monolayer deposition technology, Josephson junction transport device technology, Josephson junction transport device fabrication technology, transport qubit technology, transport qubit fabrication technology, and / or other technologies.

[0094] Devices 100c, 200, and / or 300b can provide technical improvements over the different technologies listed above. For example, utilizing the above-mentioned... Figure 1A-5The oxide removal and self-assembly monolayer deposition processes described in 8 and / or 9 to fabricate devices 100c, 200, and / or 300b can stabilize and / or encapsulate (e.g., seal) one or more components of such a device (e.g., substrate 102, one or more superconducting components 104, qubits, resonators, capacitors, etc.), thereby preventing re-oxidation of one or more surfaces of such components. In embodiments where devices 100c, 200, and / or 300b include quantum devices and / or other superconducting components including qubits and / or quantum devices, by preventing re-oxidation of such surfaces of such qubits and / or other superconducting components, devices 100c, 200, and / or 300b can assist in at least one of improved coherence time (e.g., longer coherence time), improved performance, and / or improved lifetime (e.g., longer lifetime) for such qubits and / or other superconducting components.

[0095] Devices 100c, 200, and / or 300b can provide technological improvements to the processing units associated with devices 100c, 200, and / or 300b. For example, in instances of fabricating devices 100c, 200, and / or 300b using methods and / or materials that protect the components of such devices from re-oxidation based on the description provided above (e.g., substrate 102, superconducting component 104, qubit, resonator, capacitor, etc.), devices 100c, 200, and / or 300b can facilitate improved (e.g., longer) coherence times, thereby promoting improved processing performance of quantum computing devices (e.g., quantum processors) including devices 100c, 200, and / or 300b.

[0096] A practical application of devices 100c, 200, and / or 300b is that they can be implemented in quantum computing devices (e.g., quantum computers) to improve the processing performance of such devices, which can facilitate fast and / or potentially universal quantum computing. This practical application can improve the output (e.g., computational and / or processing results) of one or more compilation jobs (e.g., quantum computing jobs) executed on such devices.

[0097] It should be understood that devices 100c, 200, and / or 300b provide a novel approach to fabricating superconducting devices, driven by relatively new quantum computing technologies. For example, devices 100c, 200, and / or 300b offer a novel approach to fabricating qubit devices (e.g., quantum processors, quantum computers, quantum circuits, quantum hardware, etc.) that can improve the coherence time, performance, and / or lifetime of such qubit devices.

[0098] Devices 100c, 200, and / or 300b can be coupled to hardware and / or software to solve problems that are inherently highly technical, non-abstract, and cannot be performed by humans as a set of mental actions. For example, devices 100c, 200, and / or 300b can be used in semiconductor and / or superconducting devices (e.g., integrated circuits) to realize quantum computing devices capable of processing information and / or performing computations that are non-abstract and cannot be performed by humans as a set of mental actions.

[0099] It should be understood that devices 100c, 200, and / or 300b can utilize various combinations of electrical components, mechanical components, and circuits that cannot be replicated in the human mind or performed by a human. For example, devices 100c, 200, and / or 300b in semiconductor and superconducting devices can enable the operation of quantum computing devices (e.g., quantum processors of quantum computing devices) to exceed the capabilities of the human mind. For example, the amount of data processed, the speed at which such quantum computing devices utilizing devices 100c, 200, and / or 300b process such data in a given time period can be greater, faster, and / or different from the amount, speed, and / or type of data processed by the human mind in the same time period.

[0100] According to several embodiments, devices 100c, 200, and / or 300b may also be fully operable to perform one or more other functions (e.g., full power-on, full execution, etc.) while simultaneously performing the operations described above. It should also be understood that such simultaneous multi-operation execution is beyond the capabilities of the human mind. It should also be understood that devices 100c, 200, and / or 300b may include information that cannot be manually obtained by an entity (e.g., a human user). For example, the type, quantity, and / or diversity of information included in devices 100c, 200, and / or 300b may be more complex than information manually obtained by a human user.

[0101] See above Figure 1A-5 The examples, non-limiting multi-step manufacturing sequences described in 8 and / or 9 can be derived by a computing system (e.g., Figure 10 The operating environment 1000 shown and described below and / or computing devices (e.g., Figure 10The multi-step manufacturing sequence, as shown in the diagram and described below (computer 1012), can be implemented for manufacturing one or more embodiments of the subject matter disclosed herein and / or shown in the accompanying drawings. In a non-limiting exemplary embodiment, such a computing system (e.g., operating environment 1000) and / or such a computing device (e.g., computer 1012) may include one or more processors and one or more memory devices on which executable instructions may be stored, which, when executed by the one or more processors, facilitate execution (see here). Figure 1A-5 The examples, non-limiting multi-step manufacturing operations described in 8 and / or 9. As a non-limiting example, the one or more processors may facilitate the manufacture of one or more systems and / or devices operable to perform the fabrication of semiconductor and / or superconductor devices, as described herein. Figure 1A-5 The execution of non-limiting multi-step manufacturing operations as described in examples 8 and / or 9.

[0102] For the sake of simplicity, the methods described herein (e.g., computer-implemented methods) are depicted and described as a series of actions. It should be understood and recognized that the subject matter innovation is not limited to the actions shown and / or the order of actions; for example, actions may occur in different orders and / or simultaneously, and may occur with other actions not presented or described herein. Furthermore, according to the disclosed subject matter, not all actions shown are necessary to implement the methods described herein (e.g., computer-implemented methods). Moreover, those skilled in the art will understand and appreciate that such methods may alternatively be represented as a series of interrelated states via state diagrams or events. Furthermore, it should be understood that the methods disclosed below and throughout this specification (e.g., computer-implemented methods) can be stored on an article of writing to facilitate the transfer and assignment of such methods (e.g., computer-implemented methods) to a computer. As used herein, the term "article of writing" is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0103] In order to provide context for the various aspects of the disclosed subject, Figure 10 The following discussion is intended to provide a general description of the suitable environment in which the various aspects of the disclosed subject matter can be realized. Figure 10 A block diagram of an example non-limiting operating environment that can facilitate one or more embodiments described herein is shown. For example, operating environment 1000 can be used to implement the embodiments described herein. Figures 1A to 5 , Figure 8 and / or Figure 9The described examples and non-limiting multi-step manufacturing operations facilitate the implementation of one or more embodiments of the subject matter disclosed herein. For the sake of brevity, repeated descriptions of similar elements and / or processes employed in other embodiments described herein are omitted.

[0104] refer to Figure 10 The suitable operating environment 1000 for implementing various aspects of this disclosure may also include a computer 1012. The computer 1012 may further include a processing unit 1014, system memory 1016, and a system bus 1018. The system bus 1018 couples system components, including but not limited to system memory 1016, to the processing unit 1014. The processing unit 1014 may be any processor among various available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 1014. The system bus 1018 may be any of several types of bus architectures, including memory buses or memory controllers, peripheral buses or external buses, and / or local buses using any of the various available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI).

[0105] System memory 1016 may also include volatile memory 1020 and non-volatile memory 1022. The Basic Input / Output System (BIOS) is stored in the non-volatile memory 1022, and the BIOS contains basic routines for transferring information between components within the computer 1012, such as during startup. The computer 1012 may also include removable / non-removable, volatile / non-volatile computer storage media. Figure 10 Disk storage 1024 is illustrated, for example. Disk storage 1024 may also include, but is not limited to, devices such as disk drives, floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. Disk storage 1024 may also include storage media, either alone or in combination with other storage media. To facilitate connection of disk storage 1024 to system bus 1018, a removable or non-removable interface, such as interface 1026, is typically used. Figure 10 Software that acts as an intermediary between the user and the basic computer resources described in the suitable operating environment 1000 is also described. Such software may also include, for example, an operating system 1028. The operating system 1028, which may be stored on disk storage 1024, is used to control and allocate the resources of computer 1012.

[0106] System application 1030 utilizes resource management by operating system 1028 through program modules 1032 and program data 1034 stored, for example, in system memory 1016 or disk storage 1024. It should be understood that this disclosure can be implemented using different operating systems or combinations of operating systems. Users input commands or information into computer 1012 via input device 1036. Input device 1036 includes, but is not limited to, pointing devices such as a mouse, trackball, pen, touchpad, keyboard, microphone, joystick, gamepad, disc satellite dish, scanner, TV tuner card, digital camera, digital camcorder, webcam, etc. These and other input devices are connected to processing unit 1014 via system bus 1018 through one or more interface ports 1038. Interface ports 1038 include, for example, serial ports, parallel ports, game ports, and Universal Serial Bus (USB). Output device 1040 uses some of the same type of ports as input device 1036. Thus, for example, a USB port can be used to provide input to computer 1012 and to output information from computer 1012 to output device 1040. Output adapter 1042 is provided to illustrate that, in addition to other output devices 1040 that require special adapters, there are other output devices 1040, such as monitors, speakers, and printers. By way of illustration and not limitation, output adapter 1042 includes video and sound cards that provide a connection between output device 1040 and system bus 1018. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer 1044.

[0107] Computer 1012 can operate in a networked environment using a logical connection to one or more remote computers (such as remote computers 1044). Remote computer 1044 can be a computer, server, router, network PC, workstation, microprocessor-based appliance, peer-to-peer device, or other public network node, and typically may also include many or all of the elements described relative to computer 1012. For simplicity, memory storage device 1046 is described using only remote computer 1044 as an example. Remote computer 1044 is logically connected to computer 1012 via network interface 1048 and then physically connected via communication connection 1050. Network interface 1048 includes wired and / or wireless communication networks, such as local area networks (LANs), wide area networks (WANs), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Wire Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks (such as Integrated Services Digital Network (ISDN)) and its variants, packet-switched networks, and Digital Subscriber Line (DSL). Communication connection 1050 refers to the hardware / software used to connect network interface 1048 to system bus 1018. Although communication connection 1050 is shown inside computer 1012 for clarity, it may also be outside computer 1012. For illustrative purposes only, the hardware / software used to connect to network interface 1048 may also include internal and external technologies such as modems, including conventional telephone-grade modems, cable modems and DSL modems, ISDN adapters and Ethernet cards.

[0108] This invention can be a system, method, apparatus, and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention. The computer-readable storage medium may be a tangible means for retaining and storing instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media may also include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital universal disk (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or protrusions in slots having instructions recorded thereon, and any suitable combination thereof. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0109] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or downloaded to an external computer or external storage device. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device. The computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). Computer-readable program instructions may execute entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may be personalized to execute computer-readable program instructions by utilizing state information of the computer-readable program instructions in order to perform aspects of the present invention.

[0110] The present invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of manufacture containing instructions that implement aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operations to be performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, such that the instructions executed on the computer, other programmable apparatus, or other device perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0111] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0112] While the subject matter has been described above in the general context of computer-executable instructions running on a computer and / or a computer program product on a computer, those skilled in the art will recognize that this disclosure may also be implemented in combination with other program modules. Typically, program modules include routines, programs, components, data structures, etc., that perform specific tasks and / or implement specific abstract data types. Furthermore, those skilled in the art will recognize that the computer-implemented methods of the present invention can be practiced with other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic products, etc. The aspects shown can also be implemented in a distributed computing environment, where tasks are performed by remote processing devices linked via a communication network. However, some (if not all) aspects of the invention can be practiced on a standalone computer. In a distributed computing environment, program modules may reside in both local and remote memory storage devices. For example, in one or more embodiments, computer-executable components may be executed from memory that may include or comprise one or more distributed memory cells. As used herein, the terms “memory” and “memory cell” are interchangeable. Furthermore, one or more embodiments described herein are capable of executing code from computer executable components in a distributed manner, for example, multiple processors working together or cooperating to execute code from one or more distributed memory units. As used herein, the term "memory" can include a single memory or memory unit at one location or multiple memory or memory units at one or more locations.

[0113] As used herein, the terms “component,” “system,” “platform,” “interface,” etc., may refer to and / or include computer-related entities or entities associated with an operating machine having one or more specific functions. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. For illustration, both an application running on a server and the server itself can be components. One or more components may reside within a process and / or a thread of execution, and components may reside on a single computer and / or be distributed across two or more computers. In another instance, a corresponding component may be executed from a different computer-readable medium having different data structures stored thereon. Components may communicate via local and / or remote processes, such as according to a signal having one or more data packets (e.g., data from a component interacting with another component in a local system, a distributed system, and / or data from a component interacting with other systems across a network such as the Internet via that signal). As another example, a component may be a device having specific functions provided by mechanical parts operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In such a case, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As another example, the component can be a device that provides a specific function through electronic components without mechanical parts, wherein the electronic components can include a processor or other means for performing software or firmware that at least partially endows the electronic components with the functions. In one aspect, the component can be emulated via a virtual machine, for example, within a cloud computing system.

[0114] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to mean any natural inclusive permutation. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing cases. Additionally, the articles "a" and "an" as used in the subject matter specification and figures should generally be interpreted as meaning "one or more," unless otherwise specified or clearly indicated from the context to the singular form. As used herein, the terms "example" and / or "exemplary" are used to indicate that something is used as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. Furthermore, any aspect or design described herein as an "example" and / or "exemplary" is not necessarily to be construed as superior to or better than other aspects or designs, nor does it imply the exclusion of equivalent exemplary structures and techniques known to those skilled in the art.

[0115] As used herein, the term "processor" can refer to substantially any computing processing unit or device, including but not limited to: a single-core processor; a single processor with software multithreading capabilities; a multi-core processor; a multi-core processor with software multithreading capabilities; a multi-core processor with hardware multithreading technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, "processor" can refer to an integrated circuit, application-specific integrated circuit (ASIC), digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic controller (PLC), complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, processors can utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user devices. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as "storage," "memory," "data storage," "data memory," "database," and substantially any other information storage component, as used in relation to the operation and function of a component, are used to refer to a "memory component," an entity embodied in "memory," or a component that includes memory. It should be understood that the memory and / or memory components described herein can be volatile or non-volatile memory, or may include both volatile and non-volatile memory. By way of example and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include, for example, RAM that can serve as an external cache memory. By way of illustration and not limitation, RAM can be obtained in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Furthermore, the memory components of the systems or computer-implemented methods disclosed herein inherently include (but are not limited to) these and any other suitable types of memory.

[0116] The above description includes only examples of systems and computer-implemented methods. Of course, for the purposes of describing this disclosure, it is impossible to describe every conceivable combination of components or computer-implemented method; however, those skilled in the art will recognize that many further combinations and substitutions of this disclosure are possible. Furthermore, the terms “comprising,” “having,” “possessing,” etc., used in the detailed description, claims, appendices, and drawings are intended to be inclusive in a manner similar to the term “including,” since inclusion is interpreted as such when “comprising” is used as a transitional word in the claims.

[0117] Various embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A quantum device, comprising: A quantum device formed on a substrate, wherein the quantum device comprises qubits, at least one surface of the quantum device comprises a niobium-based material, and at least one surface of the quantum device has one or more oxide layers removed; and A self-assembled monolayer is formed on at least one surface of the quantum device, wherein the self-assembled monolayer is formed by depositing an organic component containing thiols on at least one surface of the quantum device, wherein the thiols in the organic component interact with a niobium-based material on at least one surface of the quantum device, such that the organic component is formed on at least one surface of the quantum device.

2. The device according to claim 1, wherein, The self-assembled monolayer is formed on the qubit and the substrate.

3. The device according to claim 1, wherein, Removing one or more oxide layers involves using a diluted etchant that can hydrogen-capture at least one surface of the quantum device and / or the substrate surface.

4. The device according to claim 1, wherein, Depositing an organic component containing thiols on at least one surface of the quantum device includes using solution deposition processes and / or vapor deposition processes.

5. The device according to claim 1, wherein, in, The self-assembled monolayer on at least one surface of the quantum device can prevent oxidation of at least one surface of the quantum device, thereby promoting at least one of improved coherence time or improved lifetime of the quantum device.

6. A method for forming a self-assembled monolayer on a quantum device, comprising: Remove one or more oxide layers from at least one surface of a quantum device formed on a substrate, wherein at least one surface of the quantum device comprises a niobium-based material, and wherein the quantum device comprises qubits; and An organic component comprising thiols is deposited on at least one surface of the quantum device, wherein the thiols in the organic component interact with a niobium-based material on at least one surface of the quantum device, such that the organic component forms a self-assembled monolayer on at least one surface of the quantum device.

7. The method of claim 6, further comprising: Remove one or more second oxide layers from the substrate; as well as The self-assembled monolayer is deposited on the substrate.

8. The method according to claim 7, wherein, Removing one or more oxide layers involves using a diluted etchant that can hydrogen-capture at least one surface of the quantum device and / or the substrate surface.

9. The method according to claim 6, wherein, Depositing an organic component containing thiols on at least one surface of the quantum device includes using solution deposition processes and / or vapor deposition processes.

10. The method according to claim 6, wherein, The self-assembled monolayer on at least one surface of the quantum device can prevent oxidation of at least one surface of the quantum device, thereby contributing to at least one of improved coherence time or improved lifetime of the qubit.

11. A qubit device, comprising: One or more superconducting components are formed on a substrate, wherein at least one surface of the superconducting component contains a niobium-based material, and at least one surface of the superconducting component has one or more oxide layers removed; as well as A self-assembled monolayer formed on one or more superconducting components, wherein the self-assembled monolayer is formed by depositing an organic component containing thiols on at least one surface of the superconducting component, wherein the thiols in the organic component interact with a niobium-based material on at least one surface of the superconducting component, such that the organic component is formed on at least one surface of the superconducting component.

12. The device according to claim 11, wherein, The self-assembled monolayer is formed on the one or more superconducting components and the substrate.

13. The device according to claim 12, wherein, Removing one or more oxide layers involves using a diluted etchant that can hydrogen-capture at least one surface of the superconducting component and / or the substrate surface.

14. The device according to claim 11, wherein, Depositing an organic component containing thiols on at least one surface of the superconducting component includes solution deposition processes and / or vapor deposition processes.

15. The device according to claim 11, wherein, The self-assembled monolayer on at least one surface of the superconducting component can prevent oxidation of at least one surface of the one or more superconducting components, thereby contributing to at least one of improved coherence time or improved lifetime of the superconducting component.

16. A method for forming a self-assembled monolayer on a superconducting component, comprising: Remove one or more oxide layers from at least one surface of one or more superconducting components formed on a substrate, wherein at least one surface of the superconducting component comprises a niobium-based material; and An organic component comprising thiols is deposited on at least one surface of the superconducting component, wherein the thiols in the organic component interact with a niobium-based material on at least one surface of the superconducting component, such that the organic component forms a self-assembled monolayer on at least one surface of the superconducting component.

17. The method of claim 16, further comprising: Remove one or more second oxide layers from the substrate; as well as The self-assembled monolayer is deposited on the substrate.

18. The method according to claim 17, wherein, Removing one or more oxide layers involves using a diluted etchant that can hydrogen-capture at least one surface of the superconducting component and / or the substrate surface.

19. The method of claim 16, wherein, Depositing an organic component containing thiols on at least one surface of the superconducting component includes solution deposition processes and / or vapor deposition processes.

20. The method of claim 16, wherein, A self-assembled monolayer on at least one surface of the superconducting component can prevent oxidation of at least one surface of the superconducting component, thereby contributing to at least one of improved coherence time or improved lifetime of the superconducting component.

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