Gate interface engineering using a doped layer

Abstract

Processing methods can be performed to produce a semiconductor structure. These methods may include forming a silicon layer on a semiconductor substrate. This formation may include forming a silicon layer incorporating a dopant. These methods may include oxidizing a portion of the silicon layer while maintaining that portion in contact with the semiconductor substrate. This oxidation may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 63 / 040,107, filed June 17, 2020, entitled “GATE INTERFACE ENGINEERING WITH DOPED LAYER”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This technology relates to semiconductor systems, processes, and equipment. More specifically, this technology relates to processes for enhancing gate structures. Background Technology

[0004] Logic gate performance is related to the properties of the materials used, as well as the thickness and area of ​​the structural layers. However, challenges arise as some gate characteristics are tuned to accommodate device scaling. For example, for silicon oxide gate dielectrics, capacitance can improve with decreasing thickness, leading to higher channel mobility and faster device performance. However, as thickness continues to decrease, gate leakage can affect the device and potentially reduce yield. Additionally, thinner oxide layers may result in lower quality and short circuits. High-k materials have been employed for gate dielectrics to reduce effective oxide thickness while limiting their impact on gate leakage current. However, efforts to maximize the performance of specific high-k materials have been limited due to morphology issues associated with their formation.

[0005] Therefore, there is a need for improved systems and methods that can be used to maximize the properties of high-k materials and enable the production of high-quality devices and structures. This technology addresses these and other needs. Summary of the Invention

[0006] Processing methods can be performed to produce a semiconductor structure. These methods may include forming a silicon layer on a semiconductor substrate. This formation may include forming a silicon layer incorporating a dopant. These methods may include oxidizing a portion of the silicon layer while maintaining the portion of the silicon layer in contact with the semiconductor substrate. This oxidation may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

[0007] In some embodiments, the silicon layer may be formed by atomic layer deposition or epitaxial growth. The dopant may be or include one or more of nitrogen, phosphorus, or fluorine. The silicon layer may be formed to a thickness of less than or about 5 nm. Oxidation of a portion of the silicon layer may form a sacrificial oxide, and this method may further include removing the sacrificial oxide. This removal may include an in-situ dry chemical process. This removal may be performed in a first processing chamber, and these methods may further include forming an oxygen-containing material. These methods may include transferring a semiconductor substrate from a first processing chamber to a second processing chamber. These methods may include forming a high-k dielectric material covering the oxygen-containing material. Prior to forming the high-k dielectric material, these methods may include introducing reactive ligands onto the oxygen-containing material using a nitrogen-containing precursor or an oxygen-containing precursor.

[0008] The nitrogen-containing precursor may be or includes ammonia. The high-k dielectric material may be or includes at least one element selected from the group consisting of hafnium, zirconium, silicon, lanthanum, aluminum, titanium, or strontium. This method can be performed in one or more processing chambers without exposing the semiconductor substrate to the atmosphere. A silicon layer may be epitaxially formed on the semiconductor substrate, and the semiconductor substrate may be or includes silicon-germanium. Oxidating a portion of the silicon layer can form a sacrificial oxide, and the formation of the sacrificial oxide may include a first oxidation process. During this method, partial oxidation of the silicon layer in contact with the semiconductor substrate may include a second oxidation process different from the first oxidation process. Partial oxidation of the silicon layer in contact with the semiconductor substrate may include delivering a nitrogen- and oxygen-containing precursor to the semiconductor substrate. Partial oxidation of the silicon layer in contact with the semiconductor substrate may occur at a temperature below or about 750°C.

[0009] Some embodiments of this technology may cover methods for forming semiconductor structures. These methods may include removing oxides from the surface of a substrate contained within a semiconductor processing chamber. The substrate may be or include silicon-germanium fins. These methods may include forming a silicon layer on the semiconductor substrate. This formation may include forming a silicon layer incorporating nitrogen, fluorine, or phosphorus as dopants. These methods may include oxidizing the silicon layer to form a sacrificial oxide. This oxidation may allow a portion of the dopant to diffuse through the silicon layer and into the semiconductor substrate. These methods may include removing the sacrificial oxide. These methods may include delivering nitrous oxide to the substrate to form an oxygen-containing material. These methods may include pre-processing the oxygen-containing material by contacting the substrate with a nitrogen-containing precursor. These methods may include forming a high-k dielectric material covering the pre-processed oxygen-containing material.

[0010] In some embodiments, removal may include an in-situ dry chemical process. This removal may be performed in a first processing chamber. The method may also include transferring the substrate from the first processing chamber to a second processing chamber prior to forming a high-k dielectric material. The silicon layer may be formed by atomic layer deposition or epitaxial growth, and the silicon layer may be formed to a thickness of less than or approximately 5 nm. Forming the sacrificial oxide may include delivering oxygen-containing precursors and hydrogen-containing precursors to the substrate to form an oxygen-containing material.

[0011] Some embodiments of this technology may cover methods for forming semiconductor structures. These methods may include removing intrinsic oxide from the surface of a substrate contained within a semiconductor processing chamber. The substrate may include silicon or germanium. These methods may include forming a silicon layer on the semiconductor substrate. This formation may include forming a silicon layer incorporating dopants. These methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining the portion of the silicon layer in contact with the semiconductor substrate. This oxidation may drive a portion of the dopant through the silicon layer and into the semiconductor substrate. These methods may include removing the sacrificial oxide.

[0012] Such techniques offer numerous advantages over conventional systems and techniques. For example, these processes allow dopants to be incorporated into the channel regions of the semiconductor structure and produce a high-quality oxide layer of gate oxide. Furthermore, the formation of the gate oxide limits oxidation propagation into the underlying layers. These and other embodiments, along with their many advantages and features, are described in more detail below with reference to the accompanying drawings. Attached Figure Description

[0013] A further understanding of the nature and advantages of the disclosed technology can be achieved by referring to the remainder of the specification and the accompanying drawings.

[0014] Figure 1 A top plan view of an exemplary processing system according to an embodiment of the present technology is shown.

[0015] Figure 2 Selected operations in a method for forming a semiconductor structure according to an embodiment of the present technology are shown.

[0016] Figures 3A-3I A schematic cross-sectional view of an exemplary substrate according to an embodiment of the present technology is shown.

[0017] Several diagrams are included as illustrations. It should be understood that these diagrams are for illustrative purposes and are not considered to be drawn to scale unless specifically stated otherwise. Furthermore, as illustrations, these diagrams are provided to aid understanding and may not include all aspects or information compared to a realistic representation, and may include exaggerated material for illustrative purposes.

[0018] In the accompanying drawings, similar parts and / or features may have the same reference numerals. Furthermore, various parts of the same type may be distinguished by adding letters after the reference numerals to differentiate them. If only a first reference numeral is used in the specification, this description applies to any part of a similar component having the same first reference numeral, regardless of the letters used. Detailed Implementation

[0019] As logic gate structures are scaled down to smaller dimensions, new material structures are being sought to provide improvements. The use of high-k dielectrics increases the dielectric constant of gate stacks compared to traditional gate stacks utilizing materials such as silicon oxide. However, similar to silicon oxide, gate leakage current increases as the material thickness decreases. For example, gate leakage current increases with decreasing effective oxide thickness. Therefore, the inverse correlation between gate leakage current and effective oxide thickness can limit the performance of transistors and the resulting devices.

[0020] For FinFET structures, the gate oxide covering the fins performs multiple functions. For example, the gate oxide can form a conductive channel region beneath the gate. Defects or voids within the gate oxide, such as those formed from lower-quality oxides, can cause short circuits and structural damage. Additionally, the gate oxide can prevent germanium diffusion in the PFET or P-MOS regions of the device. Conventional techniques typically use wet oxidation techniques, such as chemox, along with other oxidation methods to form the gate oxide. Conventional techniques produce lower-quality oxide layers that are not well controlled, potentially leading to over-oxidation into the fins. This can result in less robust germanium oxide materials that are more prone to failure under thermal or electrical stress. This technology overcomes these problems by forming a controlled gate oxide layer from a defined silicon-containing material. These gate oxide layers limit over-oxidation of the SiGe fin material and provide improved electrical and thermal performance compared to conventional techniques. This technology also provides a mechanism for incorporating dopants into the channel regions and other substrate structures using the overlying layer.

[0021] While the remainder of the disclosure will routinely identify specific deposition and processing techniques utilizing the disclosed technology, it will be readily understood that these systems and methods are equally applicable to a variety of other processes that may occur in the described chambers. Accordingly, this technology should not be considered limited to use with the described processing and deposition processes. Before describing the operation of exemplary process sequences according to this technology, this disclosure will discuss a possible system that can be used with this technology to perform certain elements of a deposition or processing operation. It should be understood that this technology is not limited to the described apparatus, and the discussed processes can be performed in any number of processing chambers and systems.

[0022] Figure 1 A top plan view of one embodiment of a processing system 100 for deposition, etching, baking, and / or curing chambers according to an embodiment is shown. Figure 1The tool or processing system 100 depicted may include a plurality of process chambers 114A-114D, a transfer chamber 110, a maintenance chamber 116, an integrated metering chamber 117, and a pair of loading and locking chambers 106A-106B. The process chambers may include any number of structures or components, and any number or combination of processing chambers. It should be understood that system 100 is not intended to limit the tools that can be incorporated into chambers for performing the processes described below. According to some embodiments of the present technology, any tool, including any number of chambers, may also be used.

[0023] For transferring substrates between chambers, transfer chamber 110 may include a robotic transfer mechanism 113. Transfer mechanism 113 may have a pair of substrate transfer blades 113A respectively attached to the distal end of an extendable arm 113B. Blades 113A can be used to carry individual substrates to and from process chambers. In operation, one of the substrate transfer blades, such as blades 113A of transfer mechanism 113, can retrieve substrate W from one of the loading locking chambers, such as chambers 106A-106B, and carry substrate W to a first processing stage, for example, the processing described below in chambers 114A-114D. Chambers may be included to perform individual or combined operations of the described techniques. For example, while one or more chambers may be configured to perform deposition or formation operations, one or more other chambers may be configured to perform the described pre-processing operations and / or one or more post-processing operations. This technology covers any number of configurations and can also perform any number of additional manufacturing operations typically performed in semiconductor processing.

[0024] If a chamber is occupied, the robot can wait until processing is complete, and then remove the processed substrate from the chamber using a blade 113A, with a second blade (not shown) available to insert a new substrate. Once a substrate has been processed, it can then be moved to a second processing stage. For each move, the transfer mechanism 113 typically has one blade carrying the substrate and an empty blade to perform the substrate exchange. The transfer mechanism 113 can wait at each chamber until an exchange is possible.

[0025] Once processing is complete within the process chamber, transfer mechanism 113 can move substrate W from the final processing chamber and transfer substrate W to a cassette within loading and locking chambers 106A-106B. The substrate can then be moved from loading and locking chambers 106A-106B to the factory interface 104. Factory interface 104 is typically operable to transfer substrates between cassette loaders 105A-105D and loading and locking chambers 106A-106B in a clean atmospheric pressure environment. The clean environment in factory interface 104 is typically provided via an air filtration process such as HEPA filtration. Factory interface 104 may also include a substrate orienter / aligner (not shown) for properly aligning the substrate prior to processing. At least one substrate robot, such as robots 108A-108B, may be positioned within factory interface 104 to transfer substrates between various locations / positions within factory interface 104 and to other locations communicating with factory interface 104. Robots 108A-108B can be configured to travel from the first end to the second end of the factory interface 104 along a track system within the factory interface 104.

[0026] The processing system 100 may further include an integrated metrology chamber 117 to provide control signals, which can provide adaptive control over any process performed within the processing chamber. The integrated metrology chamber 117 may include any of a variety of metrology devices to measure various film properties, such as thickness, roughness, and composition, and the metrology devices may further be capable of automatically characterizing grating parameters such as critical dimensions, sidewall angles, and characteristic heights under vacuum.

[0027] Each of the processing chambers 114A-114D can be configured to perform one or more process steps in the fabrication of a semiconductor structure, and any number of processing chambers and combinations thereof can be used in the multi-chamber processing system 100. For example, any of the processing chambers can be configured to perform a number of substrate processing operations, including any number of deposition processes, including cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other operations, including etching, pre-cleaning, pre-processing, post-processing, annealing, plasma treatment, degassing, orientation, and other substrate processes. Some specific processes that can be performed in any of the chambers or any combination of chambers may be metal deposition, surface cleaning and preparation, thermal annealing such as rapid thermal processing, and plasma treatment. Those skilled in the art will readily understand that any other process can be similarly performed in a specific chamber incorporated into the multi-chamber processing system 100, including any of the processes described below.

[0028] Figure 2The illustration depicts a method 200 for forming a semiconductor structure. The operation of method 200 can be performed, for example, in one or more chambers incorporated into the multi-chamber processing system 100 as described above or any other multi-chamber system. Method 200 may include one or more operations prior to the commencement of the method operations, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. This method may include a number of optional operations as shown, which may or may not be specifically associated with the method according to the present technology. For example, many operations are described to provide a broader range of structure formation processes, but these operations are not critical to the technology or may be performed by alternative methods as discussed further below. Method 200 Description Figures 3A-3I The operations illustrated in Figure 3 are described in conjunction with the operations of method 200. It should be understood that Figure 3 only illustrates a partial schematic diagram, and the substrate may contain any number of transistor segments and additional materials having the aspects shown in the figures.

[0029] Method 200 may involve optional operations to advance the semiconductor structure to a specific manufacturing operation. While in some embodiments method 200 may be performed on a substrate structure, in other embodiments this method may be performed after other materials have been formed. For example... Figure 3A As shown, the semiconductor structure may represent device 300 after some processing has been completed. For example, substrate 305 may be a planar material or may be a structured device. Substrate 305 may include one or more materials configured to define pillars, trenches, or other structures, as will be understood from the similarly covered aspects of this art. Substrate 305 may include any number of materials, including silicon, silicon germanium, or silicon-containing materials such as oxides, nitrides, and carbides of silicon, as well as any other materials that may be incorporated into the structure. In some embodiments covered by this art, substrate 305 may be part of a silicon germanium fin, such as a part that may be associated with a FinFET structure, and may be part of a P-MOS region. Prior to method 200, a layer of silicon germanium may be formed on a silicon substrate or other substrate and may be patterned to form a fin structure. An isolation dielectric may be formed around the fins, and trimming operations may be performed to thin the upper portion of the fins. It should be understood that this figure is not drawn to any particular scale.

[0030] Following this process or as a result of substrate transfer, substrate 305 may include residual particulate material on the surface of intrinsic oxide 310 or silicon-germanium, such as Figure 3AAs shown in the illustration. In some embodiments, exposed material on the surface of substrate 305 may be etched, planarized, or otherwise treated to create intermittent patterns. Although illustrated as a single example, it should be understood that device 300 may include smaller segments of larger process integrations, which may include any number of additional segments that may be similar to or different from the illustrated object. For example, N-MOS regions may be located adjacent to the illustrated structure and may include any amount of patterning or manipulation performed together with or separately from the described methods. Substrate 305 may be housed or positioned in a processing region of a semiconductor processing chamber, and method 200 may be performed to generate semiconductor material, such as a high-k dielectric material, on the substrate.

[0031] Method 200 may include removing intrinsic oxide 310 from substrate 305 in optional operation 205. Removal of intrinsic oxide 310 may be performed by any number of processes. For example, it may be performed by reduction using a hydrogen-containing precursor, which reduces the oxide to ensure a relatively clean surface for silicon-germanium. Alternatively, this process may include a plasma process or processing that may include a fluorine-containing precursor and a hydrogen-containing precursor. The fluorine-containing precursor may be or include nitrogen trifluoride and any other fluorine-containing precursor. The hydrogen-containing precursor may be characterized by an amino group [-NH2] or other nitrogen- or hydrogen-containing groups. For example, the hydrogen-containing precursor may be or include a nitrogen- and hydrogen-containing precursor, such as ammonia as a non-limiting example. The plasma may be generated locally or in a remote plasma region that can be fluidly coupled to the substrate processing area. The flow rates of the fluorine-containing precursor and the hydrogen-containing precursor may be controlled to maintain a hydrogen to fluorine atom flow ratio of less than 1:2. Oxide 310 or residual material may be removed by plasma effluent 315, such as... Figure 3B (A process that may also include thermal processing to remove byproducts using a self-etching process) is shown in the figure.

[0032] The removal of intrinsic oxides in operation 205 can be performed by an in-situ dry chemical process, wherein the substrate surface may not be exposed to the atmosphere or an oxygen-containing environment. In some embodiments of method 200, the removal of intrinsic oxides in operation 205 may be performed in a first processing chamber. Method 200 may include transferring the substrate from the first processing chamber to a second processing chamber prior to the formation of a high-k dielectric material, as will be explained below. Method 200 may include performing operations in one or more processing chambers, such as by maintaining a vacuum within system 100 while transferring the substrate between one or more chambers for operation of method 200, without exposing the substrate surface to the atmosphere or air. Maintaining an integrated vacuum can advantageously reduce surface contamination and the formation of unwanted oxides. Transfer may occur between one or more chambers on a single platform, or may occur between chambers on multiple platforms. However, by utilizing a single platform, it is better to ensure that the substrate is not exposed to an oxygen-containing environment.

[0033] In operation 210, a silicon-containing material may be formed or deposited on a pre-processed or cleaned substrate surface. For example, a silicon layer or a silicon-containing material such as doped silicon, alloyed silicon, or silicon-to-metal or silicon-to-metal materials may be formed or deposited by any number of methods to form layer 320 covering the surface of substrate 305, such as... Figure 3C As shown in the diagram. In some non-limiting embodiments, silicon can be conformally epitaxially grown on the surface of a silicon-germanium fin. Alternatively, an atomic layer deposition process can be performed to produce a silicon layer conformally deposited or formed on the substrate. Conformal formation allows for controllable thickness compared to conventional deposition techniques. This layer can be formed to any height and can produce relatively high-quality silicon. For example, in various embodiments, silicon layer 320 can be formed to a height of a few angstroms or a few nanometers. In some embodiments, this layer can be formed to a thickness of less than or about 10.0 nm, and can be formed to a thickness of less than or about 8.0 nm, less than or about 5.0 nm, less than or about 4.0 nm, less than or about 3.0 nm, less than or about 2.0 nm, less than or about 1.0 nm, less than or about [missing information - likely a number]. Less than or approximately Or even a thinner thickness.

[0034] In some implementations, the silicon layer may be formed as amorphous silicon and may include dopant materials during the formation process. For example... Figure 3C As shown, dopant particles 321 can be incorporated into the silicon layer during deposition. The dopant can be delivered as an additional precursor, which can further interact with one or more silicon-containing precursors or other deposition precursors or a carrier gas to incorporate the dopant particles into the forming silicon material. Exemplary dopant materials can be nitrogen, phosphorus, fluorine, or any other material that can be incorporated into the silicon structure. While materials can be delivered in forms that allow for easier dissociation to limit the incorporation of additional materials within the silicon layer, materials can be delivered in any quantity. For example, exemplary precursors may include diatomic nitrogen, nitrogen trifluoride, fluorine, hydrogen fluoride, phosphine, or any other nitrogen-, fluorine-, or phosphorus-containing material.

[0035] After the silicon layer is formed, a portion of this layer can be oxidized at operation 215. Oxidation can be performed in any number of ways, and oxidation can completely oxidize the layer, although the oxidation may not extend completely through the silicon layer. Oxidation operation 215 can generate sacrificial oxide 322 by converting a portion of the silicon layer 320 into silicon oxide until the entire silicon layer is converted into silicon oxide. Oxidation operation 215 can oxidize a portion of the silicon layer 320 while at least partially maintaining a portion of the silicon layer 320 in contact with the semiconductor substrate 305. For example, controlled oxidation can be performed to limit the oxidation extension through the silicon-containing layer. Operation 215 may include a heat-based reaction using steam, such as an in-situ steam generation process, whereby oxidation occurs at a lower rate compared to conventional thermal techniques. Alternatively, oxidation can be performed as a thermal oxidation process utilizing hydrogen and oxygen, as well as utilizing additional precursors. For example, in some embodiments, oxygen-containing precursors, such as nitrogen- and oxygen-containing precursors, can be used. For example, nitrous oxide, or some other nitrogen- and oxygen-containing precursors, and / or additional precursors such as, for example, hydrogen, can be used to partially oxidize the silicon-containing material.

[0036] Nitrogen can be used as an oxygen carrier and may not be part of the interface or substrate. The process can also occur slowly, resulting in more controlled oxidation, and can be controlled to maintain a specific thickness of silicon along the surface of substrate 305. After the sacrificial oxide is formed, several other fabrication operations can occur, including forming a dummy polymask, followed by the formation of a dummy gate on the substrate. After the processing has been performed, a gate oxide formation process can occur, as will be further described below.

[0037] Oxidation processes can also be used to facilitate additional operations. For example, by incorporating the dopant into the silicon layer, oxidation processes can be used to thermally drive the dopant 321 through the silicon layer and into the underlying substrate, such as... Figure 3D As shown in the diagram. For example, oxidation temperature allows dopant material to fully diffuse through the silicon layer and incorporate into the underlying material. Incorporating fluorine, nitrogen, or phosphorus into the substrate (such as into the underlying channel region that may be located below the gate to be formed) can improve the operational performance and reliability of the formed device. Although doping can be performed during the development of the underlying channel region, subsequent incorporation of the dopant during the oxidation operation ensures high-quality formation across the channel region. Furthermore, this formation can occur without incorporating excessive amounts of other components of the dopant material (such as hydrogen or other components of the dopant delivered in the form of precursors).

[0038] One or more removal operations can be performed at optional operation 220 to remove the sacrificial oxide covering the held silicon 320. For example... Figure 3EAs shown, the retained silicon is characterized by being thick enough to maintain a coating thickness on the silicon-germanium substrate material. For example, in some embodiments, the silicon layer 320 may be maintained at less than or about 5 nm, and may be maintained at less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, less than or about [missing information - likely a specific thickness]. Or smaller. Removal operations may include selective etching, such as oxide selective etching. In some embodiments, plasma etching processes, such as plasma etching processes using fluorine-containing and hydrogen-containing precursors, may be performed. Removal operations may include any of the operations described above, such as by plasma etching using nitrogen trifluoride and ammonia; removal operations may also include additional thermal processing or sublimation operations. Additional or alternative fluorine- and hydrogen-containing precursors may also be used in some embodiments. By performing an oxide selective etching process at operation 220, the underlying portion of the silicon may be retained or substantially retained.

[0039] After exposing the silicon cap material, a second oxidation operation can be performed to oxidize the remaining silicon material layer covering the silicon-germanium fins. At optional operation 225, any of the operations in the previous oxidation operations can be performed to produce, as... Figure 3F The oxygen-containing material 324 shown is, for example, silicon oxide. In some embodiments, the remaining silicon material can be completely converted into silicon oxide, and there may be no residual silicon layer left. In some embodiments, as explained above, oxidation can utilize nitrous oxide and hydrogen. This tightly controls oxidation to be substantially limited to the silicon material, while limiting or preventing over-oxidation into the silicon-germanium material. As explained above, such a thermal oxidation process can provide many advantages. For example, unlike wet oxidation, the oxidation in this case can produce high-quality oxides, which can limit germanium diffusion.

[0040] Furthermore, some conventional oxidation processes, including wet and dry oxidation processes, may over-oxidize silicon-germanium, resulting in germanium oxide material. Compared to silicon oxide, germanium oxide is characterized by less stable bonding, and therefore, subsequent operations can disrupt germanium oxide bonds. This can damage the formed oxide or reduce the quality of the interfaces between materials, thereby limiting transistor efficiency or damaging the device. Forming high-quality oxides can also beneficially protect the structure in subsequent operations. For example, conventional processes that produce lower-density oxides can further degrade with additional manufacturing operations. As will be explained below, additional high-k dielectric operations and subsequent manufacturing processes that may include high-temperature processes can be performed. For example, at some point during manufacturing, flash annealing may be performed at temperatures up to 1000°C. For lower-quality or lower-density oxides, this may promote additional germanium diffusion due to the more porous oxide structure. According to some embodiments of the present technology, a denser thermal oxide process can prevent diffusion during subsequent manufacturing operations. According to embodiments of the present technology, by maintaining control over oxidation, high-quality oxide material with a specific depth can be provided with any of the aforementioned reduced thicknesses.

[0041] The resulting oxygen-containing material can be of high quality and highly ordered, meaning it has a crystal structure with no or substantially no defects. This provides an interface that prevents additional material from approaching the channel region, thus preventing leakage. The resulting oxygen-containing material 324 may include silicon dioxide. The formed oxygen-containing material 324 may have a crystal structure with a density of up to or approximately [missing information]. The thickness, and can be greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Or a greater thickness.

[0042] Method 200 may include, in an optional operation 230, conveying a pre-processed precursor to a substrate. The pre-processed precursor may be or include a nitrogen-containing precursor or an oxygen-containing precursor. The precursor may contact the substrate and may form or introduce reactive ligands on exposed surfaces of the substrate, these reactive ligands... Figure 3G The figure shows ligand 325. Unlike conventional techniques, this technique utilizes pre-processing of high-k dielectric materials configured to produce ordered growth in subsequent operations.

[0043] The preprocessing precursor can be or includes any nitrogen- or oxygen-containing precursor. Oxygen-containing precursors may be characterized by a hydroxyl group [-OH], which may be incorporated into the surface of the oxygen-containing material 324 of the substrate. Nitrogen-containing precursors may be characterized by an amino group [-NH2] or other nitrogen-containing groups. For example, nitrogen-containing precursors can be or include precursors containing nitrogen and hydrogen (such as ammonia as a non-limiting example) or precursors containing nitrogen and oxygen, or any other precursor including nitrogen.

[0044] In some embodiments, the surface termination may be or include a hydroxyl- or amine-terminated surface. Method 200 may then include forming a high-k dielectric material covering an oxygen-containing material at an optional operation 235. This technique can cover any formation or deposition of high-k materials, but in some embodiments, formation operation 235 may be or include atomic layer deposition, which may utilize any number of atomic layer deposition chambers. This formation, if performed, may be performed directly after pre-processing the substrate or the oxygen-containing material surface, and may be performed in the same chamber as pre-processing or in an additional chamber (such as an additional chamber incorporated into the same system (such as system 100)). In some embodiments, vacuum conditions may be maintained when the substrate is transferred from the pre-processing chamber to the deposition or formation chamber, which limits the substrate's exposure to air.

[0045] In performing atomic layer deposition (ALD) processes to form high-k dielectric materials, a metal-containing precursor can be delivered to a substrate to react with a pre-processed surface. For example, a transition metal-containing precursor, a metal-poor precursor, or a lanthanide-containing precursor can be delivered to a processing chamber to interact with reactive ligands exposed on the pre-processed substrate. Subsequently, an oxygen-containing precursor can be delivered in a second operation, such as after purification of the metal-containing precursor. This can produce an oxide layer, such as..., by atomic layer deposition. Figure 3H Layer 330a is shown. In a non-limiting example, a hafnium-containing precursor may be delivered in a first operation and an oxidant may be delivered in a second operation for producing a hafnium oxide film. Additional metal-containing precursors may include zirconium-containing precursors for producing zirconium-containing materials, and any other number of metal-containing precursors for producing additional metal oxide structures. For hafnium-containing precursors, and similarly for any alternative metal, the precursor may be or include halogen-containing precursors, oxygen-containing precursors, hydrogen-containing precursors, or carbon-containing precursors, incorporating hafnium into any of them.

[0046] For the oxidant, any oxygen-containing precursor that can react with the metal-containing material can be used. For example, the oxygen-containing precursor can be or include water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, a nitrogen- and oxygen-containing precursor, plasma-enhanced oxygen including locally or remotely enhanced oxygen, or any other material including oxygen that can combine with a metal (such as hafnium) to produce a metal oxide material layer covering the substrate. Similarly, any of the aforementioned metal-containing materials can be used in embodiments of this technology and can include any of a group of metals, including but not limited to hafnium, zirconium, silicon, lanthanum, aluminum, titanium, strontium, or combinations of these materials, such as, for example, hafnium silicate.

[0047] When preprocessing according to embodiments of the present technology is performed, structures containing metallic materials can be formed or deposited in an ordered manner to produce a more uniform grain structure. This can be achieved by forming reactive ligands of preprocessing precursors on a more structured surface material, such as higher-quality silicon or silicon oxide produced by embodiments of the present technology. Additionally, further improvements can be provided by performing preprocessing exposure under certain conditions.

[0048] Preprocessing can be performed at temperatures configured to activate the precursor and / or substrate surface. For example, when nitrogen- and hydrogen-containing precursors are available as preprocessing precursors, the substrate can be maintained at a temperature above or about 300°C during precursor delivery. Similarly, preprocessing using oxygen-containing precursors can be performed while maintaining the substrate temperature above or about 300°C. For any preprocessing operation, the substrate can also be maintained at temperatures above or about 400°C, above or about 500°C, above or about 600°C, above or about 700°C, above or about 800°C, or higher. As the preprocessing temperature decreases to below or about 500°C, effectiveness may decrease. Similarly, when the temperature rises to above or about 700°C, nucleation may not be improved, and excessive precursor may be introduced onto the surface, which may reduce device mobility. Therefore, in some embodiments, the temperature can be maintained between about 500°C and about 700°C during preprocessing.

[0049] Similar temperature ranges can affect the operation of one or two oxidation operations, which can carefully control the amount of silicon cap material retained in the first oxidation and limit over-oxidation in the second oxidation. To control the slow entry of oxygen into the silicon material, the temperature can be maintained below or approximately 900°C, and can be maintained below or approximately 850°C, below or approximately 800°C, below or approximately 750°C, below or approximately 700°C, below or approximately 650°C, below or approximately 600°C, or lower.

[0050] Similarly, exposure time can affect the amount of nitrogen-containing precursor incorporated, so to limit the resulting device mobility loss, precursor exposure may be less than or about 3 minutes, and in some embodiments, the exposure time may be less than or about 2.5 minutes, less than or about 2 minutes, less than or about 1.5 minutes, less than or about 1 minute, less than or about 45 seconds, less than or about 30 seconds, less than or about 15 seconds, or less. Once the appropriate amount of amino group has been incorporated, formation can be performed. Formation including atomic layer formation can be performed at any temperature, although in some embodiments, atomic layer deposition may be performed at a temperature lower than or about the temperature at which pre-processing was performed, regardless of whether the operation is performed in the same or different chambers. For example, atomic layer deposition may be performed at a second temperature relative to the pre-processing temperature, and in embodiments, the formation temperature may be lower than or about 500°C, and may be lower than or about 450°C, lower than or about 400°C, lower than or about 350°C, lower than or about 300°C, lower than or about 250°C, or lower.

[0051] After a layer of high-k material has been formed or deposited, one or more post-processing operations may be performed. In some embodiments, at optional operation 240, the substrate may be transferred from the deposition chamber to another chamber or another set of chambers for post-processing of the material. Similar to the explanation above, the transfer may occur on a single processing system having multiple chambers, and therefore transfer from any of these chambers or between any of these chambers may be performed while maintaining vacuum conditions. Method 200 may then include one or more additional post-processing operations, as indicated by optional operation 245. Post-processing operations may include one or more operations performed in one or more chambers comprising multiple chambers on the same cluster tool. Post-processing operations may include oxidation, nitriding, and / or thermal annealing.

[0052] As described above, preprocessing operations can be performed to provide sufficient terminal moieties to achieve the aforementioned uniform growth while limiting excessive precursor bonding to the substrate. For example, an incorporated nitrogen interface may reduce the mobility of the resulting transistor or decrease the speed at which carriers can move through the structure. While the aforementioned preprocessing can further improve the scaling of high-k films, it can actually reduce device mobility if left uncontrolled. However, in some embodiments, a post-processing step may include oxidizing the formed high-k material using a second oxygen-containing precursor relative to a first oxygen-containing precursor available for preprocessing operations.

[0053] For example, an oxidation operation utilizing any of the aforementioned oxygen-containing precursors can be performed to further oxidize the membrane after formation. The deposition or formation of a high-k membrane can produce a porous membrane, or a membrane comprising voids in its structure. By performing the oxidation operation, oxygen species can permeate the membrane to fill voids, as shown in layer 330b, and oxide materials, such as optional layer 320 (if not formed in the preceding operations described above), can be generated at the interface of the high-k material. This can improve the underlying interface from amine terminal groups, thereby enhancing the device's migration performance. To limit excessive increases in the thickness of the underlying oxide layer, the oxidation operation can be performed for a limited time period, and can be performed within any of the aforementioned time ranges.

[0054] When used, post-processing operations may additionally involve bringing the substrate into further contact with a second nitrogen-containing precursor relative to the pre-processed nitrogen-containing precursor. The second nitrogen-containing precursor may include any of the nitrogen-containing precursors described above, and may include nitrogen gas, as well as any nitrogen-containing precursors indicated elsewhere. The second nitrogen-containing precursor may include plasma-activated or enhanced nitrogen-containing precursors, thermally activated nitrogen, or some other nitrogen precursors, which may allow nitrogen radicals or nitrogen atoms to be incorporated into the high-k structure, thereby stabilizing or bringing the film to an equilibrium state. Unlike oxidation operations, nitriding may not increase the thickness of the underlying layer (such as silicon oxide) and may slightly increase the k-value of the resulting film.

[0055] Nitrogen incorporation can be controlled to limit its presence in the membrane to maintain structural and electrical properties. In some embodiments, post-processing nitriding may incorporate less than or about 20 atomic% nitrogen in the surface region of a high-k membrane, and may incorporate less than or about 15 atomic% nitrogen, less than or about 10 atomic% nitrogen, less than or about 8 atomic% nitrogen, less than or about 6 atomic% nitrogen, less than or about 4 atomic% nitrogen, less than or about 2 atomic% nitrogen, or even less. In some embodiments, incorporation between about 3 atomic% and about 7 atomic% may maintain a higher k value than higher nitrogen incorporation and may stabilize the membrane better than lower nitrogen incorporation. The surface region may mean the exposed surface of the material, although nitrogen incorporation may extend any distance into the membrane and may be uniform or form a decreasing gradient through the material.

[0056] Post-processing oxidation or nitriding can be performed at any of the aforementioned temperatures, but in some embodiments, post-processing oxidation and / or nitriding can be performed at a temperature range below or about 500°C, and can be performed at a temperature range below or about 400°C, below or about 300°C, below or about 200°C, below or about 100°C, or even lower, depending on the operation being performed.

[0057] Post-processing annealing can be performed after any operation including any of the aforementioned post-processing operations. Post-processing annealing can be performed in any chamber in which the previous operation was performed, or it may involve transfer to a different chamber, such as, for example, a chamber configured to perform a rapid thermal annealing process. Similarly, this chamber can be incorporated into the same platform as other chambers, which can allow transfer between chambers while maintaining vacuum conditions. Post-processing annealing can further align film bonding and further stabilize the film. In embodiments, post-processing annealing can be performed at temperatures above the deposition or oxidation temperature in some embodiments. For example, post-processing annealing can be performed at temperatures above or about 400°C, and in embodiments it can be performed at temperatures above or about 500°C, above or about 600°C, above or about 700°C, above or about 800°C, above or about 900°C, or higher.

[0058] Improved high-k materials and semiconductor structures can be produced by performing pre-processing, oxidation, and / or post-processing according to embodiments of this technology. Layers of high-k material can be produced at any thickness, including up to or about a few nanometers. However, due to the superior grain structure produced by this technology, a thinner effective oxide thickness can be achieved without sacrificing gate leakage current performance. High-k materials produced according to this technology are characterized by a k value greater than or about 10, and are characterized by k values ​​greater than or about 15, greater than or about 20, greater than or about 21, greater than or about 22, greater than or about 23, greater than or about 24, greater than or about 25, or greater.

[0059] Compared to conventional techniques, this technique further allows for an increase in dielectric constant. Furthermore, due to the resulting grain structure, the gate leakage current associated with the film can be less than or approximately one-tenth of the gate leakage current of a silicon oxide film of similar thickness, and the gate leakage current can be less than or approximately one-hundredth, one-thousandth, one-fifth, one-tenth, one-hundredth, one-hundredth, one-hundredth, one-hundredth, one-hundredth, one-hundredth, one-hundredth, or even smaller. By producing a film according to embodiments of this technique, a film with a beneficial morphology can be generated, which enhances the electrical properties of the film compared to conventional techniques.

[0060] In the foregoing description, numerous details have been set forth for illustrative purposes to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0061] Several embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the technology, many well-known processes and components have not been described. Accordingly, the above description should not be considered as limiting the scope of the technology.

[0062] Where a range of values ​​is provided, it should be understood that, unless the context explicitly specifies otherwise, each intermediate value (the smallest unit accurate to the lower limit) between the upper and lower limits of this range is also specifically disclosed. This encompasses any narrower range between any stated or unstated intermediate value within the stated range and any other stated or intermediate value within this stated range. The upper and lower limits of those narrower ranges may independently include or exclude them from this range, and each range in which any, none, or both limits are included is also covered by this technique, and may include any limits explicitly excluded from the stated range. If a stated range includes one or both limits, it also includes ranges excluding any or both of those included limits.

[0063] As used herein and in the appended claims, the singular forms “a / an” and “this / the” include plural references unless the context clearly specifies otherwise. Thus, for example, a reference to “a layer” includes a plural of such layers, and a reference to “precursor” includes a reference to one or more precursors and their equivalents known to those skilled in the art, and so on.

[0064] Furthermore, when used in this specification and in the appended claims, the terms “comprise(s) / comprising,” “contain(s) / containing,” and “include(s) / including” are intended to specify the presence of the stated feature, integral, component, or operation, but these terms do not exclude the presence or addition of one or more other features, integrals, components, operations, actions, or groups.

Claims

1. A method for forming a semiconductor structure, the method comprising the following steps: Forming a silicon layer on a semiconductor substrate, wherein the formation includes the following steps: Forming a silicon layer incorporating dopants; A portion of the silicon layer is oxidized, wherein the oxidation drives a portion of the dopant through the silicon layer and into the semiconductor substrate, and wherein the portion of the silicon layer is oxidized to form a sacrificial oxide; Remove the sacrificial oxide; Formation of oxygen-containing materials; and A high-k dielectric material is formed covering the oxygen-containing material.

2. The method for forming a semiconductor structure as claimed in claim 1, wherein the silicon layer is formed by atomic layer deposition or epitaxial growth.

3. The method of forming a semiconductor structure as claimed in claim 1, wherein the dopant comprises one or more of nitrogen, phosphorus, or fluorine.

4. The method of forming a semiconductor structure as claimed in claim 1, wherein the silicon layer is formed to a thickness of less than or about 5 nm.

5. The method for forming a semiconductor structure as claimed in claim 1, wherein the removal comprises an in-situ dry chemical process.

6. The method of forming a semiconductor structure as claimed in claim 5, wherein the removal is performed in a first processing chamber, and wherein the method further comprises the following steps: The semiconductor substrate is transferred from the first processing chamber to the second processing chamber.

7. The method for forming a semiconductor structure as claimed in claim 6, further comprising the step of: introducing a reactive ligand onto the oxygen-containing material using a nitrogen-containing precursor or an oxygen-containing precursor prior to forming the high-k dielectric material.

8. The method of forming a semiconductor structure as claimed in claim 7, wherein the nitrogen-containing precursor comprises ammonia.

9. The method of forming a semiconductor structure as claimed in claim 6, wherein the high-k dielectric material comprises at least one element selected from the group consisting of hafnium, zirconium, silicon, lanthanum, aluminum, titanium and strontium.

10. The method of forming a semiconductor structure as claimed in claim 1, wherein the method is performed in one or more processing chambers without exposing the semiconductor substrate to the atmosphere.

11. The method of forming a semiconductor structure as claimed in claim 1, wherein the silicon layer is epitaxially formed on the semiconductor substrate, and wherein the semiconductor substrate comprises silicon germanium.

12. The method of forming a semiconductor structure as claimed in claim 1, wherein a portion of the silicon layer is oxidized to form a sacrificial oxide, wherein forming the sacrificial oxide comprises a first oxidation process, and wherein the method further comprises the following steps: The oxidation of the portion of the silicon layer in contact with the semiconductor substrate includes a second oxidation process that is different from the first oxidation process.

13. The method of forming a semiconductor structure as claimed in claim 12, wherein the partial oxidation of the silicon layer in contact with the semiconductor substrate comprises delivering a nitrogen- and oxygen-containing precursor to the semiconductor substrate.

14. The method of forming a semiconductor structure as claimed in claim 13, wherein the oxidation of the portion of the silicon layer in contact with the semiconductor substrate occurs at a temperature below or about 750°C.

15. A method for forming a semiconductor structure, the method comprising the steps of: Remove oxide from the surface of a substrate contained in a semiconductor processing chamber, wherein the substrate comprises silicon-germanium fins; Forming a silicon layer on a semiconductor substrate, wherein the formation includes the following steps: A silicon layer is formed by incorporating nitrogen, fluorine, or phosphorus as dopants; and The silicon layer is oxidized to form a sacrificial oxide, wherein the oxidation causes a portion of the dopant to diffuse through the silicon layer and into the semiconductor substrate; Remove the sacrificial oxide; Nitrous oxide is delivered to the substrate to form an oxygen-containing material; The oxygen-containing material is pre-processed by contacting the substrate with a nitrogen-containing precursor. and A high-k dielectric material is formed covering the pre-processed oxygen-containing material.

16. The method of forming a semiconductor structure as claimed in claim 15, wherein the removal comprises an in-situ dry chemical process.

17. The method of forming a semiconductor structure as claimed in claim 16, wherein the removal is performed in a first processing chamber, and wherein the method further comprises the step of: transferring the substrate from the first processing chamber to a second processing chamber prior to forming the high-k dielectric material.

18. The method of forming a semiconductor structure as claimed in claim 15, wherein the silicon layer is formed by atomic layer deposition or epitaxial growth, and wherein the silicon layer is formed to have a thickness of less than or about 5 nm.

19. The method of forming a semiconductor structure as claimed in claim 15, wherein forming the sacrificial oxide comprises the step of: delivering an oxygen-containing precursor and a hydrogen-containing precursor to the substrate to form an oxygen-containing material.

20. A method for forming a semiconductor structure, the method comprising the steps of: Intrinsic oxide is removed from the surface of a substrate contained in a semiconductor processing chamber, wherein the substrate comprises silicon germanium; Forming a silicon layer on a semiconductor substrate, wherein the formation includes the following steps: Forming a silicon layer incorporating dopants; and A portion of the silicon layer is oxidized to form a sacrificial oxide while maintaining the portion of the silicon layer in contact with the semiconductor substrate, wherein the oxidation drives a portion of the dopant through the silicon layer and into the semiconductor substrate; and Remove the sacrificial oxide; Formation of oxygen-containing materials; and A high-k dielectric material is formed covering the oxygen-containing material.

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