A back contact cell, cell assembly and photovoltaic assembly

Abstract

This invention relates to the field of photovoltaic technology and provides a back-contact cell, a cell module, and a photovoltaic module. The back-contact cell includes: a silicon substrate; a plurality of N-type and P-type regions are alternately arranged along a first direction on the back surface of the silicon substrate; an N-type doped polycrystalline silicon layer is disposed on the N-type regions; and a P-type doped polycrystalline silicon layer is disposed on the P-type regions. The polarities of the N-type and P-type doped polycrystalline silicon layers are opposite. A spacer region is disposed between the N-type and P-type regions, and an intrinsic polycrystalline silicon layer is disposed in the spacer region, eliminating the need for etching trenches to isolate the N-type and P-type regions. P-type dopants are diffused at positions adjacent to the intrinsic polycrystalline silicon layers and P-type regions, with a diffusion width of D1; N-type dopants are diffused at positions adjacent to the intrinsic polycrystalline silicon layers and N-type regions, with a diffusion width of D2, where D2 > D1. This asymmetric lateral doping diffusion matches the physical differences between electrons and holes, improving the cell conversion efficiency.

Description

Technical Field

[0001] This invention belongs to the field of photovoltaic technology, and particularly relates to a back contact battery, a battery module, and a photovoltaic module. Background Technology

[0002] In traditional back-contact (BC) solar cell structures, the back side requires complex photolithography and etching processes to form alternating P-type doped regions, isolation regions, and N-type doped regions. The isolation regions are typically created by chemically etching the silicon substrate to maintain a single dopant element and a concentration consistent with the original silicon wafer, thus achieving physical and electrical isolation between the PN junctions. However, this technology is complex, costly, and requires stringent patterning precision. Achieving optimal etching depth, texture morphology, and doping uniformity is difficult, impacting yield and performance stability. Summary of the Invention

[0003] This invention provides a back-contact battery, a battery module, and a photovoltaic module, aiming to solve the problems of complex processes and poor process stability in existing technologies.

[0004] The present invention is implemented as follows: a back contact battery includes: a silicon substrate, wherein a plurality of N-type regions and P-type regions are alternately arranged on the back surface of the silicon substrate along a first direction; an N-type doped polycrystalline silicon layer is disposed on the N-type regions; a P-type doped polycrystalline silicon layer is disposed on the P-type regions; the polarities of the N-type doped polycrystalline silicon layer and the P-type doped polycrystalline silicon layer are opposite; a spacer region is disposed between the N-type regions and the P-type regions; an intrinsic polycrystalline silicon layer is disposed in the spacer region. Wherein, in the interval region, the intrinsic polysilicon layer adjacent to the P-type region is diffused with P-type doped elements, with a diffusion width of D1, and in the interval region, the intrinsic polysilicon layer adjacent to the N-type region is diffused with N-type doped elements, with a diffusion width of D2, where D2 > D1.

[0005] Optionally, D1 > 10 μm.

[0006] Optionally, the thickness of the intrinsic polycrystalline silicon layer is A, and the value of A ranges from 100nm to 300nm.

[0007] Optionally, the doping concentration of the P-type doped polysilicon layer is 1E19 atom / cm³. -3 ~6E19atom / cm -3 The doping concentration of the N-type doped polysilicon layer is 9E19 atom / cm³. -3 ~5E20atom / cm -3 .

[0008] Optionally, the width of the interval region is L, where L > (D1 + D2).

[0009] Optionally, the silicon substrate surfaces of the N-type region, P-type region, and spacer region are all polished surfaces.

[0010] Optionally, the impurity doping concentration in the spacer region is less than 1E16 atom / cm³. -3 .

[0011] Optionally, the doping concentration of the N-type dopant in the intrinsic polysilicon layer within the interval region is less than the doping concentration of the N-type dopant in the N-type doped polysilicon layer; and the doping concentration of the P-type dopant in the intrinsic polysilicon layer within the interval region is less than the doping concentration of the P-type dopant in the P-type doped polysilicon layer.

[0012] The present invention also provides a battery assembly including the aforementioned back contact battery.

[0013] The present invention also provides a photovoltaic system including the above-described battery module.

[0014] The beneficial effects achieved by this invention are due to the presence of an interlayer region between the N-type and P-type regions, on which intrinsic polysilicon is disposed, eliminating the need for etching trenches to isolate the N-type and P-type regions. P-type dopant is diffused at the position adjacent to the P-type region of the intrinsic polysilicon layer, with a diffusion width of D1, and N-type dopant is diffused at the position adjacent to the N-type region of the intrinsic polysilicon layer, with a diffusion width of D2, where D2 > D1. This asymmetric lateral doping diffusion matches the physical differences between electrons and holes, optimizes the lateral electric field distribution, and significantly improves the short-circuit current and fill factor without sacrificing the open-circuit voltage, ultimately achieving a significant improvement in battery conversion efficiency. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the back contact battery provided by the present invention.

[0016] Explanation of reference numerals in the attached figures: 100. Back contact cell; 110. Silicon substrate; 111. N-type region; 112. P-type region; 113. Spacer region; 120. N-type doped polycrystalline silicon layer; 130. P-type doped polycrystalline silicon layer; 140. Intrinsic polycrystalline silicon layer. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the invention, and should not be construed as limiting the invention. Furthermore, it should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0018] In the description of this invention, it should be understood that the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0019] Furthermore, the terms "N-type" and "P-type" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined as "N-type" or "P-type" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0020] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0021] In this invention, unless otherwise explicitly specified and limited, "above" or "below" a P-type feature can include direct contact between the N-type and P-type features, or contact between the N-type and P-type features through another feature between them. Furthermore, "above," "on top of," and "over" a P-type feature includes the N-type feature being directly above or diagonally above the P-type feature, or simply indicates that the N-type feature is at a higher horizontal level than the P-type feature. "Below," "below," and "under" a P-type feature includes the N-type feature being directly below or diagonally below the P-type feature, or simply indicates that the N-type feature is at a lower horizontal level than the P-type feature.

[0022] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0023] This invention establishes a spacer region between the N-type and P-type regions, with intrinsic polysilicon disposed on this spacer region. This eliminates the need for etching trenches to isolate the N-type and P-type regions, simplifying the manufacturing process. P-type dopant is diffused into the intrinsic polysilicon layer adjacent to the P-type region, with a diffusion width of D1. N-type dopant is diffused into the intrinsic polysilicon layer adjacent to the N-type region, with a diffusion width of D2, where D2 > D1. This asymmetric lateral doping diffusion matches the physical differences between electrons and holes, optimizing the lateral electric field distribution. Without sacrificing open-circuit voltage, it significantly improves short-circuit current and fill factor, ultimately achieving a significant increase in battery conversion efficiency.

[0024] Example 1 like Figure 1 As shown, this embodiment provides a back contact battery 100, including: a silicon substrate 110, with a plurality of N-type regions 111 and P-type regions 112 alternately arranged on the back surface of the silicon substrate 110 along a first direction; an N-type doped polycrystalline silicon layer 120 is disposed on the N-type region 111, and a P-type doped polycrystalline silicon layer 130 is disposed on the P-type region 112; the polarities of the N-type doped polycrystalline silicon layer 120 and the P-type doped polycrystalline silicon layer 130 are opposite; a spacer region 113 is disposed between the N-type region 111 and the P-type region 112, and an intrinsic polycrystalline silicon layer 140 is disposed in the spacer region 113; wherein, in the spacer region 113, the intrinsic polycrystalline silicon layer 140 adjacent to the P-type region 112 is diffused with P-type dopant elements with a diffusion width of D1, and in the spacer region 113, the intrinsic polycrystalline silicon layer 140 adjacent to the N-type region 111 is diffused with N-type dopant elements with a diffusion width of D2, where D2 > D1.

[0025] The silicon substrate 110 typically uses an n-type monocrystalline silicon wafer with two opposing sides: a light-facing side and a back-lighting side. The light-facing side directly faces the sunlight and usually has a pyramidal textured surface and an anti-reflective layer, while the back-lighting side is the other side and has various functional layers, electrodes, and passivation layers.

[0026] Two distinct regions, N-type region 111 and P-type region 112, are arranged alternately on the backlight surface of the silicon substrate 110. Specifically, a plurality of N-type regions 111 and a plurality of P-type regions 112 are arranged alternately along a first direction, and both N-type regions 111 and P-type regions 112 extend along a second direction, which intersects the first direction. The N-type regions 111 and P-type regions 112 can be arranged alternately along the transverse direction of the silicon substrate 110 and both extend along the longitudinal direction. That is, the first direction can be the transverse direction of the back contact battery 100, and the second direction can be the longitudinal direction of the back contact battery 100, which are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction can also be other directions, for example, they can be the diagonal directions of the silicon substrate 110, which is not limited here. A gap region 113 is provided between the N-type regions 111 and the P-type regions 112.

[0027] An N-type doped polysilicon layer 120 is covered on the N-type region 111. Specifically, the N-type doped polysilicon layer 120 can be formed by doping an N-type dopant element, such as phosphorus, into the intrinsic polysilicon layer 140. A P-type doped polysilicon layer 130 is covered on the P-type region 112. Specifically, the P-type doped polysilicon layer 130 can be formed by doping a P-type dopant element, such as boron, into the intrinsic polysilicon layer 140. The N-type and P-type dopants have opposite polarities, meaning the N-type doped polysilicon layer 120 and the P-type doped polysilicon layer 130 have opposite polarities. Specifically, the N-type doped polysilicon layer 120 can be a P-type doped polysilicon layer 130, and the P-type doped polysilicon layer 130 can be an N-type doped polysilicon layer 120, or the N-type doped polysilicon layer 120 can be an N-type doped polysilicon layer 120, and the P-type doped polysilicon layer 130 can be a P-type doped polysilicon layer 130. The N-type and P-type doped polysilicon layers form regions with different electrical properties, supporting the formation of the PN junction and the separation of charge carriers.

[0028] The spacer region 113 is disposed between the N-type region 111 and the P-type region 112, that is, the intrinsic polysilicon layer 140 is disposed between the N-type doped polysilicon layer 120 and the P-type doped polysilicon layer 130. The intrinsic polysilicon layer 140 itself has an extremely low carrier concentration, forming a high-resistivity buffer zone between the N-type doped polysilicon layer 120 and the P-type doped polysilicon layer 130, eliminating the lateral diffusion of N-type dopants into the P-type doped polysilicon layer 130 and the lateral diffusion of P-type dopants into the N-type doped polysilicon layer 120, thus preventing doping interference and short-circuit risks.

[0029] Within the spacer region 113, the intrinsic polysilicon layer 140 adjacent to the P-type region 112 is diffused with P-type dopant elements, with a diffusion width of D1. Similarly, within the spacer region 113, the intrinsic polysilicon layer 140 adjacent to the N-type region 111 is diffused with N-type dopant elements, with a diffusion width of D2, where D2 > D1. Understandably, the dopant elements in the N-type region 111 or the P-type region 112 can diffuse into the intrinsic polysilicon layers of the spacer regions 113 on either side.

[0030] The production process can be specifically described in the following steps: 1. An intrinsic polycrystalline silicon layer 140 is uniformly deposited on the back surface of the silicon substrate 110 by low-pressure chemical vapor deposition (LPCVD), and a dielectric film layer is formed on the intrinsic polycrystalline silicon layer 140. 2. The dielectric film on the N-type region 111 is removed by laser or wet etching, and N-type element diffusion is performed. The N-type element diffuses in the N-type region 111, and an N-type doped polysilicon layer 120 and a PSG layer are formed in the N-type region 111. 3. The dielectric film on the P-type region 112 is removed by laser or wet etching, and P-type element diffusion is performed. The P-type element diffuses in the P-type region 112, and a P-type doped polysilicon layer 130 and a BSG layer are formed in the P-type region 112. 4. Remove the PSG layer in N-type region 111 and the BSG layer in P-type region 112, and remove the dielectric film layer in spacer region 113.

[0031] It should be noted that a tunneling layer can be deposited on the back surface of the silicon substrate 110 before depositing the intrinsic polycrystalline silicon layer 140. After step 4, the passivation layer and antireflection layer are deposited on the back surface, and electrodes are respectively set in the N-type region 111 and the P-type region 112. These are all conventional process steps and will not be described in detail here.

[0032] The spacer region 113 retains the initially deposited intrinsic polysilicon layer 140. Different elements are doped into different regions, eliminating the need for etching trenches to isolate N-type regions and simplifying the process. When diffusing P-type elements into the intrinsic polysilicon layer 140 of the P-type region 112, boron is typically the P-type element. The boron element diffuses laterally into the adjacent spacer region 113, forming a boron-doped diffusion region in the intrinsic polysilicon layer 140 with a diffusion width of D1. Simultaneously, when diffusing N-type elements into the intrinsic polysilicon layer 140 of the N-type region 111, phosphorus is typically the N-type element. The phosphorus element diffuses laterally into the adjacent spacer region 113, forming a phosphorus-doped diffusion region in the intrinsic polysilicon layer 140 with a diffusion width of D2.

[0033] If there is no diffusion between the isolation region and the P / N region, i.e., a direct transition from intrinsic silicon to heavily doped silicon, a steep band bend will form at the interface. This abrupt change becomes a strong recombination center for charge carriers (electrons and holes). By allowing the dopant element to diffuse moderately to the edge of the isolation region, a gradual doping concentration can be created from the P region to the isolation region and then to the N region. This smooth transition can effectively mitigate the band bend, significantly reduce the carrier recombination rate at the interface, and thus improve the open-circuit voltage (Voc) of the battery.

[0034] D2 > D1, indicating wider N-type doping diffusion (larger D2), meaning a wider "funnel" for electron collection. Photogenerated electrons from the spacer region 113 and the edge of the P-region are more easily "pulled" by this extended N-type lateral electric field and collected at the N-type electrode. While the narrower P-type doping diffusion (smaller D1) results in a relatively smaller hole collection range, the wider, more efficient electron collection region compensates for the disadvantage of electrons in long-distance transport because hole mobility is typically lower than electron mobility, and the N-type silicon substrate 110 itself is conducive to electron transport. This significantly reduces the carrier recombination probability in the spacer region 113, improves carrier collection efficiency, and directly increases the battery's short-circuit current (Isc).

[0035] In this application, a spacer region 113 is provided between the N-type region 111 and the P-type region 112, wherein intrinsic polysilicon is disposed on the spacer region 113. This eliminates the need for etching trenches to isolate the N-type and P-type regions, simplifying the process. P-type dopants are diffused at the position adjacent to the P-type region 112 of the intrinsic polysilicon layer 140, with a diffusion width of D1. N-type dopants are diffused at the position adjacent to the N-type region 111 of the intrinsic polysilicon layer 140, with a diffusion width of D2, where D2 > D1. This asymmetric lateral doping diffusion matches the physical differences between electrons and holes, optimizes the lateral electric field distribution, and significantly improves the short-circuit current and fill factor without sacrificing the open-circuit voltage, ultimately achieving a significant improvement in battery conversion efficiency.

[0036] In some embodiments, D1 > 10 μm. When D1 is less than 10 μm, the diffusion region is too small, resulting in poor smooth transition. D1 > 10 μm, D2 > D1, which means D2 > 10 μm. When the width of the diffusion region (N-diffusion or P-diffusion) is greater than 10 μm, it has a wider diffusion region. Understandably, in a gradient doping process, a wider gradient doping region helps to form a smoother and more reasonable electric field distribution near the isolation region. This optimized electric field can more effectively "drive" photogenerated carriers to their respective collection regions (electrons to the N-region, holes to the P-region) and reduce carrier losses caused by electric field disturbances near the isolation region. This directly improves the battery's short-circuit current (Isc) and fill factor (FF).

[0037] In some embodiments, the thickness of the intrinsic polysilicon layer 140 is A, where A ranges from 100 nm to 300 nm. In industrial production, the deposited intrinsic polysilicon layer 140 is not perfect and may contain pores or defects. Setting the thickness A to ≥100 nm effectively creates a thick, "dry" (high-resistance) "insulating dam" between the first and second regions. Even if there are micro-defects or low-resistance channels penetrating a portion of the film's thickness, the remaining effective thickness of this "dam" is still sufficient to provide extremely high resistance. A thickness ≤ 300 nm avoids excessive material deposition, saves on expensive silicon source gas costs, and shortens process time.

[0038] It should be noted that the intrinsic polysilicon layer 140 is grown uniformly on the back side of the silicon substrate 110, meaning that the thickness of the intrinsic polysilicon layer 140 is uniform (due to process limitations, absolute uniformity cannot be achieved; the difference between the thickest and thinnest points is small, and there are no obvious protrusions or depressions). To further ensure the uniformity of the intrinsic polysilicon layer 140's thickness, the back surface of the silicon substrate 110 is polished, which is more conducive to the uniform deposition of the intrinsic polysilicon layer 140.

[0039] Specifically, the width of the P-type region 112 is 100 μm to 600 μm, and the doping concentration of the P-type doped polysilicon layer 130 is 1E19 atom / cm. -3 ~6E19atom / cm -3 The width of the N-type region 111 is 100 μm to 600 μm, and the doping concentration of the N-type doped polysilicon layer 120 is 9E19 atom / cm. -3 ~5E20atom / cm -3 .

[0040] Specifically, the doping concentration of the p-type doped polysilicon layer 130 can be 1E19 atom / cm³. -3 2E19atom / cm -3 3E19atom / cm -3 4E19atom / cm -3 5E19atom / cm -3 6E19atom / cm -3 It can also be 1E19atom / cm -3 ~6E19atom / cm -3 Other values ​​within the range. Specifically, the doping concentration of the N-type doped polysilicon layer 120 can be 9E19 atom / cm. -3 1E20atom / cm -3 2E20atom / cm -3 3E20atom / cm -3 4E20atom / cm-3 5E20atom / cm -3 It can also be 9E19atom / cm -3 ~5E20atom / cm -3 Other values ​​within the range. It should be noted that the doping concentration of the N-type doped polysilicon layer 120 and the P-type doped polysilicon layer 130 may be non-uniform, that is, the doping concentration is different at different locations. For example, the doping concentration is higher at locations closer to the surface facing away from the silicon substrate 110.

[0041] The concentration of the p-type doped polysilicon layer is 1E19~6E19 cm⁻¹. -3 Within a certain range, while ensuring effective hole transport, it is important to avoid increasing lattice defects or exacerbating Auger recombination due to excessive doping. The N-type doped polycrystalline silicon layer concentration is 9E19~5E20 cm⁻¹. -3 Within this range, it accommodates high electron mobility, ensuring rapid electron collection while maintaining good interface passivation. Furthermore, the p-type doped polycrystalline silicon layer has a thickness of 130 cm⁻¹ (1E¹⁹~6E¹⁹ cm⁻¹). -3 ) and N-type doped polycrystalline silicon layer 120 (9E19~5E20 cmcm) -3 Both belong to the category of heavily doped materials. When combined, they can form a PN junction with a steep carrier concentration gradient, generating a strong built-in electric field, which is beneficial for efficient carrier separation and transport, and reduces recombination losses in the junction region.

[0042] In some embodiments, the width of the interval region 113 is L, where L > (D1 + D2).

[0043] L>(D1+D2) ensures complete physical isolation between the lateral diffusion regions of N-type and P-type doped elements within the spacer region, forming a permanent intrinsic isolation band with a width of [L - (D1+D2)]. This fundamentally eliminates the formation of a leakage path between the N-region and P-region on the back side, which is an absolute necessity for ensuring high parallel resistance and high open-circuit voltage of the device. The lateral electric fields (one attracting electrons, the other attracting holes) generated by the N-type diffusion region (width D2) and the P-type diffusion region (width D1) within the spacer region, which are opposite in direction, do not overlap or cancel each other out. When charge carriers move within the spacer region, the direction of the electric force they experience is always clear, electrons are efficiently guided to the N-region, and holes are efficiently guided to the P-region, achieving maximum bipolar collection without crosstalk.

[0044] In some embodiments, the impurity doping concentration of spacer region 113 is less than 1E16. The doped impurities in spacer region 113 include P-type elements diffused from P-type doped polysilicon layer 130 and N-type elements diffused from N-type doped polysilicon layer 120. It should be noted that, since spacer region 113 is doped with P-type elements only on the side closest to P-type region 112 and with N-type elements only on the side closest to N-type region 111, the impurity doping in spacer region 113 is non-uniform. The doping concentration of spacer region 113 is the average doping concentration of spacer region 113.

[0045] If the doping concentration in spacer region 113 is too high (>1×10), 16 cm -3 A continuous, highly conductive path may form between the N / P diffusion regions, causing parasitic shunting between the N and P regions of the battery, which manifests as a decrease in parallel resistance and a surge in leakage current.

[0046] Maintaining high barrier isolation: low doping concentration (<1×10⁻⁶) 16 cm -3 This keeps the resistivity of the region high, effectively blocking the direct current path between the N-type and P-type main junctions and ensuring the isolation of the junction region.

[0047] In some embodiments, the doping concentration of the N-type dopant in the intrinsic polysilicon layer 140 within the spacer region 113 is less than the doping concentration of the N-type dopant in the N-type doped polysilicon layer 120; and the doping concentration of the P-type dopant in the intrinsic polysilicon layer 140 within the spacer region 113 is less than the doping concentration of the P-type dopant in the P-type doped polysilicon layer 130.

[0048] Gradual doping helps create a smoother, more balanced electric field distribution near the isolation region. This optimized electric field can more effectively "drive" photogenerated carriers to their respective collection regions (electrons to the N-region, holes to the P-region) and reduce carrier losses caused by electric field disturbances near the isolation region. This directly improves the battery's short-circuit current (Isc) and fill factor (FF). Specifically, the diffusion concentration can be controlled by adjusting the maximum process temperature of the diffusion process in the BC manufacturing process.

[0049] Example 2 This embodiment provides a battery assembly, including the back contact battery 100 described above.

[0050] The battery assembly may include multiple back contact batteries 100. The multiple back contact batteries 100 in the battery assembly can be connected in series to form a battery string. The battery strings can be connected in series, in parallel, or in a series-parallel combination to achieve current charging output. For example, the connection between the individual battery cells can be achieved by welding solder strips, or the connection between the individual battery strings can be achieved by busbars.

[0051] The battery module may also include a metal frame, a backsheet, photovoltaic glass, and an encapsulating film (not shown in the figures). The encapsulating film can be filled between the light-facing side of the solar cell and the photovoltaic glass, the back-facing side and the backsheet, and adjacent cells. As a filler, it can be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulating film can be EVA film or POE film, and the specific choice can be made according to the actual situation. There are no restrictions here.

[0052] Photovoltaic glass can be applied to the encapsulating film on the light-facing side of a solar cell. This photovoltaic glass can be ultra-clear glass, possessing high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%, protecting the solar cell while minimizing impact on its efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and the solar cell together, providing sealing, insulation, and waterproofing / moisture protection for the solar cell.

[0053] The backsheet can be attached to the encapsulating film on the back side of the solar cell. The backsheet protects and supports the solar cell, providing reliable insulation, water resistance, and aging resistance. Multiple backsheet options are available, typically including tempered glass, acrylic glass, and aluminum alloy TPT composite encapsulating film, etc. The specific choice depends on the specific circumstances and is not limited here. The backsheet, solar cell, encapsulating film, and photovoltaic glass can be mounted on a metal frame. The metal frame serves as the main external support structure for the entire battery module, providing stable support and installation. For example, the battery module can be installed at the desired location using the metal frame.

[0054] The beneficial effects of the battery module in this embodiment are equivalent to those of the solar cell described above, and will not be repeated here.

[0055] Example 3 This embodiment provides a photovoltaic system, including the aforementioned battery module.

[0056] Photovoltaic systems can be applied in photovoltaic power plants, such as ground-mounted, rooftop, and floating power plants, as well as in equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it's understandable that the application scenarios of photovoltaic systems are not limited to these; that is, photovoltaic systems can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation network as an example, a photovoltaic system can include photovoltaic arrays, combiner boxes, and inverters. A photovoltaic array can be a combination of multiple battery modules; for example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic arrays are connected to combiner boxes, which collect the current generated by the photovoltaic arrays. The collected current flows through an inverter and is converted into AC power required by the mains grid before being connected to the mains grid to achieve solar power supply.

[0057] The beneficial effects of the photovoltaic system in this embodiment are equivalent to the beneficial effects of the battery module described above, and will not be repeated here.

[0058] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A back-contact battery, characterized in that, include: A silicon substrate, wherein a plurality of N-type regions and P-type regions are alternately arranged along a first direction on the back surface of the silicon substrate, wherein an N-type doped polysilicon layer is disposed on the N-type regions and a P-type doped polysilicon layer is disposed on the P-type regions, wherein the polarities of the N-type doped polysilicon layer and the P-type doped polysilicon layer are opposite; a spacer region is disposed between the N-type regions and the P-type regions, wherein an intrinsic polysilicon layer is disposed in the spacer region; Wherein, in the interval region, the intrinsic polysilicon layer adjacent to the P-type region is diffused with P-type doped elements, with a diffusion width of D1, and in the interval region, the intrinsic polysilicon layer adjacent to the N-type region is diffused with N-type doped elements, with a diffusion width of D2, where D2 > D1.

2. The back contact battery as described in claim 1, characterized in that, D1 > 10 μm.

3. The back contact battery as described in claim 1 or 2, characterized in that, The thickness of the intrinsic polycrystalline silicon layer is A, and the value of A ranges from 100nm to 300nm.

4. The back contact battery as described in claim 1, characterized in that, The doping concentration of the P-type doped polysilicon layer is 1E19 atom / cm³. -3 ~6E19atom / cm -3 The doping concentration of the N-type doped polysilicon layer is 9E19 atom / cm³. -3 ~5E20atom / cm -3 .

5. The back contact battery as described in claim 1, characterized in that, The width of the interval region is L, where L > (D1 + D2).

6. The back contact battery as described in claim 1, characterized in that, The silicon substrate surfaces of the N-type region, P-type region, and spacer region are all polished.

7. The back contact battery as described in claim 1, characterized in that, The impurity doping concentration in the spacer region is less than 1E16 atom / cm³. -3 .

8. The back contact battery as described in claim 7, characterized in that, The doping concentration of the N-type dopant in the intrinsic polysilicon layer within the interval region is less than the doping concentration of the N-type dopant in the N-type doped polysilicon layer; the doping concentration of the P-type dopant in the intrinsic polysilicon layer within the interval region is less than the doping concentration of the P-type dopant in the P-type doped polysilicon layer.

9. A battery assembly, characterized in that, Includes the back contact battery as described in any one of claims 1 to 8.

10. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 9.

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