Solid state esd sic simulator

Abstract

Solid state ESD SIC simulator. An electrostatic discharge (ESD) test system includes a FET-based pulse generator that uses a pair of back-to-back FETs coupled to generate an ESD pulse based on discharging a capacitor coupled in series with a device under test (DUT). A number of FETs can be selected based on an expected ESD test voltage amplitude.

Description

Technical Field

[0001] This disclosure relates to a system for electrostatic discharge testing. Background Technology

[0002] Electrostatic discharge (ESD) testing is an essential part of verifying whether a semiconductor device is robust enough for use in commercial products. Using ESD testing, manufacturers can confirm device performance in successful tests or modify devices to make them more ESD-resistant before commercial release. Typical ESD requirements for industry standards fall into three model categories: the so-called Machine Model (MM), Human Body Model (HBM), and Charged Device Model (CDM). MM testing requires an electrical pulse rise time of 60 ns to 90 ns, with a pulse amplitude of ±400 V or higher. HBM-based testing requires a rise time of 2 ns to 10 ns and a pulse amplitude of ±8000 V. CDM testing requires a pulse amplitude of ±2000 V, with a pulse rise time of less than 300 ps. Devices must typically be tested with both positive and negative pulse voltages to confirm compliance with industry standards. Extensive ESD testing has allowed for reduced device failure rates in response to ESD and the routine use of devices that were previously susceptible to ESD damage.

[0003] Traditional ESD testing systems use mercury-lubricated high-voltage relays to generate the required pulses. These relays have several drawbacks, such as the use of hazardous materials. Semiconductors (solid-state switches) are generally not fast enough, especially devices capable of generating the large pulse voltages required. Some semiconductor devices that appear fast enough (such as avalanche transistors) have limitations, such as being suitable only for generating pulses at fixed, relatively low voltages, rather than the randomly programmable discharge voltages required for ESD testing. Furthermore, even if a semiconductor device is otherwise suitable for switching, it allows leakage currents that can damage the device under test (DUT) before ESD stress is applied. For these and other reasons, alternative ESD testing methods are needed. Summary of the Invention

[0004] An electrostatic discharge (ESD) test apparatus includes at least a first FET and a second FET coupled back-to-back, and a test voltage source operable to generate a bipolar test voltage. An ESD test capacitor is positioned to be charged by the test voltage source and discharged through the device under test (DUT) and the first and second FETs to generate a test pulse in the DUT in response to a control pulse. In some examples, first and second opto-isolators are coupled to the respective gates of the first and second FETs and are used to receive the control pulse from a pulse generator. In other examples, first and second pulse circuits are coupled to the respective outputs of the first and second opto-isolators and the respective gates of the first and second FETs. In yet another example, the pulse generator is coupled to the first and second opto-isolators to provide first and second gate pulses to the respective gates of the first and second FETs. In a typical example, the test voltage source is operable to generate a bipolar test voltage with an amplitude of at least 200 V. In another example, a current-regulating resistor is positioned such that the test voltage source is coupled to charge the ESD test capacitor through the current-regulating resistor. In some examples, the ESD test capacitor switch is selectable to generate MM, HM, or CDM pulses. Typically, the source or drain of one of the first and second FETs is coupled between the current-regulating resistor and the ESD test capacitor. In another example, the ESD test resistor is positioned in series with the ESD capacitor and the DUT, such that the ESD test current is coupled to the DUT through the ESD test resistor, and the ESD test resistor is selected based on an ESD test model. In a further embodiment, first and second power supply circuits are coupled to the first and second FETs, respectively, wherein the first and second power supply circuits provide independent voltages to the first pulse circuit and the second pulse circuit, respectively.

[0005] In some examples, the first FET and the second FET form a first back-to-back FET pair, and a plurality of FETs are coupled to the first back-to-back FET pair and operable to generate the test pulse in response to the pulse generator. The FETs in the plurality of FETs may be connected as a back-to-back FET pair. Corresponding opto-isolators, power supply circuitry, and pulse circuitry may be coupled to each of the plurality of FETs.

[0006] The ESD test apparatus includes multiple ESD pulse generators, each configured to generate an ESD test pulse in at least two or more DUTs in response to activation of at least one back-to-back FET pair. A matrix switch is coupled to the plurality of ESD pulse generators and operable to selectively couple one or more of the ESD pulse generators to any one of the two or more DUTs. An ESD controller is coupled to the matrix switch and operable to select a DUT for coupling to an ESD pulse generator. In some examples, each of the ESD pulse generators includes multiple pairs of back-to-back FETs and / or one or more sets of back-to-back FETs. In a typical example, a bipolar voltage source is provided and operable to generate a voltage of at least 400 V and coupled to charge a corresponding test pulse capacitor in each of the ESD pulse generators.

[0007] The method includes applying an ESD test pulse to the DUT by discharging an ESD test capacitor through the back-to-back SiC FET pair in response to a gate pulse applied to the gate of the back-to-back SiC FET pair. In some examples, one or more of MM, HM, or CDM ESD test pulses are selected.

[0008] The foregoing and other features and advantages of the disclosed technology will become more apparent from the following detailed description with reference to the accompanying drawings. Attached Figure Description

[0009] Figure 1A A representative ESD test pulser is shown.

[0010] Figure 1B The diagram shows an alternating stack of pairs of back-to-back FETs, which allows for higher pulse voltages than those obtained from a single pair of FETs.

[0011] Figure 1C The combination of first and second FET stacks of corresponding polarities is shown, which allows for higher pulse voltages than those obtained from a single pair of FETs.

[0012] Figure 2 A representative FET-based ESD test pulser is shown, which consists of a single pair of back-to-back FETs, each powered by a corresponding power supply.

[0013] Figure 3 A representative ESD system is shown, which includes a FET-based test pulser and a switching matrix.

[0014] Figure 4 A representative ESD testing method is shown.

[0015] Figure 5 Another FET-based test pulser is shown, which includes a power supply for each FET.

[0016] Figure 6 Another FET-based test pulser is shown. Detailed Implementation

[0017] This document discloses methods and apparatus for generating necessary voltage pulses that can be used in ESD testing or other applications without the use of mercury-lubricated relays as in conventional methods. The disclosed methods and apparatus can also generate pulses with variable amplitude, duration, and repetition rates up to several MHz, including random amplitude and polarity according to the intended ESD test pattern. Furthermore, the disclosed methods can be configured to provide pulses to multiple devices, such as those undergoing ESD compliance testing. The disclosed methods are described with reference to SiC-based semiconductor devices, but other semiconductor devices can also be used depending on the pulse requirements. Additionally, while the disclosed techniques are described with reference to ESD testing, the pulse generation methods can be configured for other applications, such as autoclaving, mass spectrometry, electron microscopy, ion implantation, transmission line pulses, or others. The disclosed semiconductor-based methods can be implemented such that leakage current is not conducted through the device under test (DUT). In some cases, these leakage currents can damage the DUT, including devices appropriately resistant to ESD-based damage.

[0018] In representative examples, the disclosed methods and apparatus can generate suitable pulse waveforms with low pulse distortion, and the pulse waveforms can meet industry standards for ESD testing. Pulse amplitudes of at least 1 kV to 8 kV or higher can be generated at a reasonable cost, with pulse durations ranging from hundreds of ps to tens of ns.

[0019] For illustrative purposes, a pair of FETs of the same type (P-channel or N-channel) with a common source or common drain connection is referred to herein as a back-to-back pair, and this connection is called a back-to-back connection. In such a back-to-back connection, the sources (or drains) of the two FETs are connected together. In such a back-to-back connection, the body diodes associated with the pair are connected in anti-parallel. In other examples, a pair of FETs of different types, i.e., a P-type FET and an N-type FET, are connected source-to-drain or drain-to-source. This connection is referred to herein as a front-to-back connection, and the pair is called a front-to-back pair. As with a back-to-back connection, the diodes associated with such a pair are connected in anti-parallel. FETs of the same type with their sources connected to their drains or their drains connected to their sources are called a series connection. As discussed below, in some examples, a set of series-connected FETs of the first type are arranged in a back-to-back connection with a series of FETs of the first type, or in a front-to-back connection with a series of FETs of the second type, which are different from the first type. For ESD and other applications, SiC-based FETs may be preferred because they are more effective at higher voltages than FETs based on other materials.

[0020] Example 1

[0021] refer to Figure 1A A representative ESD test system 100 includes a first FET 102 and a second FET 112, which are connected such that the source (or drain) of the first FET 102 is connected to the source (or drain) of the second FET 112, i.e., the first FET 102 and the second FET 112 are connected in a back-to-back configuration and form a back-to-back pair. Figure 1A In this example, the first FET 102 and the second FET 112 are N-channel SiC FETs. The first FET 102 and the second FET 112 are associated with first and second diodes 103 and 113, respectively, which are typically referred to as body diodes. The first and second diodes 103 and 113 are effectively in an anti-parallel connection. The drain (or source) of the first FET 102 is coupled to a common connection, typically ground. The drain (or source) of the second FET is connected between a current-regulating resistor 122 and an ESD test capacitor 124 and an ESD test resistor 125 forming an ESD test model group 121. The ESD test capacitor 124 is charged by a test voltage source 120 through the current-regulating resistor 122. In a typical example, the test voltage source 120 can generate a bipolar voltage with an amplitude of at least 200 V, 400 V, 500 V, 800 V, 1000 V, or greater.

[0022] A control signal generator 130 is coupled to a first opto-isolator 104 and a second opto-isolator 114, which in turn are coupled to a first pulse circuit 106 and a second pulse circuit 116, respectively. Applying control pulses to the gates of the first FET 102 and the second FET 112 via the corresponding opto-isolators and pulse circuits allows the ESD test capacitors to discharge through the first FET 102 and the second FET 112, thereby generating test pulses 126 in the device under test (DUT). The duration, amplitude, and timing shape of the test pulses in the DUT 126 are based on the capacitance of the test capacitor 124, the resistance of the test resistor 125, and the control pulses. In some examples, the processor 129 or other digital controller is positioned to select the capacitance value, test voltage, and pulse shape based on the considered ESD model, typically based on the values ​​of components in the ESD model group 121, the selected voltage, and the control pulses.

[0023] While back-to-back FET pairs can be used, in some examples, a single FET pair is not suitable for the required voltage. Figure 1B An alternative FET configuration including multiple back-to-back connected FET pairs 150, 151, 152 is shown, but more FET pairs can also be provided, as illustrated. The gate of each of the FETs can be coupled to receive a suitable pulse, such that the test capacitor 159 is discharged by the FET to generate an ESD test pulse in the DUT.

[0024] exist Figure 1C In another example shown, a first plurality of FETs 160 of the same type (connected in series) and a second plurality of FETs 180 of the same type (connected in series) are coupled back-to-back, i.e., the drain (or source) of FET 161 is connected to the source (or drain) of FET 181. FETs 161, 162, and 163 of the first plurality of 160 are connected in series, and FETs 181, 182, and 183 of the second plurality of 180 are connected in series. The body diodes of FETs 161, 162, and 163 are anti-parallel with respect to the body diodes of FETs 181, 182, and 183. Gate connections are not shown, but each gate is typically coupled to a pulse circuit or otherwise coupled to receive a pulse signal to initiate an ESD test signal. FETs can be arranged in groups and pairs, as shown... Figures 1B to 1C It's as convenient as shown.

[0025] Typically, each FET in the above configuration requires a dedicated isolated power supply. The total number of FETs required depends on the pulse voltage and FET characteristics. In one example, a 1700 V pulse generator uses 12 transistors, with 6 used to provide positive pulses and 6 used to provide negative pulses.

[0026] In other examples, various combinations of P-channel and N-channel FETs can be used.

[0027] Example 2

[0028] refer to Figure 2 A representative ESD test setup 200 includes a FET pair 202, comprising a first FET 204 and a second FET 206 with a back-to-back connection. Corresponding FET drivers 210, 220 are coupled to the gates of the first FET 204 and the second FET 206 to initiate an ESD test pulse by discharging a capacitor 230 via a DUT 248 to ground connection 250. FET drivers 210, 220 include corresponding power supplies 212, 222, opto-isolators 214, 224, and pulse drivers 216, 226. Opto-isolators 214, 224 are coupled to receive pulse input from a control pulse source (not shown). Power supplies 212, 224 are typically configured as needed. Figure 2 The middle is shown as V A1 V B1 V 01 V A2 V B2 and V 02 It provides power using some or all of several voltages, such as -5 V, 0 V, +5 V, and +20 V. The high-voltage power supply 260 is configured to charge the capacitor 230 via a current-regulating resistor 261 and is operable to supply voltages in the range of -2 kV to +2 kV or greater as needed.

[0029] Example 3

[0030] refer to Figure 3 The ESD test system 300 is operable to selectively apply an ESD test pulse to any one of a plurality of DUTs 302, and to evaluate the DUTs before or after applying the ESD test pulse using the measurement system 304. The ESD test system 300 includes an ESD pulse generator, such as pulsers 3141, ... 314 N Where N is a positive integer. Pulse generators 3141, ..., 314 N Coupled to switches including 3161, ... 316 K A switch matrix 316, where K is a positive integer, wherein the switches are coupled to corresponding capacitors 3181, ..., 318. K The capacitor can provide an ESD test pulse to a selected DUT, such as one controlled by processor 306. Typically, pulsers 3141, ... 314... N Coupled to switch 3161, ... 316K One or more of (K>N) are involved, and as shown in the figure, each is connected to three switches. The high-voltage power supply 312 is coupled to the pulser and can be a variable-voltage bipolar power supply, but a fixed unipolar power supply can also be used. In other examples, multiple power supplies can be used.

[0031] Processor 306 is coupled to memory device 308, which stores information for selecting an ESD test model to determine pulse characteristics, such as the amplitude or duration of the ESD test pulse to be applied, the polarity and number of the ESD pulses, and the selection of the DUT to be tested. Processor 308 is coupled to a switching matrix to select an appropriate DUT for testing and can select a test voltage from high-voltage power supply 312. In some examples, processor 306 is coupled to a network to transmit test results and receive instructions regarding the test pulse to be applied and the DUT to be selected.

[0032] Example 4

[0033] refer to Figure 4 A representative method for ESD testing 400 includes selecting an ESD test model at 402 and determining one or more test pulses based on the selected model at 404. Test pulses can be selected to have suitable amplitude, polarity, pulse duration, or other properties. At 406, a suitable capacitor is charged to the test voltage, and at 408, the capacitor is discharged through the DUT and one or more FET pairs, typically at least one back-to-back FET pair. At 410, the DUT is evaluated to determine its response to the test pulses. As discussed above, in some examples, multiple DUTs are tested, and different test pulses may be used for some or all of the DUTs.

[0034] Example 5

[0035] Figure 5 An example system 500 is shown, illustrating some components and values ​​to be used with HBM and MM model tests. System 500 includes a high-voltage power supply 502 connected to charge capacitor 504 with a current regulated by resistor 503. Capacitor 504 is positioned to discharge via resistor 510 through DUT 506 in response to a pulse applied to the gate of the back-to-back FET pair 512 by gate driver 514. As shown, capacitor 504 has a capacitance value of 100 μF and 200 μF for HBM and MM model pulses, respectively, and resistor 510 has a resistance value of 1.5 kΩ and 0 Ω, respectively. The resistors and capacitors used for different ESD models can be switched manually or controlled by a processor.

[0036] Example 6

[0037] refer to Figure 6 The ESD test pulse generator 600 includes isolated DC-DC converters 602 and 603, coupled to receive a +5 V input and generate isolated +20 V and -5 V outputs (labeled +20 V, +5 V, +20 V1, and -5 V1) pointing to capacitor networks 604 and 605, respectively. Opto-isolators 612 and 613 are powered by DC-DC converters 602 and 604 and coupled to a TTL control signal. In response to the TTL control signal, opto-isolators 612 and 613 generate pulse outputs to corresponding gate drivers 622 and 623, which are also powered by associated isolated DC-DC converters 602 and 603. Gate drivers 622 and 623 are coupled to the gates of corresponding FETs 632 and 633. A high-voltage power supply 640 is coupled to capacitor 642, which can be discharged to generate ESD test pulses in the DUT 644.

[0038] General Precautions

[0039] Unless the context clearly specifies otherwise, as used in this specification and claims, the singular forms “a / an” and “the” include the plural forms. Additionally, the term “comprising” means “including”. Furthermore, the term “coupled” does not exclude the existence of intermediate elements between coupled items.

[0040] The systems, apparatuses, and methods described herein should not be construed as limiting in any way. In fact, this disclosure is directed to all novel and non-obvious features and aspects of the various disclosed embodiments, whether individually or in various combinations and sub-combinations formed with each other. The disclosed systems, methods, and apparatuses are not limited to any particular aspect or feature or combination thereof, nor are they required to provide any one or more specific advantages or solve any one or more specific problems. Any operational theory is provided for ease of interpretation, but the disclosed systems, methods, and apparatuses are not limited to such operational theories.

[0041] Although the operations of the disclosed methods are described in a specific order for ease of presentation, it should be understood that this descriptive style encompasses rearrangements unless the specific order is required by the specific language set forth below. For example, in some cases, the operations described in sequence may be rearranged or performed simultaneously. Furthermore, for simplicity, the accompanying drawings may not show the various ways in which the disclosed systems, methods, and apparatus can be used in conjunction with other systems, methods, and apparatus. Additionally, this specification sometimes uses terms such as “produce” and “provide” to describe the disclosed methods. These terms are high-level abstractions of the actual operations performed. The actual operations corresponding to these terms will vary depending on the specific implementation and are readily discernible to those skilled in the art.

[0042] In some examples, values, programs, or devices are referred to as “lowest,” “best,” “smallest,” etc. It will be recognized that such descriptions are intended to indicate that there are many functional alternatives available for selection, and that such selection is not necessarily better, smaller, or preferred over other options.

[0043] As used herein, high voltage (HV) refers to a voltage with an amplitude of at least 200 V, 500 V, 1000 V, or 2000 V. In some examples, an HV power supply can produce an HV with two polarities, but multiple HV power supplies can be used, and the minimum and maximum voltages can have different amplitudes.

[0044] ESD testing can be controlled using a processor equipped with processor-executable instructions, which can be stored in local memory, at a remote memory location, or provided via a network. While the ESD pulse generator can be driven by digital pulses, a digital-to-analog converter (DAC) can also be used to generate the desired pulse shape. The processor can be coupled to an HV power supply to select the voltage and polarity, and can also be coupled to switched resistors and capacitors as needed, depending on the ESD test model used. The processor can also be coupled to a measurement system to evaluate the DUT performance before and / or after subjecting it to an ESD test pulse. Furthermore, the processor can use analog or digital control signals to select the ESD test pulse amplitude, polarity, pulse timing shape, pulse duration, and pulse repetition rate. The processor can also provide random pulse amplitude, duration, polarity, and pulse waveform.

[0045] Given that the principles of the disclosed invention can be applied to many possible embodiments, it should be recognized that the illustrated embodiments are merely preferred examples and should not be considered as limiting the scope of this disclosure.

Claims

1. An electrostatic discharge testing device, comprising: At least a first FET and a second FET are coupled back-to-back; A test voltage source operable to generate bipolar test voltages; An electrostatic discharge test capacitor is configured to be charged by the test voltage source and discharged through the device under test and the first FET and the second FET to generate a test pulse in the device under test. as well as A pulse generator, coupled to generate a control pulse, operable to cause the electrostatic discharge test capacitor to discharge and the test pulse to be generated; First and second optical isolators are coupled to the respective gates of the first FET and the second FET and are coupled to receive the control pulse from the pulse generator.

2. The electrostatic discharge testing apparatus according to claim 1, further comprising first and second pulse circuits, the first and second pulse circuits being coupled to the respective outputs of the first and second opto-isolators and the respective gates of the first FET and the second FET.

3. The electrostatic discharge testing apparatus according to claim 2, further comprising a pulse generator coupled to the first and second opto-isolators to provide first and second gate pulses to the respective gates of the first FET and the second FET.

4. The electrostatic discharge testing apparatus according to claim 3, wherein the test voltage source is operable to generate a bipolar test voltage of at least 200 V.

5. The electrostatic discharge testing apparatus according to claim 4, further comprising a current-adjusting resistor, wherein the test voltage source is coupled to charge the electrostatic discharge test capacitor through the current-adjusting resistor.

6. The electrostatic discharge testing apparatus according to claim 5, wherein the electrostatic discharge testing capacitor is operable to generate MM, HM, or CDM pulses.

7. The electrostatic discharge testing apparatus according to claim 6, wherein the source or drain of one of the first FET and the second FET is coupled between the current regulating resistor and the electrostatic discharge testing capacitor.

8. The electrostatic discharge testing device according to claim 7 further includes an electrostatic discharge testing resistor, wherein the electrostatic discharge testing resistor is connected in series with the electrostatic discharge testing capacitor and the device under test, such that the electrostatic discharge testing current is coupled to the device under test through the electrostatic discharge testing resistor.

9. The electrostatic discharge testing equipment according to claim 8, wherein the electrostatic discharge testing resistor is selected based on the electrostatic discharge testing model.

10. The electrostatic discharge testing apparatus of claim 2, further comprising first and second power supply circuits respectively coupled to the first FET and the second FET, wherein the first and second power supply circuits respectively provide independent voltages to the first and second pulse circuits.

11. The electrostatic discharge testing apparatus of claim 1, wherein the first FET and the second FET form a first back-to-back FET pair, and further comprising a plurality of FETs coupled to the first back-to-back FET pair and operable to generate the test pulse in response to the pulse generator.

12. The electrostatic discharge testing apparatus of claim 11, wherein the FETs of the plurality of FETs are connected as a back-to-back FET pair.

13. The electrostatic discharge testing apparatus of claim 11, further comprising a corresponding opto-isolator, power supply circuit, and pulse circuit coupled to each of the plurality of FETs.

14. An electrostatic discharge testing device, comprising: Multiple electrostatic discharge pulse generators, each configured to generate electrostatic discharge test pulses in at least two or more devices under test in response to activation of at least one back-to-back connected FET pair; A matrix switch, the matrix switch being coupled to the plurality of electrostatic discharge pulse generators and operable to selectively couple one or more of the electrostatic discharge pulse generators to any one of the two or more devices under test; as well as An electrostatic discharge controller, coupled to the matrix switch and operable to select the device under test for coupling to an electrostatic discharge pulse generator.

15. The electrostatic discharge testing apparatus of claim 14, wherein each of the electrostatic discharge pulse generators comprises multiple pairs of back-to-back connected FETs.

16. The electrostatic discharge testing apparatus of claim 14, wherein each of the electrostatic discharge pulse generators comprises a plurality of back-to-back connected FETs.

17. The electrostatic discharge testing apparatus of claim 15, further comprising a bipolar voltage source operable to generate a voltage of at least 400 V and coupled to charge a corresponding test pulse capacitor in each of the electrostatic discharge pulse generators.

18. A method for testing electrostatic discharge, comprising: In response to a gate pulse applied to the gate of a back-to-back SiC FET pair, an electrostatic discharge test pulse is applied to the device under test by discharging an electrostatic discharge test capacitor through the back-to-back SiC FET pair, first and second opto-isolators coupled to the respective gates of the back-to-back SiC FET pair and coupled to receive a control pulse operable to cause the discharge of the electrostatic discharge test capacitor and the generation of the test pulse.

19. The method of claim 18, further comprising selecting an MM, HM, or CDM electrostatic discharge test pulse.

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