Techniques for non-contiguous logical addresses

Abstract

The present application relates to techniques for non-contiguous logical addresses. A first set of commands for accessing a memory device may be received. The first set of commands may include non-contiguous logical addresses corresponding to contiguously indexed physical addresses. A determination may be made based on a first mapping stored in a volatile memory that the non-contiguous logical addresses correspond to contiguously indexed physical addresses. Based on the determination, a second mapping may be transferred to the volatile memory. The second mapping may include an indication of whether information stored at a set of physical addresses is valid. A second set of commands for accessing the memory device may be received, the second set of commands including non-contiguous logical addresses. Data for the second set of commands including the non-contiguous logical addresses may be retrieved from the memory device using the second mapping.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 580,333, filed by Tan et al. on January 20, 2022, entitled “TECHNIQUES FOR NON-CONSECUTIVE LOGICAL ADDRESSES,” and U.S. provisional patent application No. 63 / 232,986, filed by Tan et al. on August 13, 2021, entitled “TECHNIQUES FOR NON-CONSECUTIVE LOGICAL ADDRESSES,” each of which is assigned to its assignee and each of which is expressly incorporated herein in its entirety. Technical Field

[0003] The technical field relates to techniques for non-contiguous logical addresses. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to a logical 1 or a logical 0. In some instances, a single memory cell can support more than two possible states, either of which can be stored. To access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), three-dimensional cross-point memory (3D cross-point), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods of time even in the absence of an external power source. Summary of the Invention

[0006] An apparatus is described. The apparatus may include a memory device; and a controller coupled to the memory device and configured to cause the apparatus to: receive a first set of commands for accessing the memory device, the first set of commands including a non-contiguous first set of logical addresses; determine, based at least in part on a first mapping between logical addresses and physical addresses of the memory device, whether a first set of physical addresses are indexed contiguously, the first set of physical addresses corresponding to the first set of logical addresses; transfer a second mapping from the memory device to a volatile memory device based at least in part on determining that the first set of physical addresses are indexed contiguously, the second mapping indicating whether information stored at a second set of physical addresses including the first set of physical addresses is valid; receive a second set of commands for accessing the memory device, the second set of commands including a non-contiguous second set of logical addresses; and retrieve data from the memory device using the second mapping in response to the second set of commands from a subset of the second set of physical addresses corresponding to the second set of logical addresses.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a first set of commands for accessing a memory device, the first set of commands including a non-contiguous first set of logical addresses; determine, based at least in part on a first mapping between logical addresses and physical addresses of the memory device, whether the first set of physical addresses are indexed contiguously, the first set of physical addresses corresponding to the first set of logical addresses; transfer a second mapping from the memory device to a volatile memory device based at least in part on determining that the first set of physical addresses are indexed contiguously, the second mapping indicating whether information stored at a second set of physical addresses including the first set of physical addresses is valid; receive a second set of commands for accessing the memory device, the second set of commands including a non-contiguous second set of logical addresses; and, in response to the second set of commands, retrieve data from the memory device using the second mapping from a subset of the second set of physical addresses corresponding to the second set of logical addresses.

[0008] A method is described. The method may include receiving a first set of commands for accessing a memory device, the first set of commands including a non-contiguous first set of logical addresses; determining whether the first set of physical addresses are indexed contiguously based at least in part on a first mapping between logical addresses and physical addresses of the memory device, the first set of physical addresses corresponding to the first set of logical addresses; transferring a second mapping from the memory device to a volatile memory device based at least in part on determining that the first set of physical addresses are indexed contiguously, the second mapping indicating whether information stored at a second set of physical addresses including the first set of physical addresses is valid; receiving a second set of commands for accessing the memory device, the second set of commands including a non-contiguous second set of logical addresses; and retrieving data from the memory device using the second mapping from a subset of the second set of physical addresses corresponding to the second set of logical addresses in response to the second set of commands. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting techniques for non-contiguous logical addresses according to examples as disclosed herein is described.

[0010] Figure 2 An example of a system supporting techniques for non-contiguous logical addresses according to examples as disclosed herein is described.

[0011] Figure 3 An example of a flowchart illustrating techniques for supporting non-contiguous logical addresses according to examples as disclosed herein.

[0012] Figure 4A block diagram showing a memory system supporting techniques for non-contiguous logical addresses according to examples as disclosed herein.

[0013] Figure 5 A flowchart illustrating one or more methods of supporting techniques for non-contiguous logical addresses according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0014] A host system may consistently write and rewrite data (e.g., in the same order) to a set of non-contiguous logical addresses associated with memory locations of a memory device. In some instances, the distance between the non-contiguous logical addresses is significant, and different portions of a table providing a mapping between logical addresses and physical addresses may be separately loaded into a volatile memory of the memory system to determine the correspondence between the non-contiguous logical addresses and the corresponding physical addresses. In some instances, data written to the set of non-contiguous logical addresses is stored at consecutive physical addresses of the memory device, e.g., based on consistently writing the data in the same order, even if the data is written to the non-contiguous logical addresses.

[0015] Although the information associated with the set of non-contiguous logical addresses is stored in contiguous physical addresses, non-contiguous read techniques can be used to retrieve information from physical memory based on the logical addresses being non-contiguous. Conversely, if a set of commands is received that includes contiguous logical addresses corresponding to the set of contiguous physical addresses, a multi-plane read operation (which may also be referred to as a simultaneous or sequential read operation) may be triggered. Thus, in response to a set of read commands that include the set of non-contiguous logical addresses, individual read operations may be performed to retrieve information from individual physical addresses in the set of contiguous physical addresses, rather than performing a multi-plane read operation to retrieve information from some (or all) of the set of contiguous physical addresses. Performing individual read operations for the set of read commands may be associated with increased power consumption and higher latency compared to performing a multi-plane read operation, for example based on performing additional access operations and loading different portions of a mapping between the logical addresses and the physical addresses on which the read commands are to be performed.

[0016] In order to reduce the latency, power consumption, or both of a memory system, a pattern for accessing a memory device may be established in response to a set of read commands, the set of read commands including non-contiguous logical addresses corresponding to continuously indexed physical addresses. In response to activating the pattern, the memory system may use a validity table and metadata stored in pages of the physical memory to determine a mapping between logical addresses and physical addresses. In some instances, the memory system may also perform a multi-plane read operation in response to receiving a read command, wherein the multi-plane read operation may access consecutive physical addresses associated with the logical address of the read command. In some instances, the pattern may be activated based at least in part on receiving a threshold number of read commands having non-contiguous logical addresses corresponding to consecutive physical addresses. By activating a pattern associated with implementing multi-plane read operations performed on commands including non-contiguous logical addresses, latency, power consumption, or both associated with executing the commands may be improved.

[0017] Initial reference Figures 1 to 2 Features of the present disclosure are described in the context of systems and devices. Features of the present disclosure are also described in the context of flow charts. These and other features of the present disclosure are further illustrated and described in the context of device diagrams and flow charts related to techniques for non-contiguous logical addresses.

[0018] Figure 1 An example of a system 100 supporting techniques for non-contiguous logical addresses according to examples as disclosed herein is illustrated. The system 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0020] System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0021] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0022] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM socket interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, host system 105 may be coupled to memory system 110 via a respective physical host interface for each memory device 130 included in memory system 110, or via a respective physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but memory system 110 may include any number of memory devices 130. Furthermore, if memory system 110 includes more than one memory device 130, different memory devices 130 within memory system 110 may include the same or different types of memory cells.

[0024] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations, which can generally be referred to as access operations, at the memory devices 130, such as reading data, writing data, erasing data, or updating data, as well as other such operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or operations related to the functions attributed herein to the memory system controller 115.

[0028] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0029] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1As illustrated in FIG, memory device 130 - a may include a local controller 135 - a, and memory device 130 - b may include a local controller 135 - b.

[0030] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0031] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as single-level cells (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as multi-level cells (MLC) if configured to store two bits of information each, triple-level cells (TLC) if configured to store three bits of information each, quad-level cells (QLC) if configured to store four bits of information each, or more generally, multi-level memory cells. Multi-level memory cells may provide greater storage density relative to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0032] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which parallel operations may occur. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks included in one or more planes of memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, performing parallel operations in different planes 165 may be subject to one or more limitations, such as performing parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., with respect to command decode, page address decode circuitry, and other circuitry shared across planes 165).

[0033] In some cases, block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share (e.g., be coupled to) a common word line, and memory cells in the same string can share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0034] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level), but can be erased at a second level of granularity (e.g., at a block granularity level). That is, a page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (programmed or read simultaneously as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be overwritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 including the page 175 has been erased.

[0035] In some cases, to update some data within a block 170 while preserving other data within the block 170, the memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. The memory device 130 (e.g., the local controller 135) or the memory system controller 115 may mark or otherwise indicate the data remaining in the old block 170 as invalid or outdated and may update a logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 rather than the old invalid block 170. In some cases, such copying and remapping may be performed rather than erasing and rewriting the entire old block 170, for example due to latency or wear considerations. In some cases, one or more copies of the L2P mapping table may be stored within a memory location of the memory device 130 (e.g., within one or more blocks 170 or planes 165) for use (e.g., reference and updating) by the local controller 135 or the memory system controller 115.

[0036] In some cases, an L2P mapping table may be maintained and data may be marked as valid or invalid at a page granularity level, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that is outdated because the latest or updated version of the data is stored in a different page 175 of the memory device 130. Invalid data may have been previously programmed to an invalid page 175, but may no longer be associated with a valid logical address, such as a logical address referenced by the host system 105. Valid data may be the latest version of this data stored on the memory device 130. A page 175 that does not contain data may be a page 175 that has never been written to or has been erased.

[0037] The system 100 may include any number of non-transitory computer-readable media that support techniques for non-contiguous logical addresses. For example, the host system 105, the memory system controller 115, or the memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to the host system 105, the memory system controller 115, or the memory device 130. For example, if executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, or by the memory device 130 (e.g., by the local controller 135), such instructions may cause the host system 105, the memory system controller 115, or the memory device 130 to perform one or more associated functions as described herein.

[0038] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and related circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0039] To reduce latency, power consumption, or both of the memory system, a pattern for accessing the memory device 130 can be established in response to a set of read commands that include non-contiguous logical addresses corresponding to consecutively indexed physical addresses. In response to activating the pattern, the memory system 110 can use a validity table and metadata stored in pages of physical memory to determine a mapping between logical addresses and physical addresses. In some examples, the memory system 110 can also perform multi-plane read operations in response to receiving the read commands, wherein the multi-plane read operations can access consecutive physical addresses associated with the logical addresses of the read commands. In some examples, the pattern can be activated based at least in part on receiving a threshold number of read commands that have non-contiguous logical addresses corresponding to consecutive physical addresses.

[0040] Figure 2 An example of a system 200 that supports techniques for non-contiguous logical addresses according to examples disclosed herein is illustrated. The system 200 may be a system 200 as described in reference to Figure 1 or aspects thereof. The system 200 may include a memory system 210 configured to store data received from a host system 205 and to send the data to the host system 205 if requested by the host system 205 using an access command (e.g., a read command or a write command). The system 200 may be implemented as described with reference to Figure 1 Aspects of the described system 100. For example, memory system 210 and host system 205 can be instances of memory system 110 and host system 105, respectively.

[0041] As described herein, the memory system 210 may include a memory device 240 to store data transferred between the memory system 210 and the host system 205, for example, in response to receiving an access command from the host system 205. The memory device 240 may include a memory device 240 as described in reference Figure 1 For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0042] The memory system 210 may include a memory controller 230 for controlling the transfer of data directly into and out of the memory devices 240, such as for storing data, retrieving data, and determining memory locations in which data is to be stored and from which data is to be retrieved. The memory controller 230 may communicate with the memory devices 240 directly or via a bus (not shown) using a protocol specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, the memory system 210 may include multiple memory controllers 230, such as a different memory controller 230 for each type of memory device 240. In some cases, the memory controller 230 may be implemented as described with reference to FIG. Figure 1 Aspects of the local controller 135 are described.

[0043] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 may be used to convert data between the host system 205 and the memory device 240, such as shown by the data path 250, and may be collectively referred to as data path components.

[0044] Using buffer 225 to temporarily store data during transfer allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing arbitrary data sizes associated with commands. This can also allow bursts of commands to be processed, and once the burst stops, the buffered data can be stored or transferred (or both). Buffer 225 can include relatively fast memory (e.g., some type of volatile memory, such as SRAM or DRAM), or a hardware accelerator, or both, to allow for fast storage and retrieval of data into and out of buffer 225. Buffer 225 can include a data path switching component for bidirectional data transfer between buffer 225 and other components.

[0045] Temporary storage of data within buffer 225 may refer to storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten by data for an additional access command). Furthermore, buffer 225 may be a non-cacheable buffer. That is, the host system 205 may not read data directly from buffer 225. For example, a read command may be added to a queue without performing an operation to match the address with an address already in buffer 225 (e.g., no cache address matching or lookup operation).

[0046] The memory system 210 may further include a memory system controller 215 for executing commands received from the host system 205 and controlling the data path components when moving data. The memory system controller 215 may be a memory system controller such as the one described in the referenced example. Figure 1 An example of a memory system controller 115 is depicted. Bus 235 may be used for communication between system components.

[0047] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and store queue 270) may be used to control the processing of access commands and the movement of corresponding data. This may be beneficial, for example, if the memory system 210 processes more than one access command from the host system 205 in parallel. As examples of possible implementations, the command queue 260, buffer queue 265, and store queue 270 are depicted at the interface 220, the memory system controller 215, and the storage controller 230, respectively. However, the queues, if used, may be located anywhere within the memory system 210.

[0048] Data transferred between the host system 205 and the memory device 240 may take a different path in the memory system 210 than non-data information (e.g., commands, status information). For example, system components in the memory system 210 may communicate with each other using the bus 235, while data may use the data path 250 via data path components instead of the bus 235. The memory system controller 215 may control how and whether data is transferred between the host system 205 and the memory device 240 by communicating with the data path components over the bus 235 (e.g., using a protocol specific to the memory system 210).

[0049] If the host system 205 transmits an access command to the memory system 210, the interface 220 may receive the command, for example, according to a protocol (e.g., the UFS protocol or the eMMC protocol). Therefore, the interface 220 may be considered the front end of the memory system 210. After receiving each access command, the interface 220 may transmit the command to the memory system controller 215, for example, via the bus 235. In some cases, each command may be added to the command queue 260 by the interface 220 for transmission to the memory system controller 215.

[0050] The memory system controller 215 may determine that an access command has been received based on a communication from the interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving the command from the command queue 260. After the command has been retrieved from the command queue 260, for example, by the memory system controller 215, it may be removed from the command queue 260. In some cases, the memory system controller 215 may cause the interface 220 to remove the command from the command queue 260, for example, via the bus 235.

[0051] After determining that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0052] In either case, the memory system controller 215 may use the buffer 225 for, among other things, temporary storage of data received from or sent to the host system 205. The buffer 225 may be considered an intermediary for the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0053] To process a write command received from the host system 205, the memory system controller 215 may first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, e.g., via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the write command.

[0054] In some cases, the buffer queue 265 can be used to control the flow of commands associated with data stored in the buffer 225, including write commands. The buffer queue 265 can include access commands associated with the data currently stored in the buffer 225. In some cases, commands in the command queue 260 can be moved to the buffer queue 265 by the memory system controller 215 and can remain in the buffer queue 265 while the associated data is stored in the buffer 225. In some cases, each command in the buffer queue 265 can be associated with an address at the buffer 225. That is, a pointer can be maintained indicating the location in the buffer 225 where the data associated with each command is stored. Using the buffer queue 265, multiple access commands can be received sequentially from the host system 205, and at least some of the access commands can be processed in parallel.

[0055] If the buffer 225 has sufficient space to store the write data, the memory system controller 215 can cause the interface 220 to transmit an indication of availability to the host system 205 (e.g., a "ready to transfer" indication), for example, according to a protocol (e.g., a UFS protocol or an eMMC protocol). When the interface 220 subsequently receives data associated with a write command from the host system 205, the interface 220 can use the data path 250 to transfer the data to the buffer 225 for temporary storage. In some cases, the interface 220 can obtain the location within the buffer 225 where the data is to be stored from the buffer 225 or the buffer queue 265. The interface 220 can indicate to the memory system controller 215, for example, via the bus 235, whether the data transfer to the buffer 225 has been completed.

[0056] Once the write data has been stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve the data from buffer 225 and transfer the data to memory device 240 using data path 250. Memory controller 230 can be considered the back end of memory system 210. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235, that the data transfer to a memory device in memory device 240 has been completed.

[0057] In some cases, storage queue 270 may be used to facilitate the delivery of write data. For example, memory system controller 215 may push a write command from buffer queue 265 (e.g., via bus 235) to storage queue 270 for processing. Storage queue 270 may include an entry for each access command. In some examples, storage queue 270 may additionally include a buffer pointer (e.g., an address) that may indicate a location in buffer 225 where data associated with the command is stored, and a storage pointer (e.g., an address) that may indicate a location in memory device 240 associated with the data. In some cases, storage controller 230 may obtain the location within buffer 225 from which data is to be obtained from buffer 225, buffer queue 265, or storage queue 270. Storage controller 230 may manage the locations within memory device 240 used to store data (e.g., to perform wear leveling, garbage collection, etc.). Entries may be added to storage queue 270, for example, by memory system controller 215. After the transfer of data is complete, the entry may be removed from the store queue 270 , for example, by the memory controller 230 or the memory system controller 215 .

[0058] To process a read command received from the host system 205, the memory system controller 215 may again first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, e.g., via firmware (e.g., controller firmware), the amount of space available within the buffer 225 to store the data associated with the read command.

[0059] In some cases, the buffer queue 265 can be used to assist in buffer storage of data associated with a read command in a similar manner as discussed above with respect to a write command. For example, if the buffer 225 has sufficient space to store the read data, the memory system controller 215 can cause the memory controller 230 to retrieve the data associated with the read command from the memory device 240 and store the data in the buffer 225 using the data path 250 for temporary storage. The memory controller 230 can indicate to the memory system controller 215, for example, via the bus 235, when the data transfer to the buffer 225 has been completed.

[0060] In some cases, storage queue 270 can be used to assist in the delivery of read data. For example, memory system controller 215 can push read commands to storage queue 270 for processing. In some cases, storage controller 230 can obtain the location within memory device 240 from which data is to be retrieved from buffer 225 or storage queue 270. In some cases, storage controller 230 can obtain the location within buffer 225 from which data is to be stored from buffer queue 265. In some cases, storage controller 230 can obtain the location within buffer 225 from which data is to be stored from storage queue 270. In some cases, memory system controller 215 can move commands processed by storage queue 270 back to command queue 260.

[0061] Once the data has been stored in the buffer 225 by the memory controller 230, the data may be transferred from the buffer 225 and sent to the host system 205. For example, the memory system controller 215 may cause the interface 220 to retrieve the data from the buffer 225 using the data path 250 and transmit the data to the host system 205, e.g., according to a protocol (e.g., the UFS protocol or the eMMC protocol). For example, the interface 220 may process commands from the command queue 260 and may indicate to the memory system controller 215, e.g., via the bus 235, that the data transfer to the host system 205 has been completed.

[0062] The memory system controller 215 may execute the received commands in order (e.g., in a first-in, first-out order according to the order of the command queue 260). For each command, the memory system controller 215 may move data corresponding to the command into and out of the buffer 225, as discussed above. The command may remain in the buffer queue 265 while the data is moved into and stored within the buffer 225. If processing of the command is complete (e.g., if data corresponding to an access command has been transferred from the buffer 225), the command may be removed from the buffer queue 265, for example, by the memory system controller 215. If a command is removed from the buffer queue 265, the address where the data associated with the command was previously stored may be used to store data associated with a new command.

[0063] The memory system controller 215 may also be configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background flushing, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue a command indicating one or more LBAs, and the memory system controller 215 may identify the one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the storage controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the storage controller 230 and the storage controller 230 may be omitted.

[0064] In some examples, the host system 205 consistently writes and rewrites information to non-contiguous logical addresses associated with the memory device 240, for example, in the same order. For example, the host system 205 can consistently write and rewrite information to the non-contiguous logical addresses in the same order while performing periodic maintenance operations that periodically check or update the same set of information. In some examples, the host system 205 transmits a set of commands including non-contiguous logical addresses to the memory device 240, where each command can be associated with a subset of information (e.g., of varying size). The memory device 240 can determine the physical addresses corresponding to the non-contiguous logical addresses and write the data associated with the logical addresses to the storage elements at the corresponding physical addresses. In some examples, the memory device 240 uses a table including a mapping between physical addresses and logical addresses to determine which physical addresses correspond to the non-contiguous logical addresses. The table may be referred to as an L2P table, and while portions of the L2P table may be stored in volatile memory 275 (eg, SRAM), the entire L2P table may be too large to store on volatile memory 275 and may instead be stored in memory device 240 .

[0065] In some instances, the distance between non-contiguous logical addresses may be significant, for example, and therefore, the logical-to-physical address mappings for different non-contiguous logical addresses may be represented in different portions of the L2P table. In such cases, when processing non-contiguous logical addresses, the memory device may load different portions of the L2P table from memory device 240 into volatile memory 275 separately. For example, upon receiving a command containing a first logical address of non-contiguous logical addresses, the first portion of the L2P table may be loaded, and upon receiving a command containing a second logical address of non-contiguous logical addresses, the second portion of the L2P table may be loaded. Accessing memory cells at non-contiguously indexed logical addresses may be referred to as dirty read performance. In some cases, loading one portion of the L2P table into volatile memory 275 may overwrite another portion of the L2P table stored in volatile memory 275. Furthermore, loading portions of the L2P table into volatile memory 275 to execute a received read command may increase the latency associated with executing the received read command.

[0066] In some examples, after consistently rewriting the information to non-contiguous logical addresses a threshold number of times (e.g., in the same order), the information may be stored in physical addresses of the memory device 240 that are contiguously indexed (which may also be referred to as sequentially indexed). The contiguously indexed physical addresses are located in complementary positions across a plane (e.g., in a common index page of a common index block in another page), are located adjacent to each other (e.g., in an earlier or later indexed page), or both. Sequential read operations may be used to access information stored at the contiguously indexed physical addresses, where the sequential read operations may be used to access an increased amount of data in a shorter duration than would be possible using separate read operations to access information stored at the contiguous physical addresses.

[0067] Although the information associated with the set of non-contiguous logical addresses is stored in contiguous physical addresses, the storage controller 230 may use non-contiguous read techniques to retrieve information from the physical memory based on the logical addresses being non-contiguous. In contrast, if the storage controller 230 were to receive a set of commands including contiguous logical addresses corresponding to the set of contiguous physical addresses, a multi-plane read operation (which may also be referred to as a simultaneous or sequential read operation) may be triggered at the storage controller 230. Thus, in response to a set of read commands including the set of non-contiguous logical addresses, the storage controller 230 may perform individual read operations to retrieve information from individual physical addresses in the set of contiguous physical addresses, rather than performing a multi-plane read operation to retrieve information from part (or all) of the set of contiguous physical addresses. For example, performing individual read operations for the set of read commands based on loading different portions of a mapping between logical addresses and physical addresses to execute the read commands may be associated with increased power consumption and higher latency compared to performing a multi-plane read operation.

[0068] To reduce latency, power consumption, or both of a memory system, a pattern for accessing a memory device may be established in response to a set of read commands that include non-contiguous logical addresses corresponding to consecutively indexed physical addresses. In response to activating the pattern, the memory system may use a validity table and metadata stored in pages of physical memory to determine a mapping between logical addresses and physical addresses. In some examples, the memory system may also perform a multi-plane read operation in response to receiving a read command, wherein the multi-plane read operation may access consecutive physical addresses associated with the logical addresses of the read command. In some examples, the pattern may be activated based at least in part on receiving a threshold number of read commands having non-contiguous logical addresses corresponding to consecutive physical addresses.

[0069] By activating a mode associated with enabling multi-plane read operations executed for commands containing non-contiguous logical addresses, latency, power consumption, or both associated with executing the commands may be improved.

[0070] Figure 3 An example of a flowchart 300 is illustrated to support techniques for non-contiguous logical addresses according to examples as disclosed herein.

[0071] Flowchart 300 depicts operations associated with entering a mode for increasing performance of a memory device in response to a command containing a non-contiguously indexed logical address corresponding to a contiguously indexed physical address. Flowchart 300 also depicts operations associated with determining a mapping between logical addresses and physical addresses using a physical validity table and metadata after entering the mode. This may be performed in a memory system, such as Figure 2 The operations of flowchart 300 are performed at the memory system 210 of FIG.

[0072] It should be understood that one or more operations described in flowchart 300 may be performed earlier or later in the process, omitted, replaced, supplemented, or combined with another operation. Moreover, additional operations described herein that are not included in flowchart 300 may be included.

[0073] At block 305, a memory system may be configured to store data, for example, at an interface of the memory system (e.g., Figure 2 interface 220) from a host system (e.g., Figure 2 The host system 205 receives one or more read commands. The read commands may include a logical address and may request that a corresponding data packet be stored at the logical address.

[0074] At block 310, a determination may be made as to whether a set of consecutive read commands includes non-consecutive logical addresses corresponding to consecutive physical addresses. In some examples, a memory system controller (e.g., Figure 2 The memory system controller 215 may be used to determine whether consecutive read commands contain non-consecutive logical addresses corresponding to consecutive physical addresses. To determine whether a set of consecutive read commands contain non-consecutive logical addresses, the memory system controller may compare the logical addresses of the read commands with the logical addresses of the previous read command. Similarly, to determine whether non-consecutive logical addresses contained in consecutive read commands correspond to consecutive physical addresses, the memory system controller may compare the physical addresses corresponding to the logical addresses with the physical addresses corresponding to the previous logical addresses.

[0075] To determine which physical address corresponds to a logical address, the memory system controller may use data stored in volatile memory (e.g., Figure 2In some examples, the memory system controller may determine that the next logical address is not contained in the portion of the L2P table stored in the volatile memory and load a second portion of the L2P table into the volatile memory that contains the next logical address. After loading the second portion of the L2P table, the memory system controller may use the second portion of the L2P table to determine which physical address corresponds to the next logical address. In some examples, the memory system controller determines that the logical addresses in the consecutive read commands are non-consecutively indexed and that the corresponding physical addresses are consecutively indexed.

[0076] At diamond 315, a determination is made as to whether the number of read commands (e.g., consecutive read commands) that include non-consecutive logical addresses corresponding to consecutive physical addresses exceeds a threshold value (e.g., 10 instances). In some instances, the memory system controller tracks a certain number of such read commands. In some instances, the memory system maintains a consecutive count of such read commands and determines whether the number of such read commands exceeds a threshold value within a specified time period. In other instances, if a group of consecutive read commands includes consecutive logical addresses or includes non-consecutive logical addresses corresponding to non-consecutive physical addresses, the memory system resets the count of such read commands. If the memory system controller determines that the number of such read commands exceeds the threshold value, the memory system controller may perform the operations described at block 325. Otherwise, the memory system controller may perform the operations described at block 320.

[0077] At block 320, a non-contiguous read operation may be performed to access information stored at a physical address corresponding to a logical address included in the received read command. In some examples, the memory system controller, in conjunction with a storage controller (e.g., Figure 2 In some embodiments, the memory controller 230 may be configured to perform non-sequential read operations. In such cases, the memory system controller may perform a non-sequential read operation for each read command, which may include using a relevant portion of the L2P table and reading the identified portion of memory for each read command, respectively. In some examples, using the relevant portion of the L2P table may include first loading the relevant portion of the L2P table into volatile memory.

[0078] At block 325, a mode for increasing the performance of the memory device associated with processing read commands containing non-contiguous logical addresses (which may be referred to as a dirty read condition) may be enabled based on the number of read commands containing non-contiguous logical addresses corresponding to consecutive physical addresses exceeding a threshold. In some examples, the mode is activated at a memory system controller. In some examples, the memory system controller activates the mode at a storage controller. In some examples, after enabling the mode, a multi-plane read operation may be performed to execute the read command. In a first option (option A), after performing the operations at block 330, the operations at blocks 335 to 350 may be performed to execute the read command after entering the mode. In a second option (option B), after performing the operations at block 330, the operations at blocks 355 to 375 may be performed to execute the read command after entering the mode.

[0079] At block 330, for example, instead of using an L2P table, a physical validity table and metadata associated with the received read command may be loaded into volatile memory for use as part of the read operation. In some examples, the memory system controller loads the physical validity table associated with the physical address associated with the received read command into the volatile memory. In some examples, the physical validity table may indicate the validity of information stored in one or more blocks of physical addresses across one or more planes, where the blocks of physical addresses may include the physical address associated with the received read command. The memory system controller may also load metadata associated with pages of physical addresses included in the one or more blocks of physical addresses into the volatile memory. In some examples, each page stores metadata including an indication of which logical block address the page stores information for. Thus, between the physical validity table and the metadata, the memory system controller can determine a mapping between logical addresses received in a set of read commands that include non-contiguous logical addresses corresponding to physical addresses in the blocks of physical addresses. For example, the metadata may include the logical address corresponding to the physical address. The memory system can be configured to access metadata for subsequently indexed physical addresses and retrieve their associated logical addresses. The retrieved logical addresses can be compared with the logical addresses received in the read command. Thus, when the physical addresses of retrieved data are continuously indexed, the validity map and metadata can be used to verify that the correct physical address is being accessed, rather than using the L2P map.

[0080] The first option (Option A) for executing a read command and loading the physical validity table and metadata into volatile memory after entering the mode is described in the context of blocks 335 through 350 .

[0081] At block 335, one or more read commands may be received, for example, at an interface of the memory system. The one or more read commands may include non-contiguously indexed logical addresses corresponding to contiguously indexed physical addresses. Based on implementing a performance boost mode, the memory system controller may execute the one or more read commands using a multi-plane read operation.

[0082] At block 340, a physical address corresponding to a logical address received in a read command in one or more read commands may be identified based on the physical validity table and the metadata. In some instances, the memory system controller searches the metadata for a logical address corresponding to the received logical address. In some cases, the memory system controller may identify multiple sets of metadata (associated with different pages) containing the logical address. The memory system controller may also use the physical validity table to determine whether (or which of the pages) associated with the metadata containing the logical address is storing valid information. After determining that the page is storing valid information (or after identifying the page storing valid information), the memory system controller may determine the physical address corresponding to the logical address. In such cases, the memory system controller may not use the L2P table to determine the mapping between the logical address and the physical address, and in some instances, may remove one or more portions of the L2P table previously stored in the volatile memory from the volatile memory.

[0083] At block 345, a read operation (e.g., a multi-plane read operation) may be performed based on the identified physical address. In some examples, the memory system controller causes the storage controller to access the memory cell at the identified physical address. In some examples, the memory system controller causes the storage controller to perform a multi-plane read of the memory cell at the identified physical address and to perform a multi-plane read of the memory cell at consecutively indexed physical addresses (e.g., in other planes of the memory device).

[0084] At block 350, data may be output based on the completed read operations. In some examples, the memory system outputs data after each read operation. In some examples, the memory system controller outputs data after a multi-plane read operation corresponding to multiple received read commands. In some examples, the memory system controller encapsulates the read data in a DATAIN packet before outputting the data to the host system.

[0085] By loading the physical validity table and metadata into volatile memory, read commands containing non-contiguous logical addresses can be mapped to physical addresses without having to load them in different parts of the L2P table, thereby reducing the power consumption and latency associated with processing read commands. Furthermore, by enabling multi-plane read operations for read commands containing non-contiguous logical addresses, increased amounts of data can be read in a single operation, further reducing the power consumption and latency associated with reading the same amount of data through multiple non-contiguous read operations.

[0086] A second option (Option B) for executing a read command and loading the physical validity table and metadata into volatile memory after entering the mode is described in the context of blocks 355 through 375 .

[0087] At block 355, a pre-read operation may be performed to fill the read buffer. In some instances, the pre-read operation may include performing one or more multi-plane reads of data stored in a memory block associated with the physical validity table until some or all entries in the read buffer are occupied. In some instances, the initial address of the multi-plane read is based on a physical address associated with a read command received immediately before entering the performance boost mode. In some instances, the mapping between logical addresses and entries in the buffer may be stored in volatile memory. In some instances, the mapping between physical addresses and entries in the buffer may be stored in volatile memory. The pre-read operation may be based on a prediction that one or more physical addresses subsequently indexed relative to the physical address associated with the read operation may be requested in a subsequent read operation. This prediction may be based on a certain number of read operations accessing consecutively indexed physical addresses.

[0088] At block 360 , a physical address corresponding to a logical address received in a read command in the one or more read commands may be identified based on the physical validity table and the metadata, as similarly described with reference to block 340 .

[0089] At block 365, one or more read commands may be received, for example, at an interface of a memory system.The one or more read commands may include non-contiguously indexed logical addresses corresponding to contiguously indexed physical addresses.

[0090] At block 370, data corresponding to the received one or more commands may be identified in the buffer. In some examples, the memory system controller, the storage controller, or both may identify an entry in the buffer corresponding to a logical address included in the one or more commands. In some examples, if the data associated with the logical address is not stored in the data buffer, the storage controller may perform a read operation (e.g., a single-to-multi-plane read operation) to access the data from physical memory.

[0091] At block 375, the identified data may be output, for example, to a host system. In some examples, components of the memory system may encapsulate the data in DATAIN packets before outputting the data to the host system. In some examples, after the identified data is output to the host system, the identified data may be removed from the data buffer, for example, to free up space for additional data stored at other physical addresses.

[0092] Performing the operations of Option B may similarly reduce power consumption, latency, or both, as described with reference to Option B. In some examples, the operations of Option B may further reduce power consumption, latency, or both by using pre-read operations to store data in the read buffer, e.g., by reducing the number of access operations performed at the memory device and based on accessing the read buffer with lower latency than the memory device.

[0093] At block 380, the performance boost mode may be exited. In some examples, the performance boost mode is exited based on a subsequent set of read commands that include logical addresses corresponding to physical addresses in a different block than the block associated with the physical validity table and metadata stored in the volatile memory. In some examples, the performance boost mode is exited based on receiving a specific command (e.g., based on receiving a write command or an unmap command). In some examples, the memory system enters the non-continuous read mode based on exiting the performance boost mode.

[0094] Figure 4 A block diagram 400 is shown of a memory system 420 that supports techniques for non-contiguous logical addresses according to examples as disclosed herein. The memory system 420 may be a memory system 420 as described in reference to FIG. Figures 1 to 3 4. The memory system 420 and its various components may be examples of devices for performing various aspects of the techniques for non-contiguous logical addresses as described herein. For example, the memory system 420 may include a command interface 425, a mapping component 430, an access component 435, an operating mode manager 440, an output component 445, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0095] The command interface 425 may be configured to or otherwise support means for receiving a first set of commands for accessing a memory device, the first set of commands comprising a non-contiguous first set of logical addresses. The mapping component 430 may be configured to or otherwise support means for determining whether the first set of physical addresses are indexed contiguously based at least in part on a first mapping between logical addresses and physical addresses of the memory device, the first set of physical addresses corresponding to the first set of logical addresses. In some examples, the mapping component 430 may be configured to or otherwise support means for transferring a second mapping from the memory device to the volatile memory device based at least in part on determining that the first set of physical addresses are indexed contiguously, the second mapping indicating whether information stored at a second set of physical addresses comprising the first set of physical addresses is valid. In some examples, the command interface 425 may be configured to or otherwise support means for receiving a second set of commands for accessing the memory device, the second set of commands comprising a non-contiguous second set of logical addresses. The access component 435 can be configured to or otherwise support means for retrieving data from the memory device from a subset of the second set of physical addresses corresponding to the second set of logical addresses using the second mapping in response to the second set of commands.

[0096] In some instances, to support determining whether the first set of physical addresses are indexed consecutively, the mapping component 430 may be configured as or otherwise support a device for determining that the first set of physical addresses are indexed consecutively based at least in part on the first mapping, wherein the number of the first set of physical addresses that are indexed consecutively is greater than a threshold.

[0097] In some examples, the operating mode manager 440 may be configured to or otherwise support a device for activating a mode associated with accessing data stored at consecutive physical addresses based at least in part on determining that the first set of physical addresses are indexed consecutively, wherein a second mapping is passed to the volatile memory device and the second mapping is used to retrieve data associated with a second set of commands based at least in part on activating the mode.

[0098] In some examples, operating mode manager 440 may be configured or otherwise support means for disabling the mode based at least in part on receiving a command for accessing the memory device, the command including a logical address corresponding to a physical address that does not overlap with the second set of physical addresses.

[0099] In some examples, operating mode manager 440 may be configured or otherwise support means for disabling the mode based at least in part on receiving a command to write to the memory device or to perform an unmap operation.

[0100] In some examples, to support transferring the second mapping, the mapping component 430 may be configured to or otherwise support means for transferring to the volatile memory device a third mapping indicating whether data stored at the second set of physical addresses is valid and a third set of logical addresses stored at corresponding pages associated with the second set of physical addresses, the third set of logical addresses including at least a portion of the second set of logical addresses.

[0101] In some examples, mapping component 430 can be configured as or otherwise support means for determining a correspondence between a subset of the third set of logical addresses and the second set of physical addresses, wherein the second mapping is based at least in part on the correspondence.

[0102] In some examples, to support retrieval of data from the memory device, access component 435 may be configured or otherwise support means for performing a set of read operations on a set of consecutive physical addresses indicated in the second mapping based at least in part on receiving a second set of commands. In some examples, to support retrieval of data from the memory device, access component 435 may be configured or otherwise support means for storing a set of data in a buffer based at least in part on performing the set of read operations. In some examples, to support retrieval of data from the memory device, access component 435 may be configured or otherwise support means for identifying, in the buffer, a subset of the set of data corresponding to the second set of commands. In some examples, to support retrieval of data from the memory device, output component 445 may be configured or otherwise support means for transferring a subset of the set of data from the buffer to an output buffer for transmission to a host system based at least in part on identifying the subset of the set of data.

[0103] In some examples, output component 445 may be configured or otherwise support means for transmitting a subset of the set of data to a host system based at least in part on the transferring.

[0104] In some examples, to support retrieval of data from the memory device, mapping component 430 can be configured or otherwise support means for retrieving data without using the first mapping.

[0105] In some examples, to support determining whether the first set of physical addresses are indexed contiguously, the mapping component 430 may be configured to or otherwise support means for transferring multiple portions of the first mapping from the memory device to the volatile memory device based at least in part on the first set of logical addresses, wherein subsets of the first set of logical addresses are associated with different portions of the multiple portions based at least in part on the first set of logical addresses being non-contiguous.

[0106] In some examples, to support determining whether the first set of physical addresses is indexed consecutively, mapping component 430 may be configured or otherwise support means for communicating the entire second mapping to the volatile memory device based at least in part on determining that the first set of physical addresses is indexed consecutively.

[0107] In some examples, the second mapping indicates whether a second set of physical addresses stores valid data or invalid data, the second set of physical addresses being associated with a third set of logical addresses that includes the first set of logical addresses and the second set of logical addresses.

[0108] Figure 5 A flowchart illustrating a method 500 for supporting techniques for non-contiguous logical addresses according to examples disclosed herein is shown. The operations of the method 500 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 500 may be implemented by a memory system or components thereof as described herein. Figures 1 to 4 The memory system described herein performs. In some examples, the memory system may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0109] At 505, the method may include receiving a first set of commands for accessing a memory device, the first set of commands including a non-contiguous first set of logical addresses. The operations of 505 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 505 may be as described in reference to Figure 4 The command interface 425 is described.

[0110] At 510, the method may include determining whether to contiguously index a first set of physical addresses based at least in part on a first mapping between logical addresses and physical addresses of a memory device, the first set of physical addresses corresponding to the first set of logical addresses. The operations of 510 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 510 may be as described in reference to Figure 4 The mapping component 430 performs as described.

[0111] At 515, the method may include transferring a second map from the memory device to the volatile memory device based at least in part on determining that the first set of physical addresses is indexed consecutively, the second map indicating whether information stored at the second set of physical addresses including the first set of physical addresses is valid. The operations of 515 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 515 may be described by reference to Figure 4 The mapping component 430 performs as described.

[0112] At 520, the method may include receiving a second set of commands for accessing the memory device, the second set of commands including a second set of non-contiguous logical addresses. The operations of 520 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 520 may be as described with reference to Figure 4 The command interface 425 is described.

[0113] At 525, the method may include retrieving data from the memory device from a subset of the second set of physical addresses corresponding to the second set of logical addresses using the second mapping in response to the second set of commands. The operations of 525 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 525 may be described by reference to Figure 4 The described access component 435 performs.

[0114] In some examples, an apparatus as described herein may perform one or more methods, such as method 500. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a first set of commands for accessing a memory device, the first set of commands including a non-contiguous first set of logical addresses; determining, based at least in part on a first mapping between logical addresses and physical addresses of the memory device, whether the first set of physical addresses are indexed contiguously, the first set of physical addresses corresponding to the first set of logical addresses; transferring, based at least in part on determining that the first set of physical addresses are indexed contiguously, from the memory device to a volatile memory device a second mapping indicating whether information stored at a second set of physical addresses including the first set of physical addresses is valid; receiving a second set of commands for accessing the memory device, the second set of commands including a non-contiguous second set of logical addresses; and retrieving data from the memory device from a subset of the second set of physical addresses corresponding to the second set of logical addresses using the second mapping in response to the second set of commands.

[0115] In some instances of the method 500 and apparatus described herein, determining whether a first set of physical addresses can be indexed contiguously may include operations, features, circuit systems, logic, devices, or instructions for determining that the first set of physical addresses can be indexed contiguously based at least in part on a first mapping, where the number of the first set of physical addresses that can be indexed contiguously may be greater than a threshold.

[0116] In some examples of the method 500 and apparatus described herein, a pattern associated with accessing data stored at consecutive physical addresses is activated based at least in part on a determination that a first set of physical addresses can be indexed consecutively, wherein a second mapping can be transferred to a volatile memory device and the second mapping can be used to retrieve data associated with a second set of commands based at least in part on activating the pattern.

[0117] Some examples of the method 500 and apparatus described herein may further include operations, features, circuitry, logic, devices, or instructions for disabling the mode based at least in part on receiving a command to access the memory device, the command including a logical address corresponding to a physical address that may not overlap with the second set of physical addresses.

[0118] Some examples of the method 500 and apparatus described herein may further include operations, features, circuitry, logic, devices, or instructions for disabling the mode based at least in part on receiving a command to write to the memory device or perform an unmap operation.

[0119] In some examples of the method 500 and apparatus described herein, communicating the second mapping may include operations, features, circuitry, logic, devices, or instructions for communicating to the volatile memory device a third mapping indicating whether data stored at the second set of physical addresses may be valid and a third set of logical addresses stored at corresponding pages associated with the second set of physical addresses, the third set of logical addresses including at least a portion of the second set of logical addresses.

[0120] Some examples of the method 500 and apparatus described herein may further include operations, features, circuit systems, logic, means, or instructions for determining a correspondence between a subset of the third set of logical addresses and the second set of physical addresses, wherein the second mapping may be based at least in part on the correspondence.

[0121] In some examples of the method 500 and apparatus described herein, retrieving data from a memory device may include operations, features, circuitry, logic, devices, or instructions for: performing a set of read operations on a set of contiguous physical addresses indicated in a second mapping based at least in part on receiving a second set of commands; storing a set of data in a buffer based at least in part on performing the set of read operations; identifying a subset of the set of data in the buffer that corresponds to the second set of commands; and transferring the subset of the set of data from the buffer to an output buffer for transmission to a host system based at least in part on identifying the subset of the set of data.

[0122] Some examples of the method 500 and apparatus described herein may further include operations, features, circuitry, logic, means, or instructions for transmitting the subset of the set of data to a host system based at least in part on the transferring.

[0123] In some examples of the method 500 and apparatus described herein, retrieving data from the memory device may include operations, features, circuitry, logic, devices, or instructions for retrieving the data without using the first mapping.

[0124] In some examples of the method 500 and apparatus described herein, determining whether the first set of physical addresses can be indexed contiguously may include operations, features, circuitry, logic, devices, or instructions for transferring multiple portions of the first mapping from the memory device to the volatile memory device based at least in part on the first set of logical addresses, wherein subsets of the first set of logical addresses may be associated with different portions of the multiple portions based at least in part on the first set of logical addresses being non-contiguous.

[0125] In some examples of the method 500 and apparatus described herein, determining whether the first set of physical addresses can be indexed contiguously may include operations, features, circuitry, logic, devices, or instructions for transferring the entire second mapping to the volatile memory device based at least in part on determining that the first set of physical addresses can be indexed contiguously.

[0126] In some examples of the method 500 and apparatus described herein, the second mapping indicates whether a second set of physical addresses stores valid data or invalid data, the second set of physical addresses being associated with a third set of logical addresses including the first set of logical addresses and the second set of logical addresses.

[0127] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Furthermore, parts of two or more of the methods may be combined.

[0128] An apparatus is described. The apparatus may include a memory device; a controller coupled to the memory device and configured to cause the apparatus to: receive a first set of commands for accessing the memory device, the first set of commands including a non-contiguous first set of logical addresses; determine, based at least in part on a first mapping between logical addresses and physical addresses of the memory device, whether the first set of physical addresses are indexed contiguously, the first set of physical addresses corresponding to the first set of logical addresses; transfer a second mapping from the memory device to a volatile memory device based at least in part on determining that the first set of physical addresses are indexed contiguously, the second mapping indicating whether information stored at a second set of physical addresses including the first set of physical addresses is valid; receive a second set of commands for accessing the memory device, the second set of commands including a non-contiguous second set of logical addresses; and retrieve data from the memory device using the second mapping from a subset of the second set of physical addresses corresponding to the second set of logical addresses in response to the second set of commands.

[0129] In some examples, the apparatus may include determining, based at least in part on the first mapping, that a first set of physical addresses may be contiguously indexed, wherein a number of the first set of physical addresses that may be contiguously indexed may be greater than a threshold.

[0130] In some instances of the apparatus, the controller may be further configured to cause the apparatus to activate a mode associated with accessing data stored at consecutive physical addresses based at least in part on determining that the first set of physical addresses can be indexed consecutively, wherein a second mapping may be communicated to the volatile memory device and the second mapping may be used to retrieve data associated with a second set of commands based at least in part on activating the mode.

[0131] In some examples of the apparatus, the controller may be further configured to cause the apparatus to disable the mode based at least in part on receiving a command for accessing the memory device, the command including a logical address corresponding to a physical address that may not overlap with the second set of physical addresses.

[0132] In some examples of the apparatus, the controller may be further configured to cause the apparatus to disable the mode based at least in part on receiving a command to write to the memory device or to perform an unmap operation.

[0133] In some examples, the apparatus may include communicating to the volatile memory device a third mapping indicating whether data stored at the second set of physical addresses may be valid and a third set of logical addresses stored at corresponding pages associated with the second set of physical addresses, the third set of logical addresses including at least a portion of the second set of logical addresses.

[0134] In some examples, the apparatus may include determining a correspondence between a subset of the third set of logical addresses and the second set of physical addresses, wherein the second mapping may be based at least in part on the correspondence.

[0135] In some examples, the device may include: performing a set of read operations on a set of consecutive physical addresses indicated in a second mapping based at least in part on receiving a second set of commands; storing a set of data in a buffer based at least in part on performing the set of read operations; identifying a subset of the set of data in the buffer that corresponds to the second set of commands; and transferring the subset of the set of data from the buffer to an output buffer to be sent to a host system based at least in part on identifying the subset of the set of data.

[0136] In some examples, the apparatus may include transmitting a subset of the set of data to a host system based at least in part on the transferring.

[0137] In some examples, the apparatus may include retrieving the data without using the first mapping.

[0138] In some examples, the apparatus may include transferring multiple portions of the first mapping from a memory device to a volatile memory device based at least in part on a first set of logical addresses, wherein subsets of the first set of logical addresses may be associated with different portions of the multiple portions based at least in part on the first set of logical addresses being non-contiguous.

[0139] In some examples, the apparatus may include transferring the entire second mapping to the volatile memory device based at least in part on determining that the first set of physical addresses can be indexed consecutively.

[0140] In some examples of the apparatus, the second mapping indicates whether a second set of physical addresses stores valid data or invalid data, the second set of physical addresses being associated with a third set of logical addresses that includes the first set of logical addresses and the second set of logical addresses.

[0141] Another apparatus is described. The apparatus may include a non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a first set of commands for accessing a memory device, the first set of commands comprising a non-contiguous first set of logical addresses; determine, based at least in part on a first mapping between logical addresses and physical addresses of the memory device, whether the first set of physical addresses are indexed contiguously, the first set of physical addresses corresponding to the first set of logical addresses; transfer, based at least in part on the determination that the first set of physical addresses are indexed contiguously, a second mapping from the memory device to a volatile memory device, the second mapping indicating whether information stored at a second set of physical addresses comprising the first set of physical addresses is valid; receive a second set of commands for accessing the memory device, the second set of commands comprising a non-contiguous second set of logical addresses; and, in response to the second set of commands, retrieve data from the memory device from a subset of the second set of physical addresses corresponding to the second set of logical addresses using the second mapping.

[0142] In some instances, to determine whether to index the first set of physical addresses continuously, the instructions, when executed by a processor of the electronic device, further cause the electronic device to determine, at least in part based on the first mapping, that the first set of physical addresses can be indexed continuously, wherein the number of the first set of physical addresses that can be indexed continuously may be greater than a threshold.

[0143] In some instances of the apparatus, the instructions, when executed by a processor of an electronic device, further cause the electronic device to activate a mode associated with accessing data stored at consecutive physical addresses based at least in part on determining that the first set of physical addresses can be indexed consecutively, wherein a second mapping can be passed to a volatile memory device and the second mapping can be used to retrieve data associated with a second set of commands based at least in part on activating the mode.

[0144] In some examples, to communicate the second mapping, the instructions, when executed by a processor of the electronic device, further cause the electronic device to communicate to the volatile memory device a third mapping indicating whether the data stored at the second set of physical addresses may be valid and a third set of logical addresses stored at corresponding pages associated with the second set of physical addresses, the third set of logical addresses including at least a portion of the second set of logical addresses.

[0145] In some instances, to retrieve data from a memory device, the instructions, when executed by a processor of an electronic device, further cause the electronic device to perform a set of read operations on a set of consecutive physical addresses indicated in a second mapping based at least in part on receiving a second set of commands; store a set of data in a buffer based at least in part on performing the set of read operations; identify a subset of the set of data in the buffer that corresponds to the second set of commands; and transfer the subset of the set of data from the buffer to an output buffer to be sent to a host system based at least in part on identifying the subset of the set of data.

[0146] In some examples, to retrieve the data in response to the second set of commands, the instructions, when executed by a processor of the electronic device, further cause the electronic device to retrieve the data without using the first mapping.

[0147] In some examples, to determine whether the first set of physical addresses are indexed contiguously, the instructions, when executed by a processor of the electronic device, further cause the electronic device to transfer multiple portions of the first mapping from the memory device to the volatile memory device based at least in part on the first set of logical addresses, wherein a subset of the first set of logical addresses may be associated with different portions of the multiple portions based at least in part on the first set of logical addresses being non-contiguous.

[0148] The information and signals disclosed herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0149] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are said to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0150] The term "coupling" refers to the condition of moving from an open-circuit relationship between components, in which signals are currently unable to pass between the components via a conductive path, to a closed-circuit relationship between the components in which signals can pass between the components via the conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via the conductive path that previously did not permit signal flow.

[0151] The term "isolation" refers to a relationship between components where signals cannot flow between them. Components are isolated if an open circuit exists between them. For example, components separated by a switch between them are isolated when the switch is open. When a controller isolates two components, it prevents signals from flowing between them using the conductive path that previously allowed signal flow.

[0152] The terms "if," "when," "based on," or "based at least in part on" are used interchangeably. In some instances, if the terms "if," "when," "based on," or "based at least in part on" are used to describe a conditional action, a conditional process, or a connection between parts of a process, the terms are interchangeable.

[0153] The term "in response to" may refer to a condition or action that occurs at least in part (if not entirely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least in part as a result of the preceding condition or action occurring (whether directly before or after one or more other intermediate conditions or actions occurring after the first condition or action).

[0154] In addition, the term "directly in response to" or "directly in response to" may refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be executed, and a second condition or action may occur directly due to a previous condition or action that is independent of whether other conditions or actions occur. In some instances, a first condition or action may be executed, and a second condition or action may occur directly due to a previous condition or action that is independent of whether other conditions or actions occur, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on," "at least partially based on," or "in response to" some other step, action, event, or condition execution may be performed additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly in response to" such other condition or action.

[0155] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0156] The switch components or transistors discussed herein may represent field-effect transistors (FETs), and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via a conductive material, such as a metal. The source and drain can be conductive and can include heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be terminated by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "switched on" or "activated." If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "off" or "deactivated."

[0157] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred" or "advantageous" over other examples. The detailed description includes specific details that provide an understanding of the described technology. However, these technologies can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0158] In the drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any similar component having the same first reference label regardless of the second reference label.

[0159] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0160] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0161] As used herein, including in the claims, "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list such as at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be understood to refer to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based at least in part on."

[0162] Computer-readable media includes both non-transitory computer storage media and communication media, and communication media includes any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disc storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store the required program code in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. In addition, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves are used to transmit software from a website, server, or other remote source, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of media. Disk and disc, as used herein, include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0163] The description herein is provided to enable one of ordinary skill in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: memory device; and a controller coupled to the memory device and configured to cause the apparatus to: receiving a first set of commands for accessing the memory device, the first set of commands comprising a non-contiguous first set of logical addresses; determining whether to contiguously index a first set of physical addresses based at least in part on a first mapping between logical addresses and physical addresses of the memory device, the first set of physical addresses corresponding to the first set of logical addresses; transferring a second mapping from the memory device to a volatile memory device based at least in part on determining that the first set of physical addresses is consecutively indexed, the second mapping indicating whether information stored at a second set of physical addresses including the first set of physical addresses is valid; receiving a second set of commands for accessing the memory device, the second set of commands comprising a second non-contiguous set of logical addresses; and Data is retrieved from the memory device using the second mapping from a subset of the second set of physical addresses corresponding to the second set of logical addresses in response to the second set of commands.

2. The apparatus of claim 1 , wherein to determine whether to index the first set of physical addresses consecutively, the controller is further configured to cause the apparatus to: The first set of physical addresses is determined to be contiguously indexed based at least in part on the first mapping, wherein a number of the first set of physical addresses that are contiguously indexed is greater than a threshold.

3. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: A pattern associated with accessing data stored at consecutive physical addresses is activated based at least in part on a determination that the first set of physical addresses is consecutively indexed, wherein the second mapping is passed to the volatile memory device and is used to retrieve the data associated with the second set of commands based at least in part on activating the pattern.

4. The apparatus of claim 3, wherein the controller is further configured to cause the apparatus to: The mode is disabled based at least in part on receiving a command for accessing the memory device, the command including logical addresses corresponding to physical addresses that do not overlap with the second set of physical addresses.

5. The apparatus of claim 3, wherein the controller is further configured to cause the apparatus to: The mode is disabled based at least in part on receiving a command to write to the memory device or perform an unmap operation.

6. The apparatus of claim 1 , wherein to transfer the second mapping, the controller is further configured to cause the apparatus to: transferring to the volatile memory device: a third map indicating whether data stored at the second set of physical addresses is valid, and A third set of logical addresses is stored at respective pages associated with the second set of physical addresses, the third set of logical addresses including at least a portion of the second set of logical addresses.

7. The apparatus of claim 6, wherein the controller is further configured to cause the apparatus to: A correspondence between a subset of the third set of logical addresses and the second set of physical addresses is determined, wherein the second mapping is based at least in part on the correspondence.

8. The apparatus of claim 1 , wherein to retrieve the data from the memory device, the controller is further configured to cause the apparatus to: performing a set of read operations on a set of consecutive physical addresses indicated in the second mapping based at least in part on receiving the second set of commands; storing a set of data in a buffer based at least in part on performing the set of read operations; identifying in the buffer a subset of the set of data corresponding to the second set of commands; and The subset of the set of data is transferred from the buffer to an output buffer for transmission to a host system based at least in part on identifying the subset of the set of data.

9. The apparatus of claim 8, wherein the controller is further configured to cause the apparatus to: The subset of the set of data is transmitted to the host system based at least in part on the transferring.

10. The apparatus of claim 1 , wherein to retrieve the data in response to the second set of commands, the controller is further configured to cause the apparatus to: The data is retrieved without using the first mapping.

11. The apparatus of claim 1 , wherein to determine whether to index the first set of physical addresses consecutively, the controller is further configured to cause the apparatus to: Multiple portions of the first mapping are transferred from the memory device to the volatile memory device based at least in part on the first set of logical addresses, wherein subsets of the first set of logical addresses are associated with different portions of the multiple portions based at least in part on the first set of logical addresses being non-contiguous.

12. The apparatus of claim 11 , wherein to transfer the second mapping to the volatile memory device, the controller is further configured to cause the apparatus to: The entire second map is transferred to the volatile memory device based at least in part on determining that the first set of physical addresses is contiguously indexed.

13. The apparatus of claim 1, wherein the second mapping indicates whether the second set of physical addresses stores valid data or invalid data, the second set of physical addresses being associated with a third set of logical addresses including the first set of logical addresses and the second set of logical addresses.

14. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a first set of commands for accessing a memory device, the first set of commands comprising a non-contiguous first set of logical addresses; determining whether to contiguously index a first set of physical addresses based at least in part on a first mapping between logical addresses and physical addresses of the memory device, the first set of physical addresses corresponding to the first set of logical addresses; transferring a second mapping from the memory device to a volatile memory device based at least in part on determining that the first set of physical addresses is consecutively indexed, the second mapping indicating whether information stored at a second set of physical addresses including the first set of physical addresses is valid; receiving a second set of commands for accessing the memory device, the second set of commands comprising a second non-contiguous set of logical addresses; and Data is retrieved from the memory device using the second mapping from a subset of the second set of physical addresses corresponding to the second set of logical addresses in response to the second set of commands.

15. The non-transitory computer-readable medium of claim 14, wherein to determine whether the first set of physical addresses is indexed consecutively, the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The first set of physical addresses is determined to be contiguously indexed based at least in part on the first mapping, wherein a number of the first set of physical addresses that are contiguously indexed is greater than a threshold.

16. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A pattern associated with accessing data stored at consecutive physical addresses is activated based at least in part on a determination that the first set of physical addresses is consecutively indexed, wherein the second mapping is passed to the volatile memory device and is used to retrieve the data associated with the second set of commands based at least in part on activating the pattern.

17. The non-transitory computer-readable medium of claim 14, wherein to communicate the second mapping, The instructions, when executed by the processor of the electronic device, further cause the electronic device to: transferring to the volatile memory device: a third map indicating whether data stored at the second set of physical addresses is valid, and A third set of logical addresses is stored at respective pages associated with the second set of physical addresses, the third set of logical addresses including at least a portion of the second set of logical addresses.

18. The non-transitory computer-readable medium of claim 14, wherein to retrieve the data from the memory device, the instructions, when executed by the processor of the electronic device, further cause the electronic device to: performing a set of read operations on a set of consecutive physical addresses indicated in the second mapping based at least in part on receiving the second set of commands; storing a set of data in a buffer based at least in part on performing the set of read operations; identifying in the buffer a subset of the set of data corresponding to the second set of commands; and The subset of the set of data is transferred from the buffer to an output buffer for transmission to a host system based at least in part on identifying the subset of the set of data.

19. The non-transitory computer-readable medium of claim 14, wherein to retrieve the data in response to the second set of commands, the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The data is retrieved without using the first mapping.

20. The non-transitory computer-readable medium of claim 14, wherein to determine whether the first set of physical addresses is indexed consecutively, the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Multiple portions of the first mapping are transferred from the memory device to the volatile memory device based at least in part on the first set of logical addresses, wherein subsets of the first set of logical addresses are associated with different portions of the multiple portions based at least in part on the first set of logical addresses being non-contiguous.

21. A method comprising: receiving a first set of commands for accessing a memory device, the first set of commands comprising a non-contiguous first set of logical addresses; determining whether to contiguously index a first set of physical addresses based at least in part on a first mapping between logical addresses and physical addresses of the memory device, the first set of physical addresses corresponding to the first set of logical addresses; transferring a second mapping from the memory device to a volatile memory device based at least in part on determining that the first set of physical addresses is consecutively indexed, the second mapping indicating whether information stored at a second set of physical addresses including the first set of physical addresses is valid; receiving a second set of commands for accessing the memory device, the second set of commands comprising a second non-contiguous set of logical addresses; and Data is retrieved from the memory device using the second mapping from a subset of the second set of physical addresses corresponding to the second set of logical addresses in response to the second set of commands.

22. The method of claim 21 , wherein determining whether the first set of physical addresses is indexed consecutively comprises: The first set of physical addresses is determined to be contiguously indexed based at least in part on the first mapping, wherein a number of the first set of physical addresses that are contiguously indexed is greater than a threshold.

23. The method of claim 21, further comprising: A pattern associated with accessing data stored at consecutive physical addresses is activated based at least in part on a determination that the first set of physical addresses is consecutively indexed, wherein the second mapping is passed to the volatile memory device and is used to retrieve the data associated with the second set of commands based at least in part on activating the pattern.

24. The method of claim 21 , wherein transferring the second mapping comprises transferring to the volatile memory device: a third map indicating whether data stored at the second set of physical addresses is valid, and A third set of logical addresses is stored at respective pages associated with the second set of physical addresses, the third set of logical addresses including at least a portion of the second set of logical addresses.

25. The method of claim 21 , wherein retrieving the data from the memory device comprises: performing a set of read operations on a set of consecutive physical addresses indicated in the second mapping based at least in part on receiving the second set of commands; storing a set of data in a buffer based at least in part on performing the set of read operations; identifying in the buffer a subset of the set of data corresponding to the second set of commands; and The subset of the set of data is transferred from the buffer to an output buffer for transmission to a host system based at least in part on identifying the subset of the set of data.

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