Quantum system controller configured for quantum error correction

Abstract

A quantum system controller configured to perform (near) real-time quantum error correction is provided. The controller includes a processing device including at least one first processing element, a time-indexed command (TIC) sequencer including at least one second processing element, and a plurality of driver controller elements configured to control operation of respective components and associated with respective buffers and processing elements. The processing device is configured to generate commands, and the TIC sequencer is configured to cause appropriate driver controller elements to time-indexed execute the commands. Control of real-time operation of the quantum computer by the TIC sequencer enables the processing device to generate commands based on conditions assessed by input data indicative of quantum errors that can be present in a quantum computation being performed by the quantum computer, such that commands that resolve the quantum errors are generated and executed (near) real-time.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Application No. 63 / 235,022, filed August 19, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Various embodiments relate to quantum system controllers for quantum computers and related methods enabling the quantum system controller to perform quantum error correction. For example, some exemplary embodiments relate to quantum system controllers for quantum computers configured to perform quantum error correction and related methods. Background Technology

[0004] Large-scale quantum computers hold promise for solving problems in fields such as chemistry, materials science, and biology that are currently difficult to address with existing technologies. Solving such problems will require computation using quantum algorithms implemented with deep quantum circuits. Achieving the necessary level of precision for these deep circuits requires a high level of reliability in quantum operations. To achieve such reliability, quantum error correction (QEC) will be employed during computation to suppress noise to the desired level. Implementing such computations utilizing QEC will require a control system configured to react to errors experienced by the quantum processor within the coherence time of the qubit. Through applied efforts, novelty, and inventiveness, many shortcomings of the configuration of quantum system controllers for existing quantum computers and quantum systems for quantum computers performing QEC have been overcome by developing solutions constructed according to embodiments of the present invention, many examples of which are described in detail herein. Summary of the Invention

[0005] Example embodiments provide methods, systems, apparatuses, computer program products, etc., for performing quantum error correction. For example, various embodiments provide methods, systems, apparatuses, computer program products, etc., for determining quantum errors present and / or potentially present in computations performed using a quantum processor, and for resolving and / or correcting the determined quantum errors. For example, various embodiments provide a quantum system controller for a quantum computer configured to perform quantum error correction. For example, various embodiments provide methods for performing and / or implementing quantum error correction via a quantum system controller of a quantum computer.

[0006] In various embodiments, a quantum system controller of a quantum computer includes a classical and / or semiconductor-based processing device configured to generate a first set of commands. A temporal indexing of the first set of commands causes a quantum processor of the quantum computer to execute a first portion of a quantum circuit. In various embodiments, the processing device is configured to receive and process input data corresponding to and / or indicative of quantum states of one or more physical and / or logical qubits of the quantum processor of the quantum computer. As used herein, a logical qubit includes a plurality of data qubits that are acted upon by the same type of gate at about the same time. For example, each data qubit of a logical qubit is evolved by a quantum circuit in the same manner.

[0007] In various embodiments, the processing device is configured to receive and process the input data and generate a second set of commands such that at least a portion of the second set of commands is executed by the quantum system controller within a coherence time of the qubits relative to when the input data was collected. For example, a chronological execution of the second set of commands causes a second portion of the quantum circuit to be executed. In some cases, the second set of commands includes commands that, when executed by the quantum system controller, cause one or more corrections and / or modifications of gates to be applied to one or more data qubits of the quantum processor. For example, applying a correction to a qubit of the quantum processor can include rotating the qubit (e.g., rotating a Bloch sphere representation of the qubit), modifying a phase of a quantum state of the qubit, etc. In various embodiments, a modification to a gate to be applied to a data qubit can include rotating the gate within a reference frame of the qubit, etc. For example, in an example embodiment, a correction or modification of a gate includes rotating the gate itself or a physical qubit (e.g., a Bloch sphere representation of the physical qubit) about an axis determined by a decoding algorithm configured to process an extracted companion. For example, the rotation is a pi rotation (e.g., 180 degrees) and can be applied to multiple (e.g., two or more) physical qubits. The corrections and modifications of gates are configured to correct one or more quantum errors experienced and / or likely to be experienced by the data qubits acted upon. In an example embodiment, at least some quantum error correction is performed via software corrections applied to individual qubit registers stored by the quantum system controller.

[0008] According to a first aspect of the present disclosure, a method for operating a quantum system controller enables the quantum system controller to perform real-time, near real-time, and / or in situ quantum error correction. In an example embodiment, the method includes generating, by a processing device of a quantum system controller of a quantum computer, a first set of commands configured to cause a quantum processor of the quantum computer to execute a first portion of a quantum circuit using one or more logical qubits of the quantum processor. Each of the one or more logical qubits includes one or more data qubits. The method further includes causing, by the processing device, the first set of commands to be provided to a time-indexed command sequencer of the quantum computer to determine a timing and time-indexed execution. The time-indexed execution of the first set of commands causes one or more elements of the quantum computer to execute the first portion of the quantum circuit using the one or more logical qubits. The method further includes determining, by the processing device, that input data is required prior to generating a second set of commands configured to cause the quantum processor to execute a second portion of the quantum circuit using the one or more logical qubits of the quantum processor. Generating the input data includes reading one or more ancilla qubits of the quantum processor, and the input data corresponds to a quantum state of at least one of the one or more data qubits after a corresponding action is performed. The method further includes accessing, by the processing device, the input data in response to determining that the input data is required prior to generating the second set of commands. The method further includes processing, by the processing device, the input data, generating the second set of commands based on a result of processing the input data, and causing the second set of commands to be provided to the TIC sequencer for time-indexed execution of the second set of commands within a coherence time of the one or more data qubits. The coherence time is related to the corresponding action.

[0009] In an example embodiment, the second set of commands includes at least one quantum error correction command.

[0010] In an example embodiment, executing the at least one quantum error correction command by the appropriate processing element causes software-based quantum error correction to be performed.

[0011] In an example embodiment, performing software-based quantum error correction includes updating a register stored in a memory of the quantum system controller and corresponding to a particular data qubit or a particular logical qubit of the quantum processor to track quantum errors accumulated by the particular data qubit or the particular logical qubit.

[0012] In an example embodiment, executing the at least one quantum error correction command by the appropriate processing element causes a correction to be actively or physically performed on the particular data qubit or the particular logical qubit.

[0013] In example embodiments, the correction is selected or determined based on an accumulated error of the particular data qubit or the particular logical qubit as indicated by a register stored in a memory of the quantum system controller and corresponding to the particular data qubit or the particular logical qubit.

[0014] In example embodiments, the register stored in a memory of the quantum system controller and corresponding to the particular data qubit or the particular logical qubit is updated based on the execution of the correction.

[0015] In example embodiments, the execution of the at least one quantum error correction command by the appropriate processing element causes a gate to be applied to at least the particular data qubit or the particular logical qubit to be modified based at least in part on an accumulated error indicated by a register stored in a memory of the quantum system controller and corresponding to the particular data qubit or the particular logical qubit.

[0016] In example embodiments, the register is updated based on the gate applied to the particular data qubit or the particular logical qubit.

[0017] In example embodiments, accessing the input data includes determining whether the input data has been loaded by a control processing application being executed by the processing device, initiating analysis of the input data in response to determining that the input data has been loaded by the control processing application, determining whether the input data is present in a buffer memory of the controller in response to determining that the input data has not been loaded by the control processing application, and loading the input data to the control processing application when it is determined that the input data is present in the buffer memory.

[0018] In example embodiments, the coherence time of the one or more data qubits is a length of time for which a respective state of each data qubit of the one or more data qubits can be maintained.

[0019] In example embodiments, the quantum system controller includes a time generator configured to provide a synchronization signal configured to cause two or more time-indexed commands of the first set of commands to be executed in respective time synchronization.

[0020] In example embodiments, the quantum processor is an atomic object constraining device, and the one or more data qubits and the one or more ancilla qubits are atomic objects constrained by the atomic object constraining device.

[0021] In example embodiments, a quantum interaction is induced between an ancilla qubit of the one or more ancilla qubits and a respective data qubit prior to reading the ancilla qubit, which does not affect a quantum state of the respective data qubit.

[0022] In example embodiments, reading the ancilla qubits of the one or more ancilla qubits includes determining a quantum state of the ancilla qubits based on optical signals corresponding to the ancilla qubits captured by the one or more collection optical elements.

[0023] In example embodiments, storing the input data to a buffer memory of the controller is through an analog-to-digital converter that receives electrical signals generated based on the optical signals.

[0024] In example embodiments, the one or more data qubits of the first logical qubit are acted on by the same type of gate at about the same time.

[0025] In example embodiments, execution of the at least one command of the first command set causes at least one of: (a) a voltage source to provide a control signal to at least one electrode of the quantum processor or (b) a manipulation source to provide a manipulation signal to at least one data qubit of the quantum processor.

[0026] According to another aspect of the present disclosure, a quantum system controller configured to perform real-time, near real-time, and / or in-situ quantum error correction is provided. In an example embodiment, the quantum system controller includes a processing device including at least one first processing element; a time-indexed command (TIC) sequencer including at least one second processing element; a plurality of driver controller elements, each driver controller element (a) configured to control operation of a respective component of a quantum computer and (b) associated with a respective buffer and a respective processing element. The processing device is configured to generate a first set of commands configured to cause a quantum processor of the quantum computer to perform a first portion of a quantum circuit using one or more logical qubits of the quantum processor, each of the one or more logical qubits including one or more data qubits, and to cause the first set of commands to be provided to the TIC sequencer. The TIC sequencer is configured to cause time-indexed execution of the first set of commands to be indexed for execution by the associated respective processing elements by generating, in the associated respective buffers, time-ordered TIC queues to be executed by respective ones of the plurality of driver controller elements, wherein the time-indexed execution of the first set of commands causes the quantum computer to perform the first portion of the quantum circuit using the one or more logical qubits. The processing device is further configured to determine that input data is required prior to generating a second set of commands, wherein the second set of commands is configured to cause the quantum processor to perform a second portion of the quantum circuit using the one or more logical qubits of the quantum processor, wherein generating the input data includes reading one or more ancilla qubits of the quantum processor, and the input data corresponds to a quantum state of at least one of the one or more data qubits after a respective action is performed. The processing device is further configured to access the input data in response to determining that the input data is required prior to generating the second set of commands. The processing device is further configured to process the input data, generate the second set of commands based on a result of processing the input data, and cause the second set of commands to be provided to the TIC sequencer for time-indexed execution of the second set of commands by the respective driver controller elements within a coherence time of the one or more data qubits, the coherence time being related to the respective action.

[0027] In an example embodiment, the second set of commands includes at least one quantum error correction command.

[0028] In an example embodiment, execution of the at least one quantum error correction command by the appropriate processing element causes software-based quantum error correction to be performed.

[0029] In an example embodiment, performing software-based quantum error correction includes updating a register stored in a memory of the quantum system controller and corresponding to a particular data qubit or a particular logical qubit of the quantum processor to track quantum errors accumulated by the particular data qubit or the particular logical qubit.

[0030] In example embodiments, execution of the at least one quantum error correction command by the appropriate processing element causes a correction to be actively or physically performed on the particular data qubit or the particular logical qubit.

[0031] In example embodiments, the correction is selected or determined based on an accumulated error of the particular data qubit or the particular logical qubit indicated by a register stored in the memory of the quantum system controller and corresponding to the particular data qubit or the particular logical qubit.

[0032] In example embodiments, the register stored in the memory of the quantum system controller and corresponding to the particular data qubit or the particular logical qubit is updated based on the execution of the correction.

[0033] In example embodiments, execution of the at least one quantum error correction command by the appropriate processing element causes a gate to be applied to at least the particular data qubit or the particular logical qubit based at least in part on an accumulated error indicated by a register stored in the memory of the quantum system controller and corresponding to a particular data qubit of the particular logical qubit.

[0034] In example embodiments, the register is updated based on the gate applied to the particular data qubit or the particular logical qubit.

[0035] In example embodiments, accessing the input data includes determining whether the input data has been loaded by a control processing application being executed by the processing device; responsive to determining that the input data has been loaded by the control processing application, beginning to analyze the input data; responsive to determining that the input data has not been loaded by the control processing application, determining whether the input data is present in a buffer memory of the controller; and when it is determined that the input data is present in the buffer memory, loading the input data to the control processing application.

[0036] In example embodiments, the coherence time of the one or more data qubits is a length of time for which a respective state of each data qubit of the one or more data qubits can be maintained.

[0037] In example embodiments, the quantum system controller includes a time generator configured to provide a synchronization signal configured to cause two or more time-indexed commands of the first set of commands to be executed in respective time synchronization.

[0038] In example embodiments, the quantum processor is an atomic object constraining device, and the one or more data qubits and the one or more ancilla qubits are atomic objects constrained by the atomic object constraining device.

[0039] In example embodiments, causing quantum interaction between the ancilla qubit and the corresponding data qubit prior to reading the ancilla qubit of the one or more ancilla qubits does not affect the quantum state of the corresponding data qubit.

[0040] In example embodiments, reading the ancilla qubit of the one or more ancilla qubits includes determining the quantum state of the ancilla qubit based on an optical signal corresponding to the ancilla qubit captured by the one or more collection optical elements.

[0041] In example embodiments, storing the input data to the buffer memory of the controller is by an analog-to-digital converter that receives an electrical signal generated based on the optical signal.

[0042] In example embodiments, the one or more data qubits of the first logical qubit are acted on by the same type of gate at about the same time.

[0043] In example embodiments, execution of the at least one command of the first command set causes at least one of: (a) a voltage source to provide a control signal to at least one electrode of the quantum processor or (b) a manipulation source to provide a manipulation signal to at least one data qubit of the quantum processor.

[0044] According to another aspect of the present disclosure, a quantum computer is provided. The quantum computer includes a quantum system controller configured to perform real-time, near real-time, and / or in situ quantum error correction. The quantum computer also includes a plurality of components configured to be operated by the quantum system controller, and / or whose operation is controlled by the quantum system controller. In an example embodiment, the quantum system controller includes a processing device including at least one first processing element; a time-indexed command (TIC) sequencer including at least one second processing element; a plurality of driver controller elements each (a) configured to control operation of a respective component of the plurality of components of the quantum computer and (b) associated with a respective buffer and a respective processing element. The processing device is configured to generate a first set of commands configured to cause a quantum processor of the quantum computer to execute a first portion of a quantum circuit using one or more logical qubits of the quantum processor, each of the one or more logical qubits including one or more data qubits, and to cause the first set of commands to be provided to the TIC sequencer. The TIC sequencer is configured to cause time-indexed execution of the first set of commands for time-indexed execution by the associated respective processing elements by generating, in the associated respective buffers, time-ordered TIC queues to be executed by respective ones of the plurality of driver controller elements, wherein the time-indexed execution of the first set of commands causes the quantum computer to execute the first portion of the quantum circuit using the one or more logical qubits. The processing device is further configured to determine that input data is required prior to generating a second set of commands, wherein the second set of commands is configured to cause the quantum processor to execute at least a second portion of the quantum circuit using the one or more logical qubits of the quantum processor, wherein generating the input data includes reading one or more ancilla qubits of the quantum processor, and the input data corresponds to a quantum state of at least one of the one or more data qubits after a respective action is performed. The processing device is further configured to access the input data in response to determining that the input data is required prior to generating the second set of commands. The processing device is further configured to process the input data, generate the second set of commands based on a result of processing the input data, and cause the second set of commands to be provided to the TIC sequencer for time-indexed execution of the second set of commands by the respective driver controller elements within a coherence time of the one or more data qubits, the coherence time being related to the respective action.

[0045] In an example embodiment, the second set of commands includes at least one quantum error correction command.

[0046] In an example embodiment, execution of the at least one quantum error correction command by the appropriate processing element causes a software-based quantum error correction to be performed.

[0047] In example embodiments, executing the software-based quantum error correction includes updating a register stored in a memory of the quantum system controller and corresponding to the particular data qubit or the particular logical qubit to track quantum errors accumulated by the particular data qubit or the particular logical qubit.

[0048] In example embodiments, executing the at least one quantum error correction command by the appropriate processing element causes the correction to be actively or physically performed on the particular data qubit or the particular logical qubit.

[0049] In example embodiments, the correction is selected or determined based on accumulated errors of the particular data qubit or the particular logical qubit as indicated by a register stored in a memory of the quantum system controller and corresponding to the particular data qubit or the particular logical qubit.

[0050] In example embodiments, the register stored in a memory of the quantum system controller and corresponding to the particular data qubit or the particular logical qubit is updated based on executing the correction.

[0051] In example embodiments, executing the at least one quantum error correction command by the appropriate processing element causes a gate to be applied to at least the particular data qubit or the particular logical qubit based at least in part on accumulated errors indicated by a register stored in a memory of the quantum system controller and corresponding to the particular data qubit of the particular logical qubit.

[0052] In example embodiments, the register is updated based on the gate applied to the particular data qubit or the particular logical qubit.

[0053] In example embodiments, accessing the input data includes determining whether the input data has been loaded by a control processing application being executed by the processing device; responsive to determining that the input data has been loaded by the control processing application, beginning to analyze the input data; responsive to determining that the input data has not been loaded by the control processing application, determining whether the input data is present in a buffer memory of the controller; and when it is determined that the input data is present in the buffer memory, loading the input data to the control processing application.

[0054] In example embodiments, the coherence time of the one or more data qubits is a length of time for which a respective state of each data qubit of the one or more data qubits can be maintained.

[0055] In example embodiments, the quantum system controller includes a time generator configured to provide a synchronization signal configured to cause two or more time-indexed commands of the first set of commands to be executed in respective time synchronization.

[0056] In example embodiments, the quantum processor is an atomic object constraining device, and the one or more data qubits and the one or more ancilla qubits are atomic objects constrained by the atomic object constraining device.

[0057] In example embodiments, causing a quantum interaction between an ancilla qubit and a corresponding data qubit, prior to reading the ancilla qubit of the one or more ancilla qubits, does not affect a quantum state of the corresponding data qubit.

[0058] In example embodiments, reading the ancilla qubit of the one or more ancilla qubits includes determining a quantum state of the ancilla qubit based on an optical signal corresponding to the ancilla qubit captured by the one or more collection optical elements.

[0059] In example embodiments, storing the input data to the buffer memory of the controller is by an analog-to-digital converter that receives an electrical signal generated based on the optical signal.

[0060] In example embodiments, the one or more data qubits of the first logical qubit are acted on by the same type of gate at about the same time.

[0061] In example embodiments, execution of the at least one command of the first command set causes at least one of: (a) a voltage source to provide a control signal to at least one electrode of the quantum processor or (b) a manipulation source to provide a manipulation signal to at least one data qubit of the quantum processor.

[0062] In example embodiments, the plurality of components includes a plurality of voltage sources, a plurality of manipulation sources, and components of an optical collection system. BRIEF DESCRIPTION OF DRAWINGS

[0063] Having now generally described the application, the same will be better understood by reference to the following drawings, which are not necessarily to scale, and in which:

[0064] FIG. 1 is a schematic diagram illustrating an example quantum computing system including a quantum system controller, in accordance with example embodiments.

[0065] FIG. 2 schematics of example quantum system controllers of quantum computers configured to perform one or more deterministic reshaping and / or reordering functions, in accordance with various embodiments.

[0066] FIG. 3 is a schematic diagram of operations performed by a quantum system controller of FIG. 2 , e.g., for controlling operation of a quantum computer, in accordance with various embodiments.

[0067] FIG. 4is a schematic diagram showing how a quantum system controller controls the evolution of one or more qubits, in accordance with various embodiments.

[0068] FIG. 5 is a flowchart showing modifications to a quantum circuit by a quantum system controller in response to processing of input data, in accordance with various embodiments.

[0069] FIG. 6 is a flowchart showing various processes, operations, and / or procedures performed by a processing device of a quantum system controller, in accordance with various embodiments.

[0070] FIG. 7 is a flowchart showing various processes, operations, and / or procedures performed by a quantum system controller, in accordance with various embodiments.

[0071] FIG. 8A and FIG. 8B schematic diagrams showing two example processes affecting quantum error correction, in accordance with various embodiments, are provided.

[0072] FIG. 9 schematic diagrams showing example processes affecting quantum error correction with respect to two logical qubits, in accordance with various embodiments, are provided.

[0073] FIG. 10A , FIG. 10B and FIG. 10C examples of performing quantum error correction on various types of quantum errors, in accordance with example embodiments, are schematically illustrated.

[0074] FIG. 11 flowcharts of processes, procedures, operations, etc. performed, e.g., by a processing device of a quantum system controller, in accordance with various embodiments, are provided.

[0075] FIG. 12 schematic diagrams of example computing entities of a quantum computer system that can be used in accordance with example embodiments are provided. DETAILED DESCRIPTION

[0076] The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. The term “or” (also represented by “ / ”) is used herein in both the alternative and conjunctive sense, unless otherwise indicated. The terms “illustrative” and “exemplary” are used as examples only and not to imply a quality level. The terms “generally,” “substantially,” and “about” mean within engineering and / or manufacturing tolerances and / or within user measurement capabilities, unless otherwise indicated. Like reference numerals refer to like elements throughout.

[0077] Example embodiments provide methods, systems, apparatuses, computer program products, and the like for performing quantum error correction. For example, various embodiments provide methods, systems, apparatuses, computer program products, and the like for determining quantum errors that exist and / or can exist in computations performed using quantum processors and addressing and / or correcting the determined quantum errors. For example, various embodiments provide a quantum system controller for a quantum computer configured for performing quantum error correction. For example, various embodiments provide methods for performing quantum error correction and / or enabling performance of quantum error correction by a quantum system controller of a quantum computer.

[0078] In various embodiments, the quantum system controller of the quantum computer includes a classical and / or semiconductor-based processing device configured to generate a first set of commands. In various embodiments, the temporal indexing of the first set of commands causes one or more qubits to be transmitted within the quantum processor, one or more quantum gates to be performed on one or more qubits, one or more data qubits to interact with one or more ancilla qubits evolving along a path of the quantum circuit, one or more qubits (e.g., data qubits, ancilla qubits, etc.) to be read, and the like. For example, the temporal indexing of the first set of commands causes the quantum processor of the quantum computer to execute a first portion of a quantum circuit. In various embodiments, the processing device is configured to receive and process input data corresponding to and / or indicative of quantum states of one or more physical and / or logical qubits of the quantum processor of the quantum computer. In various embodiments, the quantum system controller generates a first set of commands corresponding to the execution of the first portion of the quantum circuit and, based on analyzing and / or processing the input data corresponding to and / or indicative of quantum states of one or more physical and / or logical qubits of the quantum processor of the quantum computer after executing the first portion of the quantum circuit, the quantum system controller generates a second set of commands including software and / or physical corrections to one or more quantum errors corresponding to one or more data qubits of the quantum processor.

[0079] In various embodiments, the quantum processor includes a plurality of physical qubits (e.g., atomic objects such as ions) evolving along one or more lines of a quantum circuit. In various embodiments, some of the physical qubits are used as data qubits that evolve in a controlled manner to perform quantum computations corresponding to the quantum circuit. In various embodiments, some of the physical qubits are used as ancilla qubits. For example, the ancilla qubits can be used to extract information intermediate circuits from the data qubits.

[0080] In various embodiments, data qubits are grouped or organized into logical qubits. In various embodiments, a logical qubit includes a plurality of data qubits that are acted on by the same type of gate at approximately the same time. For example, each data qubit of a logical qubit evolves through a quantum circuit in the same way. In other words, each data qubit of a logical qubit evolves along the same line of a quantum circuit. In various embodiments, a block or group of data qubits can correspond to a single logical qubit or multiple (e.g., two or more) logical qubits.

[0081] In various embodiments, ancilla qubits (e.g., atomic objects such as ions) of a quantum processor are caused to interact with data qubits of the quantum processor and then read (e.g., a read manipulation light beam is caused to be incident on the ancilla qubits, and then the emission or non-emission of photons by the ancilla qubits is monitored) to determine the quantum state of the ancilla qubits and the data qubits that were caused to interact with the ancilla qubits. In various embodiments, the ancilla qubits are used to interact with a single data qubit, multiple (e.g., two or more) data qubits associated with the same logical qubit, or multiple (e.g., two or more) data qubits associated with two or more logical qubits. Based on processing and / or analysis of the values determined by reading the one or more ancilla qubits and / or input data, a processing device of the quantum system controller generates a second set of commands configured to resolve, compensate for, and / or correct for one or more quantum errors that can be present in the evolution of one or more data qubits of the quantum processor (e.g., based on analysis and / or processing of the determined quantum states of the one or more ancilla qubits).

[0082] In various embodiments, the second set of commands includes one or more commands that use software corrections and / or physical corrections of the one or more data qubits to resolve, compensate for, and / or correct for one or more errors that can be present in the evolution of the one or more data qubits. In various embodiments, the physical corrections include corrections that are applied directly to the qubits (e.g., rotating the qubits, modifying the phase of the quantum state of the qubits, etc.) and / or modifying gates to be applied to the data qubits (e.g., rotating the gates relative to a reference frame of the data qubits, etc.).

[0083] For example, in various embodiments, the processing device is configured to receive and process input data and generate a second set of commands such that at least a portion of the second set of commands is executed by the quantum system controller within a coherence time of the qubits relative to when the input data was collected (e.g., in a time-indexed manner). For example, in various embodiments, the time-ordered execution of the second set of commands causes a second portion of the quantum circuit to be executed. In some cases, the second set of commands includes commands that, when executed by the quantum system controller, cause one or more corrections and / or modifications of gates to be applied to one or more data qubits of the quantum processor. For example, applying a correction to a qubit of the quantum processor can include rotating the qubit, modifying a phase of a quantum state of the qubit, and / or the like. In various embodiments, modifying a gate to be applied to a data qubit can include rotating the gate within a reference frame of the qubit, and / or the like. The corrections and modifications of gates are configured to correct for one or more quantum errors experienced and / or likely to be experienced by the data qubits being acted upon. In example embodiments, at least some quantum error correction is performed through software corrections applied to respective qubit registers stored by the quantum system controller.

[0084] In various embodiments, the processing device is configured to perform real-time and / or near real-time tracking of error states of each data qubit (e.g., in respective qubit registers stored by the quantum system controller). Thus, in example embodiments, not only are final, discrete corrections applied to the data qubits, the quantum system controller also performs (near) real-time tracking of corrections needed to alter gates that would otherwise be performed in executing the intended quantum circuit. Thus, the quantum system controller can modify operations used to execute the quantum circuit based on the (near) real-time tracked error states and / or the (near) real-time tracked corrections of respective data qubits in executing the quantum circuit. The applied corrections can not absolutely correct for errors associated with the data qubits, and thus the error states of the data qubits (e.g., stored by respective qubit registers) are updated based on the applied corrections such that the error states of the data qubits reflect current error states of the data qubits.

[0085] In various embodiments, the quantum processor can take a variety of forms. For example, the quantum processor can include various types of data qubits, such as trapped atomic objects (e.g., constrained in atomic object constraining devices such as ion traps), Josephine junctions, quantum dot spins, and / or electron localization, and / or other types of qubits. In various embodiments, the quantum circuit is configured to control evolution of quantum states of the data qubits such that one or more computations are performed via execution of the quantum circuit by the quantum processor. In various embodiments, the second set of commands includes commands configured to cause one or more quantum error corrections to be applied and / or cause a second portion of the quantum circuit to be executed.

[0086] Large quantum computers (e.g., including hundreds to thousands of qubits) are expected to solve problems currently intractable by classical and / or small quantum computers (e.g., including tens of qubits) in areas such as chemistry, materials science, and biology. Solving such problems will require computation employing quantum algorithms implemented using deep quantum circuits. Achieving the necessary level of precision for these deep circuits requires a high level of reliability of quantum operations. To achieve such reliability, quantum error correction (QEC) can be employed during computation to suppress noise to the required level. Implementing such computation with QEC will require a powerful quantum system controller. In particular, the quantum system controller will need to be able to determine quantum errors that can be present with one or more data qubits, determine corrections (e.g., software corrections and / or active quantum error correction) to address the quantum errors, and perform quantum error correction in real-time and / or near real-time as the quantum circuit is executed. For example, quantum error correction can be performed between execution of two gates on a data qubit. For example, quantum error correction can need to be performed in a time period that is less than the coherence time of the data qubit. Accordingly, various embodiments provide technical solutions to the technical problem of how to enable a quantum system controller to perform quantum error correction (e.g., within the coherence time of the corresponding data qubit) to improve the performance of a quantum computer.

[0087] For example, various embodiments provide a quantum system controller and / or corresponding method that enables quantum error correction by transforming and reordering conditional gates and classical logic from a quantum description into serialized, potentially conditional operations to be executed by a quantum processor. The transformation converts universal quantum gates into gates that can be executed by the quantum processor and aligns the number of operations with the parallelism allowed on the quantum processor. The quantum system controller places (e.g., at physical locations within the quantum processor) and commands both quantum and classical operations that maximize parallelism on the quantum processor, minimize execution time and heat generation (e.g., introduction of thermal noise), while ensuring that any dependencies are preserved. Exemplary Quantum computing system including atomic object constraining apparatus

[0088] FIG. 1A schematic diagram of an example quantum computing system 100 according to example embodiments is provided, in which a quantum processor includes an atomic object confinement device 120 (e.g., an ion trap, etc.) in which a plurality of atomic objects (e.g., atoms, ions, etc.) are confined. In various embodiments, the quantum computing system 100 includes a computing entity 10 and a quantum computer 110. In various embodiments, the quantum computer 110 includes a quantum system controller 30 and a quantum processor 115. In various embodiments, the quantum system controller 30 is configured, programmed, etc. to control the quantum processor 115. In example embodiments, the quantum processor 115 includes a plurality of qubits (e.g., data qubits, ancilla qubits, etc. that can be organized into logical qubits).

[0089] In various embodiments, the quantum processor 115 includes a device for controlling the evolution of the quantum state of a qubit. For example, in example embodiments, the quantum processor 115 includes a cryostat and / or vacuum chamber 40 enclosing the confinement device 120 (e.g., an ion trap), one or more manipulation sources 60, one or more voltage sources 50, and / or one or more optical collection systems 70. For example, the cryostat and / or vacuum chamber 40 can be a temperature and / or pressure controlled chamber. In example embodiments, the one or more manipulation sources 60 can include one or more lasers (e.g., optical lasers, microwave sources, etc.). In various embodiments, the one or more manipulation sources 60 are configured to manipulate and / or cause controlled quantum state evolution of one or more atomic objects within the confinement device. In various embodiments, atomic objects within the atomic confinement device (e.g., ions trapped within an ion trap) act as data qubits and / or ancilla qubits of the quantum processor 115 of the quantum computer 110. For example, in example embodiments in which the one or more manipulation sources 60 include one or more lasers, the lasers can provide one or more laser beams to atomic objects trapped within the confinement device 120 within the cryostat and / or vacuum chamber 40. For example, the manipulation sources 60 can generate and / or provide laser beams configured to ionize atomic objects, initialize atomic objects within a defined two-state qubit space of the quantum processor, perform a gate of one or more qubits of the quantum processor, read a quantum state of one or more qubits of the quantum processor, etc.

[0090] In various embodiments, the quantum computer 110 includes an optical collection system 70 configured to collect and / or detect photons produced by the qubits (e.g., during a readout process). The optical collection system 70 can include one or more optical elements (e.g., lenses, mirrors, waveguides, fiber optic cables, etc.) and one or more photodetectors. In various embodiments, the photodetectors can be photodiodes, photomultiplier tubes, charge-coupled device (CCD) sensors, complementary metal-oxide-semiconductor (CMOS) sensors, microelectromechanical systems (MEMS) sensors, and / or other photodetectors sensitive to light at the expected fluorescence wavelength of the qubits of the quantum computer 110. In various embodiments, the detectors can be in electrical communication with the quantum system controller 30 via one or more A / D converters 225 (see FIG. 2 ) via one or more A / D converters 225 (see

[0091] In various embodiments, the quantum computer 110 includes one or more voltage sources 50. For example, the voltage sources 50 can include a plurality of voltage drivers and / or voltage sources and / or at least one RF driver and / or voltage source. In example embodiments, the voltage sources 50 can be electrically coupled to corresponding potential producing elements (e.g., electrodes) of the confinement apparatus 120.

[0092] In various embodiments, the computing entity 10 is configured to allow a user to provide input to the quantum computer 110 (e.g., via a user interface of the computing entity 10) and to receive, view, etc. output from the quantum computer 110. The computing entity 10 can communicate with the quantum system controller 30 of the quantum computer 110 via one or more wired or wireless networks 20 and / or via direct wired and / or wireless communication. In example embodiments, the computing entity 10 can translate, configure, format, etc. information / data, quantum computing algorithms and / or circuits, etc. into a computational language, executable instructions, command set, etc. that the quantum system controller 30 can understand and / or implement.

[0093] In various embodiments, the quantum system controller 30 is configured to control the voltage sources 50, a cryostat system and / or vacuum system that controls the temperature and pressure within the cryostat and / or vacuum chamber 40, the manipulation sources 60, and / or other systems configured to manipulate and / or cause a controlled evolution of the quantum state of one or more atomic objects within the confinement device. For example, the quantum system controller 30 can cause a controlled evolution of the quantum state of one or more atomic objects within the confinement device to perform a quantum circuit and / or algorithm. For example, the quantum system controller 30 can cause a readout process including coherent shelving to be performed, possibly as part of performing a quantum circuit and / or algorithm. Further, the quantum system controller 30 is configured to communicate and / or receive input data from the optical collection system 70, and a readout corresponding to the quantum state of a qubit of the quantum computer 110. In various embodiments, the atomic objects confined within the confinement device are used as qubits of the quantum computer 110.

[0094] Exemplary architecture of a quantum system controller

[0095] In various embodiments, the quantum computer 110 includes the quantum system controller 30 and the quantum controller 115. The quantum system controller 30 is configured to control various components of the quantum processor 115. Various embodiments provide that the quantum system controller 30 is configured to perform one or more quantum error corrections. For example, various embodiments are configured to perform one or more quantum error corrections on one or more data qubits in real-time and / or near real-time with respect to the occurrence of one or more quantum errors experienced by the one or more data qubits. For example, the quantum system controller 30 is configured to perform a quantum error correction within a coherence time of one or more data qubits on which and / or with respect to which the quantum error correction is being performed.

[0096] In various embodiments, the quantum system controller 30 is in communication with the optical collection system 70 such that the quantum system controller 30 is configured to receive input data captured and / or generated by the optical collection system 70. The quantum system controller 30 is further configured to perform quantum error corrections via software-based corrections and / or via physically applying quantum error corrections to one or more data qubits (e.g., by controlling one or more voltage sources 50 and / or manipulation sources 60). In various embodiments, the quantum system controller 30 is further configured to control a cryostat system and / or vacuum system that controls the temperature and pressure within the cryostat and / or vacuum chamber 40, a cooling system, and / or other systems that control environmental conditions (e.g., temperature, humidity, pressure, etc.) within the cryostat and / or vacuum chamber 40.

[0097] As FIG. 2As shown, in various embodiments, quantum system controller 30 can include various quantum system controller elements, including processing device 205, memory 210, driver controller elements 215, communication interface 220, analog-to-digital (A / D) converter elements 225, time generator 230, time indexed command (TIC) sequencer 235, etc. In various embodiments, quantum system controller 30 is configured to receive input data generated by the optical collection system via A / D converter 225. In various embodiments, processing device 205 is configured to generate one or more TICs (e.g., a first set of commands and a second set of commands) based at least in part on the input data and / or processing thereof. In various embodiments, TIC sequencer 235 is configured to execute and / or cause execution of the TICs at particular indexed times (e.g., based at least in part on signals generated by time generator 230). In various embodiments, the TICs are executed by driver controller elements 215 at the indexed times such that driver controller elements 215 control voltage source 50 and / or steering source 60 to cause quantum processor 115 to execute at least a portion of a quantum circuit, quantum correction, etc., respectively.

[0098] In various embodiments, processing device 205 includes a processing element, such as a programmable logic device (CPLD), a microprocessor, a co-processing entity, an application specific instruction set processor (ASIP), an integrated circuit, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic array (PLA), a hardware accelerator, other processing elements and / or circuitry, etc. The term circuitry can refer to a fully hardware embodiment or a combination of hardware and computer program products. In example embodiments, processing device 205 of quantum system controller 30 includes and / or is in communication with a clock.

[0099] In various embodiments, the memory 210 includes a non-transitory memory, such as one or more of a volatile and / or non-volatile storage device, such as a hard disk, ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, Memory Stick, CBRAM, PRAM, FeRAM, RRAM, SONOS, Millipede, RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, etc. In various embodiments, the memory 210 can store a command queue (e.g., an executable queue) to be executed to cause a quantum algorithm and / or circuit to be executed, qubit records corresponding to qubits of a quantum computer (e.g., in a qubit record data store, a qubit record database, a qubit record table, etc.), a calibration table, computer program code (e.g., in one or more computer languages, a specialized quantum system controller language, etc.), etc. In example embodiments, execution of at least a portion of the computer program code stored in the memory 210 (e.g., by the processing device 205) causes the quantum system controller 30 to perform one or more steps, operations, processes, procedures, etc. to generate one or more command sets (e.g., a first command set and / or a second command set) configured to cause the quantum processor 115 to execute at least a portion of a quantum circuit and / or to perform quantum correction; to update one or more physical and / or logical qubit registries, etc. In example embodiments, execution of at least a portion of the computer program code stored in the memory 210 (e.g., by the TIC sequencer 235) causes the quantum system controller 30 to cause one or more commands (e.g., commands of one or more command sets) to be executed in a time-indexed manner based at least in part on a clock of the quantum system controller and / or the time generator 230.

[0100] In various embodiments, the memory 210 includes one or more buffers 212. In various embodiments, the TIC sequencer is configured to buffer TIC commands (e.g., the first set of commands and / or the second set of commands) for time indexed execution and / or execution by respective ones of the driver controller elements 215. For example, the buffers 212 can correspond to one driver controller element 215. TIC commands to be executed by a respective driver controller element 215 are stored to the corresponding buffer 212. The respective driver controller element 215 then executes the commands stored to its corresponding buffer 212 according to the indexed time associated with each command. For example, each command can indicate a time at which the command is to be executed by the respective driver controller element 215, such that the TIC is executed at the appropriate time as determined based on one or more timing and / or clock signals (e.g., generated by the time generator 230). In various embodiments, the buffers 212 are first-in-first-out (FIFO) buffers.

[0101] In various embodiments, the driver quantum system controller elements 215 include one or more drivers and / or quantum system controller elements, each of which is configured to control one or more drivers. In various embodiments, the driver quantum system controller elements 215 can include drivers and / or driver controllers. For example, a driver controller can be configured to cause one or more corresponding drivers to operate according to executable instructions, commands, etc. generated, scheduled, and executed by the quantum system controller 30. For example, the processing device 205 can generate one or more commands to be executed by a first driver. The TIC sequencer 235 can schedule the one or more commands (e.g., associate and / or index the one or more commands with respective times). The driver controller element 215 configured to control the first driver can then execute the one or more commands according to the respective time index based at least in part on timing and / or clock signals generated by the time generator 230.

[0102] In various embodiments, the driver controller elements 215 enable the quantum system controller 30 to operate voltage sources 50, steering sources 60, cooling systems, vacuum systems, etc. In various embodiments, a driver can be a laser driver (e.g., configured to operate and / or control one or more steering sources 60); a vacuum component driver; a driver for controlling current and / or voltage flow applied to electrodes (e.g., configured to operate and / or control one or more voltage sources 50) for maintaining and / or controlling the confinement apparatus 120 (and / or other drivers for providing a sequence of driver actions to potential generating elements of the confinement apparatus); a cryostat and / or vacuum system component driver; a cooling system driver, etc.

[0103] In various embodiments, each driver controller element 215 includes a processing element such as an FPGA. To enable synchronized execution of the TICs, clock and synchronization signals and / or pulses are distributed across each driver controller element 215 of the system while skew is minimized. A global system time is established within each driver controller element 215 (e.g., its FPGA) as a count that increments at the clock rate (e.g., based on timing, clock, and / or synchronization signals). In example embodiments, to start program execution (e.g., to initiate execution of a quantum circuit), a command is sent to each driver controller element 215 (e.g., its FPGA) to instruct that the system time should count from 0 on the next explicit parallel instruction compute (epic) of a synchronization pulse. Thus, a distributed time generation is established within the quantum system controller 30.

[0104] Each driver controller element 215 corresponds to an endpoint within the system (e.g., a component of the manipulation source 60, a component of the voltage source 50, a component of the cooling and / or vacuum system, a component of the optical collection system 70, etc.). Each endpoint within the quantum computer 110 represents a separate hardware control. In various embodiments, each endpoint has its own set of accepted micro-commands. Examples include, but are not limited to, a direct digital synthesizer (DDS) of the voltage source 50, a component of the optical collection system 70 such as a photomultiplier tube (PMT), a component of the manipulation source 60 such as a laser driver and / or optical modulator switch, and / or a general purpose output (GPO). Separate commands for the DDS allow for setting the power level, frequency, and phase of the control signal produced thereby. In various embodiments, commands for a PMT interface include start / stop photon counting and count reset. Commands for a GPO endpoint include setting and / or clearing one or more output lines. These output lines can be used to control external hardware in a manner that is synchronized with quantum circuit execution.

[0105] In various embodiments, each driver controller element 215 (e.g., system endpoint) features a dedicated and / or corresponding buffer 212 (e.g., FIFO buffer) for storing many TICs in a time-sequential sequence. The dedicated and / or corresponding buffer 212 provides distributed storage for the TICs such that operations can be performed simultaneously across each driver controller 215 of the quantum system controller 30 and / or quantum computer 110 in parallel.

[0106] In various embodiments, quantum system controller 30 includes means for transmitting and / or receiving signals from one or more light receiver components (e.g., of optical collection system 70). For example, quantum system controller 30 can include one or more analog-to-digital (A / D) converter elements 225 configured to receive signals from one or more optical receiver components (e.g., photodetectors of optical collection system 70), calibration sensors, etc. In various embodiments, A / D converter elements 225 are configured to write input data generated by converting received signals generated by one or more optical receiver components of optical collection system 70 to memory 210. In various embodiments, A / D converter elements 225 of memory 210 are configured to be part of memory 210 that is arranged and / or allocated to an application operating on and / or executed by processing device 205, processing device 205 being configured to analyze and / or process the input data and generate a second command set and / or software-based quantum error correction commands based at least in part on the analysis and / or processing of the input data.

[0107] In various embodiments, quantum system controller 30 can include a communication interface 220 for interfacing and / or communicating with computing entity 10. For example, quantum system controller 30 can include a communication interface 520 for receiving executable instructions, command sets, etc. from computing entity 10 and providing outputs received from quantum computer 110 (e.g., from optical collection system 70) and / or results of processing of the outputs to computing entity 10. In various embodiments, computing entity 10 and quantum system controller 30 can communicate via a direct wired and / or wireless connection and / or via one or more wired and / or wireless networks 20.

[0108] In various embodiments, quantum system controller 30 includes a timing generator 230. In various embodiments, timing generator 230 is configured to generate and provide clock, timing, and / or synchronization signals. The clock, timing, and / or synchronization signals are received by processing device 205, memory 210, TIC sequencer 235, driver controller elements 215, and / or other components of quantum system controller 30. TIC sequencer 235 and / or driver controller elements 215 are configured to use the clock, timing, and / or synchronization signals received thereby to synchronize execution of TICs by various driver controller elements 215 to function as a distributed clock. In various embodiments, timing generator includes a crystal oscillator, phase-locked loop, etc. configured to cause periodic timing, clock, and / or synchronization signals to be generated and provided.

[0109] For example, a dedicated buffer corresponding to the first driver controller element 215 stores a first TIC to be executed at a first time and a second TIC to be executed at a second time. A buffer corresponding to the second driver controller element 215 stores a third TIC to be executed at the first time, and a buffer corresponding to the third driver controller element 215 stores a fourth TIC to be executed at the second time. The first, second, and third driver controller elements receive a timing, clock, and / or synchronization signal indicative of the first time. In response to recording the received timing, clock, and / or synchronization signal indicative of the first time, the first driver controller element executes the first TIC (and does not execute the second TIC) and the second driver controller element executes the third TIC in a synchronized manner. The third driver controller element records the received timing, clock, and / or synchronization signal indicative of the first time and does not execute the fourth command. The first, second, and third driver controller elements then receive a timing, clock, and / or synchronization signal indicative of the second time. In response to recording the received timing, clock, and / or synchronization signal indicative of the second time, the first driver controller element executes the second TIC and the third driver controller element executes the fourth TIC in a synchronized manner. The second driver controller element records the received timing, clock, and / or synchronization signal indicative of the second time and waits for a corresponding buffer to include an additional TIC.

[0110] In various embodiments, the quantum system controller 30 further includes a TIC sequencer 235. In various embodiments, the TIC sequencer 235 includes a processing element, such as a CPLD, a microprocessor, a co-processing entity, an ASIP, an integrated circuit, an ASIC, an FPGA, a PLA, a hardware accelerator, other processing elements and / or circuitry, and / or the like. In various embodiments, the TIC sequencer 235 includes one or more processing devices configured to receive commands generated by the processing devices 205, index each command and / or associate each command with a respective time at which the respective command should be executed to generate a TIC, and save and / or store each TIC to a respective buffer 212 corresponding to a driver controller element 215 for which the respective TIC is intended to be executed. For example, the TIC sequencer 235 is configured to store TICs to be executed by respective driver controller elements 215 in corresponding buffers 212 in a time-ordered manner.

[0111] In various embodiments, the TIC enables synchronized hardware operations of various components of the quantum system controller 30 (e.g., driver controller elements 215). In various embodiments, the TIC is an atomic operation configured to execute at a precise time that is synchronized across all hardware endpoints (e.g., driver controller elements 215) in the quantum system (e.g., quantum computer 110). In various embodiments, the TIC includes an execution time (e.g., an index and / or associated time at which the TIC is to be executed), an endpoint ID configured to identify an endpoint (e.g., hardware element, driver controller element 215, etc.) for which a command is intended to be executed, a command ID configured to identify a command to be executed (e.g., can be machine language code, a reference to a command stored in a local library stored by the driver controller element 215, etc.), and any data required by the endpoint (e.g., driver controller element 215) to execute the command (e.g., one or more values as input to the command).

[0112] Exemplary operation of a quantum system controller

[0113] In various embodiments, the quantum system controller 30 is configured to control operations of the quantum computer 110. For example, the quantum system controller 30 is configured to control operations performed by the quantum processor 115 to cause the quantum processor to perform one or more quantum computations via execution of one or more quantum circuits. Within quantum error correction logic and generally for the entire program flow control, it is advantageous for the quantum system controller 30 to be able to control the application of gates and updates to the classical state, one or more logical qubits, one or more data qubits, one or more ancilla qubits, etc. of the quantum processor. Thus, in various embodiments, control flow is handled at least in part through real-time or near real-time control mechanisms of the quantum system controller 30. In various embodiments, this enables dependency analysis for reordering operations, grouping of operations to improve parallelism, selection of operations as conditional operations or as part of conditional blocks, and placement of operations to minimize timing, and improves performance of quantum circuits.

[0114] To enable real-time or near real-time control flow, measurement of local updates to the classical state (e.g., one or more logical qubits, one or more data qubits, one or more ancilla qubits, etc.) are replicated to other portions of the quantum computer 110 as needed. To minimize additional latency injected in the operation of the quantum computer 110, dependencies we have tracked are used to inject appropriate sending and receiving between various elements of the quantum computer 110.

[0115] For example, in various embodiments, measurements that produce results that need to be distributed are tagged. Operations that depend on values determined based on measurements that produce results that need to be distributed can also be tagged to facilitate identification. For example, measurements tagged for sending information (e.g., digital signal values) are distributed (e.g., by components of the quantum computer 110 that generate the measurements and / or the quantum system controller 30) to other components of the quantum computer 110 that did not record and / or generate the measurements and / or the quantum system controller 30. Thus, components of the quantum system controller 30 that use the measurements that were not generated by the components themselves have fast and efficient access to the measurements. In various embodiments, each component of the quantum computer and / or the quantum system controller 30 has a synchronization point that is injected before use to ensure that they have received the measurements and updated the appropriate classical state before proceeding.

[0116] In various embodiments, the nominal execution mode of the quantum system controller 30 is to generate TICs, load the queue so that the TIC sequencer hardware (e.g., the TIC sequencer 235) can actuate them at the right time, and cause the driver controller elements to execute the TICs at the appropriate time. However, when quantum error correction requires a decision, this process is interrupted so that different correction actions can be taken based on intermediate circuit measurements (e.g., based on syndrome extraction and decoding). The quantum system controller 30 is designed to quickly process incoming measurement values (e.g., digital signal values and / or input data), make any decisions that are needed, and resume command generation within the coherence time of the physical qubits (e.g., data qubits that collectively make up logical qubits of a quantum circuit).

[0117] FIG. 3 An example process 300 that can be used by the quantum system controller 30 configured to perform control flow including real-time and / or in-situ quantum error correction is shown. For example, the processing device 205 of the quantum system controller 30 performs a control process 340 to determine a next stage of a quantum circuit to be executed by a quantum processor, to identify one or more quantum errors that can exist for one or more data qubits of the quantum processor, to determine one or more software-based and / or active quantum error corrections to be performed, etc. The processing device 205 then performs a command generation 350 to generate one or more commands configured to cause the quantum processor 115 to execute at least a portion of the quantum circuit, to perform error correction (e.g., by updating a register of qubits via software-based quantum error correction and / or by performing one or more data qubit corrections and / or quantum gate modifications to physically resolve quantum errors), etc. For example, during the command generation 350, the processing device 205 generates commands to cause the quantum processor 115 and / or the quantum system controller 30 to perform processing identified and / or determined by the control process 340.

[0118] The TIC sequencer 235 receives the commands generated by the processing device 205 during the command generation 350 and performs TIC sequencing 360. In embodiments, the TIC sequencing 360 includes time indexing the commands and / or associating the commands with the time at which the commands should be executed to generate the TICs. In embodiments, the TIC sequencing 360 includes determining which drive controller element 215 should execute each TIC and saving and / or storing each TIC to a respective buffer 212 corresponding to the drive controller element 215 that should execute that TIC.

[0119] The drive controller elements 215 execute the TIC commands stored to their respective corresponding buffers 212 to cause one or more steering sources 60 to generate and provide steering signals and / or cause one or more voltage sources 50 to generate and provide control signals. The steering signals and / or control signals cause transport, controlled quantum state evolution, and / or quantum state reading and / or determination of one or more data qubits 380 of the quantum processor 115.

[0120] At various points in the execution of the quantum circuit, it can be necessary and / or desirable to read one or more data qubits to determine their quantum state and / or read one or more ancilla qubits that interact with the respective data qubits so that one or more quantum errors that can exist in the respective data qubits can be determined. In such a case, the steering and / or control signals generated by the execution of the TICs can cause the ancilla qubits to interact with the respective data qubits and / or cause a reading procedure to be performed so that the quantum state of the ancilla qubits or the data qubits is determined. In particular, the ancilla qubits or data qubits to be read can be illuminated with a particular wavelength of steering signal. If the ancilla qubit or data qubit is in a first quantum state of a defined qubit space, the qubit will emit a signature signal. If the ancilla qubit or data qubit is in a second quantum state of the defined qubit space, the qubit will not emit the signature signal.

[0121] The optical collection system 70 is configured to collect signals emitted by the ancilla qubits and / or data qubits of the quantum processor 115 to determine when the qubits emit or do not emit the signature signal. For example, the optical collection system 70 performs optical signal collection 310. The A / D converter 225 and / or another element of the quantum system controller 30 converts the optical signals detected by the optical collection system 70 to digital signal values and stores the digital signal values to the system buffer 212. For example, control system buffering 320 can be performed to store the digital signal values corresponding to the reading of the physical and / or ancilla qubits of the quantum processor to the system buffer 212 in the memory 210 for quick and efficient access to the digital signal values by the processing device 205.

[0122] The processing device 205 can then access the digital signal values from the system buffer 212 (e.g., load the digital signal values into the operational memory 210 of the processing device 205) and perform value processing 330. In embodiments, the processing device 205 performs value processing 330 to process the digital signal values to determine and / or generate input data based thereon. In one example embodiment, the input data is stored to the system buffer 212 and / or operational memory 210 of the processing device 205 for use during control processing 340.

[0123] The processing 300 continues with some processes, operations, etc. of the processing 300 occurring concurrently. For example, the TIC sequencer 235 can perform TIC sequencing 360 concurrently with the processing device 205 performing value processing 330, control processing 340, and / or command generation 350. Similarly, the driver controller element 215 can perform TICs in a time indexed manner while the TIC sequencer performs additional TIC sequencing 235. Additionally, the optical signal collection 310 and / or system buffering 320 can occur concurrently with other portions of the processing 300 being performed. In particular, the TIC sequencer 235 as a dedicated processing element separate from the processing device 205 enables the processing device 205 to quickly and efficiently perform signal value processing 330, control processing 340, and command generation 350 while the TIC sequencer 235 continues to manage the time indexed execution of TICs. This enables the quantum processor 115 to continue to perform various processing, processes, and / or operations without significant delay due to the processing device 205 processing new input data. This further enables the quantum system controller 30 to proactively perform quantum error correction in real-time and / or near real-time between different portions of the quantum circuit and / or within the coherence time of the data qubits to be acted upon.

[0124] FIG. 4A diagram is provided that illustrates how the processing device 205, the TIC sequencer 235, and the time generator 230 are used in coordination to cause the execution of the time indices of the TICs by the driver controller elements (DCEs) 215. For example, the timing generator 230 provides clock, timing, and / or synchronization signals such that each component of the quantum system controller 30 is configured to maintain distributed time and the DCEs 215 (e.g., DCE 215A - DCE 215N) are configured to execute the TICs in a time-indexed and synchronized manner. For example, the processing device 205 generates commands (e.g., first and / or second command sets) and provides the commands to the TIC sequencer 235. The TIC sequencer time- indexes the commands that generate the TICs and saves and / or stores the TICs to buffers 212 that correspond to the DCEs 215 that are to execute the respective TICs. For example, a first TIC can be stored to a first buffer 212A that corresponds to a first DCE 215A such that the first DCE 215A executes the first TIC. For example, an Nth TIC can be stored to an Nth buffer 212N that corresponds to an Nth DCE 215N such that the Nth DCE 215N executes the Nth TIC. For example, the TIC sequencer 230 causes the TICs to be made available to software running on the respective DCEs 215 by the dedicated and / or respective firmware buffers. The execution of the TICs by the DCEs 215 causes the respective DCEs 215 to control the one or more manipulation sources 60 and / or voltage sources 50 to cause the generation and provision of one or more manipulation signals and / or control signals to respective portions and / or elements of the quantum processor 115.

[0125] In embodiments, the quantum system controller 30 can cause the quantum processor 115 to execute a first portion of a quantum circuit by generating and executing a first command set. The input data can then be processed to make one or more decisions and / or determinations about the commands to be executed as part of a second command set that is configured to cause the quantum processor to execute a second portion of the quantum circuit. FIG. 5 A flowchart is provided that illustrates how the quantum system controller 30 (e.g., the processing device 205 during the control processing 340) utilizes the processing of the input data to determine which commands to include in the second command set.

[0126] Beginning with step / operation 502, one or more commands A are executed by the quantum system controller 30 and / or its driver controller elements 215. The execution of the one or more commands A causes the quantum processor 115 to at least execute a first portion of a quantum circuit.

[0127] At step / operation 504, the input data is processed and a determination is made based on the processing of the input data. In other words, step / operation 504 is a conditional execution point at which the next step to be performed by the quantum computer is determined in real-time or near real-time with respect to the quantum circuit being executed by the quantum computer. For example, the processing device 205 of the quantum system controller 30 processes the input data indicative of the quantum state of the one or more data qubits (as a result of the execution of the first portion of the quantum circuit), the one or more quantum errors that can be present in the one or more data qubits (e.g., as a result of the execution of the first portion of the quantum circuit), and / or the like. The determination is made from the input data and / or the processing thereof. For example, condition B is evaluated with the input data as its input and / or variables thereof to determine a conditional result. When condition B evaluates to yes or true, the processing continues to step / operation 506.

[0128] At step / operation 506, the processing device 205 determines and generates a command sequence C. In example embodiments, the command sequence C includes software and / or active quantum error correction. For example, the command sequence C can include one or more commands configured to cause the data qubits to be acted upon (e.g., for a Bloch sphere representation of the data qubits to be rotated) by applying, for example, a manipulation signal to the data qubits. For example, the command sequence C can include one or more operations to execute the second portion of the quantum circuit. The command sequence C can be provided to the TIC sequencer 235 for generating TICs and / or for buffering for execution by the respective driver controller elements 215. The processing can then continue to step / operation 508 or can follow a different path than when condition B has evaluated to no or false. For example, the quantum circuit can branch after step / operation 504 based on the evaluation of condition B from the input data.

[0129] At step / operation 508, the processing device 205 determines and generates a command sequence D. In example embodiments, the command sequence D includes one or more commands configured to cause the quantum computer 110 to execute the second portion of the quantum circuit. For example, the command sequence D can be provided to the TIC sequencer 235 for generating TICs and / or for buffering for execution by the respective driver controller elements 215. In embodiments, the execution of the command sequence D or the command sequence C and the command sequence D (e.g., by the respective driver controller elements 215) by the quantum system controller 30 causes the second portion of the quantum circuit to be executed.

[0130] FIG. 6A flowchart is provided that illustrates processing, procedures, operations, etc. that are performed when the processing device 205 determines that input data is needed to perform further control processing 340 and / or command generation 350. For example, when it is determined at step / operation 504 that condition B is to be evaluated based on input data, the processing device 205 can perform processing, procedures, operations, etc. similar to those shown in FIG. 6 FIG. 6 to access input data so that condition B can be evaluated based thereon. In another example, during execution of the first portion of the quantum circuit, software running on the quantum system controller 30 (e.g., the processing device 205) tracks the generation of commands / TICs that will result in digital signal values and / or input data being issued (e.g., commands / TICs corresponding to read processes). Once input data or digital signal values are needed, e.g., to be consumed by the control processing 340 software (e.g., possibly through the value processing 330 software), processing, procedures, operations, etc. similar to those shown in FIG. 6 FIG. 6 can be performed.

[0131] For example, execution of the second portion of the quantum circuit can depend on values based on one or more qubits of the first portion of the quantum circuit being executed. In another example, the processing device 205 can determine that a gate or other physical and / or quantum operation of one or more data qubits is to be performed, which can require active quantum error correction to address one or more quantum errors that can exist in the one or more data qubits. For example, in embodiments, active quantum error correction includes adjusting and / or modifying a gate or other physical and / or quantum operation to be performed on the one or more data qubits prior to execution of the gate and / or physical and / or quantum operation, and / or adjusting the one or more data qubits to implement corrections thereon. For example, corrections can include rotations of data qubits in their bloch sphere representations.

[0132] From step / operation 602, it is determined that input data is needed. For example, the processing device 205 determines that input data needs to be processed in order for the control processing 340 and / or command generation 350 to continue, such that one or more decisions and / or determinations of the control processing 340 and / or command generation 350 can be performed. At step / operation 604, the processing device 205 determines whether input data is loaded. For example, the processing device 205 determines whether input has been loaded into the operational memory 210 used to perform the control processing 340 and / or command generation 350, respectively.

[0133] When it is determined that the input data is loaded, the process continues to step / operation 606. At step / operation 606, the input data is processed and / or provided as input to the control process 340 and / or command generation 350 process, such that the sequence can continue execution. When it is determined that the input data is not loaded, the process continues to step / operation 608. At step / operation 608, the processing device 205 queries the system buffer 212 and / or checks the address of the system buffer where the input data is expected to be located. At step / operation 610, it is determined whether the input data is present in the system buffer 212. For example, the processing device 205 determines whether new or updated input data is available in the system buffer 212 (e.g., based on a timestamp associated with the input data and the time the input data was loaded into the operating memory).

[0134] When it is determined at step / operation 610 that the input data is available, the process continues to step / operation 612. At step / operation 612, the processing device 205 loads the input data from the system buffer into the operating memory. The processing device 205 then performs step / operation 606 to process and / or provide the input data as input to the control process 340 and / or command generation 350 process, such that the sequence can continue execution.

[0135] When it is determined at step / operation 610 that the input data is not available, the process returns to step / operation 608 to continue to check whether the input data is available until the input data becomes available for the process to continue forward. Since the control software operating on and / or executed by the processing device 205 is not responsible for the real-time nature of the system (e.g., ensuring that commands are executed at the appropriate time), the control software operating on and / or executed by the processing device 205 is able to alternate between command generation and checking for the arrival of input data.

[0136] FIG. 7 A flowchart illustrating operations, processes, procedures, etc. performed by the quantum system controller 30 to cause generation of input data that can be used to determine quantum errors that can be present for data qubits is provided. For example, the processing device 205 executes the control process 340 and the command generation 350 to generate commands that, when executed in a time- indexed manner by the appropriate driver controller elements 215, cause the quantum computer 100 to use one or more data qubits (possibly organized into one or more logical qubits) of the quantum processor 115 to execute a first portion of a quantum circuit. In embodiments, these commands can include generation commands for control signals configured to cause at least one qubit to be transported from a first location to a second location and / or a reordering of one or more qubits, generation commands for one or more manipulation signals configured to cause execution of one or more single or multi (e.g., two) qubit gates, commands for a read process, etc.

[0137] The processing device 205 can then determine that, in order to generate a second set of commands configured to be executed by the quantum system controller 30 to cause a second part of the quantum circuit (e.g. after the first part of the quantum circuit) to be executed, information is required about the results of one or more operations performed during the first part of the quantum circuit. For example, the second part of the quantum circuit can comprise the execution of a gate which, when not corrected for one or more possible quantum errors, can result in obtaining inaccurate results (e.g. resulting in the introduction of quantum errors which are difficult to determine, interpret and / or correct). Accordingly, information about quantum errors which can be present in the one or more data qubits is determined by generating and processing input data corresponding to the one or more data qubits. FIG. 7 An example embodiment is shown which illustrates how input data corresponding to a data qubit is generated.

[0138] From step / operation 702, the quantum system controller 30 causes the ancilla qubit to interact with the data qubit. For example, the processing device 205 generates commands which cause the ancilla qubit to be initialised (e.g. cause the ancilla qubit to be in a known initial quantum state), the ancilla qubit and / or the data qubit to be transmitted with a required proximity, interactions to be performed such that information about the quantum state of the data qubit is encoded onto the ancilla qubit whilst not changing the quantum state of the data qubit (or by changing the quantum state of the data qubit in a known way which can be interpreted and / or corrected) etc. The TIC sequencer 235 executes the TIC sequencing 330 to generate TICs from the commands generated by the processing device 205 and store the TICs to the appropriate buffers. The driver controller elements 215 then each execute the TICs stored to the corresponding buffers 212 in a time indexed manner (e.g. based on clock, timing and / or synchronisation signals generated by the time generator 230) to cause the initialisation of the ancilla qubit (e.g. cause the ancilla qubit to be in a known initial quantum state), the ancilla qubit and / or the data qubit to be transmitted with a required proximity, interactions to be performed such that information about the quantum state of the data qubit is encoded onto the ancilla qubit whilst not changing the quantum state of the data qubit (or by changing the quantum state of the data qubit in a known way which can be interpreted and / or corrected) etc. to be implemented.

[0139] At step / operation 704, transport of ancilla qubits and / or data qubits is performed to separate the ancilla qubits and data qubits. For example, processing device 205 generates commands that cause transport of ancilla qubits and / or data qubits to a separation location, etc. TIC sequencer 235 executes TIC sequencing 330 to generate TICs from the commands generated by processing device 205 and store the TICs to appropriate buffers. Driver controller elements 215 then each execute the TICs stored to the corresponding buffers 212 in a time- indexed manner (e.g., based on clock, timing, and / or synchronization signals generated by time generator 230) to cause transport of ancilla qubits and / or data qubits to a separation location, etc.

[0140] At step / operation 706, the ancilla qubits are read. For example, processing device 205 generates commands that cause a read process to be performed on the ancilla qubits. In embodiments, the read process includes a particular wavelength of a manipulation signal incident on the ancilla qubits, a shelving process to be implemented, monitoring of signals generated by one or more photodetectors of optical collection system 70, etc. TIC sequencer 235 executes TIC sequencing 330 to generate TICs from the commands generated by processing device 205 and store the TICs to appropriate buffers. Driver controller elements 215 then each execute the TICs stored to the corresponding buffers 212 in a time- indexed manner (e.g., based on clock, timing, and / or synchronization signals generated by time generator 230) to cause the read process to be performed on the ancilla qubits.

[0141] At step / operation 708, input signals (e.g., captured and / or detected by optical collection system 70 in response to performance of the read process on the ancilla qubits) are processed to determine input data corresponding to the ancilla qubits. For example, one or more photodetectors of optical collection system 70 collect and / or detect optical signals and generate electrical signals based thereon. Optical collection system 70 then communicates the electrical signals encoding the collected and / or detected optical signals to one or more A / D converters 225 of quantum system controller 30. A / D converters 225 convert the analog electrical signals to digital electrical signals, which encode the collected and / or detected optical signals. The resulting digital signal values are stored to system buffers 212 and / or provided to value processing 330. In example embodiments, processing device 205 accesses the digital signal values from system buffers and / or receives the digital signal values and performs value processing 330 to generate input data based on the digital signal values. In example embodiments, value processing 330 includes processing the digital signal values to determine a quantum state of the ancilla qubits and / or one or more quantum errors that can be present in a corresponding data qubit that interacted with the ancilla qubits at step / operation 702. The input data can then be stored to system buffers 212, loaded to operational memory 210 used by processing device 205 to perform control processing 340, etc.

[0142] At step / operation 710, an indication that input data is available and where the input data is stored is stored to the system buffer 212. For example, the processing device 205 can store an indication to the system buffer 212 that input data is available so that at step / operation 610 the processing device 205 can easily and quickly determine whether input data is available. In embodiments, the indication includes an address or location where the input data is stored so that the processing device 205 can easily and quickly load the input data at step / operation 612.

[0143] In embodiments, the status is flagged in a CPU register for the processing device 205 with the lowest possible latency for software access whenever input data and / or digital signal values are available. During normal operation of the control processing 340 and / or command generation 350, the CPU register is periodically checked to see if results are pending (e.g., a flag or other indicator of input data and / or digital signal values is available). If so, the input data and / or digital signal values are moved to program memory (e.g., working memory) which is immediately available once it is specified in the control sequence that the input data and / or digital signal values are needed (e.g., determined by the control processing 340). When the input data and / or digital signal values are moved to program memory (e.g., working memory), the flag or other indicator of the availability of new input data and / or digital signal values is reset.

[0144] It should be appreciated that quantum computers come in a variety of formats. For example, FIG. 1 The illustrated quantum computer 100 uses atomic objects constrained within atomic object constraining devices 120 as physical and ancilla qubits. In embodiments, the quantum computer uses Josephson junctions, photons, electron spins, and / or another two-state quantum system (or a well-defined multi-state quantum system) as qubits. Depending on the type of qubits used and various other factors, various quantum error correction techniques can be selected for use.

[0145] As described above, the separation of the processing device 205 configured to perform the value processing 330, the control processing 340, and the command generation 350 and the TIC sequencer 235 configured to perform the TIC sequencing enables the processing device 205 to quickly and efficiently process the input data and continue control processing and command generation while the quantum system controller 30 continues to perform the TIC. This enables the quantum system controller 30 to make dynamic decisions based on the input data. The dynamic decisions enable real-time or near real-time execution of software-based active quantum error correction by introducing quantum errors into the quantum computation and / or logical and / or data qubits. In particular, the embodiments enable execution of quantum error correction (e.g., software-based and / or active quantum error correction) within the coherence time of the data qubits. Further, the storage of the input data, the digital signal values that can be used to generate the input data, and / or the indication of availability of the input data and / or the digital signal values, and the storage of the locations in the system buffer 212 to which the input data and / or the digital signal values are stored enables faster and more efficient loading of the input data and / or the digital signal values for processing.

[0146] Accordingly, the embodiments provide a quantum system controller and / or method of operation thereof to enable use of various quantum error correction techniques. Generally, a quantum error-correcting code (QECC) is a quantum algorithm that detects and corrects errors by encoding qubits into many additional qubits to provide redundancy, thereby protecting quantum information. Qubits encoded into a QECC are referred to as logical qubits, and gates that act on these logical qubits are referred to as logical gates. As described above, a logical qubit includes a plurality of data qubits. QECCs will now be described in more detail based on FIG. 1 Some examples of quantum error correction performed by the quantum system controller 30 will now be described in more detail based on the quantum computer 100 shown and an example QECC known as the Pauli stabilizer code.

[0147] In the embodiments, the process of protecting quantum information encoded in a quantum system employing a QECC includes a repeated cycle of syndrome extraction. In these rounds, a joint measurement of a set of multiple data qubits (referred to as data qubits) storing data is made. The measurement outcomes of these measurements (e.g., input data) are referred to as syndromes. After a suitable number of rounds of syndrome extraction, the syndromes are provided to an algorithm known as a decoding algorithm. The decoding algorithm uses the syndrome information to determine a correction to the QECC in an attempt to mitigate quantum errors (e.g., quantum errors that have been introduced to various logical and / or data qubits) that have accumulated in the quantum computation, for example, due to noise (e.g., noise in the manipulation and / or control signals, etc.).

[0148] In embodiments, to avoid inadvertently introducing additional noise to one or more data qubits, corrections determined by the decoding algorithm are stored and tracked in software, rather than being physically applied, when possible. For example, in cases where possible, the corrections used are software-based corrections, with active quantum error correction applied only under certain conditions and / or circumstances. For example, for the example Pauli stabilizer codes (e.g., including surface and color codes), these software-based and / or software-tracked corrections are referred to as Pauli frames, as the corrections for these codes are a set of Pauli operators. In embodiments, each data qubit corresponds to a Pauli frame. For example, in example embodiments, each data qubit register stored and / or maintained by the quantum system controller 30 includes a Pauli frame. When a new correction is determined for a data qubit, the Pauli frame corresponding to the data qubit is updated with the new correction evolving the Pauli frame each time the decoding algorithm is executed.

[0149] As noted above, to reduce the introduction of additional noise to data qubits, active quantum error correction can be performed only under certain conditions and / or circumstances. For example, certain quantum gates require active quantum error correction to be applied (e.g., by incorporating corrections into the gate operation) before the gate operation is executed or adapted, adjusted, and / or modified. For Pauli stabilizer codes, such gates requiring active quantum error correction are referred to as non-Clifford gates, while other gates (referred to as Clifford gates) do not require active quantum error correction. Notably, however, in general, the Pauli frame corresponding to a data qubit will need to be rotated in software according to which Clifford gates are applied. Thus, in example embodiments, the quantum system controller 30 employs software-tracked Pauli frames and either physically applies the Pauli frame before a logical non-Clifford gate (see FIG. 8A ) or adapts the selection of logical gates based on corrections (see FIG. 8B ). After each physical application of a software Pauli frame due to a non-Clifford gate, the Pauli frame corrections continue to be appropriately tracked and updated in software.

[0150] FIG. 8A and FIG. 8B Two possible techniques for performing active quantum error correction in a Pauli stabilizer code framework are illustrated. FIG. 8AThe repetition of syndrome extraction 815 is shown for a single logical qubit 810. The results of syndrome extraction 815 are processed using a decoding algorithm 820 (e.g., executed by processing device 205, possibly as part of value processing 330 and / or control processing 340). The results of syndrome extraction 815 and / or the results of processing the syndrome extraction results using decoding algorithm 820 are used to update the software-tracked Pauli frame 805 for the logical qubit to perform software-based quantum error correction. Thus, when a Clifford gate 830 is executed on logical qubit 810 (e.g., gates are executed approximately simultaneously on all data qubits of logical qubit 810), in the illustrated embodiment no active quantum error correction is performed. However, prior to executing a non-Clifford gate 845, corrections 840 are determined for logical qubit 810 based on the software-tracked Pauli frame 805 for the logical qubit (e.g., as part of control processing 340, and then corresponding commands are generated as part of command generation 350), and applied to the logical qubit (e.g., to each data qubit of logical qubit 810 at approximately the same time). Non-Clifford gate 845 is then applied to logical qubit 810 after corrections 840 have been applied. The repetition of syndrome extraction 815 continues after execution of non-Clifford gate 845, with the software-tracked Pauli frame 805 being updated accordingly. This scheme extends in an analogous manner to multiple logical qubits and gates, as FIG. 9 shown.

[0151] FIG. 8B Another technique for performing active quantum error correction according to a Pauli stabilizer code framework is shown. From FIG. 8Bthe results of the syndrome extraction 815 are processed using a decoding algorithm 820 (e.g., executed by the processing device 205, possibly as part of the value processing 330 and / or the control processing 340). The results of the syndrome extraction 815 and / or the results of processing the syndrome extraction results using the decoding algorithm 820 are used to update the software-tracked Pauli frame 805 for the logical qubit to perform software-based quantum error correction. Thus, when the Clifford gate 830 is executed on the logical qubit 810 (e.g., the gate is executed approximately simultaneously on all data qubits of the logical qubit 810), no active quantum error correction is performed in the illustrated embodiment. However, prior to the representation of the non-Clifford gate, an adjustment and / or modification of the non-Clifford gate is determined. In the illustrated embodiment, the non-Clifford gate is executed as a first non-Clifford gate 845A and a second non-Clifford gate 845B that are applied in succession to the logical qubit 810. In particular, a correction is applied to the logical qubit 810 by adaptively selecting an appropriate non-Clifford gate 845 (e.g., by the control processing 340 based at least in part on the software-tracked Pauli frame 805 for the logical qubit 810), and then the adaptively selected non-Clifford gate 845A, 845B is applied to the logical qubit 810 (e.g., based on corresponding commands that are generated as part of the command generation 350 and queued for execution as part of the TIC sequencing 360). Thus, the non-Clifford gates 845A, 845B both apply corrections determined based on the software-tracked Pauli frame 805 and apply a non-Clifford gate corresponding to the execution of the quantum circuit. The repeated execution of the syndrome extraction 815 continues after the execution of the non-Clifford gate 845, and the software-tracked Pauli frame 805 is updated accordingly. It will be appreciated that the execution of the quantum circuit can use one or both of the active quantum error correction techniques illustrated in FIG. 8A and 8B depending on the quantum circuit and / or quantum system.

[0152] FIG. 9Two logical qubits 910A, 910B are shown encoded into two surface codes in the framework of the Pauli stabilizer code. In particular, a first software trace Pauli frame 905A tracks quantum errors and / or quantum error correction for a first logical qubit 910A, and a second software trace Pauli frame 905B tracks quantum errors and / or quantum error correction for a second logical qubit 910B. The software trace Pauli frames 905A, 905B are evolved and / or updated (via syndrome extraction and processing of the results of syndrome extraction using a decoding algorithm, as indicated by the dashed lines pointing from the respective logical qubit lines 911A, 911B to the respective software trace Pauli frame lines 906A, 906B) as logical gates are applied to the logical qubits 910A, 910B. For example, the first software trace Pauli frame 905A is updated to indicate the execution of a Hadamard gate 920 on the first logical qubit 910A. The first and second software trace Pauli frames 905A, 905B are then updated to indicate the occurrence of a controlled NOT gate, with the first logical qubit 910A acting as the control qubit and the second logical qubit 910B acting as the target qubit. Since both the Hadamard gate and the controlled NOT gate are Clifford gates, no active quantum error correction is applied immediately prior to the execution of these two gates. Prior to the execution of a first non-Clifford gate 945A on the first logical qubit 910A, a correction 940A is determined based on the first software trace Pauli frame 905A and applied to the first logical qubit 910A. A second correction 940B is determined based on the first software trace Pauli frame 905A and applied to the first logical qubit 910A, while a third correction 940C is determined based on the second software trace Pauli frame 910B and applied to the second logical qubit 910B. A second non-Clifford gate 945B is then executed on both the first and second logical qubits 910A, 910B. The Pauli frames 905A, 905B for each logical qubit 910A, 910B (pfo and pfl) are updated at various points in the quantum circuit as new corrections 940 are determined following multiple rounds of syndrome extraction and decoding. The Pauli frames 905A, 905B are also updated according to how gates (Clifford gates and non-Clifford gates) will act on the operators represented by the respective Pauli frames. In this example, corrections are applied prior to non-Clifford gates and the corresponding Pauli frame updates and continue to be tracked in software. In another example embodiment, and / or at different points in the partially illustrated quantum circuit, active quantum error correction can be performed through adaptation, selection, modification, etc. of the non-Clifford gates applied to the logical qubits.

[0153] In embodiments, the syndrome extraction consists of a series of quantum gates that are encoded as parallel operations across data qubits and ancilla qubits. In example embodiments, the syndrome extraction includes FIG. 7The steps / operations 702-706 shown in FIG. 7. In embodiments, a round of syndrome extraction requires ancilla qubits to have quantum interactions with two or more data qubits of the same logical qubit or different logical qubits. This requires compiling a transport pattern that allows each ancilla-data qubit interaction while minimizing the total number of rounds of gates and time spent moving physical qubits. The measurement results generated by performing a readout procedure on the ancilla qubits store and / or encapsulate the results of the syndrome extraction.

[0154] To implement syndrome extraction, in embodiments, a user (e.g., operating (classical) computing entity 10) can express a general quantum circuit to be translated and optimized (e.g., by quantum system controller 30) for execution by quantum processor 110. In embodiments, a user (e.g., operating (classical) computing entity 10) can add any necessary or desired constraints to the operation by adding quantum circuits and barriers of quantum circuits, and the associated barriers are translated and optimized by quantum system controller 30 for execution of the quantum circuit by quantum processor 115. In embodiments, the quantum circuit is encoded, optimized, and parallelized to a set of parallel operations on the quantum system by a compilation process (e.g., performed by quantum system controller 30). In example embodiments, the compilation process is performed in real-time and / or near real-time with execution of at least a portion of the quantum circuit by quantum processor 115.

[0155] In embodiments, once the syndrome is extracted, it must be decoded to determine the most likely error that occurred and / or was introduced into the logical and / or data qubits in the quantum circuit (see FIG. 7 the steps / operations 708 shown in FIG. 7). These calculations are only classical evaluations of the ancilla measurements, whose goal is to update the software- tracked Pauli frame of each logical qubit, which tracks the most likely correction that needs to be applied to that logical qubit. The syndrome measurements extracted in multiple rounds can be used in combination to more accurately determine the most likely error that occurred.

[0156] In embodiments, the real-time algorithms used to decode the extracted syndrome measurements are encoded into the same description as the quantum circuit that is directly handled by the main program running on quantum system controller 30. In embodiments, for more complex calculations, quantum system controller 30 can perform external calls to a classical computer that works in tandem and in real-time to perform the calculations using sandboxed classical code that is executed in real-time and return the results to quantum system controller 30 in real-time or near real-time.

[0157] In embodiments, quantum error correction is performed when a quantum gate is encountered that is to be executed on a logical qubit having a non-identical Pauli-frame. In embodiments, the quantum error correction can be software-based quantum error correction or active quantum error correction, e.g., applying corrections to the logical and / or data qubits of the logical qubit and / or updating and / or modifying the quantum gate. In embodiments, to apply active quantum error correction, the Pauli-frame of the logical qubit indicates that one or more quantum gates are to be applied to the set of data qubits that make up the logical qubit. For example, active quantum error correction can be performed in the case where a non-Clifford gate is to be applied, where some or all of the Pauli-frames cannot be interpreted by and / or updated by the update.

[0158] FIG. 10A It is shown how the corrections determined based on the Pauli-frame of the logical qubit are applied to the logical qubit. In particular, FIG. 10A It is shown how a real-time decision fundamentally influences which logical gates should be applied as corrections to the logical qubit, and how the Pauli-frame should be updated (in this case, reset back to the Identity Pauli-frame state). FIG. 10A The left column describes each step, the middle column illustrates the high-level system primitives used in each step, and the right column lists the quantum system controller 30 primitive (software) element types used in that step.

[0159] FIG. 10B It is shown how the logical gates are adapted, adjusted, and / or modified based on the Pauli-frame of the logical qubit on which they are to be implemented. For example, in embodiments, the logical gates can take the Pauli-frame as an input parameter, and the logical gates can be dynamically (e.g., in real-time or near real-time) updated, adapted, and / or modified and then applied to cause the correct gate to be applied in the reference frame of the data qubits. Any necessary updates to the Pauli-frame are also made.

[0160] For example, FIG. 10B It is shown how a logical T gate (e.g., an exemplary non-Clifford gate) is adjusted, adapted, and / or modified when applied to a logical qubit. For example, FIG. 10B It is shown how a real-time or near real-time decision fundamentally influences which logical gates should be applied to the logical qubit (e.g., a T gate or T gate), and how the Pauli-frame should be uniquely updated based on the current Pauli-frame of the logical qubit. FIG. 10B The left column describes each step, the middle column illustrates the high-level system primitives used in each step, and the right column lists the quantum system controller 30 primitive (software) element types used in that step.

[0161] For some gates (e.g., Clifford gates), for example, software-based correction can be performed by simply updating the Pauli frame or internal tracking of the logical qubit state and / or one or more data qubits of the logical qubit (rather than applying any gates to the physical qubits). The benefit of doing so is that this update tracked in software does not accumulate errors due to inaccurate application of physical gates or additional transport of data qubits. Software-based quantum correction keeps the quantum state of the logical qubit (and / or its constituent data qubits) with perfect fidelity to the accuracy of the software tracking employed.

[0162] FIG. 10C It is shown how the application of logical operations to logical qubits can be imposed using software-based quantum error correction without requiring any physical operations in the quantum processor 115. FIG. 10C It is shown how real-time or near real-time decisions affect which Pauli frame update is applied. However, as FIG. 10C It is shown that for the software-based quantum error correction process, no quantum gates need to be applied to perform quantum error correction. FIG. 10C The left column describes each step, the middle column illustrates the high-level system primitives used in each step, and the right column lists the quantum system controller 30 primitive (software) element types used in that step.

[0163] FIG. 11 A flowchart is provided that illustrates the processes, procedures, operations, etc. of real-time processing control including quantum error correction performed by the processing device 205 of the quantum system controller 30. Beginning with step / operation 1102, a first set of commands is generated. For example, the processing device 205 executes and / or operates executable code and / or instructions configured to cause the processing device 205 to execute the command generation 350 based at least in part on a quantum circuit to be executed. In example embodiments, the quantum circuit is received by the computing entity 10 from the quantum system controller 30 (e.g., over the communication interface 220). In embodiments, the commands include commands to be executed by the driver controller elements 215 configured to control and / or operate the voltage sources 50, the steering sources 60, components of the optical collection system 70, etc. For example, the commands can be configured to cause transport of one or more physical qubits within the quantum processor 115, execution of one or more quantum gates on physical qubits of the quantum processor 115, resetting of photon counts of photodetectors of the optical collection system 70, etc.

[0164] At step / operation 1104, the processing device 205 provides the first set of commands to the TIC sequencer 235. In example embodiments, the commands of the first set of commands are configured to be executed simultaneously. For example, the set of commands can be configured to cause a plurality of voltage sources to generate control signals that are provided to electrodes of the atomic object confinement apparatus 120 of the quantum processor 115, thereby causing the physical qubits to transport within the atomic object confinement apparatus in a prescribed manner. In another example, the set of commands can be configured to cause the one or more manipulation sources 60 to generate one or more manipulation signals that are provided to the quantum processor 115 such that the manipulation signals are incident on one or more physical qubits to produce one or more gates.

[0165] In embodiments, the processing device 205 provides the commands of the first set of commands to the TIC sequencer 235 each time a command is generated. In embodiments, the processing device 205 provides the set of commands to the TIC sequencer 235. In example embodiments, the processing device 205 generates all of the commands of the first set of commands and provides the entire first set of commands to the TIC sequencer 235.

[0166] At step / operation 1106, the processing device 205 (e.g., corresponding to executable instructions and / or code of the value processing 330 and / or the control processing 340 executing on the processing device 205) determines that input data is needed. For example, the processing device 205 can determine that a condition needs to be evaluated in order to continue generating commands to cause execution of the quantum circuit. For example, as shown in FIG. 5 the second set of commands to be generated can depend on the evaluation of the condition. For example, based on the evaluation of condition B, the processing device 205 can determine whether the second set of commands should include only sequence D or should include both sequence C and sequence D. When the processing device 205 determines that a condition is to be evaluated and / or input data needs to be processed to determine the second set of commands, the processing device 205 accesses the input data. For example, the processing device 205 can access and / or load the input data following a method similar to that shown in FIG. 6

[0167] At step / operation 1108, the processing device 205 (e.g., corresponding to executable instructions and / or code of the value processing 330 and / or the control processing 340 executing on the processing device 205) processes and / or analyzes the input data. For example, the processing device 205 processes and / or analyzes the input data to evaluate a condition, etc. For example, the input data can be used to determine quantum states of one or more data qubits and / or logical qubits. For example, the input data can be used for quantum errors that can have been introduced into the quantum computation, the logical qubits, and / or the data qubits.

[0168] ​At step / operation 1110, the processing device 205 (e.g., executable instructions and / or code corresponding to the command generation 350 executing on the processing device 205) determines the command to be generated as a second command set and the processing device 205 (e.g., executable instructions and / or code corresponding to the command generation 350 executing on the processing device 205) generates the second command set. In embodiments, the commands comprise commands to be executed by the drive controller elements 215 configured to control and / or operate the voltage sources 50, the steering sources 60, components of the optical collection system 70, etc. For example, the commands can be configured to cause transport of one or more physical qubits within the quantum processor 115, execution of one or more quantum gates on the physical qubits of the quantum processor 115, resetting of photon counts of photodetectors of the optical collection system 70, etc. In embodiments, execution of the second command set, e.g., by the appropriate drive controller elements 215, results in execution of quantum error correction (e.g., software-based error correction and / or active quantum error correction) and / or at least a second portion of the quantum circuit to be executed.

[0169] At step / operation 1112, the processing device 205 provides the second command set to the TIC sequencer 235. In embodiments, the processing device 205 provides the commands in the second command set to the TIC sequencer 235 each time a command is generated. In embodiments, the processing device 205 provides groups of commands to the TIC sequencer 235. For example, in example embodiments, the commands of the second command set are configured to be executed simultaneously. For example, a group of commands can be configured to cause a plurality of voltage sources to generate control signals that are provided to electrodes of the atomic object confinement devices 120 of the quantum processor 115 that result in the physical qubits being transported within the atomic object confinement devices in a prescribed manner. In another example, a group of commands can be configured to cause one or more steering sources 60 to generate one or more steering signals that are provided to the quantum processor 115 such that the steering signals are incident on one or more physical qubits to produce one or more gates. In example embodiments, the processing device 205 generates all of the commands of the second command set and provides the entire second command set to the TIC sequencer 235.

[0170] Technical advantages

[0171] Embodiments provide a quantum system controller and corresponding methods for performing high-reliability quantum computing. To achieve such reliability, embodiments employ quantum error correction (QEC) to suppress and / or reduce noise to a desired and / or minimum level during computation (e.g., during execution of a quantum circuit). In particular, the quantum system controller includes being configured to determine quantum errors that can be present in one or more data and / or logical qubits, determine corrections (e.g., software-based corrections and / or active quantum error correction) to address the quantum errors, and perform quantum error correction in real-time and / or near real-time while executing the quantum circuit. For example, in example embodiments, the quantum system controller is configured to perform quantum error correction between execution of two gates on a data or logical qubit. For example, the quantum system controller is configured to perform quantum error correction in a time period that is less than a coherence time of the data qubit. In various cases, the coherence time of the data qubit is less than twenty minutes, less than ten minutes, less than five minutes, or less than one minute. In embodiments, quantum error correction of embodiments takes approximately 0.1 to 0.2 seconds to perform. For example, the latency of the quantum system controller is approximately 10 to a few hundred microseconds. Thus, embodiments provide technical solutions to the technical problem of how to enable a quantum system controller to perform quantum error correction (e.g., within a coherence time of a respective data qubit) to improve performance of a quantum computer.

[0172] Embodiments described herein provide a quantum system controller and / or corresponding methods that implement quantum error correction by converting and reordering conditional gates and classical logic from a quantum description into serialized, potentially conditional operations to be executed by a quantum processor. The conversion converts universal quantum gates into gates that can be executed by the quantum processor and aligns the number of operations with the parallelism allowed by the quantum processor. The quantum system controller places (e.g., at physical locations within the quantum processor) and commands both quantum and classical operations to maximize parallelism on the quantum processor to minimize execution time and heating (e.g., introduction of thermal noise), all while ensuring that any dependencies are preserved.

[0173] For example, the quantum system controller 30 includes a processing device 205 that performs value processing 330, control processing 340, and command generation 350 for the quantum computer. However, a separate processing element, the TIC sequencer 235, is responsible for the real-time or near-real-time operation of the quantum system controller 30 and the quantum computer 110 (e.g., executing commands in parallel and / or simultaneously using TIC). Therefore, the processing device 205 can pause the execution of command generation 350 to access and / or load input data, evaluate conditions based on the input data, perform control processing based on the evaluation of conditions based on the input data, and then return to command generation to generate commands to enable the quantum processor to perform active quantum error correction and / or continue executing the quantum circuitry. However, pausing command generation does not slow down or pause the continuous real-time or near-real-time execution of TIC by the quantum system controller, as this process is managed by the TIC sequencer 235. Furthermore, using flags in a buffer memory and automatically loading digital signal values ​​and / or input data into program and / or operation memory based on these flags reduces latency and / or lag introduced by the processing device accessing and / or loading digital signal values ​​and / or input data. Therefore, the embodiments improve the functionality of quantum system controllers and quantum computers by achieving higher reliability measurements through real-time or near-real-time quantum error correction and by increasing the speed and operational efficiency of the quantum system controller.

[0174] Exemplary computing entity

[0175] FIG. 12 An illustrative schematic representation of an example computing entity 10 that can be used in conjunction with embodiments of the present disclosure is provided. In various embodiments, computing entity 10 is a classical (e.g., semiconductor-based) computer configured to allow a user to provide input to quantum computer 110 (e.g., through a user interface of computing entity 10) and to receive, display, analyze, and / or similar output from quantum computer 110.

[0176] like FIG. 12 As shown, computing entity 10 may include an antenna 1212, a transmitter 1204 (e.g., a radio), a receiver 1206 (e.g., a radio), and a processing element 1208 for providing signals to and receiving signals from the transmitter 1204 and receiver 1206. The signals provided to and received from the transmitter 1204 and receiver 1206 may include signaling information / data according to the air interface standard of the applicable wireless system for communication with various entities such as quantum system controller 30, other computing entities 10, etc.

[0177] In this regard, the computing entity 10 can be capable of operating with one or more air interface standards, communication protocols, modulation types, and access types. For example, the computing entity 10 can be configured to receive and / or provide communications using a wired transmission protocol, such as fiber optic distributed data interface (FDDI), digital subscriber line (DSL), Ethernet, asynchronous transfer mode (ATM), frame relay, data over cable service interface specification (DOCSIS), or any other wired transmission protocol.

[0178] Similarly, the computing entity 10 can be configured to communicate via a wireless external communication network using any of a variety of protocols, such as general packet radio service (GPRS), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 IX (lxRTT), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Time Division-Synchronous Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX), Bluetooth®, or any other wireless communication protocol.

[0179] The wireless communication can be based on any wireless communication protocol, such as, for example, Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), Evolved Universal Terrestrial Radio Access Network (E-UTRAN), Evolution-Data Optimized (EVDO), High Speed Packet Access (HSPA), High-Speed Downlink Packet Access (HSDPA), IEEE 802.11 (Wi-Fi), Wi-Fi Direct, 802.16 (WiMAX), ultra wideband (UWB), infrared (IR) protocol, near field communication (NFC) protocol, Wibree, Bluetooth protocols, wireless universal serial bus (USB) protocol, and / or any other wireless protocol.The computing entity 10 can use such protocols and standards to use Border Gateway Protocol (BGP), Dynamic Host Configuration Protocol (DHCP), Domain Name System (DNS), File Transfer Protocol (FTP), Hypertext Transfer Protocol (HTTP), HTTP over TLS / SSL / Secure, Internet Message Access Protocol (IMAP), Network Time Protocol (NTP), Simple Mail Transfer Protocol (SMTP), Telnet, Transport Layer Security (TLS), Secure Sockets Layer (SSL), Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Datagram Congestion Control Protocol (DCCP), Stream Control Transmission Protocol (SCTP), HyperText Markup Language (HTML), etc.

[0180] Via these communication standards and protocols, computing entity 10 can use such as Unstructured Supplementary Service information / data (USSD), Short Message Service (SMS), Multimedia Messaging Service (MMS), Dual-Tone Multi-Frequency Signaling (DTMF), and / or Subscriber Identity Module Dialer (SIM dialer). For example, computing entity 10 can also download changes, add-ons, and updates to, for example, its firmware, software (e.g., including executable instructions, applications, program modules), and operating system.

[0181] Computing entity 10 can also include user interface devices that include one or more user input / output interfaces (e.g., display 1216 and / or speaker / speaker driver coupled to processing element 1208, as well as touch screen, keyboard, mouse, and / or microphone coupled to processing element 1208). For example, the user output interface can be configured to provide applications, browsers, user interfaces, interfaces, dashboards, screens, webpages, pages, and / or similar words used herein interchangeably to execute on and / or accessible by computing entity 10 to cause display or aural presentation of information / data and to interact therewith via one or more user input interfaces. The user input interface can include any of a number of devices allowing computing entity 10 to receive data, such as a keyboard 1218 (hard- or soft), touch display, voice / speech or motion interface, scanner, reader, or other input device. In embodiments including a keypad 1218, keypad 1218 can include (or cause display of) the conventional numeric (0-9) and related keys (#, *), and other keys for operating computing entity 10 and can include a full set of alphabetic keys or a set of keys that can be activated to provide a full set of alphanumeric keys. In addition to providing input, user input interfaces can also be used to activate or deactivate certain functions, such as screen savers and / or sleep modes. Through such input, computing entity 10 can gather information / data, user interaction / input, and the like.

[0182] The computing entity 10 can also include volatile memory or storage 1222 and / or non-volatile memory or storage 1224, which can be embedded and / or can be removable. For example, non-volatile memory can be ROM, PROM, EPROM, EEPROM, flash memory, MMCs, SD memory cards, Memory Sticks, CBRAM, PRAM, FeRAM, RRAM, SONOS, racetrack memory, etc. Volatile memory can be RAM, DRAM, SRAM, FPMDRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, etc. The volatile and non-volatile memory or storage can store databases, database instances, database management system entities, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, and / or the like to implement the functionality of the computing entity 10.

[0183] CONCLUSION

[0184] Many modifications and other embodiments of the present invention set forth herein will come to mind to one skilled in the art to which the invention pertains having the benefit of the teachings presented in the foregoing description and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

[0185] The following additional clauses are part of the specification:

[0186] 1. A method comprising:

[0187] generating, by a processing device of a quantum system controller of a quantum computer, a first set of commands configured to cause a quantum processor of the quantum computer to execute a first portion of a quantum circuit using one or more logical qubits of the quantum processor, each logical qubit of the one or more logical qubits comprising one or more data qubits;

[0188] causing, by the processing device, the first set of commands to be provided to a time-indexed command (TIC) sequencer of the quantum computer to determine timing and time-indexed execution, wherein the time-indexed execution of the first set of commands causes one or more elements of the quantum computer to execute the first portion of the quantum circuit using the one or more logical qubits;

[0189] determining, by the processing device, that input data is required prior to generating a second command set configured to cause the quantum processor to perform a second portion of the quantum circuit using one or more logical qubits of the quantum processor, wherein generating the input data comprises reading one or more ancilla qubits of the quantum processor, and the input data corresponds to a quantum state of at least one of the one or more data qubits after performing a corresponding action;

[0190] in response to determining that input data is required prior to generating the second command set, accessing, by the processing device, the input data; and

[0191] processing, by the processing device, the input data, generating the second command set based on a result of processing the input data, and causing the second command set to be provided to the TIC sequencer for time-indexed execution of the second command set within a coherence time of the one or more data qubits, the coherence time being related to the corresponding action.

[0192] 2. The method of item 1, wherein accessing the input data comprises:

[0193] determining whether the input data has been loaded by a control processing application being executed by the processing device;

[0194] in response to determining that the input data has been loaded by the control processing application, beginning to analyze the input data;

[0195] in response to determining that the input data has not been loaded by the control processing application, determining whether the input data exists in a buffer memory of the controller; and

[0196] when it is determined that the input data exists in the buffer memory, loading the input data to the control processing application.

[0197] 3. The method of item 1, wherein the coherence time of the one or more data qubits is a length of time for which a respective state of each data qubit of the one or more data qubits can be maintained.

[0198] 4. The method of item 1, wherein the controller comprises a time generator configured to provide a synchronization signal configured to cause two or more time-indexed commands in the first command set to be performed in respective time synchronization.

[0199] 5. The method of item 1, wherein the quantum processor is an atomic object confinement device, and the one or more data qubits and the one or more ancilla qubits are atomic objects confined by the atomic object confinement device.

[0200] 6. The method of item 1, wherein prior to reading an ancilla qubit of the one or more ancilla qubits, a quantum interaction is induced between the ancilla qubit and a corresponding data qubit that does not affect a quantum state of the corresponding data qubit.

[0201] 7. The method of item 1, wherein reading an ancilla qubit of the one or more ancilla qubits includes determining a quantum state of the ancilla qubit based on an optical signal corresponding to the ancilla qubit captured by one or more collection optical elements.

[0202] 8. The method of item 7, wherein the input data is stored to a buffer memory of a controller by an analog-to-digital converter that receives an electrical signal generated based on the optical signal.

[0203] 9. The method of item 1, wherein the one or more data qubits of the first logical qubit are acted on by the same type of gate at about the same time.

[0204] 10. The method of item 1, wherein execution of at least one command of the first set of commands causes at least one of (a) a voltage source to provide a control signal to at least one electrode of the quantum processor or (b) a manipulation source to provide a manipulation signal to at least one data qubit of the quantum processor.

[0205] 11. A quantum system controller, comprising:

[0206] a processing device comprising at least one first processing element;

[0207] a time-indexed command (TIC) sequencer comprising at least one second processing element; and

[0208] a plurality of driver controller elements, each driver controller element (a) configured to control operation of a respective component of a quantum computer and (b) associated with a respective buffer and a respective processing element,

[0209] wherein:

[0210] the processing device is configured to generate a first set of commands configured to cause a quantum processor of the quantum computer to execute a first portion of a quantum circuit using one or more logical qubits of the quantum processor, each logical qubit of the one or more logical qubits comprising one or more data qubits and cause the first set of commands to be provided to the TIC sequencer,

[0211] The TIC sequencer is configured to cause time-indexed execution of the first set of commands by generating, in the associated respective buffer, a time-ordered TIC queue executed by a respective one of the plurality of driver controller elements for time-indexed execution by the associated respective processing element,

[0212] wherein the time-indexed execution of the first set of commands causes the quantum computer to execute a first portion of a quantum circuit using one or more logical qubits;

[0213] The processing device is further configured to determine that input data is required prior to generating the second set of commands, wherein the second set of commands is configured to cause the quantum processor to execute at least a second portion of the quantum circuit using one or more logical qubits of the quantum processor, wherein generating the input data comprises reading one or more ancilla qubits of the quantum processor, and the input data corresponds to a quantum state of at least one of the one or more data qubits after execution of the respective action;

[0214] The processing device is further configured to, in response to determining that input data is required prior to generating the second set of commands, access the input data; and

[0215] The processing device is further configured to process the input data, generate the second set of commands based on a result of processing the input data, and cause the second set of commands to be provided to the TIC sequencer for time-indexed execution of the second set of commands by the respective driver controller element within a coherence time of the one or more data qubits, the coherence time being related to the respective action.

[0216] 12. The quantum system controller of item 11, wherein the processing device is configured to access the input data by:

[0217] determining whether the input data has been loaded by a control processing application being executed by the processing device;

[0218] in response to determining that the input data has been loaded by the control processing application, beginning to analyze the input data;

[0219] in response to determining that the input data has not been loaded by the control processing application, determining whether the input data exists in a buffer memory of the controller; and

[0220] when it is determined that the input data exists in the buffer memory, loading the input data to the control processing application.

[0221] 13. The quantum system controller of item 11, wherein the coherence time of the one or more data qubits is a length of time for which a respective state of each data qubit of the one or more data qubits can be maintained.

[0222] 14. The quantum system controller of item 11, further comprising a time generator configured to provide a synchronization signal to the TIC sequencer and to each of the plurality of driver controller elements, the synchronization signal configured to cause two or more time-indexed commands in the first command set to be executed at a corresponding time synchronization.

[0223] 15. The quantum system controller of item 11, wherein the quantum processor is an atomic object confinement device and the one or more data qubits and the one or more ancilla qubits are atomic objects confined by the atomic object confinement device.

[0224] 16. The quantum system controller of item 11, wherein prior to reading an ancilla qubit of the one or more ancilla qubits, a quantum interaction is caused between the ancilla qubit and a corresponding data qubit that does not affect a quantum state of the corresponding data qubit.

[0225] 17. The quantum system controller of item 11, wherein reading an ancilla qubit of the one or more ancilla qubits comprises determining a quantum state of the ancilla qubit based on an optical signal corresponding to the ancilla qubit captured by one or more collection optical elements of an optical collection system in communication with the quantum system controller.

[0226] 18. The quantum system controller of item 17, wherein the input data is stored to a buffer memory of the controller by an analog-to-digital converter that receives an electrical signal generated based on the optical signal.

[0227] 19. The quantum system controller of item 11, wherein the one or more data qubits of the first logical qubit are acted upon by gates of the same type at approximately the same time.

[0228] 20. The quantum system controller of item 11, wherein execution of at least one command in the first command set causes at least one of: (a) a voltage source to provide a control signal to at least one electrode of the quantum processor, or (b) a manipulation source to provide a manipulation signal to at least one data qubit of the quantum processor.

Claims

1. A method comprising: A first set of commands is generated by the processing device of the quantum system controller of the quantum computer, the first set of commands being configured to cause the quantum processor of the quantum computer to execute a first part of a quantum circuit using one or more logical qubits of the quantum processor, each of the one or more logical qubits comprising one or more data qubits; A first set of commands is provided to the time indexing command (TIC) sequencer of the quantum computer by a processing device to determine timing and time index execution, wherein the time index execution of the first set of commands causes one or more elements of the quantum computer to execute a first part of a quantum circuit using the one or more logical qubits; The processing device determines that input data is required before generating a second command set, which is configured to cause the quantum processor to execute a second part of the quantum circuit using one or more logical qubits of the quantum processor. The generated input data includes: The reading process is initiated by the processing device. A TIC is generated by a TIC sequencer, and the TIC is configured to cause the reading process to be executed. The electrical signal generated by the optical collection system is received as part of one or more auxiliary qubits of the readout quantum processor. Value processing is performed on the digital signal value corresponding to the electrical signal to determine the input data. The input data is stored in a system buffer within the memory of the quantum system controller, and The indicator indicating the availability of input data is stored in the CPU register of the processing device. The input data corresponds to at least one of one or more data qubits in a quantum state after the execution of the first part of the quantum circuit; The CPU registers of the processing device are periodically checked to determine whether an indicator indicating the availability of input data is stored in the CPU registers; In response to determining that an indicator stored in the CPU register of the processing device indicates that input data is available, the processing device moves the input data into program memory so that the input data can be used for processing by the processing device; and The input data is processed by a processing device, and a second command set is generated based on the result of the processing of the input data. The second command set is then provided to the TIC sequencer for time-indexed execution of the second command set within a coherent time of one or more data qubits, the coherent time being related to the corresponding action.

2. The method of claim 1, wherein accessing the input data comprises: Determine whether the input data has been loaded by the control processing application being executed by the processing device; Upon determining that the input data has been loaded by the control processing application, the analysis of the input data begins. In response to determining that the input data has not been loaded by the control processing application, determine whether the input data exists in the controller's buffer memory; and Once it is determined that the input data exists in the buffer memory, the input data is loaded into the control processing application.

3. The method of claim 1, wherein the coherence time of the one or more data qubits is the length of time during which the corresponding state of each of the one or more data qubits can be maintained.

4. The method according to claim 1, wherein, The controller includes a time generator configured to provide a synchronization signal, which is configured to cause two or more time-indexed commands in a first command set to be executed synchronously at corresponding times.

5. The method according to claim 1, wherein, The quantum processor is an atomic object constraint device, and the one or more data qubits and the one or more auxiliary qubits are atomic objects constrained by the atomic object constraint device.

6. The method of claim 1, wherein before reading the auxiliary qubits of the one or more auxiliary qubits, a quantum interaction is induced between the auxiliary qubits of the one or more auxiliary qubits and the corresponding data qubits, which does not affect the quantum state of the corresponding data qubits.

7. The method of claim 1, wherein reading the auxiliary qubits of the one or more auxiliary qubits comprises determining the quantum state of the auxiliary qubits of the one or more auxiliary qubits based on optical signals corresponding to the auxiliary qubits of the one or more auxiliary qubits captured by one or more collecting optical elements.

8. The method according to claim 7, wherein, The input data is stored in the controller's buffer memory by an analog-to-digital converter that receives an electrical signal generated based on the optical signal.

9. The method of claim 1, wherein execution of at least one command in the first command set results in at least one of the following: (a) a voltage source provides a control signal to at least one electrode of the quantum processor or (b) a manipulation source provides a manipulation signal to at least one data qubit of the quantum processor.

10. A quantum system controller, comprising: A processing device, comprising at least one first processing element; The Time Indexing Command (TIC) sequencer includes at least one second processing element; and Multiple driver controller elements, each driver controller element (a) configured to control the operation of a corresponding component of the quantum computer and (b) associated with a corresponding buffer and a corresponding processing element, in: The processing device is configured to generate a first command set, which is configured to cause the quantum processor of the quantum computer to execute a first portion of a quantum circuit using one or more logical qubits of the quantum processor, each logical qubit including one or more data qubits, and to provide the first command set to the TIC sequencer. The TIC sequencer is configured to induce time-indexed execution of the first command set by generating a time-ordered TIC queue in an associated corresponding buffer, to be executed by the associated corresponding processing element. The time-indexed execution of the first command set enables the quantum computer to execute the first part of the quantum circuit using one or more logical qubits; The processing device is further configured to determine input data required before generating a second command set, wherein the second command set is configured to cause the quantum processor to execute at least a second portion of the quantum circuit using one or more logical qubits of the quantum processor, wherein generating the input data includes: The reading process is initiated by the processing device. A TIC is generated by a TIC sequencer, and the TIC is configured to cause the reading process to be executed. The electrical signal generated by the optical collection system is received as part of one or more auxiliary qubits of the readout quantum processor. Value processing is performed on the digital signal value corresponding to the electrical signal to determine the input data. The input data is stored in a system buffer within the memory of the quantum system controller, and The indicator indicating the availability of input data is stored in the CPU register of the processing device. The input data corresponds to at least one of one or more data qubits in a quantum state after the execution of the first part of the quantum circuit; The processing device is also configured to periodically check the CPU registers of the processing device to determine whether an indicator indicating the availability of input data is stored in the CPU registers; The processing device is further configured to access input data in response to determining that input data is required before generating the second command set; and The processing device is also configured to process input data, generate a second command set based on the result of processing the input data, and provide the second command set to the TIC sequencer for time-indexed execution of the second command set by a corresponding driver controller element within a coherent time of one or more data qubits, the coherent time being related to the corresponding action.

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