Systems and methods for processing virtual partition cells injected into a hierarchical integrated circuit design

Abstract

Aspects described herein relate to physical verification of a design of an integrated circuit to be fabricated on a semiconductor die. One example method involves inserting a dummy partition cell into a parent cell of a layout of the design of the integrated circuit (54). Sub-cells of the parent cell have a first portion that overlaps the dummy partition cell and a second portion that is outside the dummy partition cell (54-1). The method also includes creating, by one or more processors, a cell hierarchy having the sub-cells and the dummy partition cell descended from the parent cell, where the sub-cells have multiple instances in the hierarchy of cells (54-2), and performing a design rule check run set on the parent cell based on the hierarchy (56).

Description

Technical Field

[0001] This disclosure generally relates to physical verification systems. Specifically, this disclosure relates to systems and methods for processing virtual partitioning cells injected into hierarchical integrated circuit designs. Background Technology

[0002] Physical verification is typically a process that uses electronic design automation (EDA) software tools to verify integrated circuit (IC) layout designs to ensure correct electrical and logic functionality and manufacturability. Physical verification involves Design Rule Check (DRC), Layout and Schematic (LVS), Antenna Check, and Electrical Rule Check (ERC).

[0003] The design step that generates IC placement is physical design. To manage the complexity of Very Large Scale Integration (VLSI) circuitry, a hierarchical approach to physical design has been implemented. In addition to the placement of standard cells, hierarchical physical design typically decomposes the design into blocks based on logical and physical layers. A block is essentially a large cell containing sub-cells. Hierarchical verification tools can leverage the hierarchical structure of the design to efficiently process it. Model data can represent the layout geometry used to implement the circuitry associated with each cell. In hierarchical verification, model data can represent unresolved geometry data for each cell in the hierarchical structure and can be sent to the cell's parent cell for resolution. If some DRC (Digital Curve Controller) run commands involve comparisons with other geometry data that is not available for that cell, the geometry data may not be resolvable in a sub-cell. Therefore, the unresolved geometry data can be sent to the parent cell for resolution. In at least some hierarchical verifications, all cells in the design are processed from bottom to top in this hierarchical manner.

[0004] However, design layering in the design process may not be sufficient to meet the increasingly larger designs and faster turnaround times (TAT) desired by designers. Computational resources for larger designs have grown to hundreds or thousands of central processing units (CPUs) through threaded and distributed processing for faster TAT. Physical verification tools can inject virtual cells into partitioned large cells in the IC layout for additional layering, reducing memory footprint and improving scalability with threaded and distributed processing, potentially enabling even faster TAT. Summary of the Invention

[0005] This disclosure generally relates to physical verification systems. Specifically, this disclosure relates to systems and methods for processing virtual partitioning cells injected into a layered integrated circuit design.

[0006] An example method includes: inserting virtual partition cells into a parent cell of a layout of an integrated circuit design, wherein child cells of the parent cell have a first portion overlapping the virtual partition cells and a second portion outside the virtual partition cells; creating a cell hierarchy by one or more processors, the cell hierarchy having child cells and virtual partition cells descending from the parent cell, wherein the child cells have multiple instances in the cell hierarchy; and performing a design rule check run set on the parent cell based on the hierarchy.

[0007] An example device includes a memory and one or more processors coupled to the memory. The memory and the one or more processors can be configured to: insert virtual partition cells in a parent cell of an integrated circuit design layout, wherein child cells of the parent cell have a first portion overlapping the virtual partition cells and a second portion outside the virtual partition cells; create a cell hierarchy with child cells and virtual partition cells descending from the parent cell, wherein the child cells have multiple instances in the cell hierarchy; and perform a design rule check run set on the parent cell based on the hierarchy.

[0008] One aspect includes a non-transient computer-readable medium storing instructions that cause a device to: insert a virtual partition cell in a parent cell of an integrated circuit design layout, the child cells of the parent cell having a first portion overlapping the virtual partition cell and a second portion outside the virtual partition cell; create a cell hierarchy having child cells and virtual partition cells descending from the parent cell, wherein the child cells have multiple instances in the cell hierarchy; and perform a design rule check run set on the parent cell based on the hierarchy. Attached Figure Description

[0009] This disclosure will be more fully understood from the following detailed description and the accompanying drawings, which illustrate the examples described herein. The drawings are provided to illustrate and understand the examples described herein, and are not intended to limit the scope of the invention to these specific examples. Furthermore, the drawings are not necessarily drawn to scale.

[0010] Figure 1 This is a flowchart of a method for physical verification analysis according to an exemplary embodiment of the present disclosure.

[0011] Figure 2 A parent cell is depicted in an exemplary embodiment of the present invention, comprising sub-cells in an integrated circuit design.

[0012] Figure 3 The example embodiments shown correspond to the present disclosure are illustrated. Figure 2 A hierarchical tree.

[0013] Figure 4 An example embodiment of the present disclosure is shown in Figure 2Insert virtual partition units into the parent unit.

[0014] Figure 5 An example embodiment based on this disclosure is shown. Figure 4 The creation of a logical hierarchical structure for inserting virtual partition units.

[0015] Figure 6 An exclusion region is shown where model data is sent to and processed by a parent unit according to an example embodiment of this disclosure.

[0016] Figure 7 An example embodiment of the present disclosure illustrates the assignment of an identifier to... Figure 5 A simplified part of the network within the hierarchical structure.

[0017] Figure 8 An aspect of reslicing the results to a virtual partition cell is illustrated according to an example embodiment of this disclosure.

[0018] Figure 9 A set of example processes for converting and verifying design data and instructions used during the design, inspection, and fabrication of integrated circuits on semiconductor dies, representing integrated circuits in which the examples described herein can be implemented, are illustrated.

[0019] Figure 10 A diagram depicts an example computer system in which the examples described in this article may operate. Detailed Implementation

[0020] The aspects described herein relate to the physical verification of designs for integrated circuits to be fabricated on semiconductor dies. Examples described herein provide a system and method for processing injected virtual partitioning cells (also referred to herein as virtual shearing cells) relative to overlapping sub-cells (e.g., at the same level). In one example, the system and method include growing or increasing the boundaries or extent of the virtual partitioning cells as the enclosed sub-cells grow, and excluding virtual partitioning cells on the model data sent to the parent cell for resolution. In one example, the system and method also include flattening computation consistent with both the parent cell and its virtual partitioning cells. The system and method can efficiently partition the workload of a large parent cell into its virtual partitioning cells and can enable virtual partitioning cells and the parent cell to work together to deliver the benefits of reduced memory footprint and improved scalability. Therefore, some examples can achieve faster TAT in physical verification.

[0021] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and in all drawings, elements with similar structures or functions are indicated by similar reference numerals. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description of the claimed technical solution or as a limitation on the scope of the claimed technical solution. Furthermore, the examples shown do not need to possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and can be practiced in any other example, even if not so shown or explicitly described. Furthermore, the methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented in various other orders with more or fewer operations (e.g., including different serial or parallel executions of various operations). Moreover, as used in the art, various terms are used herein, and these terms are intended to include the full meaning of those terms as understood by one of ordinary skill in the art.

[0022] Figure 1 This is a flowchart of a method 50 for physical verification analysis according to an exemplary embodiment of the present disclosure. The method 50 is described below in the context of the various figures to illustrate various aspects. These figures are provided by way of example only, and those skilled in the art will readily understand the application of the method 50 in other examples.

[0023] As described in further detail below, method 50 can be implemented by one or more instruction sets stored on a non-transitory computer-readable medium, which can be one or more software modules. One or more processors of a computer system can be configured to read and execute one or more instruction sets, causing the one or more processors to perform various operations or steps of method 50. Further details are provided below. In some examples, some operations or steps of method 50 can be implemented as one or more instruction sets as one or more software modules, and other operations or steps of method 50 can be implemented as one or more other instruction sets as one or more other software modules. In some examples, different software modules can be distributed and stored on different non-transitory computer-readable media on different computer systems for execution by corresponding one or more processors of the different computer systems.

[0024] The various figures described below are described in the context of their respective figures. Figure 1 These diagrams are drawn and described to illustrate... Figure 1 Various aspects. Other example implementations can achieve different designs, different layered structures, or other different aspects.

[0025] exist Figure 1At point 52, an electronic representation of the design of the integrated circuit chip to be fabricated on a semiconductor die is obtained. The electronic representation can be in any format, such as including OASIS files or GDS files. The design includes a layout of cells, which can be logically represented in a hierarchy of these cells. Cells can represent various functional and / or logical units in the design. Cells can be, for example, layouts of static random access memory (SRAM) cells, buffer cells, etc. These cells indicate the layout of devices within the corresponding cells and the connectivity of the devices. Cells can be, for example, any standard library cells and / or non-standard (e.g., user-defined) cells. The layout of the design can have any number of cell instances of cell types. For example, two or more instances of the same type of buffer cell can be included in the design, and each of these instances of the same type of buffer cell is a separate cell for analysis. Any number of cells and any hierarchy can be implemented. For example, 10 to 20 levels of hierarchy can be implemented in the design. Overlap between sub-cells is unavoidable in the design. Any number of sub-cells can overlap with one or more other sub-cells, and any number of sub-cells can not overlap with any other sub-cells.

[0026] Figure 2 A parent unit 100 is depicted according to an example embodiment of the present disclosure, comprising sub-units in an integrated circuit design. The parent unit 100 includes sub-units 102, 104, 106, 108, 110, and 112 in the integrated circuit design (e.g., the original design of the integrated circuit). As shown, each sub-unit of 102, 106, 108, and 110 does not overlap with any other sub-unit, and sub-units 104 and 112 overlap each other. Figure 2 It shows Figure 2 The cell boundaries or extents of the units are defined, and for clarity, the actual circuit and physical device layouts are omitted. For example, the boundary for cell 110 is defined by... Figure 2 The line boundary of the rectangle used for unit 110 is shown in the figure.

[0027] Initially, each subunit 102, 104, 106, 108, 110, and 112 is at the same logical level in the hierarchical structure. Logically, each subunit 102, 104, 106, 108, 110, and 112 is a direct descendant (or child) of the parent unit 100 that includes subunits 102, 104, 106, 108, 110, and 112. Figure 3 An example embodiment of the present disclosure is shown with Figure 2 The corresponding hierarchical tree.

[0028] exist Figure 1At point 54, virtual partition cells are inserted or injected into the integrated circuit design. Virtual partition cells allow the identification of physical and / or connection relationships between different sub-cells, where the processing of virtual partition cells can reduce memory usage and improve scalability. The insertion of virtual partition cells does not insert additional devices, connections, or other features into the integrated circuit design, but rather inserts logical constructs into the design that indicate the extent or boundaries of the virtual partition cells to enable the insertion of additional layers of layering as described below. The insertion of virtual partition cells can be achieved through any suitable technique. For example, virtual partition cells can be inserted in a manner that avoids certain objects (also known as barriers). Barriers can be regions within a layout that cannot be divided into smaller pieces when the cell layout is partitioned, which may result in performance penalties during design rule checking operations. For example, densely packed areas of shape in a cell layout can be considered objects that can be avoided when inserting virtual partition cells. Other techniques for inserting virtual partition cells may not involve barrier considerations. For example, rows of virtual partition cells can be injected as a way to partition the layout to improve design rule checking performance. In some cases, one or more virtual partition cells may be added that overlap with or completely contain one or more other cells due to the number and location of other cells in the layout.

[0029] Each virtual partition unit inserts a logical hierarchical level within the hierarchical structure of the parent unit into which it is inserted. Any and every unit contained in or overlapping with the inserted virtual partition unit in any part becomes a child unit of that corresponding virtual partition unit. Like child units, in practice, overlap between one or more virtual partition units and one or more other child units may be unavoidable in the design.

[0030] Figure 4 It shows in Figure 2 Virtual partition units 202 and 204 are inserted into the parent unit 100. For example... Figure 4 As shown, virtual partition unit 202 includes subunit 110 and overlaps with corresponding portions of subunits 102 and 104. The size and position of virtual partition units 202 and 204 in parent unit 100 are merely examples to provide knowledge and understanding of the aspects described herein, and do not limit the scope of this disclosure to these specific examples. Virtual partition unit 204 includes subunit 112 and partially overlaps with subunit 104 (this overlap differs from the overlap of virtual partition unit 202).

[0031] Logical hierarchies are created by inserting 54 virtual partition units. In the hierarchical structure, sub-units with portions overlapping the virtual partition units and portions outside the virtual partition units are copied within the hierarchical structure, such as... Figure 1As shown in 54-1. As shown in 54-2, the same identifier (e.g., the same identifier number) is applied to the replicated subunits that are copied in the hierarchical structure.

[0032] When creating a logical hierarchy, a virtual partition unit becomes a direct descendant or child of the parent unit into which it is inserted. If a child unit has a portion within the boundaries or range of a virtual partition unit (e.g., overlapping with the virtual partition unit), then the child unit is a direct descendant or child of the given virtual partition unit. Additionally, if any part of the child unit is not outside the virtual partition unit, the child unit is removed as a direct descendant of the parent unit, and thus, if the child unit is completely contained within the virtual partition unit, the virtual partition unit increases the hierarchical level between the child unit and the parent unit (making the child unit a grandchild unit). As indicated by these guidelines, if a child unit has a portion overlapping with a virtual partition unit and a portion outside the virtual partition unit but still within its direct ancestor or parent unit, then the child unit is copied, having one instance as a direct descendant or child of the virtual partition unit and another instance as a direct descendant or child of the direct ancestor or parent unit. In other words, a first instance of the child unit may be in the first layer of the hierarchical structure, while a second instance of the child unit may be in the second layer of the hierarchical structure, which is lower than the first layer.

[0033] Figure 5 It shows the basis Figure 4 The logical hierarchical structure is created by inserting virtual partition units 202 and 204. For example... Figure 4 and 5As shown, virtual partition units 202 and 204 are direct descendants or children of parent unit 100. Subunits 102, 104, and 110 have corresponding portions within virtual partition unit 202 and are direct descendants or children of virtual partition unit 202. Subunits 104 and 112 have corresponding portions within virtual partition unit 204 and are direct descendants or children of virtual partition unit 204. Subunits 110 and 112 are completely contained within virtual partition units 202 and 204, respectively, and therefore, subunits 110 and 112 are removed from being direct descendants of parent unit 100. In the example shown, subunit 102 has a portion within virtual partition unit 202 and a portion within parent unit 100 that is not within virtual partition unit 202. Therefore, subunit 102 has two (replicated) instances 302 and 304 in the hierarchical structure, where instance 302 is a direct descendant or child of parent unit 100, and instance 304 is a direct descendant or child of virtual partition unit 202. Similarly, subunit 104 has a portion within virtual partition unit 202, a portion within virtual partition unit 204, and a portion within parent unit 100 that is not within virtual partition unit 202 or virtual partition unit 204. Therefore, subunit 104 has three (replicated) instances 306, 308, and 310 in the hierarchical structure, where instance 306 is a direct descendant or child of parent unit 100, instance 308 is a direct descendant or child of virtual partition unit 202, and instance 310 is a direct descendant or child of virtual partition unit 204.

[0034] For each subunit, as shown in 54-2, multiple instances of the corresponding subunit within the hierarchical structure have the same identifier. For example, refer to... Figure 5 The system provides a unique identifier to multiple instances 302 and 304 of subunit 102 that is identical to other units within parent unit 100, and provides a unique identifier to multiple instances 306, 308, and 310 of subunit 104 that is identical to other units within parent unit 100. Alternatively, a unique identifier can be provided for each other subunit that has a single instance.

[0035] Return to reference Figure 1At point 56, a Design Rule Check (DRC) run set is executed on the design with inserted virtual partition cells. The DRC run set can be a set of commands (also called Design Rule Check commands) executed to detect violations of design rules in the design. Through this execution, intermediate layers can be derived from the layout of various cells, and each sub-cell can have boundaries or extents that grow or shrink based on the execution of these commands. For each virtual partition cell, the corresponding virtual partition cell can grow or shrink based on any sub-cell completely within or surrounded by the virtual partition cell. At point 56-1, the size of the virtual partition cell is adjusted as the size of the original sub-cells contained within the virtual partition cell is adjusted. Any sub-cells having a portion within the extent or boundary of the virtual partition cell and another portion outside the extent or boundary of the virtual partition cell are not used to grow or shrink that virtual partition cell. (See reference...) Figure 4 Virtual partition unit 202 can grow or shrink based on whether subunit 110 grows or shrinks, regardless of whether subunits 102 and 104 grow or shrink. Similarly, virtual partition unit 204 can grow or shrink based on whether subunit 112 grows or shrinks, regardless of whether subunit 104 grows or shrinks.

[0036] The performance of a DRC run set can be a distributed, bottom-up process. For example, a DRC run set can be executed against the lowest unit in the hierarchy, followed by the next lowest unit in the hierarchy, and so on, until the parent unit is executed. Units without child-parent or other descendant / ancestor relationships can be processed independently, which allows for concurrent processing of units. Therefore, non-overlapping virtual partition units can be processed simultaneously. In other words, virtual partition unit 202 and virtual partition unit 204 do not overlap. Since the processing of one virtual partition unit (e.g., virtual partition unit 202) does not depend on the result of processing another virtual partition unit (e.g., virtual partition unit 204), non-overlapping virtual partition units 202 and 204 can be processed simultaneously. Therefore, virtual partition unit 202 (including region 404 of unit 104) can be processed simultaneously with virtual partition unit 204 (e.g., including region 406 of unit 104).

[0037] Results from the processing unit can be sent to the direct ancestor unit to incorporate these results into the ancestor unit's processing. In other words, once a DRC run set has been executed on a child unit, the results of the DRC run set for the child unit can be provided to execute a DRC run set on the parent unit. Therefore, the geometry data for the parent unit can be used to parse specific DRC run set commands based on the results of the DRC run set for the child unit.

[0038] For any virtual partition cell that overlaps with a sub-cell and has a portion outside the virtual partition cell, at 56-2, the model data for the portion of the sub-cell outside the virtual partition cell is excluded from the virtual partition cell during processing, and at 56-3, the excluded model data is sent to a direct ancestor cell (e.g., a parent cell) for processing during the processing of the direct ancestor cell. This allows virtual partition cells to be processed independently, and the results of processing the virtual partition cell are sent to the parent cell of the virtual partition cell, which can lead to a reduction in the model data for the parent cell, which can further reduce the resources used for processing the parent cell, such as memory. Whether a sub-cell has a portion overlapping with a virtual partition cell and whether it has another portion outside the virtual partition cell can be determined based on instances of sub-cells in the hierarchy. Sub-cells that satisfy this condition have instances that are descendants of the virtual partition cell and at least one other instance in the hierarchy that is not a descendant of the virtual partition cell.

[0039] Figure 6 The diagram illustrates the areas where model data is sent to and processed by the parent unit 100. Region 402 is the area where sub-unit 102 overlaps with virtual partition unit 202, with the remainder of sub-unit 102 outside virtual partition unit 202. Region 404 is the area where sub-unit 104 overlaps with virtual partition unit 202, with the remainder of sub-unit 104 outside virtual partition unit 202. Region 406 is the area where sub-unit 104 overlaps with virtual partition unit 204, with the remainder of sub-unit 104 outside virtual partition unit 204. Model data of sub-unit 102 corresponding to the overlapping region 402 is excluded from processing by the parent unit 100, and model data of sub-unit 102 corresponding to the remaining non-overlapping region (excluding region 402 and outside virtual partition unit 202) is excluded from processing by virtual partition unit 202 and can be sent to the parent unit 100 for processing by the parent unit 100. The model data of subunit 104 corresponding to region 404 is excluded from processing by parent unit 100, and the model data of subunit 104 corresponding to region 406 is also excluded from processing by parent unit 100. The model data of subunits 102 and 104 corresponding to the corresponding remaining regions (excluding regions 404 and 406 respectively and outside of virtual partition units 202 and 204) are excluded from processing by the corresponding virtual partition units 202 and 204, and can be sent to parent unit 100 for processing by parent unit 100.

[0040] Return to reference Figure 1At point 58, connectivity analysis of the design is performed. Network connectivity within a cell and between cells is identified. Each network is then assigned a unique identifier (also referred to herein as an identifier). Each cell is assigned a network identifier. Networks within a parent cell and its included sub-cells that do not have connections outside the parent cell are given a unique flat network identifier (e.g., an identifier number) within the parent cell. The flat network is calculated by offsetting the number of networks in the sub-cells of the next sub-cell.

[0041] Figure 7 As an example, assigning an identifier to Figure 5 The simplified portion of the hierarchical structure represents aspects of the network. Networks in the parent unit 100 are identified and assigned, while networks in the first instance of the child unit are identified and assigned using cumulative offsets. Although not shown, each unit may have an internal offset within the unit for assigning numerical identifiers to the networks.

[0042] Parent unit 100 is shown having M1 networks (e.g., networks 1 to M1). Parent unit 100 has no cumulative offset or a cumulative offset of 0. A first instance 302 of child unit 102 is shown having M2 networks (e.g., networks 1 to M2) with a cumulative offset of M1. Therefore, the networks of the first instance 302 of child unit 102 are assigned numeric identifiers from network (M1+1) to network (M1+M2). A first instance 306 of child unit 104 is shown having M3 networks (e.g., networks 1 to M3) with a cumulative offset of (M1+M2). Therefore, the networks of the first instance 306 of child unit 104 are assigned numeric identifiers from network (M1+M2+1) to network (M1+M2+M3). A first instance of child unit 106 is shown having M4 networks (e.g., networks 1 to M4) with a cumulative offset of (M1+M2+M3). Therefore, the network of the first instance of sub-unit 106 is assigned the numerical identifier from network (M1+M2+M3+1) to network (M1+M2+M3+M4). This continues for the corresponding first instance of the unit, which can be summarized as shown in sub-unit 110. The cumulative offset of sub-unit 110 is Where j is the number of previous units being analyzed, such that the sum is the accumulation of the number of networks of the previous units being analyzed. Subunit 110 has M (j+1) A network, such that the assigned numeric identifier is a network. To the Internet Accumulated offsets can be maintained in a lookup table that associates each accumulated offset with a corresponding instance of the cell. Although virtual partition cell 202 is not shown as including a network, a virtual partition cell may include one or more networks.

[0043] Subsequent instances of a subunit, such as those descending from a virtual partition unit, can refer to the first instance of the corresponding subunit. Therefore, each instance of a given subunit can have the same cumulative offset in the lookup table. As described above, determining which instances are subsequent instances can be based on the identifiers of multiple instances of the subunits defined in the hierarchical structure of 54.

[0044] Figure 7 A second instance 304 of a sub-unit 102 with M2 networks (as described above) is shown, and the cumulative offset is the cumulative offset (Offset_302) of the first instance 302. Similarly, Figure 7 A second instance 308 (as described above) of a sub-unit 104 with M3 networks is shown, and the cumulative offset is the cumulative offset (Offset_306) of the first instance 306. Therefore, the assigned numeric identifiers of the corresponding networks in multiple instances of the same sub-unit are the same in multiple instances of the same sub-unit in the hierarchical structure.

[0045] The identifier for the flattened net used to descend from the virtual partition cell can be resolved in two passes. The flattened net can be calculated, and the replicated sub-cells descending from the virtual partition cell can be skipped in the first pass. In the second pass, the flattened net offset of the replicated sub-cell is obtained through the same instance identifier derived from the parent cell, thus achieving the same flattened net number in either the virtual partition cell or the parent cell. The following pseudocode illustrates these passes:

[0046] For the flat network of virtual partition unit C:

[0047]

[0048] The sub-cells of cell P are sorted using virtual cut units before non-virtual cut units. Numerical identifiers are assigned in this way to result in a continuous network of numbers contained in the parent cell, sub-cells, and virtual partition cells.

[0049] It can also determine network connectivity between units. (Reference) Figure 7 Example connection 502 is shown between network 1 of subunit 102 (e.g., numeric identifier network (M1+M2+M3+1)) and network 2 of parent unit 100 (e.g., numeric identifier network 2). Other connections between networks of different units can be similarly determined. The connection of a subunit to multiple instances in the hierarchical structure can be associated with a first instance of the subunit, and subsequent instances can refer to (e.g.) the first instance.

[0050] At point 60, after executing the DRC run set, the results of the DRC from the parent unit are re-sliced ​​into virtual partition units. For example, refer to... Figure 8The diagram illustrates sub-cell data 602 contained within virtual partition unit 202. As previously described, sub-cell 102 (e.g., corresponding to sub-cell data 702) has a portion overlapping with virtual partition unit 202 and a portion outside of virtual partition unit 202. Proximity flag 604 marks sub-cell data 602 as proximate to sub-cell data 702. After a check is performed in the DRC run set, the results in parent unit 100 are recut and / or repartitioned to the corresponding virtual partition unit 202 and the virtual partition unit 202 range. For example, the geometric data used to parse the DRC run set command of the parent unit may be proximate to the cell associated with sub-cell data 602. Therefore, due to this proximity, the results of the DRC run set for sub-cell data 702 can be provided to (e.g., recut or repartitioned to) virtual partition unit 202 for use when performing the DRC run set for sub-cell 202. This result can be recut into any number of non-overlapping virtual partition units. In other words, performing the DRC run set may involve performing a chain of DRC commands. A portion of the result of a command executed against the parent unit can be resliced ​​into a virtual partition unit. Therefore, executing a subsequence of DRC commands against a virtual partition unit can be based on a portion of the result of a previous command executed against the parent unit.

[0051] By performing the above operations, the virtual partition unit and the parent unit can jointly complete the check of the parent unit, and the memory consumption can be greatly reduced. Virtual partition units can run simultaneously to improve scalability.

[0052] Operations 54-60 can be performed multiple times. For example, different iterations can achieve different virtual partition units. Operations 54-60 can be repeated for each set of commands to be executed in a DRC. Figure 1 As shown in section 62, it is determined whether there are any more DRC run set commands to be executed. If yes, method 50 loops to 54, and if no, the method can terminate or return. In some examples, the connectivity analysis in section 58 can be omitted during iteration.

[0053] Information gathered from physical verification allows for the resolution and resolution of any violations of design rules and / or connectivity issues within the design. Iterative physical verification can be performed based on any resolved design. The design can then be analyzed, as described below.

[0054] Those skilled in the art will readily understand the various data structures that can be implemented in the above process. For example, classes can define parent units, virtual partition units, and child units. Each class can indicate any logical increment and / or decrement to indicate a logical hierarchical structure. Each instance of an object of a class can include data indicating boundaries or extents in the layout, can include networks in the corresponding unit, or other information or data. Different data structures and / or modified data structures can be used in different examples. Furthermore, those skilled in the art will readily understand the various modifications to the logical and / or mathematical expressions of the examples described herein. Other examples consider such modifications.

[0055] Figure 9 This describes a set of example processes 900 used during the design, inspection, and fabrication of integrated circuits on semiconductor dies to convert and inspect design data and instructions representing integrated circuits. Each of these processes can be constructed and enabled as multiple modules or operations. The term "EDA" stands for Electronic Design Automation. At 910, these processes begin by creating product ideas using information provided by the designer; at 912, the information is converted to create an integrated circuit using a set of EDA processes. When the design is complete, at 934, the design is tape-out, which occurs when patterns (e.g., geometric patterns) for the integrated circuit are sent to a manufacturing facility to create a mask set, which is then used to fabricate the integrated circuit. After tape-out, at 936, the integrated circuit is fabricated on the semiconductor die, and at 938, packaging and assembly processes are performed to produce the finished integrated circuit (often also referred to as a "chip" or "integrated circuit chip") at 940.

[0056] The specifications for circuits or electronic structures can range from low-level transistor material placement to high-level description languages. High-level representations can be used to design circuits and systems using hardware description languages ​​(HDLs) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be translated into logic-level register-transfer-level (RTL) descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower-level representation, as a more detailed description, adds more useful details to the design description, such as, for example, more details about the modules included in that description. More detailed lower-level representations can be computer-generated, exported from design libraries, or created by another design automation process. An example of a specification language used to specify more detailed lower-level representations is SPICE, used for detailed descriptions of circuits with many analog components. Descriptions at each representation level are enabled by the corresponding tools for that layer (e.g., formal verification tools). The design process can use... Figure 9 The sequence shown. The described process can be implemented using EDA products (or tools).

[0057] During system design, at point 914, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0058] During logic design and functional verification, at point 916, modules or components in the circuit are specified using one or more description languages, and specifications are checked against functional accuracy. For example, components of the circuit can be verified to generate outputs that match the specification requirements of the designed circuit or system. Functional verification can be performed using simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some examples, a specific system of components, referred to as a simulator or prototype system, is used to accelerate functional verification.

[0059] During synthesis and design testing, at point 918, the HDL code is converted into a netlist. In some examples, the netlist can be a graphical structure where the edges of the graphical structure represent components of the circuit, and the nodes of the graphical structure represent how the components are interconnected. Both HDL code and netlist are layered artifacts that can be used by EDA products to verify that the integrated circuit performs as specified in the design during manufacturing. The netlist can be optimized for a target semiconductor manufacturing technology. Furthermore, the finished integrated circuit can be tested to verify that it meets specification requirements.

[0060] During netlist verification, at 920, the netlist is checked to ensure it conforms to timing constraints and HDL code. During design planning, at 922, the overall layout plan for the integrated circuit is constructed and analyzed for timing and top-level routing.

[0061] During layout or physical implementation, at point 924, physical placement (location of circuit components such as transistors or capacitors) and routing (connection of circuit components via multiple conductors) occur, and cells can be selected from a library to enable specific logic functions. As used herein, the term "cell" can specify a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are enabled for both physical structure and simulation. Parameters such as size are specified for the selected cell (based on standard cells), and it is made accessible in a database for use in EDA products.

[0062] During analysis and extraction, at position 926, circuit functionality is verified at the placement level, allowing for improvements to the placement design. During physical verification, at position 928, the placement design is checked to ensure that manufacturing constraints are correct, such as Design Rule Check (DRC) constraints, electrical constraints, lithographic constraints, and that circuit functionality matches the HDL design specifications. Physical verification at position 928 may include... Figure 1 Method 50 for physical verification analysis. During resolution enhancement, at 930, the geometry of the layout is transformed to improve how the circuit design is manufactured.

[0063] During tape-out, data is created to generate a photomask (if appropriate, after applying lithographic enhancement). During mask data preparation, at 932, the tape-out data is used to generate a photomask for producing the finished integrated circuit.

[0064] Computer systems (such as) Figure 10 The storage subsystem of the computer system 1000 can be used to store programs and data structures used by some or all of the EDA products described herein, as well as products for developing units for the library and for physical and logical designs for using the library.

[0065] Figure 10 An example of a computer system 1000 is shown, within which a set of instructions can be executed to cause the computer system to perform any or more of the methods discussed herein (including...). Figure 1 Method 50 and / or Figure 9 Method 928). In some implementations, the computer system may be connected (e.g., networked) to other machines or computer systems in a local area network (LAN), intranet, extranet, and / or the Internet. The computer system may operate as a server or client computer system in a client-server network environment, as a peer-to-peer computer system in a peer-to-peer (or distributed) network environment, or as a server or client computer system in a cloud computing infrastructure or environment.

[0066] A computer system can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a web device, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) specifying actions to be taken by the computer system. Furthermore, while a single computer system is shown, the term computer system should also be understood to include any collection of computer systems that individually or jointly execute a set (or more) of instructions to perform any one or more methods discussed herein.

[0067] Example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1018, which communicate with each other via a bus 1030. The main memory 1004 includes a non-transitory computer-readable medium or a non-transitory computer-readable medium. The main memory 1004 (e.g., a non-transitory computer-readable medium) may store one or more sets of instructions 1026 that, when executed by the processing device 1002, cause the processing device 1002 to perform some or all of the operations, steps, methods, and processes described herein, including... Figure 1 Method 50 and / or Figure 9 928.

[0068] Processing device 1002 represents one or more processors such as a microprocessor, central processing unit, etc. More specifically, processing device 1002 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, a processor implementing other instruction sets, or (multiple) processors implementing combinations of instruction sets, or includes CISC microprocessors, RISC microprocessors, VLIW microprocessors, processors implementing other instruction sets, or (multiple) processors implementing combinations of instruction sets. Processing device 1002 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1002 may be configured to execute instructions 1026 for performing some or all of the operations, steps, methods, and processes described herein, including Figure 1 Method 50 and / or Figure 9 928.

[0069] The computer system 1000 may further include a network interface device 1008 for communication via a network 1020. The computer system 1000 may also include a video display unit 1010 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generation device 1016 (e.g., a speaker), a video processing unit 1028, and an audio processing unit 1032.

[0070] Data storage device 1018 may include machine-readable storage medium 1024 (e.g., non-transient computer-readable medium) on which one or more instruction sets 1026 or software are stored to implement any one or more methods or functions described herein (including...). Figure 1 Method 50 and / or Figure 9 Method 928). During the execution of instruction 1026 by computer system 1000, instruction 1026 may also reside wholly or at least partially in main memory 1004 and / or processing device 1002, which also includes machine-readable storage media.

[0071] In some implementations, instruction 1026 includes instructions for implementing the functions described above. Although machine-readable storage medium 1024 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more instruction sets. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding instruction sets for execution by a computer system and causing the computer system and processing device 1002 to perform any one or more of the methods described above. Therefore, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0072] Certain parts described in detail above are presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most efficient way for those skilled in the art of data processing to communicate the substance of their work to others skilled in the art. An algorithm can be a sequence of operations that leads to a desired result. These operations require physical manipulation of physical quantities. These quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, items, numbers, etc.

[0073] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. Unless otherwise stated, as is apparent from this disclosure, it should be understood that throughout the specification, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data, expressed as physical (electronic) quantities within the registers and memories of the computer system, into other data, similarly expressed as physical quantities within the computer system's memory or registers or other such information storage devices.

[0074] This disclosure also relates to an apparatus for performing the operations described herein. The apparatus may be specifically constructed for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0075] The algorithms and demonstrations presented herein do not inherently relate to any particular computer or other device. Various other systems can be used in conjunction with the program based on the teachings herein, or it may prove convenient to construct more specialized devices to perform the method. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of the invention described herein can be implemented using a variety of programming languages.

[0076] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media include any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media include machine-readable (e.g., computer-readable) storage media, such as read-only memory (ROM), random access memory (RAM), disk storage media, optical storage media, flash memory devices, etc.

[0077] In the foregoing disclosure, implementations of this disclosure have been described with reference to specific example implementations thereof. It will be apparent that various modifications may be made thereto without departing from the broader scope of implementation of this disclosure as set forth in the following claims. Where elements are referred to in the singular in this disclosure, more than one element may be depicted in the drawings, and the same elements are labeled with the same numerals. Therefore, this disclosure and the drawings are to be considered illustrative rather than restrictive.

Claims

1. A method comprising: A virtual partition cell is inserted into the parent cell of the layout of the integrated circuit design, wherein the child cell of the parent cell has a first portion overlapping the virtual partition cell and a second portion outside the virtual partition cell; A cell hierarchy is created by one or more processors, having the sub-units and the virtual partition units descending from the parent unit, wherein the sub-units have multiple instances in the cell hierarchy, wherein a first instance of the multiple instances of the sub-units is in a first layer of the hierarchy, wherein a second instance of the multiple instances of the sub-units is in a second layer of the hierarchy, the second layer being lower than the first layer in the hierarchy; Based on the hierarchical structure, a design rule check run set is performed on the parent unit; as well as The connectivity analysis of the parent unit is performed by assigning network identifiers to the sub-units and the virtual partition units based on the hierarchical structure.

2. The method of claim 1, wherein the plurality of instances of the subunit are associated with the same identification number.

3. The method of claim 1, wherein the design rule check run set for the virtual partition unit is performed by excluding the second portion of the subunit that is processed outside the virtual partition unit.

4. The method of claim 1, further comprising: The size of the virtual partition unit is adjusted based on the size of another sub-unit contained within the adjusted virtual partition unit.

5. The method of claim 1, wherein the second instance descends from the virtual partition unit in the hierarchical structure.

6. The method of claim 1, wherein the second instance is associated with the first portion of the sub-unit, the first portion of the sub-unit overlapping the virtual partition unit, and wherein the first instance is associated with the second portion of the sub-unit, the second portion of the sub-unit being outside the virtual partition unit.

7. The method of claim 1, wherein the second instance in the hierarchical structure has a network whose identifier is assigned by reference to the first instance of the sub-unit in the hierarchical structure.

8. The method of claim 1, wherein virtual partition units are ordered before non-virtual partition units in the hierarchical structure.

9. The method of claim 1, further comprising: Another virtual partition unit is inserted into the parent unit of the layout, wherein: The virtual partition unit and the other virtual partition unit do not overlap in the layout of the design; and The design rule check run set is executed simultaneously, at least partially, for the virtual partition unit and the other virtual partition unit.

10. The method of claim 1, wherein the design rule check run set for the design rule check command is executed in order from the lowest unit in the hierarchy to the highest unit in the hierarchy.

11. The method of claim 1, wherein executing the design rule check run set for the design rule check command comprises: Execute the design rule check command for the sub-unit; as well as After executing the design rule check command for the sub-unit, the design rule check command is executed for the parent unit.

12. The method of claim 1, wherein performing the design rule check on the run set comprises: Execute the first design rule check command on the parent unit to generate model data; as well as Based on the model data generated by executing the first design rule check command on the parent unit, a second design rule check command is executed on the virtual partition unit.

13. An apparatus comprising: Memory; as well as One or more processors coupled to the memory, wherein the memory and the one or more processors are configured to: A virtual partition cell is inserted into the parent cell of the layout of the integrated circuit design, wherein the child cell of the parent cell has a first portion overlapping the virtual partition cell and a second portion outside the virtual partition cell; Create a unit hierarchical structure having the sub-units and the virtual partition units descending from the parent unit, wherein the sub-units have multiple instances in the unit hierarchical structure, wherein a first instance of the multiple instances of the sub-units is in a first layer of the hierarchy, wherein a second instance of the multiple instances of the sub-units is in a second layer of the hierarchy, the second layer being lower than the first layer in the hierarchy; Based on the hierarchical structure, a design rule check run set is performed on the parent unit; as well as The connectivity analysis of the parent unit is performed by assigning network identifiers to the sub-units and the virtual partition units based on the hierarchical structure.

14. The apparatus of claim 13, wherein the plurality of instances of the subunit are associated with the same identification number.

15. The apparatus of claim 13, wherein the design rule check run set for the virtual partition unit is performed by excluding a second portion of the subunits that are processed outside the virtual partition unit.

16. The apparatus of claim 13, wherein the memory and the one or more processors are further configured to adjust the size of the virtual partition unit based on the size of another sub-unit contained in the adjusted virtual partition unit.

17. The apparatus of claim 13, wherein the memory and the one or more processors are configured to perform the design rule check run set in such a way as: Execute a first design rule check command on the parent unit to generate model data; and Based on the model data generated by executing the first design rule check command on the parent unit, the second design rule check command is executed on the virtual partition unit.

18. A non-transient computer-readable medium storing instructions that cause a device to perform the following operations: A virtual partition cell is inserted into the parent cell of the layout of the integrated circuit design, wherein the child cell of the parent cell has a first portion overlapping the virtual partition cell and a second portion outside the virtual partition cell; Create a unit hierarchical structure having the sub-units and the virtual partition units descending from the parent unit, wherein the sub-units have multiple instances in the unit hierarchical structure, wherein a first instance of the multiple instances of the sub-units is in a first layer of the hierarchy, wherein a second instance of the multiple instances of the sub-units is in a second layer of the hierarchy, the second layer being lower than the first layer in the hierarchy; Based on the hierarchical structure, a design rule check run set is performed on the parent unit; as well as The connectivity analysis of the parent unit is performed by assigning network identifiers to the sub-units and the virtual partition units based on the hierarchical structure.

Images