Shift register unit and driving method thereof, gate driving circuit and display device

Abstract

A shift register unit and its driving method, gate driving circuit, and display device are disclosed. The shift register unit includes: an input circuit (110), a first control circuit (120), an output circuit (140), an output noise reduction circuit (130), and a reset circuit (150); the input circuit (110) is connected to an input terminal (IN) and configured to control the level of a first node (P1) in response to an input signal input to the input terminal (IN); the first control circuit (120) is connected to the first node (P1), a second node (P2), and a first clock signal terminal (CK), and configured to control the level of the second node (P2) under the control of the level of the first node (P1) and the first clock signal provided by the first clock signal terminal (CK). The output circuit (140) is connected to the output terminal (OUT) and configured to output an output signal at the output terminal (OUT) under the control of the level of the second node (P2); the output noise reduction circuit (130) is connected to the output terminal (OUT) and configured to reduce noise at the output terminal (OUT) under the control of the level of the first node (P1); the reset circuit (150) is connected to the total reset terminal (RST) and the first voltage terminal (VGH) and configured to turn off the output noise reduction circuit (130) in response to the total reset signal provided by the total reset terminal (RST). The total reset signal is an invalid level in the first operation phase and includes at least one valid level in the second operation phase. The shift register unit can avoid the output reset and noise reduction capability of the output noise reduction circuit being affected by the transistor in the output noise reduction circuit (130) being continuously turned on for a long time, thereby extending the service life of the shift register unit and improving the display quality of the display panel.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a shift register unit and its driving method, a gate driving circuit, and a display device. Background Technology

[0002] In the field of display technology, pixel arrays in display panels, such as liquid crystal displays (LCDs) or organic light-emitting diode (OLED) displays, typically include multiple rows of gate scan signal lines and multiple columns of data lines interspersed with them. Driving the gate scan signal lines can be achieved through bonded integrated driver circuits. In recent years, with the continuous improvement of amorphous silicon thin-film transistor (TFT) or oxide TFT fabrication processes, it is also possible to directly integrate the gate scan signal line driving circuit onto the TFT array substrate to form a GOA (Gate driver on Array) to drive the gate scan signal lines. For example, a GOA comprising multiple cascaded shift register units can be used to provide switching voltage signals (scan signals) to the multiple rows of gate scan signal lines of the pixel array, thereby controlling the sequential conduction of the multiple rows of gate scan signal lines. Simultaneously, data signals are provided from the data lines to the corresponding pixel units in the pixel array, forming the grayscale voltages required for each grayscale level of the displayed image in each pixel unit, thus displaying a frame of image. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a shift register unit, including: an input circuit, a first control circuit, an output circuit, an output noise reduction circuit, and a reset circuit; the input circuit is connected to an input terminal and configured to control the level of a first node in response to an input signal input to the input terminal; the first control circuit is connected to the first node, a second node, and a first clock signal terminal and configured to control the level of the second node under the control of the level of the first node and a first clock signal provided by the first clock signal terminal; the output circuit is connected to an output terminal and configured to output an output signal at the output terminal under the control of the level of the second node; the output noise reduction circuit is connected to the output terminal and configured to reduce noise at the output terminal under the control of the level of the first node; the reset circuit is connected to a total reset terminal and a first voltage terminal and configured to turn off the output noise reduction circuit in response to a total reset signal provided by the total reset terminal, wherein the total reset signal is an invalid level in a first operation phase and includes at least one valid level in a second operation phase.

[0004] For example, at least one embodiment of the shift register unit provided in this disclosure further includes a second control circuit, which is connected to the first node, the third node, and the second clock signal terminal, and is configured to control the level of the third node under the control of the level of the first node and the second clock signal provided by the second clock signal terminal; the output noise reduction circuit is also connected to the third node and is configured to output an invalid level of the output signal at the output terminal in response to the level of the third node.

[0005] For example, in a shift register unit provided in at least one embodiment of this disclosure, the reset circuit is also connected to the third node and configured to reset the third node in response to a total reset signal provided by the total reset terminal, so as to turn off the output noise reduction circuit.

[0006] For example, in a shift register unit provided in at least one embodiment of this disclosure, the second control circuit includes a first sub-circuit; the first sub-circuit is connected to the first node, the second clock signal terminal and the third node, and is configured to control the level of the third node under the control of the level of the first node.

[0007] For example, in the shift register unit provided in at least one embodiment of this disclosure, the second control circuit further includes a second sub-circuit; the second sub-circuit is connected to a second voltage terminal, the first node and the first control node, and is configured to control the level of the first control node in response to a second voltage provided by the second voltage terminal; the first sub-circuit is also connected to the first control node and is configured to control the level of the third node in response to the level of the first control node.

[0008] For example, at least one embodiment of the shift register unit provided in this disclosure further includes a third control circuit, which is connected to the second node, the fourth node and the second clock signal terminal, and is configured to control the level of the fourth node under the control of the level of the second node and the second clock signal provided by the second clock signal terminal.

[0009] For example, in a shift register unit provided in at least one embodiment of this disclosure, the third control circuit includes a third sub-circuit and a fourth sub-circuit; the third sub-circuit is connected to the second clock signal terminal and the second control node, and is configured to control the level of the second control node under the control of the level of the second node; the fourth sub-circuit is connected to the second clock signal terminal, the second control node and the fourth node, and is configured to control the level of the fourth node in response to the second clock signal provided by the second clock signal terminal.

[0010] For example, in the shift register unit provided in at least one embodiment of this disclosure, the third control circuit further includes a fifth sub-circuit, which is connected to the second voltage terminal, the second node, and the third control node, and is configured to control the level of the third control node in response to the second voltage provided by the second voltage terminal; the third sub-circuit is also connected to the third control node and is configured to control the level of the second control node in response to the level of the third control node.

[0011] For example, in the shift register unit provided in at least one embodiment of this disclosure, the second control circuit further includes a sixth sub-circuit, which is connected to the second control node, the first voltage terminal and the first sub-circuit, and is configured to control the level of the first control node to remain stable in response to the level of the second control node.

[0012] For example, at least one embodiment of the shift register unit provided in this disclosure further includes a fourth control circuit, which is connected to the first node, the first voltage terminal and the fourth node, and is configured to control the level of the fourth node in response to the level of the first node.

[0013] For example, at least one embodiment of the shift register unit provided in this disclosure further includes a fifth control circuit, which is connected to the second control node, the third node and the first voltage terminal, and is configured to control the level of the third node in response to the level of the second control node.

[0014] For example, at least one embodiment of the present disclosure provides a shift register unit that further includes a sixth control circuit, which is connected to the total reset terminal, the first voltage terminal and the first node, and is configured to reset the first node under the control of a reset signal provided by the total reset terminal.

[0015] For example, in a shift register unit provided in at least one embodiment of this disclosure, the input circuit includes an input transistor, the gate of the input transistor is connected to the first clock signal terminal to receive the first clock signal, the first terminal of the input transistor is connected to the input terminal to receive the input signal, and the second terminal of the input transistor is connected to the first node.

[0016] For example, in a shift register unit provided in at least one embodiment of this disclosure, the reset circuit includes a reset transistor, the gate of which is connected to the total reset terminal to receive the total reset signal, the first terminal of which is connected to the first voltage terminal to receive a first voltage, and the second terminal of which is connected to the third node.

[0017] For example, in the shift register unit provided in at least one embodiment of this disclosure, the output noise reduction circuit includes an output noise reduction transistor, the gate of the output noise reduction transistor is connected to the third node, the first terminal and the second voltage terminal of the output noise reduction transistor are connected to receive a second voltage, and the second terminal of the output noise reduction transistor is connected to the output terminal.

[0018] For example, in the shift register unit provided in at least one embodiment of this disclosure, the output noise reduction circuit further includes an output noise reduction capacitor, the first terminal of the output noise reduction capacitor is connected to the second voltage terminal to receive the second voltage, and the second terminal of the output noise reduction capacitor is connected to the third node.

[0019] For example, in a shift register unit provided in at least one embodiment of this disclosure, the output circuit includes an output transistor and an output capacitor; the gate of the output transistor is connected to the fourth node, the first terminal of the output transistor is connected to the output terminal, and the second terminal of the output transistor is connected to the first voltage terminal to receive a first voltage; the first terminal of the output capacitor is connected to the fourth node, and the second terminal of the output capacitor is connected to the first voltage terminal to receive the first voltage.

[0020] For example, in a shift register unit provided in at least one embodiment of this disclosure, the first sub-circuit includes a first control transistor, a second control transistor, and a first control capacitor; the gate of the first control transistor is connected to the first control node, the first terminal of the first control transistor is connected to the second clock signal terminal to receive the second clock signal, the second terminal of the first control transistor is connected to the first terminal of the first control capacitor; the second terminal of the first control capacitor is connected to the first control node; the gate and the first terminal of the second control transistor are connected to each other and are both connected to the first control node, and the second terminal of the second control transistor is connected to the third node.

[0021] For example, in a shift register unit provided in at least one embodiment of this disclosure, the second sub-circuit includes a third control transistor, the gate of which is connected to the second voltage terminal, the first terminal of which is connected to the first node, and the second terminal of which is connected to the first control node.

[0022] For example, in a shift register unit provided in at least one embodiment of this disclosure, the sixth sub-circuit includes a fourth control transistor; the gate of the fourth control transistor is connected to the second control node, the first terminal of the fourth control transistor is connected to the first voltage terminal to receive a first voltage, and the second terminal of the fourth control transistor is connected to the first terminal of the first control capacitor.

[0023] For example, in a shift register unit provided in at least one embodiment of this disclosure, the sixth control circuit includes a fifth control transistor; the gate of the fifth control transistor is connected to the total reset terminal to receive the total reset signal, the first terminal of the fifth control transistor is connected to the first voltage terminal to receive a first voltage, and the second terminal of the fifth control transistor is connected to the first node.

[0024] For example, in a shift register unit provided in at least one embodiment of this disclosure, the first control circuit includes a sixth control transistor and a seventh control transistor; the gate of the sixth control transistor is connected to the first node, the first terminal of the sixth control transistor is connected to the first clock signal terminal to receive the first clock signal, and the second terminal of the sixth control transistor is connected to the second node; the gate of the seventh control transistor is connected to the first clock signal terminal to receive the first clock signal, the first terminal of the seventh control transistor and the second voltage terminal are connected to receive a second voltage, and the second terminal of the seventh control transistor is connected to the second node.

[0025] For example, in a shift register unit provided in at least one embodiment of this disclosure, the third sub-circuit includes an eighth control transistor and a third control capacitor, the fourth sub-circuit includes a ninth control transistor, and the fifth sub-circuit includes a tenth control transistor; the gate of the tenth control transistor is connected to the second voltage terminal to receive the second voltage, the first terminal of the tenth control transistor is connected to the second node, and the second terminal of the tenth control transistor is connected to the third control node; the first terminal of the third control capacitor is connected to the third control node, and the second terminal of the third control capacitor is connected to the second control node; the gate of the eighth control transistor is connected to the third control node, the first terminal of the eighth control transistor is connected to the second clock signal terminal to receive the second clock signal, and the second terminal of the eighth control transistor is connected to the second control node; the gate of the ninth control transistor is connected to the second clock signal terminal to receive the second clock signal, the first terminal of the ninth control transistor is connected to the second control node, and the second terminal of the ninth control transistor is connected to the fourth node.

[0026] For example, in a shift register unit provided in at least one embodiment of this disclosure, the fourth control circuit includes an eleventh control transistor, the gate of which is connected to the first node, the first terminal of which is connected to the fourth node, and the second terminal of which is connected to the first voltage terminal to receive a first voltage.

[0027] For example, in a shift register unit provided in at least one embodiment of this disclosure, the fifth control circuit includes a twelfth control transistor, the gate of which is connected to the second control node, the first terminal of which is connected to the third node, and the second terminal of which is connected to the first voltage terminal to receive a first voltage.

[0028] At least one embodiment of this disclosure also provides a gate drive circuit, including a plurality of cascaded shift register units provided in any embodiment of this disclosure.

[0029] At least one embodiment of this disclosure also provides a driving method for a shift register unit, including a first operation stage and a second operation stage; in the first operation stage, the driving method includes a first sub-stage, a second sub-stage, and a third sub-stage: in the first sub-stage, the input circuit controls the level of a first node in response to the effective level of an input signal input to the input terminal; the first control circuit controls the level of a second node under the control of the level of the first node and a first clock signal provided by the first clock signal terminal; in the second sub-stage, the output circuit outputs an output signal at the output terminal under the control of the level of the second node; in the third sub-stage, the output noise reduction circuit reduces noise at the output terminal under the control of the level of the first node; in the second operation stage, the driving method includes at least one reset stage, in which an effective level of a total reset signal is applied to the total reset terminal, and an ineffective level of the first clock signal is applied to the first clock signal terminal, and the reset circuit, in response to the effective level of the total reset signal, turns off the output noise reduction circuit.

[0030] For example, in the driving method provided in at least one embodiment of this disclosure, where the shift register unit further includes a second control circuit, the second control circuit is connected to the first node, the third node, and the second clock signal terminal, and is configured to control the level of the third node under the control of the level of the first node and the second clock signal provided by the second clock signal terminal; the output noise reduction circuit is also connected to the third node and is configured to output an invalid level of the output signal at the output terminal in response to the level of the third node; the reset phase further includes: applying an invalid level of the second clock signal to the second clock signal terminal, and the reset circuit resetting the third node in response to the valid level of the total reset signal, so that the output noise reduction circuit is turned off in response to the level of the third node.

[0031] At least one embodiment of this disclosure also provides a display device, including the gate driving circuit provided in any embodiment of this disclosure. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0033] Figure 1 A schematic block diagram of a shift register unit provided for at least one embodiment of this disclosure;

[0034] Figure 2 A schematic block diagram of another shift register unit provided for at least one embodiment of this disclosure;

[0035] Figure 3 A schematic block diagram of another shift register unit provided for at least one embodiment of this disclosure;

[0036] Figure 4 A schematic block diagram of another shift register unit provided for at least one embodiment of this disclosure;

[0037] Figure 5 A schematic block diagram of another shift register unit provided for at least one embodiment of this disclosure;

[0038] Figure 6 A schematic block diagram of another shift register unit provided for at least one embodiment of this disclosure;

[0039] Figure 7 A schematic block diagram of another shift register unit provided for at least one embodiment of this disclosure;

[0040] Figure 8 A schematic block diagram of another shift register unit provided for at least one embodiment of this disclosure;

[0041] Figure 9 for Figure 7 The circuit diagrams shown illustrate specific implementations of the shift register unit in some examples;

[0042] Figure 10 for Figure 7 The circuit diagrams shown illustrate specific implementations of the shift register unit in other examples;

[0043] Figure 11 for Figure 8 The circuit diagrams shown illustrate specific implementations of the shift register unit in some examples;

[0044] Figure 12 for Figure 2 The circuit diagrams shown illustrate specific implementations of the shift register unit in some examples;

[0045] Figure 13 for Figure 5 The circuit diagram shown illustrates the specific implementation of the shift register unit excluding the second and sixth sub-circuits.

[0046] Figure 14 for Figure 7 The circuit diagrams shown are of specific implementations of the shift register unit in some other examples;

[0047] Figure 15A It shows Figure 14 The signal timing diagram shown is shown when the shift register unit 10 is working;

[0048] Figure 15B It shows Figure 11 The signal timing diagram shown is shown when the shift register unit 10 is working;

[0049] Figure 16 A schematic diagram of a gate driving circuit provided for at least one embodiment of the present disclosure;

[0050] Figure 17 This is a schematic diagram of a display device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0052] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0053] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and known components have been omitted.

[0054] To keep pixel brightness fluctuations within a reasonable range, data refresh is still necessary for static images because the voltage controlling pixel brightness changes over time due to transistor leakage. To reduce display panel power consumption, the refresh rate can be lowered. However, to ensure the display quality remains unaffected, the transistor leakage rate needs to be reduced. Oxide semiconductors (OSS) possess ultra-low leakage characteristics, meeting this requirement.

[0055] When a gate drive circuit drives multiple rows of sub-pixel units in a display panel, it is necessary to output the effective level of the gate scan drive signal row by row during the display phase to drive the multiple rows of sub-pixel units to emit light. Simultaneously, to ensure normal display, during the blanking phase, the reset transistors of each shift register unit in the gate drive circuit need to be turned on to reset and reduce noise at the output, thus outputting an invalid level of the gate scan signal during the blanking phase. However, during the blanking phase, especially when driving the display panel at low frequencies, the continuous operation of the reset transistors for extended periods can affect the output reset and noise reduction capabilities, thereby impacting the lifespan of the gate drive circuit.

[0056] At least one embodiment of this disclosure provides a shift register unit, including: an input circuit, a first control circuit, an output circuit, an output noise reduction circuit, and a reset circuit; the input circuit is connected to an input terminal and configured to control the level of a first node in response to an input signal input to the input terminal; the first control circuit is connected to the first node, a second node, and a first clock signal terminal and configured to control the level of the second node under the control of the level of the first node and a first clock signal provided by the first clock signal terminal; the output circuit is connected to an output terminal and configured to output an output signal at the output terminal under the control of the level of the second node; the output noise reduction circuit is connected to the output terminal and configured to reduce noise at the output terminal under the control of the level of the first node; the reset circuit is connected to a total reset terminal and a first voltage terminal and configured to turn off the output noise reduction circuit in response to a total reset signal provided by the total reset terminal, wherein the total reset signal is an invalid level in a first operation phase and includes at least one valid level in a second operation phase.

[0057] Some embodiments of this disclosure also provide gate driving circuits, display devices, and driving methods corresponding to the above-described shift register units.

[0058] The shift register unit provided in this embodiment resets the output noise reduction circuit through a reset circuit during the second operation stage, thereby avoiding the impact on the output reset and noise reduction capability of the output noise reduction circuit due to the transistors in the output noise reduction circuit being continuously turned on for a long time. This can extend the service life of the shift register unit and improve the display quality of the display panel.

[0059] Furthermore, in the embodiments of this disclosure, for clarity and conciseness, the terms "one frame," "each frame," or "a certain frame" are defined to include a first operation phase and a second operation phase performed sequentially. For example, the first operation phase may be a display period, and the second operation phase may be a blanking phase. The embodiments of this disclosure do not impose limitations on this. The following description uses the example of the first operation phase being the display period and the second operation phase being the blanking phase. For example, during the display period, the gate driving circuit outputs an effective level of the gate driving signal. This effective level of the gate driving signal can drive multiple rows of sub-pixel units in the display panel to complete the scanning and display of a complete image from the first row to the last row. During the blanking phase, the gate driving circuit outputs an invalid level of the gate driving signal, thereby preventing display abnormalities on the panel.

[0060] The embodiments and examples of this disclosure will now be described in detail with reference to the accompanying drawings.

[0061] Figure 1 This is a schematic block diagram of a shift register unit provided for at least one embodiment of the present disclosure. Figure 1 As shown, in some examples, the shift register unit 10 may include an input circuit 110, a first control circuit 120, an output noise reduction circuit 130, an output circuit 140, and a reset circuit 150. By cascading multiple shift register units 10, a gate driving circuit can be obtained. This gate driving circuit is used to drive the display panel and sequentially provide scanning signals to multiple gate lines of the display panel, thereby performing progressive or interlaced scanning during the display of a frame.

[0062] For example, such as Figure 1As shown, input circuit 110 is connected to input terminal IN and configured to control the level of first node P1 in response to an input signal input to input terminal IN. For example, in some examples, input circuit 110 is connected to input terminal IN, first clock signal terminal CK, and first node P1, and configured to be turned on under the control of a first clock signal provided by first clock signal terminal CK, so that input terminal IN and first node P1 are connected, thereby allowing the input signal provided by input terminal IN to be input to first node P1, charging the potential of first node P1 to an operating potential (e.g., a potential that can turn on the transistor connected to first node P1). For example, in other examples, input circuit 110 may be connected to input terminal IN and first node P1, configured to be turned on under the control of an input signal provided by input terminal IN, so that input terminal IN and first node P1 are connected, thereby allowing the input signal provided by input terminal IN to be input to first node P1, pulling the potential of first node P1 up to an operating potential. It should be noted that as long as the first node P1 can be charged at the corresponding stage, the embodiments of this disclosure are not limited in this respect.

[0063] For example, the first control circuit 120 is connected to the first node P1, the second node P2, and the first clock signal terminal CK, and is configured to control the level of the second node P2 under the control of the level of the first node P1 and the first clock signal provided by the first clock signal terminal CK. For example, in some examples, the first control circuit 120 is connected to the first node P1, the second node P2, the second voltage terminal VGL, and the first clock signal terminal CK, and is configured to be turned on under the control of the level of the first node P1 and the first clock signal provided by the first clock signal terminal CK, so that the second node P2 is connected to the second voltage terminal VGL to receive the second voltage or connected to the first clock signal terminal CK to receive the first clock signal, thereby realizing the control of the level of the second node P2.

[0064] For example, output circuit 140 is connected to output terminal OUT and configured to output an output signal at output terminal OUT under the control of the level of second node P2. For example, in some examples, output circuit 140 is connected to output terminal OUT, fourth node P4, and first voltage terminal VGH, and configured to be turned on under the control of the level of fourth node P4, so that the first voltage provided by the first voltage terminal VGH is output as an output signal to output terminal OUT. Fourth node P4 is connected to second node P2, for example, through third control circuit 170, meaning output circuit 140 is indirectly connected to second node P2, i.e., indirectly controlled by second node P2, and can therefore also be configured to be turned on under the control of the level of second node P2, so that the first voltage provided by the first voltage terminal VGH is output as an output signal to output terminal OUT.

[0065] It should be noted that in the embodiments of this disclosure, "under the control of the level of the second node" can mean that the second node indirectly controls the output circuit. That is, whether the output circuit is turned on or off can be controlled by the level output of other circuits (e.g., the third control circuit) related to the level of the second node (i.e., the level of the fourth node P4). Of course, it can also be directly controlled by the level of the second node P2. The embodiments of this disclosure do not limit this. The following embodiments are similar and will not be described again.

[0066] For example, the output noise reduction circuit 130 is connected to the output terminal OUT and configured to reduce noise at the output terminal OUT under the control of the level of the first node P1. For example, in some examples, the output noise reduction circuit 130 is connected to the second voltage terminal VGL, the third node P3, and the output terminal OUT, and configured to connect the output terminal OUT and the second voltage terminal VGL when the third node P3 is turned on, thereby allowing the second voltage VGL to pull down (e.g., discharge) the output terminal OUT to achieve noise reduction. The third node P3 is connected to the first node P1, for example, through the second control circuit 160, meaning the output noise reduction circuit 130 is indirectly connected to the first node P1, i.e., indirectly controlled by the first node P1. Therefore, it can also be configured to turn on under the control of the level of the first node P1, causing the second voltage provided by the second voltage terminal VGL to be output to the output terminal OUT to achieve noise reduction.

[0067] Reset circuit 150 is connected to the total reset terminal RST and the first voltage terminal VGH, and is configured to turn off the output noise reduction circuit 130 in response to a total reset signal provided by the total reset terminal RST. For example, the total reset signal is an invalid level in a first operating phase and includes at least one valid level (e.g., a level that turns on a transistor) in a second operating phase. For example, reset circuit 150 is connected to the third node P3, the total reset terminal RST, and the first voltage terminal VGH, and is configured to connect the first voltage terminal VGH to the third node P3 in response to a total reset signal provided by the total reset terminal RST, thereby resetting the third node P3 and causing the output noise reduction circuit 130 to turn off in response to the level of the third node P3.

[0068] For example, in the second operation phase, i.e. the blanking phase, the total reset signal includes at least one effective level, which enables the reset circuit 150 to conduct in response to at least one effective level of the total reset signal during the blanking phase, resetting the third node P3 to the first voltage at least once, and causing the output noise reduction circuit 130 to turn off at least once in response to the level of the third node P3. This avoids the transistors included in the output noise reduction circuit 130 from being continuously turned on for a long time during the blanking phase, which would affect the performance of the transistors and thus affect the output reset and noise reduction capability of the output noise reduction circuit 130. This extends the service life of the circuit and ensures the display quality of the display panel.

[0069] It should be noted that during the first operation stage, i.e. the display stage, the transistors in the output noise reduction circuit will not be continuously turned on. For example, during the stage when the output circuit outputs the output signal in the display stage, the output noise reduction circuit is turned off. Therefore, during this display stage, the reset signal is at an invalid level, which ensures the normal operation of the shift register unit.

[0070] For example, such as Figure 1 As shown, the shift register unit 10 also includes a second control circuit 160. For example, the second control circuit 160 is connected to the first node P1, the third node P3, and the second clock signal terminal CB, and is configured to control the level of the third node P3 under the control of the level of the first node P1 and the second clock signal provided by the second clock signal terminal CB. For example, in some examples, the second control circuit 160 is connected to the first node P1, the third node P3, and the second clock signal terminal CB, and is configured to connect the third node P3 and the second clock signal terminal CB under the control of the level of the first node P1, so as to provide the second clock signal provided by the second clock signal terminal CB to the third node P3, thereby realizing the control of the level of the third node P3.

[0071] For example, in this example, the output noise reduction circuit 130 is also connected to the third node P3 and configured to output an invalid level (e.g., a level that turns off the transistor) at the output terminal OUT in response to the level of the third node P3. For example, the reset circuit is also connected to the third node P3 and configured to reset the third node P3 in response to the total reset signal provided at the total reset terminal RST, thereby turning off the output noise reduction circuit 130. For a detailed description, please refer to the above description of the output noise reduction circuit 130 and the reset circuit 150, which will not be repeated here.

[0072] For example, such as Figure 1 As shown, in some other examples, the shift register unit 10 further includes a third control circuit 170. The third control circuit 170 is connected to the second node P2, the fourth node P4, and the second clock signal terminal CB, and is configured to control the level of the fourth node P4 under the control of the level of the second node P2 and the second clock signal provided by the second clock signal terminal CB. For example, in some examples, the third control circuit 170 is connected to the second node P2, the fourth node P4, and the second clock signal terminal CB, and is configured to connect the fourth node P4 and the second node P2 under the control of the level of the second node P2 and the second clock signal provided by the second clock signal terminal CB, so as to provide the level of the second node P2 to the fourth node P4, thereby realizing the control of the level of the fourth node P4.

[0073] Figure 2This is a schematic block diagram of another shift register unit provided for at least one embodiment of the present disclosure. For example, as... Figure 2 As shown, the second control circuit 160 includes a first sub-circuit 161. For example, the first sub-circuit 161 is connected to a first node P1, a second clock signal terminal CB, and a third node P3, and is configured to control the level of the third node P3 under the control of the level of the first node P1. For example, in some examples, the first sub-circuit 161 is connected to the first node P1, the second clock signal terminal CB, and the third node P3, and is configured to connect the second clock signal terminal CB to the third node P3 under the control of the level of the first node P1, thereby controlling the level of the third node P3.

[0074] Figure 3 This is a schematic block diagram of another shift register unit provided for at least one embodiment of the present disclosure. For example, as... Figure 3 As shown, the second control circuit 160 further includes a second sub-circuit 162; the second sub-circuit 162 is connected to the second voltage terminal VGL, the first node P1, and the first control node P11, and is configured to control the level of the first control node P11 in response to the second voltage provided by the second voltage terminal VGL; the first sub-circuit 161 is also connected to the first control node P11, and is configured to control the level of the third node P3 in response to the level of the first control node P11. For example, in some examples, the second sub-circuit 162 is turned on in response to the second voltage provided by the second voltage terminal VGL, so that the first node P1 and the first control node P11 are connected, thereby making the level of the first control node P11 the same as the level of the first node P1; in this example, the first sub-circuit 161 is turned on in response to the level of the first control node P11, so that the second clock signal terminal CB is connected to the third node P3, thereby controlling the level of the third node P3.

[0075] Figure 4 This is a schematic block diagram of another shift register unit provided for at least one embodiment of the present disclosure. For example, as... Figure 4 As shown, the second control circuit 160 also includes a sixth sub-circuit 163. For example, the sixth sub-circuit 163 is connected to the second control node P21, the first voltage terminal VGH, and the first sub-circuit 161, and is configured to maintain a stable level of the first control node P11 in response to the level of the second control node P21. For example, in some examples, the sixth sub-circuit 163 is turned on in response to the level of the second control node P21, causing the first voltage terminal VGH to be connected to the first sub-circuit 161. This prevents changes in the second clock signal provided by the second clock signal terminal CB connected to the first sub-circuit 161 from affecting the level of the first control node P11, thereby ensuring the normal operation of the shift register unit.

[0076] Figure 5This is a schematic block diagram of another shift register unit provided for at least one embodiment of the present disclosure. For example, as... Figure 5 As shown, the third control circuit includes a third sub-circuit 171 and a fourth sub-circuit 172. The third sub-circuit 171 is connected to the second clock signal terminal CB and the second control node P21, and is configured to control the level of the second control node P21 under the control of the level of the second node P2. The fourth sub-circuit 172 is connected to the second clock signal terminal CB, the second control node P21, and the fourth node P4, and is configured to control the level of the fourth node P4 in response to the second clock signal provided by the second clock signal terminal CB. For example, in some examples, the third sub-circuit 171 is turned on under the control of the level of the second node P2, so that the second clock signal terminal CB is connected to the second control node P21, thereby providing the second clock signal provided by the second clock signal terminal CB to the second control node P21 to control the level of the second control node P21; the fourth sub-circuit 172 is turned on in response to the second clock signal provided by the second clock signal terminal CB, so that the second control node P21 is connected to the fourth node P4, thereby inputting the level of the second control node P21 to the fourth node P4 to control the level of the fourth node P4.

[0077] Figure 6 This is a schematic block diagram of another shift register unit provided for at least one embodiment of the present disclosure. For example, as... Figure 6 As shown, the third control circuit 170 further includes a fifth sub-circuit 173. For example, the fifth sub-circuit 173 is connected to the second voltage terminal VGL, the second node P2, and the third control node P31, and is configured to control the level of the third control node P31 in response to the second voltage provided by the second voltage terminal VGL. The fifth sub-circuit 173 is also connected to the third control node P31 and is configured to control the level of the second control node P21 in response to the level of the third control node P31. For example, in some examples, the fifth sub-circuit 173 conducts in response to the second voltage provided by the second voltage terminal VGL, inputting the level of the second node P2 to the third control node P31 to control the level of the third control node P31. In this example, the fifth sub-circuit 173 is configured to conduct in response to the level of the third control node P31, such that the second clock signal terminal CB is connected to the second control node P21, thereby providing the second clock signal provided by the second clock signal terminal CB to the second control node P21 to control the level of the second control node P21.

[0078] Figure 7 This is a schematic block diagram of another shift register unit provided for at least one embodiment of the present disclosure. For example, as... Figure 7 As shown, in Figure 6Based on the example shown, the shift register unit 10 further includes a fourth control circuit 180. For example, the fourth control circuit 180 is connected to the first node P1, the first voltage terminal VGH, and the fourth node P4, and is configured to control the level of the fourth node P4 in response to the level of the first node P1. For example, in some examples, the fourth control circuit 180 turns on in response to the level of the first node P1, causing the first voltage terminal VGH to be connected to the fourth node P4, thereby inputting a first voltage provided by the first voltage terminal VGH to the fourth node P4 to control the level of the fourth node P4.

[0079] For example, such as Figure 7 As shown, the shift register unit 10 also includes a fifth control circuit 190. For example, the fifth control circuit 190 is connected to the second control node P21, the third node P3, and the first voltage terminal VGH, and is configured to control the level of the third node P3 in response to the level of the second control node P21. For example, in some examples, the fifth control circuit 190 is configured to conduct in response to the level of the second control node P21, causing the third node P3 to be connected to the first voltage terminal VGH to receive the first voltage, thereby controlling the level of the third node P3.

[0080] Figure 8 This is a schematic block diagram of another shift register unit provided for at least one embodiment of the present disclosure. For example, as... Figure 8 As shown, in Figure 7 Based on the example shown, the shift register unit further includes a sixth control circuit 200. For example, the sixth control circuit 200 is connected to the global reset terminal RST, the first voltage terminal VGH, and the first node P1, and is configured to reset the first node P1 under the control of a reset signal provided by the global reset terminal RST. For instance, in some examples, the sixth control circuit 200 is configured to conduct in response to a reset signal provided by the global reset terminal RST, causing the first node P1 to be connected to the first voltage terminal VGH to receive a first voltage, thereby resetting the first node P1.

[0081] For example, in this example, during the blanking phase, when the reset signal is active, the first node P1 is reset, thereby turning off the first control circuit 120, the second control circuit 160, and the fourth control circuit 180, and causing the transistors T2, T4, T5, and T8 (e.g., Figure 9 (As shown) Short-term recovery can further stabilize the state of the shift register unit and extend the service life of the circuit.

[0082] Those skilled in the art will understand that, although Figures 1-8The illustrations show multiple control circuits and multiple reset circuits; however, the above examples do not limit the scope of protection of this disclosure. In practical applications, those skilled in the art can choose to use or not use one or more of the above circuits as appropriate. Various combinations and variations based on the foregoing circuits do not depart from the principles of this disclosure, and will not be elaborated further.

[0083] exist Figure 7 When the shift register unit shown does not include the sixth sub-circuit 163, Figure 9 for Figure 7 The circuit diagrams shown are of specific implementations of the shift register unit in some examples, and are also present in some embodiments of this disclosure. Figure 7 The shift register unit 10 shown can be implemented as follows: Figure 9 The circuit structure is shown below. Figure 9 As shown, the shift register unit 10 includes: input transistors M1 to M14 (the tenth control transistor), a third control capacitor C1, an output capacitor C2, an output noise reduction capacitor C3, and a first control capacitor C4. It should be noted that... Figure 9 The transistors shown are all P-type transistors, but the embodiments disclosed herein are not limited to them. For example, at least some of the transistors in the shift register unit 10 may also be N-type transistors.

[0084] exist Figure 7 When the shift register unit shown includes the sixth sub-circuit 163, Figure 10 for Figure 7 The circuit diagram shown illustrates the specific implementation of the shift register unit in some examples, i.e., in Figure 9 Based on the example shown, a fourth control transistor T16 is also included. The following is in conjunction with... Figure 9 and Figure 10 right Figure 7 The specific implementation of the shift register unit shown will be described in detail.

[0085] For example, such as Figure 9 As shown, the input circuit 110 includes an input transistor T1. The gate of the input transistor T1 is connected to the first clock signal terminal CK to receive the first clock signal. The first terminal of the input transistor T1 is connected to the input terminal IN to receive the input signal. The second terminal of the input transistor T1 is connected to the first node P1.

[0086] For example, in other embodiments, the gate and first terminal of the input transistor T1 may both be connected to the input terminal IN to receive the input signal, thereby inputting the input signal to the first node P1 in response to the input signal being turned on.

[0087] For example, such as Figure 9As shown, the reset circuit 150 includes a reset transistor T12. The gate of the reset transistor T12 is connected to the total reset terminal RST to receive the total reset signal. The first terminal of the reset transistor T12 is connected to the first voltage terminal VGH to receive the first voltage. The second terminal of the reset transistor T12 is connected to the third node P3.

[0088] For example, the output noise reduction circuit 130 includes an output noise reduction transistor T10, the gate of the output noise reduction transistor T10 is connected to the third node P3, the first terminal and the second voltage terminal VGL of the output noise reduction transistor T10 are connected to receive the second voltage, and the second terminal of the output noise reduction transistor T10 is connected to the output terminal OUT.

[0089] For example, the output noise reduction circuit 130 also includes an output noise reduction capacitor C3, the first terminal and the second voltage terminal VGL of the output noise reduction capacitor C3 are connected to receive a second voltage, and the second terminal and the third node P3 of the output noise reduction capacitor C3 are connected.

[0090] For example, in some examples, the output noise reduction circuit 130 may not include the output noise reduction capacitor C3, such as... Figure 14 As shown, the parasitic capacitance C31 of the output noise reduction transistor T10 is used as the output noise reduction capacitor C3. Since the output noise reduction transistor T10 is relatively large, its own parasitic capacitance C31 is also relatively large. Therefore, the parasitic capacitance C31 can act as the output noise reduction capacitor C3. For example, the capacitance value of the parasitic capacitance C31 is less than or equal to the capacitance value of the output noise reduction capacitor. Reducing the capacitance value of the output noise reduction circuit 130 can improve the reset speed, and the reset speed of the third node P3 will also be faster. It can also increase the fluctuation margin of the threshold voltage Vth of the output transistor T10, which is beneficial to extending the service life of the shift register unit. At the same time, it can also reduce the occupied area and size of the shift register unit, which is beneficial to achieving a narrow bezel.

[0091] For example, such as Figure 9 As shown, the output circuit 140 includes an output transistor T9 and an output capacitor C2; for example, the gate of the output transistor T9 is connected to the fourth node P4, the first terminal of the output transistor T9 is connected to the output terminal OUT, and the second terminal of the output transistor T9 is connected to the first voltage terminal VGH to receive the first voltage; the first terminal of the output capacitor C2 is connected to the fourth node P4, and the second terminal of the output capacitor is connected to the first voltage terminal VGH to receive the first voltage.

[0092] For example, such as Figure 9As shown, the first sub-circuit 161 includes a first control transistor T4, a second control transistor T5, and a first control capacitor C4; the gate of the first control transistor T4 is connected to the first control node P11, the first terminal and the second clock signal terminal CB of the first control transistor T4 are connected to receive the second clock signal, the second terminal of the first control transistor T4 is connected to the first terminal of the first control capacitor C4, the second terminal of the first control capacitor C4 is connected to the first control node P11; the gate and the first terminal of the second control transistor T5 are connected to each other and both are connected to the first control node P11, and the second terminal of the second control transistor T5 is connected to the third node P3.

[0093] For example, the second sub-circuit 162 includes a third control transistor T13, the gate of the third control transistor T13 is connected to the second voltage terminal VGL, the first terminal of the third control transistor T13 is connected to the first node P1, and the second terminal of the third control transistor T13 is connected to the first control node P11.

[0094] For example, such as Figure 10 As shown, the sixth sub-circuit 163 includes a fourth control transistor T16; the gate of the fourth control transistor T16 is connected to the second control node P21, the first terminal of the fourth control transistor T16 is connected to the first voltage terminal VGH to receive the first voltage, and the second terminal of the fourth control transistor T16 is connected to the first terminal of the first control capacitor C4. This allows the voltage at the first terminal of the first control capacitor C4 to be stabilized at the first voltage when the second control node P21 is at an active level. This prevents the voltage at the first control node P11 from jumping with the second clock signal provided by the second clock signal terminal CB connected to the first control transistor T4 due to the charge conservation principle of the first control capacitor C4. This avoids the second clock signal terminal CB affecting the voltage at the first control node P11, thereby affecting the leakage current of the output noise reduction transistor T10 and reducing noise at high output levels.

[0095] For example, such as Figure 9 As shown, the first control circuit 120 includes a sixth control transistor T2 and a seventh control transistor T3; the gate of the sixth control transistor T2 is connected to the first node P1, the first terminal of the sixth control transistor T2 is connected to the first clock signal terminal CK to receive the first clock signal, and the second terminal of the sixth control transistor T2 is connected to the first node P1; the gate of the seventh control transistor T3 is connected to the first clock signal terminal CK to receive the first clock signal, the first terminal of the seventh control transistor T3 and the second voltage terminal VGL are connected to receive the second voltage, and the second terminal of the seventh control transistor T3 is connected to the second node P2.

[0096] For example, such as Figure 9-11As shown, the third sub-circuit 171 includes an eighth control transistor T6 and a third control capacitor C1; the fourth sub-circuit includes a ninth control transistor T7; and the fifth sub-circuit includes a tenth control transistor T14. The gate and second voltage terminal VGL of the tenth control transistor T14 are connected to receive a second voltage. The first terminal and second node P2 of the tenth control transistor T14 are connected, and the second terminal and third control node P31 of the tenth control transistor T14 are connected. The first terminal and third control node P31 of the third control capacitor C1 are connected, and the second terminal and second control node P21 of the third control capacitor C1 are connected. The gate and third control node P31 of the eighth control transistor T6 are connected, and the first terminal and second clock signal terminal CB of the eighth control transistor T6 are connected to receive a second clock signal. The second terminal and second control node P21 of the eighth control transistor T6 are connected. The gate and second clock signal terminal CB of the ninth control transistor T7 are connected to receive a second clock signal. The first terminal and second control node P2 of the ninth control transistor T7 are connected, and the second terminal and fourth node P4 of the ninth control transistor T9 are connected.

[0097] For example, the third control transistor T13 reduces leakage current at the first control node P11, and the tenth control transistor T14 reduces leakage current at the third control node P31, thereby enabling a faster response speed for the gate drive signal output.

[0098] For example, the fourth control circuit 180 includes an eleventh control transistor T8, the gate of the eleventh control transistor T8 is connected to the first node P1, the first terminal of the eleventh control transistor T8 is connected to the fourth node P4, and the second terminal of the eleventh control transistor T8 is connected to the first voltage terminal VGH to receive a first voltage.

[0099] For example, the fifth control circuit 190 includes a twelfth control transistor T11, the gate of the twelfth control transistor T11 is connected to the second control node P21, the first terminal of the twelfth control transistor T11 is connected to the third node P3, and the second terminal of the twelfth control transistor P21 is connected to the first voltage terminal VGH to receive a first voltage.

[0100] Figure 11 for Figure 8 The circuit diagrams shown are of specific implementations of the shift register unit in some examples, and are also present in some embodiments of this disclosure. Figure 8 The shift register unit 10 shown can be implemented as follows: Figure 11 The circuit structure is shown below. Figure 11 As shown, in Figure 9 Based on the example shown, the shift register unit 10 further includes a fifth control transistor T15. It should be noted that, in Figure 11 The circuit structure shown and Figure 9The circuit structures shown are basically the same; for detailed descriptions, please refer to [reference needed]. Figure 9 The details described in the text will not be repeated here.

[0101] For example, such as Figure 11 As shown, the sixth control circuit 200 includes a fifth control transistor T15; the gate and the total reset terminal RST of the fifth control transistor T15 are connected to receive the total reset signal, the first terminal and the first voltage terminal VGH of the fifth control transistor T15 are connected to receive the first voltage, and the second terminal and the first node P1 of the fifth control transistor T15 are connected.

[0102] Figure 12 for Figure 2 The circuit diagrams shown are of specific implementations of the shift register unit in some examples, and are also present in some embodiments of this disclosure. Figure 2 The shift register unit 10 shown can be implemented as follows: Figure 12 The circuit structure is shown below. Figure 12 As shown, in Figure 9 Based on the example shown, the second control circuit 160 of the shift register unit 10 includes only the first sub-circuit, that is, in Figure 9 The example shown excludes the third control transistor T13. It should be noted that... Figure 12 The circuit structure shown and Figure 9 The circuit structures shown are basically the same; for a detailed description, please refer to [reference needed]. Figure 9 The details described in the text will not be repeated here.

[0103] Figure 13 for Figure 5 The circuit diagram shown illustrates a specific implementation of the shift register unit excluding the second and sixth sub-circuits, as described in some embodiments of this disclosure. Figure 5 The shift register unit 10 shown can be implemented without the second and sixth sub-circuits as follows: Figure 13 The circuit structure is shown below. Figure 13 As shown, in Figure 9 Based on the example shown, the second control circuit 160 of the shift register unit 10 includes only the first sub-circuit, and the third control circuit 170 includes only the third and fourth sub-circuits, that is, in Figure 9 Based on the example shown, excluding the third control transistor T13 and the tenth control transistor T14, this example not only does not affect the function of the shift register unit, but also facilitates the implementation of a narrow bezel. It should be noted that... Figure 13 The circuit structure shown and Figure 9 The circuit structures shown are basically the same; for a detailed description, please refer to [reference needed]. Figure 9 The details described in the text will not be repeated here.

[0104] As previously described, in the shift register unit 10 provided in the embodiments of this disclosure, the potential at the second control node P21 can be maintained by the third control capacitor C1, the potential at the fourth node P4 can be maintained by the output capacitor C2, the potential at the third node P3 can be maintained by the output noise reduction capacitor C3 or the parasitic capacitor C31, and the potential at the first control node P11 can be maintained by the first control capacitor C4. The third control capacitor C1, the output capacitor C2, the output noise reduction capacitor C3, and the first control capacitor C4 can be capacitor devices manufactured by process technology, for example, by manufacturing dedicated capacitor electrodes. The electrodes of the capacitor can be implemented by metal layers, semiconductor layers (e.g., doped polysilicon), etc., or in some examples, by designing circuit wiring parameters, the third control capacitor C1, the output capacitor C2, the output noise reduction capacitor C3, and the first control capacitor C4 can also be implemented by the parasitic capacitance between the various devices. The connection method of the third control capacitor C1, output capacitor C2, output noise reduction capacitor C3 and the first control capacitor C4 is not limited to the method described above. Other applicable connection methods are also acceptable, as long as they can store and write the levels to the second control node P21, the fourth node P4, the third node P3 and the first control node P11.

[0105] It should be noted that in some embodiments of this disclosure, VGH represents both a first voltage terminal and a first voltage, and VGL represents both a second voltage terminal and a second voltage. The first voltage VGH may be, for example, a high level, and the second voltage VGL may be, for example, a low level. For example, the first voltage VGH may be greater than the second voltage VGL. The following embodiments are the same and will not be described again.

[0106] Additionally, it should be noted that in some embodiments of this disclosure, high and low levels are relative. A high level represents a higher voltage range (e.g., a high level can be 5V, 10V, or other suitable voltages), and multiple high levels can be the same or different. Similarly, a low level represents a lower voltage range (e.g., a low level can be 0V, -5V, -10V, or other suitable voltages), and multiple low levels can be the same or different. For example, the minimum value of a high level is greater than the maximum value of a low level.

[0107] It should be noted that, in some embodiments of this disclosure, controlling the level of a node (e.g., the first node P1) includes charging the node to raise its level or discharging the node to lower its level. For example, a capacitor electrically connected to the node (e.g., capacitors C1-C4 mentioned above) can be provided. Charging the node means charging the capacitor electrically connected to the node; similarly, discharging the node means discharging the capacitor electrically connected to the node. The capacitor can be used to maintain the node at a high or low level.

[0108] It should be noted that CK represents both the first clock signal terminal and the first clock signal, and CB represents both the second clock signal terminal and the second clock signal. The following embodiments are the same and will not be repeated.

[0109] In embodiments of this disclosure, for example, when the circuits are implemented as N-type transistors, the term "pull-up" refers to charging a node or an electrode of a transistor to raise the absolute value of the voltage level of that node or electrode, thereby enabling the operation of the corresponding transistor (e.g., turning it on); "pull-down" refers to discharging a node or an electrode of a transistor to lower the absolute value of the voltage level of that node or electrode, thereby enabling the operation of the corresponding transistor (e.g., turning it off).

[0110] For example, when the circuits are implemented as P-type transistors, the term "pull-up" means discharging a node or an electrode of a transistor to lower the absolute value of the voltage level of that node or electrode, thereby enabling the corresponding transistor to operate (e.g., turn on); "pull-down" means charging a node or an electrode of a transistor to raise the absolute value of the voltage level of that node or electrode, thereby enabling the corresponding transistor to operate (e.g., turn off).

[0111] It should be noted that in the description of the various embodiments of this disclosure, the first node P1, the second node P2, the third node P3, the fourth node P4, the first control node P11, the second control node P21, and the third control node P31 do not represent actual existing components, but rather represent the junction points of related electrical connections in the circuit diagram.

[0112] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The embodiments of this disclosure use thin-film transistors as an example for illustration. The source and drain of the transistors used here can be structurally symmetrical, so their structures can be indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal and the other as the second terminal. Furthermore, transistors can be classified into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the cut-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the cut-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0113] Furthermore, the transistors in the embodiments of this disclosure are all described using P-type transistors as an example. In this case, the first terminal of the transistor is the drain, and the second terminal is the source. It should be noted that this disclosure includes, but is not limited to, this. For example, one or more transistors in the shift register unit 10 provided in the embodiments of this disclosure can also be N-type transistors. In this case, the first terminal of the transistor is the source, and the second terminal is the drain. It is only necessary to connect the terminals of the selected type of transistor according to the terminals of the corresponding transistors in the embodiments of this disclosure, and provide the corresponding high or low level at the corresponding voltage terminals. When using N-type transistors, indium gallium zinc oxide (IGZO) can be used as the active layer of the thin-film transistor. Compared with using low-temperature polysilicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon) as the active layer of the thin-film transistor, the size of the transistor can be effectively reduced and leakage current can be prevented.

[0114] At least one embodiment of this disclosure also provides a method for driving a shift register unit. Figure 15A It shows Figure 14 The signal timing diagram of shift register unit 10 when it is working is shown.

[0115] For example, such as Figure 15A As shown, the driving method includes a first operation phase S1 and a second operation phase S2; in the first operation phase S1, the driving method includes a first sub-phase t1, a second sub-phase t2, and a third sub-phase t3. A frame includes the first operation phase S1 (i.e., the display phase) and the second operation phase S2 (i.e., the blanking phase). The display phase is used to drive the display panel to display, and the blanking phase is the phase between the display phase of the current frame and the display phase of the next frame. Figure 15A The signal levels shown in the timing diagram are only schematic and do not represent the actual level values.

[0116] In the first sub-stage t1, the input circuit 110 controls the level of the first node P1 in response to the effective level of the input signal input at the input terminal IN; the first control circuit 120 controls the level of the second node P2 under the control of the level of the first node P1 and the first clock signal provided by the first clock signal terminal CK.

[0117] In the second sub-stage t2, under the control of the level of the second node P2, the output circuit 140 outputs an output signal at the output terminal OUT.

[0118] In the third sub-stage t3, the output noise reduction circuit 130 reduces noise at the output terminal OUT under the control of the level of the first node P1.

[0119] In other examples, the driving method also includes a fourth sub-stage t4, a fifth sub-stage t5, and a sixth sub-stage t6.

[0120] The following is combined with Figure 15A and Figure 14 The operation method of the shift register unit 10 provided in at least one embodiment of this disclosure will be described in detail. For example, the first sub-stage t1 is the input stage t1, the second sub-stage t2 is the output stage t2, and the third sub-stage t3 is the reset stage t3; the fourth sub-stage t4 is the first hold time period t4; the fifth sub-stage t5 is the second hold time period t5; and the sixth sub-stage t6 is the third hold time period t6. In the first operation stage S1, the total reset signal terminal RST is provided with a high level, and the reset transistor T12 is turned off in response to the high level of the total reset signal.

[0121] During input phase t1, the first clock signal terminal CK provides a low level, the second clock signal terminal CB provides a high level, and the input terminal IN provides a high level. Input transistor T1 turns on in response to the low level of the first clock signal, and the third control transistor T13 turns on in response to the second voltage provided by the second voltage terminal VGL. The potential of the first node P1 is high, the potential of the first control node P11 is high, and the first control transistor T4 and the second control transistor T5 turn off in response to the high voltage of the first control node P11. The sixth control transistor T2 turns off in response to the high level of the first node P1, the seventh control transistor T3 turns on in response to the low level of the first clock signal, and the tenth control transistor T14 turns on in response to the second voltage provided by the second voltage terminal VGL. When the voltage is turned on, the potential of the second node P2 is low, the potential of the third control node P31 is low, the eighth control transistor T6 turns on in response to the low level of the third control node P31, the potential of the second control node P21 is high, the ninth control transistor T7 turns off in response to the high level of the second clock signal, the eighth control transistor T8 turns off in response to the high level of the first node, the twelfth control transistor T11 turns off in response to the high level of the second control node P21, the potential of the third node P3 remains high, the potential of the fourth node P4 remains high, the output noise reduction transistor T10 turns off in response to the high level of the third node, the ninth transistor T9 turns off in response to the low level of the fourth node P4, and the output terminal OUT outputs a low level.

[0122] During output phase t2, the first clock signal terminal CK provides a high level, the second clock signal terminal CB provides a low level, the input terminal IN provides a low level, input transistor T1 is off, the third control transistor T13 is on, and the potentials of the first node P1 and the first control node P11 remain high. The first control transistor T4 is off, the second control transistor T5 is off, the sixth control transistor T2 and the seventh control transistor T3 are off, and the potential of the second node P2 remains low. The eighth control transistor T6 is on, inputting the low level provided by the second clock signal terminal CB to the second control node P2. 1. When the second control node P21 changes from high level to low level, according to the charge conservation principle of the third control capacitor C1, the potential of the third control node P31 is further pulled down by the third control capacitor C1. The ninth control transistor T7 is turned on, the eighth control transistor T8 is turned off, the twelfth control transistor T11 is turned on in response to the low level of the second control node P21, the potential of the fourth node P4 is low level, and the potential of the third node P3 is still high level. Therefore, the ninth transistor T9 is turned on, the output noise reduction transistor T10 is turned off, and the output terminal OUT outputs the high level provided by the first voltage terminal VGH.

[0123] During the reset phase t3, the first clock signal terminal CK provides a low level, the second clock signal terminal CB provides a high level, the input terminal IN provides a low level, the input transistor T1 is turned on, the potential of the first node P1 is pulled low, the third control transistor T13 is turned on, the potential of the first control node P11 is pulled low, the second control transistor T5 is turned on, and the potential of the third node P3 is pulled low; the output noise reduction transistor T10 responds to the level of the third node P3 by turning on, outputting the second voltage provided by the second voltage terminal VGL to the output terminal OUT, and the output terminal OUT outputs a low level. To achieve noise reduction at the output terminal OUT; the sixth control transistor T2 and the seventh control transistor T3 are turned on, the potential of the second node P2 is low, the tenth control transistor T14 is turned on, the eighth control transistor T6 is turned on, the second control node P21 becomes high according to the second clock signal terminal CB, the potential of the third control node P3 is pulled high according to the charge conservation principle of the third control capacitor, and the ninth control transistor T7 is turned off; the eighth control transistor T8 is turned on in response to the low level of the first node, and the potential of the fourth node P4 is pulled high, and the ninth transistor T9 is turned off.

[0124] During the first hold period t4 of the hold phase, the first clock signal terminal CK provides a high level, the second clock signal terminal CB provides a low level, the input terminal IN provides a low level, the input transistor T1 is off, the potential of the first node P1 remains low, the third control transistor T13 is on, the first control transistor T4 is on, the second clock signal terminal CB pulls down the potential of the first control node P11 through the first control capacitor C4, the second control transistor T5 is on, thereby keeping the potential of the third node P3 below VGL+Vth, where Vth is the threshold voltage of the output noise reduction transistor T10. Output noise reduction transistor T10 is turned on, thereby maintaining the potential of the gate drive signal output at the output terminal OUT at the second voltage, that is, maintaining it at a low level, unaffected by noise interference; the seventh control transistor T3 is turned off, the sixth control transistor T2 is turned on, the potential of the second node P2 is the high level provided by the first clock signal terminal CK, the tenth control transistor T14 is turned on, the potential of the third control node P31 is high, the potential of the second control node P21 is high, the ninth control transistor T7 is turned on, the eighth control transistor T8 is turned on, the potential of the fourth node P4 is high, and the ninth transistor T9 is turned off.

[0125] During the second hold period t5 of the hold phase, the first clock signal terminal CK provides a low level, the second clock signal terminal CB provides a high level, the input terminal IN provides a low level, the input transistor T1 is turned on, the potential of the first node P1 is low, the third control transistor T13 is turned on, the first control node P11 is low, the first control transistor T4 responds to the low level of the first control node P11 and turns on, the potential of the input clock signal provided by the second clock signal terminal CB increases, according to the charge conservation principle of the first control capacitor C4, thereby raising the potential of the first control node P11, the second control transistor T5 is turned off, and it does not affect the potential of the third node P3, so that the potential of the third node P3 is maintained at a low level. The voltage is below VGL+Vth, where Vth is the threshold voltage of the output noise reduction transistor T10. This causes the output noise reduction transistor T10 to turn on, thereby maintaining the potential of the gate drive signal output at the output terminal OUT at the second voltage, i.e., low level, unaffected by noise interference. The seventh control transistor T3 is turned on, the potential of the second node P2 is low level, the sixth control transistor T2 is turned on, the tenth control transistor T14 is turned on, the potential of the third control node P31 is low level, the eighth control transistor T6 is turned on, the potential of the second control node P21 is high level, the ninth control transistor T7 is turned off, the eighth control transistor T8 is turned off, the potential of the fourth node P4 remains high level, and the ninth transistor T9 is turned off.

[0126] During the third hold period t6 of the hold phase, the first clock signal terminal CK provides a high level, the second clock signal terminal CB provides a low level, the input terminal IN provides a low level, the input transistor T1 is off, the potential of the first node P1 remains low, the first control transistor T4 is on, the second clock signal terminal CB pulls down the potential of the first control node P11 through the first control capacitor C4, the second control transistor T5 is on, thereby keeping the potential of the third node P3 below VGL+Vth, where Vth is the threshold voltage of the output noise reduction transistor T10, thus keeping the output noise reduction transistor... When transistor T10 is turned on, the potential of the gate drive signal output at the output terminal OUT is maintained at the second voltage, i.e., low level, and is not affected by noise interference; the seventh control transistor T3 is turned off, the sixth control transistor T2 is turned on, the potential of the second node P2 is high level, the tenth control transistor T14 is turned on, the potential of the third control node P31 is high level, the eighth control transistor T6 is turned off, the potential of the second control node P21 is high level, the ninth control transistor T7 is turned on, the eighth control transistor T8 is turned on, the potential of the fourth node P4 is high level, and the ninth transistor T9 is turned off.

[0127] During the holding phase, the potential of the third node P1 can be maintained below VGL+Vth, where Vth is the threshold voltage of the output noise reduction transistor T10, which turns on the output noise reduction transistor T10, thereby maintaining the potential of the gate drive signal output at the output terminal OUT at the second voltage, unaffected by noise interference.

[0128] exist Figure 9-14 In the shift register unit shown, the first control transistor T4, the first control capacitor C4, and the second control transistor T5 form a charge pump structure. A charge pump is a pump-like structure in a circuit, primarily utilizing capacitors, clock signals, and diode rectification (in...). Figure 9-14 In the middle, the second control transistor T5 adopts a diode connection method to realize the redistribution of charge and achieve the purpose of boosting (or bucking) voltage.

[0129] For example, such as Figure 15A As shown, in the second operation phase S2, the driving method of the shift register unit includes at least one reset phase t7. Figure 15A Only one reset phase t7 is shown in the figure, and the embodiments of this disclosure are not limited thereto.

[0130] For example, during at least one reset phase t7, an active level (e.g., low level) of the global reset signal is applied to the global reset terminal RST, and an inactive level (e.g., high level) of the first clock signal is applied to the first clock signal terminal CLK. Responding to the active level of the global reset signal, the reset circuit 150 turns off the output noise reduction circuit 130.

[0131] For example, if the shift register unit 10 further includes a second control circuit 160, the second control circuit 160 is connected to the first node P1, the third node P3, and the second clock signal terminal CB, and is configured to control the level of the third node P3 under the control of the level of the first node P1 and the second clock signal provided by the second clock signal terminal CB; the output noise reduction circuit 130 is also connected to the third node P3 and is configured to output an invalid level of the output signal at the output terminal OUT in response to the level of the third node P3; the reset phase t7 further includes: applying an invalid level of the second clock signal to the second clock signal terminal CB, and the reset circuit 150 resetting the third node P3 in response to the valid level of the total reset signal, so that the output noise reduction circuit 130 is cut off in response to the level of the third node P3.

[0132] like Figure 15A As shown, during the reset phase t7, the first clock signal terminal CK provides a high level, the second clock signal terminal CB provides a high level, the input terminal IN provides a low level, the total reset terminal RST provides a low level, the input transistor T1 is cut off, the potential of the first node P1 remains low, the third control transistor T13 is turned on, the first control node P11 is low, the first control transistor T4 turns on in response to the low level of the first control node P11, the potential of the input clock signal provided by the second clock signal terminal CB increases, and according to the charge conservation principle of the first control capacitor C4, the potential of the first control node P11 is thus pulled up. The second control transistor T5 is turned off. Since the reset transistor T12 is turned on in response to the low level of the total reset signal, the first voltage terminal VGH is connected to the third node P3, thereby pulling up the voltage of the third node P3. The output noise reduction transistor T10 is turned off, so that the output noise reduction transistor T10 is turned off in at least one reset stage t7 of the second operation stage S2. This can prevent the output noise reduction transistor T10 from being turned on continuously in the second operation stage S2, thus affecting the output reset and noise reduction capability of the output noise reduction circuit 130. This can extend the service life of the shift register unit and improve the display quality of the display panel. During this stage, the sixth control transistor T2 is turned on, and the seventh control transistor T3 is turned off, connecting the second node P2 to the first clock signal terminal CK. The potential of the second node P2 is high at the first clock signal terminal CK. The tenth control transistor T14 is turned on, and the potential of the third control node P31 is high. The eighth control transistor T6 is turned off, and the potential of the second control node P21 remains high. The ninth control transistor T7 is turned off, and the eighth control transistor T8 is turned on. The potential of the fourth node P4 remains high, and the ninth transistor T9 is turned off.

[0133] It should be noted that other circuits (e.g., Figure 9-10 The driving method of the circuit shown in Figures 12-13 and Figure 14 The driving method for the circuit shown is similar and can be referred to. Figure 14 and Figure 15A The description of the driving method in the code will not be repeated here.

[0134] Figure 15B It shows Figure 11 The signal timing diagram of shift register unit 10 during operation is shown in Figure 15. Figure 11 The working process of the shift register unit shown is the same as Figure 14 The operation of the shift register unit shown is similar, with the only difference being: during the reset phase t7, the fifth control transistor T15 is turned on in response to the high level of the reset signal, connecting the first node P1 and the first voltage terminal VGH, thus making the level of the first node P1 high. Since the third control transistor T13 is turned on, the first control node P11 is connected to the first node P1, thus making the level of the first control node P11 high. The remaining process can be referred to... Figure 15A The details of its introduction will not be repeated here.

[0135] At least one embodiment of this disclosure also provides a gate driving circuit 20, such as Figure 16 As shown, the gate drive circuit 20 includes a plurality of cascaded shift register units 10, wherein any one or more shift register units 10 may adopt the structure of the shift register unit 10 provided in any embodiment of the present disclosure or a variation thereof.

[0136] At least one embodiment of this disclosure also provides a display device 1, such as... Figure 17 As shown, the display device 1 includes a gate driving circuit 20 provided in this embodiment and a plurality of sub-pixel units 410 arranged in an array. For example, the display device 1 also includes a display panel 40, in which a pixel array composed of a plurality of sub-pixel units 410 is disposed.

[0137] The output terminal OUT of each shift register unit 10 in the gate driving circuit 20 is electrically connected to the sub-pixel unit 410 of each row. For example, the gate driving circuit 20 is electrically connected to the sub-pixel unit 410 through a gate line GL. The gate driving circuit 20 is used to provide a driving signal to the pixel array, such as driving the scanning transistor and sensing transistor in the sub-pixel unit 410.

[0138] For example, the display device 1 may further include a data driving circuit 30 for providing data signals to the pixel array. For example, the data driving circuit 30 is electrically connected to the sub-pixel unit 410 via a data line DL.

[0139] It should be noted that the display device 1 in this embodiment can be any product or component with display function, such as a liquid crystal panel, liquid crystal TV, monitor, OLED panel, OLED TV, electronic paper display device, mobile phone, tablet computer, laptop computer, digital photo frame, navigator, etc.

[0140] The technical effects of the display device 1 provided by the embodiments of this disclosure can be referred to the corresponding description of the gate driving circuit 20 in the above embodiments, and will not be repeated here.

[0141] The following points should be noted regarding this disclosure:

[0142] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0143] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the drawings used to describe embodiments of the invention. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0144] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0145] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A shift register unit, comprising: The circuit consists of an input circuit, a first control circuit, an output circuit, an output noise reduction circuit, and a reset circuit; among which, The input circuit is connected to the input terminal and configured to control the level of the first node in response to an input signal input to the input terminal; The first control circuit is connected to the first node, the second node and the first clock signal terminal, and is configured to control the level of the second node under the control of the level of the first node and the first clock signal provided by the first clock signal terminal; The output circuit is connected to the output terminal and configured to output an output signal at the output terminal under the control of the level of the second node. The output noise reduction circuit is connected to the output terminal and is configured to reduce noise at the output terminal under the control of the level of the first node. The reset circuit is connected to the total reset terminal and the first voltage terminal, and is configured to turn off the output noise reduction circuit in response to the total reset signal provided by the total reset terminal, wherein the total reset signal is an invalid level in the first operation phase and includes at least one valid level in the second operation phase.

2. The shift register unit according to claim 1 further includes a second control circuit, wherein, The second control circuit is connected to the first node, the third node, and the second clock signal terminal, and is configured to control the level of the third node under the control of the level of the first node and the second clock signal provided by the second clock signal terminal; The output noise reduction circuit is also connected to the third node and configured to output an invalid level of the output signal at the output terminal in response to the level of the third node.

3. The shift register unit according to claim 2, wherein, The reset circuit is also connected to the third node and configured to reset the third node in response to a total reset signal provided by the total reset terminal, so as to turn off the output noise reduction circuit.

4. The shift register unit according to claim 2, wherein, The second control circuit includes a first sub-circuit; The first sub-circuit is connected to the first node, the second clock signal terminal, and the third node, and is configured to control the level of the third node under the control of the level of the first node.

5. The shift register unit according to claim 4, wherein, The second control circuit also includes a second sub-circuit; The second sub-circuit is connected to the second voltage terminal, the first node, and the first control node, and is configured to control the level of the first control node in response to the second voltage provided by the second voltage terminal; The first sub-circuit is also connected to the first control node and configured to control the level of the third node in response to the level of the first control node.

6. The shift register unit according to claim 5 further includes a third control circuit, wherein, The third control circuit is connected to the second node, the fourth node and the second clock signal terminal, and is configured to control the level of the fourth node under the control of the level of the second node and the second clock signal provided by the second clock signal terminal.

7. The shift register unit according to claim 6, wherein, The third control circuit includes a third sub-circuit and a fourth sub-circuit; The third sub-circuit is connected to the second clock signal terminal and the second control node, and is configured to control the level of the second control node under the control of the level of the second node; The fourth sub-circuit is connected to the second clock signal terminal, the second control node, and the fourth node, and is configured to control the level of the fourth node in response to the second clock signal provided by the second clock signal terminal.

8. The shift register unit according to claim 7, wherein, The third control circuit also includes a fifth sub-circuit. The fifth sub-circuit is connected to the second voltage terminal, the second node, and the third control node, and is configured to control the level of the third control node in response to the second voltage provided by the second voltage terminal; The third sub-circuit is also connected to the third control node and configured to control the level of the second control node in response to the level of the third control node.

9. The shift register unit according to claim 8, wherein, The second control circuit also includes a sixth sub-circuit. The sixth sub-circuit is connected to the second control node, the first voltage terminal, and the first sub-circuit, and is configured to respond to the level of the second control node and control the level of the first control node to remain stable.

10. The shift register unit according to claim 7 further includes a fourth control circuit, wherein, The fourth control circuit is connected to the first node, the first voltage terminal, and the fourth node, and is configured to control the level of the fourth node in response to the level of the first node.

11. The shift register unit according to claim 8 further includes a fifth control circuit, wherein, The fifth control circuit is connected to the second control node, the third node and the first voltage terminal, and is configured to control the level of the third node in response to the level of the second control node.

12. The shift register unit according to any one of claims 1-5 further includes a sixth control circuit, wherein, The sixth control circuit is connected to the total reset terminal, the first voltage terminal, and the first node, and is configured to reset the first node under the control of the reset signal provided by the total reset terminal.

13. The shift register unit according to any one of claims 1-5, wherein, The input circuit includes an input transistor. The gate of the input transistor is connected to the first clock signal terminal to receive the first clock signal, the first terminal of the input transistor is connected to the input terminal to receive the input signal, and the second terminal of the input transistor is connected to the first node.

14. The shift register unit according to claim 3, wherein, The reset circuit includes a reset transistor. The gate of the reset transistor is connected to the total reset terminal to receive the total reset signal, the first terminal of the reset transistor is connected to the first voltage terminal to receive the first voltage, and the second terminal of the reset transistor is connected to the third node.

15. The shift register unit according to claim 3, wherein, The output noise reduction circuit includes an output noise reduction transistor. The gate of the output noise reduction transistor is connected to the third node, the first terminal and the second voltage terminal of the output noise reduction transistor are connected to receive the second voltage, and the second terminal of the output noise reduction transistor is connected to the output terminal.

16. The shift register unit according to claim 15, wherein, The output noise reduction circuit also includes an output noise reduction capacitor. The first terminal of the output noise reduction capacitor is connected to the second voltage terminal to receive the second voltage, and the second terminal of the output noise reduction capacitor is connected to the third node.

17. The shift register unit according to claim 6, wherein, The output circuit includes an output transistor and an output capacitor; The gate of the output transistor is connected to the fourth node, the first terminal of the output transistor is connected to the output terminal, and the second terminal of the output transistor is connected to the first voltage terminal to receive the first voltage. The first terminal of the output capacitor is connected to the fourth node, and the second terminal of the output capacitor is connected to the first voltage terminal to receive the first voltage.

18. The shift register unit according to claim 9, wherein, The first sub-circuit includes a first control transistor, a second control transistor, and a first control capacitor; The gate of the first control transistor is connected to the first control node, the first terminal of the first control transistor is connected to the second clock signal terminal to receive the second clock signal, and the second terminal of the first control transistor is connected to the first terminal of the first control capacitor. The second terminal of the first control capacitor is connected to the first control node; The gate and first electrode of the second control transistor are connected to each other and both are connected to the first control node, and the second electrode of the second control transistor is connected to the third node.

19. The shift register unit according to claim 18, wherein, The second sub-circuit includes a third control transistor. The gate of the third control transistor is connected to the second voltage terminal, the first electrode of the third control transistor is connected to the first node, and the second electrode of the third control transistor is connected to the first control node.

20. The shift register unit according to claim 18, wherein, The sixth sub-circuit includes a fourth control transistor; The gate of the fourth control transistor is connected to the second control node, the first terminal of the fourth control transistor is connected to the first voltage terminal to receive the first voltage, and the second terminal of the fourth control transistor is connected to the first terminal of the first control capacitor.

21. The shift register unit according to claim 12, wherein, The sixth control circuit includes a fifth control transistor; The gate of the fifth control transistor is connected to the total reset terminal to receive the total reset signal, the first terminal of the fifth control transistor is connected to the first voltage terminal to receive the first voltage, and the second terminal of the fifth control transistor is connected to the first node.

22. The shift register unit according to any one of claims 1-5, wherein, The first control circuit includes a sixth control transistor and a seventh control transistor; The gate of the sixth control transistor is connected to the first node, the first terminal of the sixth control transistor is connected to the first clock signal terminal to receive the first clock signal, and the second terminal of the sixth control transistor is connected to the second node. The gate of the seventh control transistor is connected to the first clock signal terminal to receive the first clock signal, the first terminal and the second voltage terminal of the seventh control transistor are connected to receive the second voltage, and the second terminal of the seventh control transistor is connected to the second node.

23. The shift register unit according to claim 9, wherein, The third sub-circuit includes an eighth control transistor and a third control capacitor; the fourth sub-circuit includes a ninth control transistor; and the fifth sub-circuit includes a tenth control transistor. The gate of the tenth control transistor is connected to the second voltage terminal to receive the second voltage; the first terminal of the tenth control transistor is connected to the second node; and the second terminal of the tenth control transistor is connected to the third control node. The first terminal of the third control capacitor is connected to the third control node, and the second terminal of the third control capacitor is connected to the second control node; The gate of the eighth control transistor is connected to the third control node, the first terminal of the eighth control transistor is connected to the second clock signal terminal to receive the second clock signal, and the second terminal of the eighth control transistor is connected to the second control node. The gate of the ninth control transistor is connected to the second clock signal terminal to receive the second clock signal, the first terminal of the ninth control transistor is connected to the second control node, and the second terminal of the ninth control transistor is connected to the fourth node.

24. The shift register unit according to claim 10, wherein, The fourth control circuit includes an eleventh control transistor. The gate of the eleventh control transistor is connected to the first node, the first terminal of the eleventh control transistor is connected to the fourth node, and the second terminal of the eleventh control transistor is connected to the first voltage terminal to receive the first voltage.

25. The shift register unit according to claim 11, wherein, The fifth control circuit includes a twelfth control transistor. The gate of the twelfth control transistor is connected to the second control node, the first terminal of the twelfth control transistor is connected to the third node, and the second terminal of the twelfth control transistor is connected to the first voltage terminal to receive the first voltage.

26. A gate drive circuit comprising a plurality of cascaded shift register units as described in any one of claims 1-25.

27. A driving method for a shift register unit as described in claim 1, comprising a first operation phase and a second operation phase; in, In the first operation phase, the driving method includes a first sub-phase, a second sub-phase, and a third sub-phase: In the first sub-stage, the input circuit controls the level of the first node in response to the effective level of the input signal input at the input terminal; The first control circuit controls the level of the second node under the control of the level of the first node and the first clock signal provided by the first clock signal terminal; In the second sub-stage, the output circuit outputs an output signal at the output terminal under the control of the level of the second node; In the third sub-stage, the output noise reduction circuit reduces noise at the output terminal under the control of the level of the first node; In the second operation phase, the driving method includes at least one reset phase. During the at least one reset phase, an active level of the total reset signal is applied to the total reset terminal, and an inactive level of the first clock signal is applied to the first clock signal terminal. The reset circuit responds to the effective level of the total reset signal, causing the output noise reduction circuit to turn off.

28. The driving method according to claim 27, wherein, In the case where the shift register unit further includes a second control circuit, the second control circuit is connected to the first node, the third node, and the second clock signal terminal, and is configured to control the level of the third node under the control of the level of the first node and the second clock signal provided by the second clock signal terminal; The output noise reduction circuit is also connected to the third node and configured to output an invalid level of the output signal at the output terminal in response to the level of the third node. The reset phase further includes: applying an invalid level of the second clock signal to the second clock signal terminal. The reset circuit, in response to the effective level of the total reset signal, resets the third node so that the output noise reduction circuit is turned off in response to the level of the third node.

29. A display device comprising the gate driving circuit as described in claim 26.

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