A highly symmetrical data transmission architecture

Abstract

The present invention provides a highly symmetrical data transmission architecture, comprising: a standard digital delay array, whose input terminal receives a transmit signal, a first output control terminal connected to a fixed delay module, and an output terminal of the fixed delay module connected to a falling edge detection terminal of a driver receiving unit; a first D-type flip-flop array, whose first input terminal is connected to the output terminal of the driver receiving unit and whose second input terminal is connected to the standard digital delay array; a transmit falling delay signal and a receive falling delay signal, sampled by the first D-type flip-flop array, to obtain a transmit reference signal equal to the falling delay of the receive falling delay signal; and a trigger unit, configured to receive the transmit reference signal and the receive rising delay signal. The output of the trigger unit uses the generated transmit reference signal to adjust the receive rising delay signal of the standard digital delay array so that the rising edge delay is equal to the falling edge delay. The present invention can significantly improve the symmetry of data transmission in a transceiver.

Description

Technical Field

[0001] The present invention relates to the technical field of bus interface networks, and in particular to a highly symmetrical data transmission architecture. Background Art

[0002] In industrial control and in-vehicle networks, buses, such as the CAN bus and RS485 bus, are often used to transmit signals. A transmitter sends a signal to the bus, which is then received by a receiver. This delay occurs between the transmitted and received signals. The signal rise and fall delays often differ, resulting in different duty cycles for the transmitted and received signals and causing delay variation. This delay variation can fluctuate with power supply, temperature, and process variations, making it uncontrollable and unable to meet strict transmission symmetry standards, such as CiA 601-4 (CAN in Automation (CiA) 601 Part 4: Signal Improvement). Summary of the Invention

[0003] In view of this, an embodiment of the present application provides a highly symmetrical data transmission architecture, which can make the delay of the rising edge of the signal consistent with the delay of the falling edge, so as to significantly improve the symmetry of the data transmitted by the transceiver.

[0004] The present application provides the following technical solution: a highly symmetric data transmission architecture, including a delay adjustment loop, wherein the delay adjustment loop includes:

[0005] A standard digital delay array, wherein an input terminal of the standard digital delay array is connected to a transmission signal, a first output control terminal of the standard digital delay array is connected to a fixed delay module, and an output terminal of the fixed delay module is connected to a falling edge detection terminal of a driving and receiving unit; after the falling edge of the transmission signal passes through a fixed falling delay time, a transmission falling delay signal generated is transmitted to the driving and receiving unit, and the receiving falling delay signal is outputted by the driving and receiving unit;

[0006] a first D flip-flop array, wherein a first input end of the first D flip-flop array is connected to an output end of the driving receiving unit for receiving the receiving fall delay signal, and a second input end of the first D flip-flop array is connected to the standard digital delay array for receiving the sending fall delay signal array; using the receiving fall delay signal to sample a plurality of different sending fall delay signals via the first D flip-flop array, and the sampling results are screened by a first selection unit to obtain a sending reference signal having a fall delay equal to the receiving fall delay signal;

[0007] a trigger unit, wherein an input end of the trigger unit is connected to the output end of the first selection unit and the output end of the driving and receiving unit, respectively, and is used to receive the sending reference signal and the receiving rising delay signal generated by the driving and receiving unit, and an output end of the trigger unit is connected to the second selection unit;

[0008] The second output control terminal of the standard digital delay array of the second selection unit is used to adjust the rising delay time of the standard digital delay array according to the output result of the trigger unit, and output it to the rising edge detection terminal of the driving and receiving unit, thereby forming the delay adjustment loop, so that the delay times of the transmitted signal and the received signal are consistent.

[0009] According to one embodiment of the present application, the trigger unit includes a D flip-flop, a first input end of the D flip-flop is connected to the output end of the first selection unit for receiving the sending reference signal, a second input end of the D flip-flop is connected to the output end of the driving receiving unit for receiving the receiving rising delay signal generated by the driving receiving unit, and the receiving rising delay signal is sampled by the D flip-flop using the sending reference signal, and the sampling result is transmitted to the second selection unit for screening;

[0010] The second selection unit is connected to screen out standard digital delay units with a rising delay equal to that of the transmitted reference signal, adjusts the rising delay time of the standard digital delay array, and outputs it to the rising edge detection end of the driving and receiving unit.

[0011] According to one embodiment of the present application, the trigger unit includes a second D flip-flop array, a third D flip-flop array, and a subtractor, wherein the input end of the second D flip-flop array is connected to the output end of the driving and receiving unit and the rising delay signal of the transmission signal, and the third D flip-flop array is connected to the output end of the first selection unit and the rising delay signal of the transmission signal, and is used to use the transmission reference signal output by the first selection unit and the reception rising delay signal generated by the driving and receiving unit to sample the rising delay signals of multiple different transmission signals;

[0012] The output ends of the second D flip-flop array and the third D flip-flop array are respectively connected to the subtractor, and the output end of the subtractor is connected to a second selection unit; the sampling results of the second D flip-flop array and the third D flip-flop array are passed through the subtractor to obtain a delay difference, and the second selection unit adjusts the rising delay time of the standard digital delay array according to the delay difference and outputs it to the rising edge detection end of the driving and receiving unit.

[0013] According to one embodiment of the present application, the first selection unit includes an XOR gate array and a first multi-way switch array, the input end of the XOR gate array is connected to the output end of the first D-type flip-flop array, the output end of the XOR gate array is connected to the input end of the first multi-way switch array, and the output end of the first multi-way switch array is connected to the input end of the trigger unit; the sampling results of the first D-type flip-flop array are connected to the first multi-way switch array after adjacent signals are XORed in pairs by the XOR gate array, and a sending reference signal equal to the falling delay of the received falling delay signal is screened.

[0014] According to one embodiment of the present application, the driving receiving unit includes an edge detector, a driver and a receiving module connected in sequence, the falling edge detection end of the edge detector is connected to the fixed delay module, and the rising edge detection end of the edge detector is connected to the second selection unit; the output end of the receiving module is respectively connected to the first D flip-flop array and the trigger unit.

[0015] According to one embodiment of the present application, the delay adjustment loop also includes a first inverter and a second inverter, the input end of the first inverter is connected to the output end of the receiving module, the output end of the first inverter is respectively connected to the input end of the second inverter and the input end of the first D trigger array, and the output end of the second inverter is connected to the input end of the trigger unit.

[0016] According to an embodiment of the present application, the second selection unit includes a second multi-way switch array, which is used to select the output result of the trigger unit and adjust the rise delay time of the standard digital delay array.

[0017] Compared to existing technologies, the highly symmetrical data transmission architecture of the present invention provides an adaptive transmit / receive architecture. By constructing a reference signal RXD_Ref with equal rising and falling edge delays, and employing a standard digital delay cell array, the generated reference signal is used to adjust the rising delay of the received signal, ensuring that the rising edge delay is equal to the falling edge delay. By self-adjusting the standard digital delay cells, the duty cycle of the transmit and receive signals remains consistent, independent of process and environmental fluctuations such as voltage and temperature. This significantly improves the symmetry of the transceiver's transmitted data, meeting stringent standards such as the symmetry requirements for transmit, bus, and receive data as specified in CiA 601-4. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 This is an illustration of the transceiver symmetry indicators proposed by the CiA601-4 standard;

[0020] Figure 2 This is the highly symmetric data transmission architecture proposed in the first embodiment of the present invention;

[0021] Figure 3 The voltage waveforms of nodes at each level of the architecture proposed in the first embodiment of the present invention;

[0022] Figure 4 This is a highly symmetric data transmission architecture proposed in the second embodiment of the present invention;

[0023] Figure 5 The voltage waveforms of nodes at each level of the architecture proposed in the second embodiment of the present invention are shown. DETAILED DESCRIPTION

[0024] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0025] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of this application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments, and the technical solutions of the present invention will be clearly and completely described. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0026] like Figure 1 As shown, Figure 1The figure shows the transceiver symmetry metrics proposed by the CiA 601-4 standard. The transmit signal first generates a low-level signal for 5 Tbits, followed by a high-level signal for one Tbit. The driver drives the bus in response, and the differential bus Vdiff, after a delay, follows the transmit signal. The receiver then detects the bus voltage and outputs the receive signal RXD. The input signal TXD, bus, and receive signal RXD are sampled, and the Tbit(TXD), Tbit(bus), and Tbit(RXD) times are measured. CiA 601-4 requires that the error between Tbit(bus) and Tbit(TXD) must be within + / -10ns, the error between Tbit(RXD) and Tbit(bus) must be within -20ns to +15ns, and the error between Tbit(RXD) and Tbit(TXD) must be within -30ns to +20ns.

[0027] The present invention provides a highly symmetrical data transmission architecture. The input transmit signal first passes through a fixed standard digital delay unit before being fed to a driver. The driver drives the bus, and the receiver listens to the bus and generates a receive signal. This signal is used to sample the falling edges of different input signal delay units. A multiplexer selects a reference signal RXD_Ref with the same delay as the falling edge of the receive signal (the rising and falling delays of this signal are equal). This reference signal is then used to select standard digital delay units with the same rising edge delay. When the next signal cycle begins or after several cycles of adjustment, the rising and falling delay times become equal, and the duty cycles of the transmitted and received signals remain consistent.

[0028] like Figure 2 As shown, an embodiment of the present invention provides a highly symmetrical data transmission architecture, including: a delay adjustment loop, wherein the delay adjustment loop includes:

[0029] A standard digital delay array 20, wherein the input terminal of the standard digital delay array 20 is connected to a transmission signal, the first output control terminal of the standard digital delay array 20 is connected to a fixed delay module 21, and the output terminal of the fixed delay module 21 is connected to a falling edge detection terminal of a driver receiving unit. After the falling edge of the transmission signal passes through a fixed falling delay time, the generated transmission falling delay signal is transmitted to the driver receiving unit, and the driver receiving unit outputs the reception falling delay signal.

[0030] a first D flip-flop array 26, wherein a first input end of the first D flip-flop array 26 is connected to the output end of the driving receiving unit for receiving the received fall delay signal, and a second input end of the first D flip-flop array 26 is connected to the standard digital delay array 20 for receiving the transmitted fall delay signal array; the received fall delay signal is used to sample a plurality of different transmitted fall delay signals via the first D flip-flop array 26, and the sampling results are filtered by a first selection unit to obtain a transmitted reference signal having a fall delay equal to the received fall delay signal;

[0031] a trigger unit, wherein an input end of the trigger unit is connected to the output end of the first selection unit and the output end of the driving and receiving unit, respectively, and is used to receive the sending reference signal and the receiving rising delay signal generated by the driving and receiving unit, and an output end of the trigger unit is connected to the second selection unit;

[0032] The second selection unit is connected to the second output control terminal of the standard digital delay array 20 and is used to adjust the rising delay time of the standard digital delay array 20 according to the output result of the trigger unit and output it to the rising edge detection terminal of the driving and receiving unit, forming the delay adjustment loop so that the delay times of the transmitted signal and the received signal are consistent.

[0033] In this embodiment, the trigger unit includes a D trigger 2a, a first input end of the D trigger 2a is connected to the output end of the first selection unit, and is used to receive the sending reference signal. The second input end of the D trigger 2a is connected to the output end of the driving and receiving unit, and is used to receive the receiving rising delay signal generated by the driving and receiving unit. The receiving rising delay signal is sampled by the D trigger 2a using the sending reference signal, and the sampling result is transmitted to the second selection unit for screening; the second selection unit is connected to screen out a standard digital delay unit with a rising delay equal to that of the sending reference signal, adjusts the rising delay time of the standard digital delay array 20, and outputs it to the rising edge detection end of the driving and receiving unit.

[0034] In this embodiment, the first selection unit includes an XOR gate array 27 and a first multi-way switch array 28. The input end of the XOR gate array 27 is connected to the output end of the first D-type flip-flop array 26, the output end of the XOR gate array 27 is connected to the input end of the first multi-way switch array 28, and the output end of the first multi-way switch array 28 is connected to the input end of the D-type flip-flop 2a. The sampling results of the first D-type flip-flop array 26 are connected to the first multi-way switch array 28 after adjacent signals are XORed in pairs by the XOR gate array 27 to obtain a transmission reference signal equal to the fall delay of the received fall delay signal.

[0035] In this embodiment, the driving receiving unit includes an edge detector 22, a driver 23 and a receiving module 24 connected in sequence, the falling edge detection end of the edge detector 22 is connected to the fixed delay module 21, and the rising edge detection end of the edge detector 22 is connected to the second selection unit; the output end of the receiving module 24 is respectively connected to the first D flip-flop array 26 and the D flip-flop 2a.

[0036] In this embodiment, the delay adjustment loop also includes a first inverter 25 and a second inverter 29, the input end of the first inverter 25 is connected to the output end of the receiving module 24, the output end of the first inverter 25 is respectively connected to the input end of the second inverter 29 and the input end of the first D trigger array 26, and the output end of the second inverter 29 is connected to the input end of the D trigger 2a.

[0037] In this embodiment, the second selection unit includes a second multi-way switch array 2 b, which is used to select the output result of the D flip-flop 2 a and adjust the rise delay time of the standard digital delay array 20 .

[0038] Combine Figure 2 As shown, in the highly symmetric data transmission architecture proposed in the first embodiment of the present invention, the transmit signal TXD is first input into the standard digital delay array 20. After a fixed delay, the TXD_Delay_fixed signal is connected to the falling edge detection port of the edge detector 22 and then provided to the driver 23 and the receiving module 24. The output RXD_Delay_fixed signal of the receiving module 24 is sampled by the first D-type flip-flop array 26 on the falling edge signals of different TXD_Delay_Arrays. The adjacent signals are then XORed with each other by the XOR gate array 27 and then connected to the first multiplexer array 28 to select the TXD_Ref signal with the same falling delay as the RXD_Delay_fixed signal. This signal is then sampled by the D-type flip-flop 2a on the rising edge of the RXD signal and then output to the second multiplexer array module 2b for incrementing or decrementing the standard delay unit. The output end is then connected to the rising edge detection port of the edge detector 22. The edge detector 22 synthesizes the signals from the two input ports into a new signal and provides it to the driver 23. This cycle repeats until the delay time of the transmit signal TXD is consistent with that of the receive signal RXD. According to the transceiver symmetry index requirements proposed by CiA 601-4, appropriate standard delay units are selected to ensure that the result is both fast and meets the standard requirements.

[0039] Attachment Figure 3The voltage waveforms of the key nodes at each level of the architecture of the first embodiment of the present invention are shown in FIG. The falling edge of TXD is given to the driving module after a fixed falling delay time TXD_Delay_fixed. The receiving module will output the corresponding RXD falling signal. The RXD falling signal is used to sample the TXD falling edge signal array to obtain a TXD_Ref signal that is identical to the RXD falling edge signal. The rise delay and fall delay of this signal are the same. The rising edge of the TXD_Ref signal is then used to sample the output RXD signal. If the sampling result is a high level, it means that the rise delay is less than the fall delay. In this case, the standard delay unit connected to the rising edge of TXD is increased, so that the rise delay increases, until the sampling result becomes a low level. If the sampling result is a low level, it means that the rise delay is greater than the fall delay. In this case, the standard delay unit connected to the rising edge of TXD is reduced, so that the rise delay decreases, until the sampling result becomes a high level. The rise delay and fall delay of the final output signal are no more than one standard delay unit.

[0040] like Figure 4 As shown, in the second embodiment of the present invention, the trigger unit includes a second D flip-flop array 4a, a third D flip-flop array 4b and a subtractor 4c, the input end of the second D flip-flop array 4a is connected to the output end of the driving and receiving unit and the rising delay signal of the transmission signal, and the third D flip-flop array 4b is connected to the output end of the first selecting unit and the rising delay signal of the transmission signal, and is configured to sample a plurality of different rising delay signals of the transmission signal by using the transmission reference signal output by the first selecting unit and the reception rising delay signal generated by the driving and receiving unit;

[0041] The output ends of the second D flip-flop array 4a and the third D flip-flop array 4b are respectively connected to the subtractor 4c, and the output end of the subtractor 4c is connected to a second selection unit; it is used to obtain a delay difference between the sampling results of the second D flip-flop array 4a and the third D flip-flop array 4b after passing through the subtractor 4c, and the second selection unit adjusts the rising delay time of the standard digital delay array 40 according to the delay difference and outputs it to the rising edge detection end of the driving and receiving unit.

[0042] Figure 4The highly symmetrical data transmission architecture proposed in the second embodiment of the present invention is shown in FIG. The transmit signal TXD is first input to the standard digital delay array 40. After a fixed delay, the TXD_Delay_fixed signal is connected to the falling edge detection port of the edge detector 42, and then to the driver 43 and the receiving module 44. The RXD_Delay_fixed signal output by the receiving module 44 is sampled by the first D flip-flop array 46 for the falling edge signals of different TXD_Delay_Arrays. The adjacent signals are then XORed with each other by the XOR gate array 47, and then connected to the first multiplexer array 49 to select the signal that matches the RXD_Delay_fixed signal. The TXD_Ref signal with the same fixed falling delay is then sampled using the TXD_Ref and RXD signals via the second D flip-flop array 4a and the third D flip-flop array 4b, respectively, to sample the rising edge of the TXD_Delay_Array signal. The two results are fed back to the TXD standard digital delay array 40 after passing through the subtractor 4c to adjust the rising delay time of the TXD signal. The delay difference is then connected to the rising edge detection port of the edge detector 42. The edge detector 42 synthesizes the signals from the two input ports into a new signal and then feeds it to the driver 43 for subsequent transmission.

[0043] Attachment Figure 5 The figure shows the voltage waveforms at each key node of the second embodiment of the present invention. The falling edge of TXD is fed to the driver module after a fixed falling delay time, TXD_Delay_fixed. The receiving module then outputs a corresponding RXD falling signal. This RXD falling signal is used to sample the TXD falling edge signal array, generating a TXD_Ref signal identical to the RXD falling edge signal. This signal has the same rise and fall delays. The TXD_Ref signal and the RXD signal are then used to sample the rising edge signal of the TXD delay array. The sampling results are passed through a subtractor to generate a difference, DeltaTXD_Delay, which is fed back to the TXD delay array. This allows for a one-time adjustment of the standard delay unit connected to the TXD rising edge. After one cycle, the rise and fall delay times of the output signal will be equal.

[0044] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A highly symmetric data transmission architecture, characterized in that: include: A delay adjustment loop, the delay adjustment loop comprising: A standard digital delay array, wherein an input terminal of the standard digital delay array is connected to a transmission signal, a first output control terminal of the standard digital delay array is connected to a fixed delay module, and an output terminal of the fixed delay module is connected to a falling edge detection terminal of a driving and receiving unit; after the falling edge of the transmission signal passes through a fixed falling delay time, a transmission falling delay signal generated is transmitted to the driving and receiving unit, and the receiving falling delay signal is outputted by the driving and receiving unit; a first D flip-flop array, wherein a first input end of the first D flip-flop array is connected to an output end of the driving receiving unit for receiving the receiving fall delay signal, and a second input end of the first D flip-flop array is connected to the standard digital delay array for receiving the sending fall delay signal array; using the receiving fall delay signal to sample a plurality of different sending fall delay signals via the first D flip-flop array, and the sampling results are screened by a first selection unit to obtain a sending reference signal having a fall delay equal to the receiving fall delay signal; a trigger unit, wherein an input end of the trigger unit is connected to the output end of the first selection unit and the output end of the driving and receiving unit, respectively, and is used to receive the sending reference signal and the receiving rising delay signal generated by the driving and receiving unit, and an output end of the trigger unit is connected to the second selection unit; The second selection unit is connected to the second output control terminal of the standard digital delay array, and is used to adjust the rising delay time of the standard digital delay array according to the output result of the trigger unit, and output it to the rising edge detection terminal of the driving and receiving unit, thereby forming the delay adjustment loop, so that the delay times of the transmitted signal and the received signal are consistent.

2. The highly symmetric data transmission architecture according to claim 1, characterized in that: The trigger unit includes a D flip-flop, wherein a first input end of the D flip-flop is connected to the output end of the first selection unit for receiving the sending reference signal, and a second input end of the D flip-flop is connected to the output end of the driving receiving unit for receiving the receiving rising delay signal generated by the driving receiving unit. The sending reference signal is used to sample the receiving rising delay signal via the D flip-flop, and the sampling result is transmitted to the second selection unit for screening; The second selection unit selects a standard digital delay unit having a rising delay equal to that of the transmitted reference signal, adjusts the rising delay time of the standard digital delay array, and outputs the adjusted delay time to the rising edge detection terminal of the driving and receiving unit.

3. The highly symmetric data transmission architecture according to claim 1, wherein: The trigger unit includes a second D flip-flop array, a third D flip-flop array and a subtractor, wherein the input end of the second D flip-flop array is connected to the output end of the driving and receiving unit and the rising delay signal of the transmission signal, and the third D flip-flop array is connected to the output end of the first selecting unit and the rising delay signal of the transmission signal, and is used to sample a plurality of different rising delay signals of the transmission signal by using the transmission reference signal output by the first selecting unit and the reception rising delay signal generated by the driving and receiving unit; The output ends of the second D flip-flop array and the third D flip-flop array are respectively connected to the subtractors, and the output ends of the subtractors are connected to the second selection unit; The second selection unit is used to obtain a delay difference between the sampling results of the second D flip-flop array and the third D flip-flop array after passing through the subtractor, and adjust the rising delay time of the standard digital delay array according to the delay difference, and output it to the rising edge detection end of the driving and receiving unit.

4. The highly symmetric data transmission architecture according to claim 1, wherein: The first selection unit includes an XOR gate array and a first multi-way switch array. The input end of the XOR gate array is connected to the output end of the first D-type flip-flop array, the output end of the XOR gate array is connected to the input end of the first multi-way switch array, and the output end of the first multi-way switch array is connected to the input end of the trigger unit. The sampling results of the first D-type flip-flop array are connected to the first multi-way switch array after adjacent signals are XORed in pairs by the XOR gate array to obtain a transmission reference signal equal to the fall delay of the received fall delay signal.

5. The highly symmetric data transmission architecture according to claim 1, wherein: The driving receiving unit includes an edge detector, a driver and a receiving module connected in sequence, the falling edge detection end of the edge detector is connected to the fixed delay module, and the rising edge detection end of the edge detector is connected to the second selection unit; the output end of the receiving module is respectively connected to the first D flip-flop array and the trigger unit.

6. The highly symmetric data transmission architecture according to claim 5, characterized in that: The delay adjustment loop also includes a first inverter and a second inverter, the input end of the first inverter is connected to the output end of the receiving module, the output end of the first inverter is respectively connected to the input end of the second inverter and the input end of the first D flip-flop array, and the output end of the second inverter is connected to the input end of the trigger unit.

7. The highly symmetric data transmission architecture according to claim 1, wherein: The second selection unit includes a second multi-way switch array, which is used to select the output result of the trigger unit and adjust the rise delay time of the standard digital delay array.

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