Metadata management for abnormal shutdown of the memory subsystem

Abstract

This invention relates to metadata management for abnormal shutdowns of a memory subsystem. It maintains a logical-to-physical (L2P) data structure and a physical-to-logical (P2L) data structure. The L2P data structure includes entries mapping logical addresses to physical addresses. The P2L data structure includes data items mapping physical addresses to logical addresses. Each P2L data item also includes a data movement status, a base address, and a boundary indicator. A movement operation is detected, indicating that data referenced by a logical address will be moved from a source physical address to a target physical address. In response to detecting the movement operation, the data movement status associated with the source physical address in the P2L data structure is updated.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to a memory subsystem, and more specifically, to metadata management for abnormal shutdown of a memory subsystem. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of this disclosure provides a system comprising: a plurality of memory devices; and a processing means operatively coupled to the memory devices to perform operations including: maintaining on one of the plurality of memory devices a logical-to-physical L2P data structure comprising a plurality of (L2P) entries, each L2P entry mapping a logical address to a physical address identifying a super management unit (SMU) on one of the plurality of memory devices; maintaining on the memory devices a physical-to-logical P2L data structure comprising a plurality of (P2L) entries, each P2L entry mapping a physical address identifying an SMU on the memory device to a corresponding logical address, wherein the P2L entries include a data movement state, a base address, and a boundary indicator; detecting an SMU movement operation, wherein the SMU movement operation indicates that data referenced by a logical SMU (LSMU) will move from a source physical SMU (PSMU) to a target PSMU; and updating the data movement state associated with the source PSMU in the P2L data structure in response to detecting the SMU movement operation.

[0004] Another aspect of this disclosure provides a method comprising: performing a scan of a physical-to-logical (P2L) data structure of a memory subsystem, wherein the P2L data structure includes one or more P2L entries, wherein the P2L entries map physical addresses of identified super management units (SMUs) on a memory device to corresponding logical addresses, and wherein the P2L entries include data movement states and boundary indicators; in response to identifying in the P2L data structure a first entry including a first data movement state indicating that the first entry is associated with an SMU movement as a target physical SMU (PSMU), identifying a first boundary indicator associated with the first entry; identifying a plurality of management units (MUs) referenced by the SMU, wherein each of the plurality of MUs includes a second boundary indicator; identifying a subset of MUs among the plurality of MUs having corresponding second boundary indicators that do not match the first boundary indicator; and performing the SMU movement for each MU in the subset of MUs.

[0005] Another aspect of this disclosure provides a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: maintaining a logical-to-physical L2P data structure comprising a plurality of (L2P) entries on a memory device of a memory subsystem, each L2P entry mapping a logical address to a physical address identifying a super management unit (SMU) on the memory device; maintaining a physical-to-logical P2L data structure comprising a plurality of (P2L) entries on the memory device, each P2L entry mapping a physical address identifying an SMU on the memory device to a corresponding logical address, wherein a P2L entry includes a data movement state, a base address, and a boundary indicator; detecting an SMU movement operation, wherein the SMU movement operation indicates that data referenced by a logical SMU (LSMU) will move from a source physical SMU (PSMU) to a target PSMU; and updating the data movement state associated with the source PSMU in the P2L data structure in response to detecting the SMU movement operation. Attached Figure Description

[0006] This disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are merely for illustration and understanding.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This document describes a physical-to-logical mapping table, a logical-to-physical mapping table, and a management unit mapping table according to some embodiments of this disclosure.

[0009] Figure 3 A block diagram illustrating an implementation of a method performed by a computer system for updating a metadata table in case of an abnormal shutdown, according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart of an example method for performing a super management unit movement operation according to some embodiments of the present disclosure.

[0011] Figure 5 This is a flowchart illustrating an example method for performing a recovery procedure after an abnormal shutdown, according to some embodiments of this disclosure.

[0012] Figure 6 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0013] This disclosure relates to metadata management for abnormal shutdown of a memory subsystem. The memory subsystem may be a storage device, a memory module, or a combination of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] The memory subsystem may include high-density non-volatile memory devices, where data needs to be retained when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits being stored. Logic states may be represented by binary values ​​such as “0” and “1” or combinations of such values.

[0015] A memory device may consist of bits arranged in a two-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell. Hereinafter, a block refers to a cell of the memory device used to store data and may include a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks may be grouped together to form a plane of the memory device to allow concurrent operation on each plane. The memory device may include circuitry for performing concurrent memory page accesses on two or more memory planes. For example, the memory device may include corresponding access line driver circuitry and power circuitry for each plane of the memory device to facilitate concurrent access to pages in two or more memory planes containing different page types.

[0016] Data operations can be performed by the memory subsystem. Data operations can be host-initiated. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on a memory device at the memory subsystem and to read data from a memory device on the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may include a logical address (e.g., logical block address (LBA) and namespace) for the host data, which is the location associated with the host data by the host system. Logical address information (e.g., LBA, namespace) may be part of the metadata for the host data. The metadata may also include error handling data (e.g., ECC codewords, parity codes), data version (e.g., age to distinguish the data being written), a validity bitmap (specifying which LBAs contain valid data), etc.

[0017] To isolate various aspects of the physical implementation of the memory devices employed by the memory subsystem from the host system, the memory subsystem may maintain a data structure that maps each logical address to a corresponding physical address. In some implementations, the physical address may include a channel identifier, die identifier, page identifier, plane identifier, and / or frame identifier. This mapping data structure is referred to herein as a logic-to-physical (L2P) table. The memory subsystem may also maintain a data structure that maps each physical address to a logical address. This mapping data structure is referred to herein as a physical-to-logic (P2L) table. Both the P2L and L2P tables are collectively referred to herein as the address mapping data structure.

[0018] In some types of memory devices (e.g., NAND), pages can be grouped to form blocks. In other types of memory devices (e.g., 3D crossover), pages can be grouped across dies and channels to form management units (MUs). Therefore, each entry in the address-mapped data structure can refer to a management unit (MU), which contains one or more pages grouped together for management purposes (e.g., a set of pages, crossover channels, dies, and / or partitions). Additionally, in some types of memory devices (e.g., 3D crossover), management units can be grouped together to form super management units (SMUs). Therefore, the address-mapped data structure can map physical SMUs (PSMUs) to logical SMUs (LSMUs) and vice versa.

[0019] Address-mapped data structures are maintained by the firmware of the memory subsystem controller and stored on one or more non-volatile memory devices of the memory subsystem. To improve the overall efficiency of data transfer between the host system and the memory subsystem, the address-mapped data structures may be cached at least partially by one or more volatile memory devices of the memory subsystem. In some memory subsystems, to maintain data integrity, the address-mapped data structures stored on one or more volatile memory devices are periodically stored on or copied to non-volatile memory devices. The process of storing the address-mapped data structures to non-volatile memory devices is called metadata dumping. Any mapping updates performed during metadata dumping are not stored on non-volatile memory devices, which can lead to potential data loss in the event of abnormal shutdown.

[0020] An abnormal shutdown occurs when the memory subsystem is shut down (or powered off) without following a predefined shutdown procedure. The predefined shutdown procedure may include operations to ensure data integrity. For example, a portion of the predefined shutdown procedure may include ensuring that data stored in volatile memory is written to non-volatile memory. For example, system metadata (including address-mapped data structures) may be maintained in volatile memory (e.g., cache memory) and may occasionally be written to non-volatile memory. If an abnormal shutdown occurs before the system metadata is written to non-volatile memory, a recovery procedure can be performed at the next power-on event to recover any lost metadata. For example, the recovery procedure may include scanning the metadata overhead of the physical addresses stored on the non-volatile memory device to reconstruct the physical-to-logical mapping information.

[0021] For example, in some memory devices within a memory subsystem (e.g., NAND), the access unit of the memory device may be 4 kilobytes. A physical address identifies a page within the memory device, and each page can store approximately 4 kilobytes of host data plus overhead bytes to store metadata for the host data, including (e.g.) error handling data (e.g., ECC codewords, parity codes), data version, valid bitmaps, etc. The page referenced by the physical address can store the associated logical address as part of the metadata overhead. Some memory subsystems can access the physical address on a non-volatile memory device to determine if the mapped data structure is valid after an abnormal shutdown, and can further use the metadata overhead to reconstruct the mapped data structure.

[0022] Some memory devices within the memory subsystem are not byte-addressable. For example, some memory devices (e.g., 3D crosspoints) have 64-byte access units. These memory devices do not have enough storage space to store the same amount of metadata overhead as a memory device with 4 kilobytes of access units. That is, if each physical address references 64 bytes of data, then using the extra bytes per physical address to store metadata overhead would result in more space being used to store the overhead than to store the actual data. Consequently, some memory subsystems cannot rely on metadata overhead to reconstruct valid mapped data structures after an abnormal shutdown. Furthermore, frequent metadata dumps can degrade performance and adversely affect the quality of service of the memory subsystem.

[0023] This disclosure addresses the above and other deficiencies by having a memory subsystem that manages address-mapped data structures in a manner that prevents data loss in the event of an abnormal shutdown. The memory subsystem controller stores a physical-to-logical (P2L) table on a volatile memory device and uses it as the primary mapping data structure between the physical and logical addresses of a particular memory device. The metadata management system also stores a logical-to-physical (L2P) table on the volatile memory device. To maintain system metadata integrity, the metadata management system stores backups or copies of the P2L and L2P tables on a non-volatile memory device within the memory subsystem. In the event of an abnormal shutdown, the metadata management system can rely on the L2P and P2L table storage on the non-volatile memory device to recover any data that may be lost due to the abnormal shutdown.

[0024] To ensure metadata integrity, the P2L and L2P tables stored on volatile memory devices should match those stored on non-volatile memory devices. Sometimes, the memory subsystem controller performs media management operations to manage physical wear and tear on memory devices and extend the overall lifetime of the memory subsystem. For example, the memory subsystem controller may perform media management operations (e.g., wear leveling operations) to distribute physical wear across data cells of the memory device. Media management operations may involve moving data from one (source) physical address to another (destination) physical address on the memory device. Moving data from the source physical address to the destination physical address involves updating the P2L and L2P tables to ensure that logical addresses point to the correct physical addresses (i.e., updating logical addresses to point to the destination physical address after the move). During data movement, the L2P and P2L tables on the volatile memory device may not match those on the non-volatile memory device, potentially leading to data loss in the event of an abnormal shutdown. In this case, the metadata management system can ensure that the tables on the non-volatile memory device are recoverable without data loss.

[0025] To ensure the availability of tables on recoverable non-volatile memory devices, the metadata management system can store movement status in P2L entries associated with source physical addresses. Movement status indicates whether a P2L entry is associated with an ongoing data movement and whether the physical address specified by the P2L entry is a source or destination physical address. The metadata management system can further store boundary indicators associated with each physical address. Boundary indicators can be a one-bit data field and can be used to track which data has been moved from the source physical address to the destination physical address. For example, if the data referenced by the entry has been moved to the destination address, the boundary indicator can be "0", and if the data has not been moved, the boundary indicator can be "1". In some implementations, a boundary indicator of "1" indicates that the data has been moved and "0" indicates that it has not been moved. After an abnormal shutdown, the metadata management system can identify the boundary indicators and can resume movement operations from the identified boundary indicators indicating that the data referenced by the physical address has not been moved. The metadata management system can update the mapping of the destination physical address in the P2L table to point to a logical address and further update the status associated with the destination physical address entries in the P2L table.

[0026] A metadata management system can cause data to be moved by copying data from a source physical address to a target physical address. After the move, the metadata management system can update the L2P table on both the volatile and non-volatile memory devices to reflect the data move. That is, the logical address associated with the moved data now points to the target physical address. The metadata management system can then update the P2L table entry associated with the source physical address on both the volatile and non-volatile memory devices. The metadata management system can unmap the source physical address and update the move status associated with the source physical address to indicate that it no longer involves data movement. In one example, the metadata management system can unmap the source physical address to a default value by updating the source physical address table entry in both the P2L and L2P tables to a default value. The default value can be randomly generated or can be a predefined value that indicates to the memory subsystem that the unmapping entry is no longer involved. Finally, the metadata management system can update the move status associated with the target physical address to indicate that it no longer involves data movement operations on both the volatile and non-volatile memory devices.

[0027] Following an abnormal shutdown, at the point of power-on, the metadata management system can use P2L and L2P tables stored on a non-volatile memory device to determine whether an abnormal shutdown occurred during a data migration operation. The metadata management system can scan the P2L table to identify entries with a migration status indicating its participation in the data migration. This status indicates that an abnormal shutdown occurred during the data migration. The metadata management system can then use the boundaries stored in the P2L table to complete the data migration operation.

[0028] Advantages of this disclosure include, but are not limited to, improved performance of the memory subsystem by avoiding metadata dump operations, where the entire metadata data structure is copied to a non-volatile memory device. By maintaining system metadata on both volatile and non-volatile memory devices, the memory subsystem has so far avoided consuming significant resources to perform metadata dumps. Furthermore, aspects of this disclosure do not require the considerable metadata overhead of storing it at every physical address, while maintaining system metadata integrity in the event of abnormal shutdown.

[0029] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0030] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0031] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing power.

[0032] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0033] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0034] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0035] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0036] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory cells can perform bit storage based on changes in volume resistance, in conjunction with stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0037] Each of the memory devices 130 may contain one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may contain one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may contain SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages that may refer to logical units of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks. Some types of memory, such as 3D cross-connects, may group pages across the die and channels to form management units (MUs).

[0038] While non-volatile memory components, such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0039] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0040] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0041] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0042] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0043] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0044] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0045] The storage subsystem 110 includes a metadata management component 113 that ensures valid address mapping of system metadata in the event of an abnormal shutdown. In some embodiments, the storage subsystem controller 115 includes at least a portion of the metadata management component 113. In some embodiments, the metadata management component 113 is part of the host system 110, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the metadata management component 113 and is configured to perform the functionality described herein.

[0046] Metadata management component 113 manages the address mapping data structures associated with non-byte addressable memory devices in the memory subsystem to ensure valid L2P and P2L mappings after abnormal power-off. Metadata management component 113 maintains address mapping data structures (i.e., P2L and L2P tables) on both volatile and non-volatile memory devices.

[0047] In some embodiments, the memory subsystem controller 115 may perform a move operation, such as a media management operation. The metadata management component 113 may detect the move operation. The move operation may involve moving data referenced by a logical SMU from a source physical SMU to a target SMU. In addition to mapping the PSMU to the LSMU, the address mapping data structure may also contain data fields used by the metadata management component 113 to track move operations. For example, the metadata management component 113 may update the move status data field of the source PSMU to indicate that the LSMU referenced by the source PSMU is involved in the move operation. About Figure 2 Further describe the address mapping data structure.

[0048] In some embodiments, the metadata management component 113 may use a P2L table stored on a non-volatile memory device (e.g., memory device 130) to reconstruct valid mappings after an abnormal shutdown. For example, the metadata management component 113 may use data fields (e.g., mobility status data fields) to determine whether the LSMU referenced by the PSMU was involved in mobility operations during the abnormal shutdown. The metadata management component 113 may then use the data fields in the P2L to reconstruct valid mappings. Further details regarding the operation of the metadata management component 113 are described below.

[0049] Figure 2 This describes the P2L mapping table 200, L2P mapping table 230, and management unit mapping table 240 according to some embodiments of this disclosure. In the embodiments, Figure 1 The metadata management component 113 can maintain the P2L mapping table 200 and the L2P mapping table 230 on one or more volatile memory devices (e.g., in...). Figure 1 In the cache memory of memory device 140), and on one or more non-volatile memory devices (e.g., Figure 1 (Memory device 130). In some embodiments, the MU mapping table 240 is not stored by the memory subsystem, and in Figure 2 The explanation provided is for illustrative purposes.

[0050] In an embodiment, the P2L mapping table 200 can map PSMU 202 to LSMU 204. P2L mapping table 200 entries may also include a movement state 206, a base 208, and a boundary 210. In an embodiment, state 206 may be a 2-bit data field and may indicate whether the entry is involved in an ongoing SMU movement operation. For example, state 206 entry "N" (stored as "00") may indicate that the PSMU 202 entry is not associated with an SMU movement; state 206 entry "D" (stored as "01") may indicate that the PSMU 202 entry is associated with an ongoing SMU movement as a target PSMU; and state 206 entry "S" (stored as "10") may indicate that the PSMU 202 entry is associated with an ongoing SMU movement as a source PSMU.

[0051] Base 208 may represent the base offset of MU mapping table 240. As noted above, MU mapping table 240 is illustrated for illustrative purposes and is not stored by the memory subsystem. In embodiments, each PSMU may refer to a group of MUs. For example, such as Figure 2 As described, the PSMU entry "001" represents a group of MUs in the MU mapping table 240. The MU mapping table 240 may contain 2048 entries and may include physical MU (PMU) 212 fields mapped to logical MU (LMU) 214 fields and boundary 220 fields. In embodiments, the PMU may be the same as the PBA, and the LMU may be the same as the LBA. The base offset 208 is used to indicate that PMU 212 is mapped to LMU 214 "0", i.e., the base PMU to LMU mapping. In some embodiments, the base PMU to LMU mapping may be changed to ensure proper wear leveling of the memory device. That is, the memory subsystem may change the starting PMU address instead of repeatedly starting data storage on the memory device at the same PMU. By storing the base 208 in the P2L mapping table 200, the memory subsystem controller 115 can avoid storing the MU mapping table 240 together. The memory subsystem controller 115 can use, as shown in... Figure 2 The base address 208 described herein is used to reconstruct the MU mapping table 240.

[0052] In some embodiments, there is an additional hierarchy of MUs grouped into stripes (not described). For example, a stripe mapping table can group multiple PMUs into a stripe (e.g., 2048 MUs per stripe) and can store boundary indicators for each stripe. In embodiments where MUs are grouped into stripes, MU mapping table 240 is not stored in the memory subsystem, but rather in a stripe mapping table (not described). The stripe mapping table stores boundary indicators for each stripe, such as "0" or "1". However, for illustrative purposes, MU mapping table 240 stores the boundary indicators for each PMU 212 in the SMU.

[0053] Boundary 210 in P2L mapping table 200 can be used to track whether the mapping in MU mapping table 240 has been updated according to SMU movement. For example, before any data is moved from a source PMU to a target PMU, metadata management component 113 can flip boundary indicator 210. That is, metadata management component 113 can flip boundary 210 to indicate that the data referenced by PSMU 202 has been moved. In an example, PSMU 202 entry "001" can be associated with an SMU movement operation, and metadata management component 113 can update boundary 210 from "T" to "Non-T". In an embodiment, "T" can be "1" and "Non-T" can be "0".

[0054] During SMU operation, metadata management component 113 can read data referenced by each PMU 212 entry and move said data to the source PSMU (according to the SMU move operation). Metadata management component 113 can perform this move one PMU 212 entry at a time. After each PMU entry is moved (or simultaneously), metadata management component 113 can update the boundary 220 of the PMU entry in MU mapping table 240 by reversing the binary value of boundary 220 to indicate that the data has been moved (e.g., changing "0" to "1" or vice versa). To continue the above example (as... Figure 2 As explained in the document, PMU entries in MU mapping table 240 with boundary 220 of “0” can indicate that the data referenced by those PMU 212 entries has been moved according to the SMU move, and entries with boundary 220 of “1” can indicate that the data referenced by those PMU 212 entries has not been updated according to the SMU move.

[0055] L2P mapping table 230 can map LSMU 232 to PSMU 234. The following further describes how the metadata management component 113 updates the table to ensure system metadata integrity in the event of an abnormal shutdown.

[0056] Figure 3 This diagram illustrates an embodiment of a method 350 performed by a computer system for updating a metadata table during an abnormal shutdown, according to some embodiments of the present disclosure. Method 350 may be performed by... Figure 1 The computing system 100 is implemented. In some embodiments, the P2L mapping table 300 can be connected to... Figure 2 The P2L mapping table 200 is the same, and the L2P mapping table 330 can be the same as... Figure 2 The L2P mapping table 230 is the same. In embodiments, the P2L mapping table 300 and the L2P mapping table 330 may be stored in one or more volatile memory devices (e.g., Figure 1The P2L mapping table 300 and L2P mapping table 330 may be stored on one or more non-volatile memory devices (e.g., memory device 140). Furthermore, the P2L mapping table 300 and L2P mapping table 330 may be stored on one or more non-volatile memory devices (e.g., memory device 140). Figure 1 On the memory device 130). Figure 1 The metadata management component 113 can implement method 350.

[0057] Operation 351 describes the initial state of the address mapping data structure prior to an SMU move operation. Metadata management component 113 can receive or otherwise intercept SMU move operations. SMU move operations are similar to those of the LSMU and are illustrated as follows: Figure 3 The moving LSMU (MLSMU) is mapped to the source PSMU (SPSMU) in the L2P mapping table 330. In the P2L mapping table 300, the source PSMU (SPSMU) is mapped to the MLSMU. The entries in the P2L mapping table 300 for the SPSMU have state 306 "N", base 308 "A", and boundary 310 "T". The target PSMU (DPSMU) in the P2L mapping table 300 is unmapped and has state 306 "N", base 308 "B", and boundary 310 "T". State "N" indicates that the L2P entry is not associated with an SMU moving operation.

[0058] At operation 352, in response to receiving an SMU move instruction, the metadata management component 113 may update the state 306 of the P2L mapping table 300 entry corresponding to the SPSMU referenced in the SMU move. The metadata management component 113 may update the state 306 indicating that the SPSMU participates in the SMU move as a source address to "S". The metadata management component 113 may perform operation 352 on both the P2L mapping table 300 stored on one or more volatile memory devices and the P2L mapping table stored on one or more non-volatile memory devices.

[0059] In an embodiment, during or immediately after operation 352, the metadata management component 113 may identify the value of the boundary 310 associated with the DPSMU item, i.e., identify the value of "T". In some embodiments, the metadata management component 113 may refer to a MU mapping table or a stripe mapping table to determine whether the boundary is "0" or "1" (i.e., whether the value of "T" is "0" or "1"). By identifying the boundary value in the stripe mapping table or the MU mapping table, the metadata management component 113 may invert the binary boundary bit value to the opposite value (i.e., change the boundary from "0" to "1", or vice versa).

[0060] At operation 353, the metadata management component 113 may update the P2L mapping table 300 entry corresponding to the DPSMU. The DPSMU may be mapped to an MLSMU. The state 306 of the DPSMU indicating that the DPSMU is participating in SMU movement as a destination address is updated to "D". The base 308 of the DPSMU is updated to base "C". In an embodiment, the base is randomly selected from a predefined list of possible bases. In addition, the boundary 310 for the DPSMU entry is switched from "T" to "Non-T". For example, "T" may represent "0" and "Non-T" may represent "1". In an embodiment, the metadata management component 113 may first perform operation 353 on the P2L mapping table 300 stored on a volatile memory device, and then perform operation 353 on the P2L mapping table stored on a non-volatile memory device.

[0061] In an embodiment, immediately following the execution of operation 353, the metadata management component 113 may cause an SMU move operation to be performed. That is, the metadata management component 113 (or another component within the memory subsystem 115) may perform an SMU move operation by moving data stored at a source physical address to a target physical address. For example, the metadata management component 113 may... Figure 2 The metadata management component 113 starts at PMU 212 "0" in the MU mapping table 240 and moves the data to the target PSMU. The metadata management component 113 can then update the boundary 220 of the MU mapping table 240 at operation 353 to the value indicated by the DPSMU entry in the P2L mapping table 300 (i.e., "not T"). More specifically, the metadata management component 113 can read the source PSMU content on the PMU one at a time, update the boundary 220 by inverting the binary bit values ​​associated with the PMU, and then write the content to the target PSMU. The metadata management component 113 can then move to the next PMU and perform the same move operation until it has cycled through the entire MU mapping table 240. In this embodiment, as mentioned above, there are additional levels of grouping called stripes, and the metadata management component 113 can move one stripe at a time.

[0062] In this embodiment, the metadata management component 113 can use boundary 220 to identify the PMU 212 that begins moving data to the target PSMU. That is, the metadata management component 113 can perform these operations after an abnormal shutdown, in which case some PMUs 212 in the MU mapping table 240 may have already moved to the target PSMU. To identify which PMU 212 has moved, the metadata management component 113 can scan the MU mapping table 240 to identify which PMU 212 has a boundary 220 that matches the boundary in the P2L mapping table 300 after operation 353, i.e., "Not T". In this case, "Not T" can be "0", and therefore the metadata management component 113 can identify PMU 212 "B+1" as the boundary (because boundary 220 does not match "Not T"). Therefore, the metadata management component 113 can begin moving the data referenced by PMU 212 "B+1" and continue to "B+2", etc., until the entire PSMU has been moved.

[0063] At operation 354, once the data has been moved according to the SMU move instruction, the metadata management component 113 can update the L2P mapping table 330 to map the MLSMU to the DPSMU. In an embodiment, the metadata management component 113 may first perform operation 354 on the P2L mapping table 300 stored on the volatile memory device, and then perform operation 354 on the P2L mapping table stored on the non-volatile memory device.

[0064] At operation 355, the metadata management component 113 may update the P2L mapping table 300 entry of the SPMSU to unmap and update the state 306 indicating that the SPSMU will not participate in SMU movement to "N". In an embodiment, the metadata management component 113 may first perform operation 355 on the P2L mapping table 300 stored on a volatile memory device, and then perform operation 355 on the P2L mapping table stored on a non-volatile memory device.

[0065] At operation 356, the metadata management component 113 may update the state 306 in the P2L mapping table 300 entry for the DPSMU, which indicates that the DPSMU is not involved in SMU movement, to "N". The metadata management component 113 may perform operation 356 on both the P2L mapping table 300 stored on one or more volatile memory devices and the P2L mapping table stored on one or more non-volatile memory devices.

[0066] Figure 4This is a flowchart of an example method 400 for performing SMU movement operations according to some embodiments of the present disclosure. Method 400 may be performed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The metadata management component 113 executes. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise stated. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0067] At operation 410, the processing logic maintains a logic-to-physical (L2P) data structure comprising multiple L2P entries on the memory devices of the multiple memory devices, each L2P entry mapping a logical address to a physical address of a super management unit (SMU) on the memory device that identifies the multiple memory devices. In an embodiment, the processing logic maintains the L2P data structure on both volatile and non-volatile memory devices.

[0068] At operation 420, the processing logic maintains a physical-to-logical (P2L) data structure on the memory device, comprising multiple P2L entries. Each P2L entry maps the physical address of the SMU on the memory device to a corresponding logical address. The P2L entry includes a data movement state, a base address, and a boundary indicator. In this embodiment, the processing logic maintains the P2L data structure on both volatile and non-volatile memory devices.

[0069] In some embodiments, the data movement status can indicate whether a P2L entry is involved in an ongoing SMU movement operation, and if so, whether it is involved in a source physical SMU or a target physical SMU. For example, a data movement status "N," which can be stored as "00," can indicate that a P2L entry is not associated with an ongoing SMU movement operation. A data movement status "D," which can be stored as "01," can indicate that a P2L entry is involved in an ongoing SMU movement operation as a target physical SMU. A data movement status "S," which can be stored as "10," can indicate that a P2L entry is involved in an ongoing SMU movement operation as a source physical SMU.

[0070] At operation 430, a logic detection SMU move operation is processed, wherein the SMU move operation indicates that data referenced by the logical SMU (LSMU) will be moved from the source physical SMU (PSMU) to the target PSMU. The SMU move operation may be part of a wear leveling process performed by the memory subsystem controller.

[0071] At operation 440, in response to detecting an SMU move operation, the processing logic updates the data move state associated with the source PSMU in the P2L data structure. The processing logic can update the data move state to indicate that the source PSMU is associated with the SMU move operation. For example, the processing logic can update the data move state associated with the source PSMU item in the P2L data structure to "S" or "10". The processing logic can also update the data move state on the P2L data structure stored on both volatile and non-volatile memory devices.

[0072] In this embodiment, the processing logic updates the P2L data entries corresponding to the target PSMU on both the volatile and non-volatile memory devices to map them to the LSMU. The processing logic may also update the base address of the P2L entries corresponding to the target PSMU on both the volatile and non-volatile memory devices. The updated base address may be randomly selected from a predefined list of base addresses. This predefined list of base addresses may contain all MU physical addresses included in the PSMU.

[0073] The processing logic can also update the data movement status of the P2L entry corresponding to the target PSMU on both volatile and non-volatile memory devices. The processing logic can update the movement status to indicate that the target PSMU is associated with the SMU movement. For example, the processing logic can update the data movement status associated with the target PSMU entry in the P2L data structure to "D" or "01".

[0074] Furthermore, the processing logic updates the first boundary indicator corresponding to the P2L entry of the target PSMU on both the volatile and non-volatile memory devices. The processing logic can update the first boundary indicator by inverting its binary value. That is, the first boundary indicator can be a 1-bit data field and therefore can store either "0" or "1". The processing logic can update the first boundary indicator by inverting the bit, for example, by inverting the first boundary indicator from "0" to "1" or from "1" to "0".

[0075] In an embodiment, the processing logic may then cause an SMU move operation to be performed. Performing an SMU move operation may involve identifying a plurality of MUs referenced by a source PSMU and reading data referenced by each of the plurality of MUs. The processing logic may read data one MU at a time. The processing logic may update the second boundary indicator associated with a MU by inverting the binary value of the second boundary indicator (i.e., by inverting the bits from "0" to "1" or from "1" to "0"). The processing logic may then write the data to the target PSMU. By reading data from the source PMU one MU at a time and updating the boundary indicator before writing the data to the target PSMU, the second boundary indicator effectively tracks which MUs have been moved and which have not.

[0076] In some embodiments, in response to performing an SMU move operation, the processing logic updates the L2P entries corresponding to the LSMU on both the volatile and non-volatile memory devices to map them to the target PSMU. The processing logic further updates the P2L entries corresponding to the source PSMU on both the volatile and non-volatile memory devices to unmap the source PSMU. To unmap the source PSMU, the processing logic may update the P2L entries to map them to default values. Furthermore, the processing logic updates the data move status to indicate that the source PSMU is not associated with an SMU move.

[0077] In an embodiment, the processing logic updates the data movement state associated with the P2L entry corresponding to the target PSMU on both the volatile and non-volatile memory devices to indicate that the target PSMU is not associated with SMU movement. For example, the processing logic may update the data movement state to "N" or "00".

[0078] Figure 5 This is a flowchart of an example method 500 for performing a recovery procedure after an abnormal shutdown according to some embodiments of the present disclosure. Method 500 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The metadata management component 113 executes. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise stated. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0079] At operation 510, the processing logic performs a physical-to-logical (P2L) data structure scan at the power-on event of the memory subsystem. The P2L data structure includes one or more P2L entries, each mapping a physical address of the Super Management Unit (SMU) on the memory device to a corresponding logical address. Each P2L entry includes data movement status and boundary indicators. In some embodiments, the processing logic performs the P2L data structure scan at the power-on event. The P2L data structure may be stored on a non-volatile memory device.

[0080] In an embodiment, the processing logic scans P2L entries to identify any P2L entry that indicates the associated entry is linked to the SMU movement as a target physical SMU in a movement state. For example, a movement state indicating that a P2L entry is linked to the SMU movement as a target PSMU could be a state "D" stored as "01". If a P2L entry has a state "D" indicating that the SMU movement operation is in progress (i.e., incomplete) when the memory subsystem is consuming power (or when the memory subsystem consumes P2L data structures stored on the volatile memory device), then the P2L entry is considered complete.

[0081] At operation 520, in response to identifying a first item in the P2L data structure, including an indication that the first item is associated with the SMU movement as a first data movement state of the target physical SMU (PSMU), the processing logic identifies a first boundary indicator associated with the first item. In embodiments, as described in the examples above, the boundary indicator may be "T" or "not T". In some instances, a boundary indicator of "T" may represent "1", and a boundary indicator of "not T" may represent "0". The boundary indicator can identify the time at which the MU within the SMU stops the SMU movement operation.

[0082] At operation 530, the processing logic identifies a plurality of management units (MUs) referenced by the SMU, wherein each of the plurality of MUs includes a second boundary indicator. In an embodiment, the SMU may reference a MU mapping data structure. Entries in the MU mapping data structure may have a second boundary indicator, such as "0" or "1", indicating whether a move operation has been performed on the associated MU. In some embodiments, MUs are grouped together into stripes, in which case the SMU may reference multiple stripes, and each strip may contain a second boundary indicator.

[0083] At operation 540, the processing logic identifies a subset of MUs among the multiple MUs that have a corresponding second boundary indicator that does not match the first boundary indicator. For example, if the first boundary indicator is "T" (or "1"), then the processing logic can identify a MU among the multiple MUs referenced by an SMU with a corresponding second boundary indicator value of "0".

[0084] At operation 550, the processing logic performs an SMU move for each MU in a subset of the MUs. Performing an SMU operation may include reading data referenced by the source PMU, inverting the binary value of the second boundary indicator (i.e., changing it from "1" to "0", or vice versa), and writing the data to the target PMU.

[0085] In an embodiment, in response to identifying a first entry in a P2L data structure that includes a data movement state indicating that the first entry is associated with an SMU movement as a target PSMU, the processing logic identifies the logical SMU (LSMU) address associated with the first entry. The processing logic further identifies a second entry corresponding to the LSMU in a logic-to-physical (L2P) data structure and a third entry corresponding to the PSMU in the second entry in the P2L data structure. In response to determining that the data movement state of the third entry does not indicate that the LSMU is participating in the SMU movement as a source PSMU, the processing logic determines that the P2L table is corrupted and reports an error to the memory subsystem controller. In an embodiment, the processing logic may report the error by, for example, sending a notification to the memory subsystem controller via an interrupt.

[0086] In some embodiments, the processing logic performs a second scan of the P2L data structure. The processing logic rescans the P2L data structure to identify any P2L entries that indicate the data movement state of the associated P2L entry as the source PSMU associated with the SMU movement. For example, the data movement state indicating that the P2L entry is associated with the source PSMU associated with the SMU movement may be a state "S" stored as "10". If the P2L entry has a state "S" indicating that the SMU movement operation is in progress (i.e., incomplete) when the memory subsystem is losing power (or when the memory subsystem loses the P2L data structure stored on the volatile memory device).

[0087] In response to identifying a second item in the P2L data structure, including a second data movement state indicating that the second item is associated with an SMU movement as a source PSMU, the processing logic updates the second majority state associated with the second item to indicate that the second item is not associated with an SMU movement. Furthermore, the processing logic identifies the logical SMU associated with the second item in the P2L data structure. The processing logic can then identify a third item corresponding to the LSMU in the L2P data structure. The processing logic can update the third item in the L2P data structure to map to the target PSMU. The processing logic can update the second item in the P2L data structure to unmap the source PSMU.

[0088] Figure 6 An example machine is described as representing computer system 600, within which a set of instructions is executable to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of metadata management component 113). In alternative embodiments, the machine may connect (e.g., network) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0089] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be understood to include any collection of machines that individually or jointly execute a set of instructions (or multiple sets of instructions) to perform any or more of the methods discussed herein.

[0090] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0091] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0092] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) storing one or more instruction sets 626 or software embodying any one or more methods or functions described herein. Instructions 626 may also reside wholly or at least partially in main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage media. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0093] In one embodiment, instruction 626 includes instructions for implementing a metadata management component (e.g., Figure 1 The metadata management component 113) provides functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0094] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithms are described and represented in a way that those skilled in the art of data processing can most effectively communicate the essence of their work to others skilled in the art. An algorithm here is generally considered a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0095] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0096] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each connected to a computer system bus.

[0097] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0098] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0099] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A system comprising: Multiple memory devices; as well as A processing device operatively coupled to the plurality of memory devices to perform operations including: A logical-to-physical L2P data structure comprising multiple L2P entries is maintained on a first memory device among the plurality of memory devices, each L2P entry mapping a logical address to a physical address that identifies a super management unit (SMU) on a second memory device among the plurality of memory devices. A physical-to-logical P2L data structure including multiple P2L entries is maintained on the first memory device. Each P2L entry maps the physical address of the SMU on the second memory device to a corresponding logical address. The P2L entry includes data movement status, base address, and boundary indicator. Detect an SMU move operation, wherein the SMU move operation indicates that data referenced by the logical SMU, i.e., the LSMU, will be moved from the source physical SMU to the target PSMU; as well as In response to detecting the SMU movement operation, the data movement state associated with the source PSMU in the P2L data structure is updated.

2. The system of claim 1, wherein the second memory device is a volatile memory device, and wherein the L2P data structure and the P2L data structure are maintained on a non-volatile memory device.

3. The system of claim 1, wherein the data movement state is updated to indicate that the source PSMU is associated with the SMU movement operation as the source PSMU.

4. The system of claim 1, wherein the operation further comprises: Update the P2L entry corresponding to the target PSMU to map it to the LSMU; Update the base address corresponding to the P2L entry of the target PSMU, wherein the updated base address is randomly selected; Update the data movement status of the P2L entry corresponding to the target PSMU, the data movement status indicating that the target PSMU is associated with the SMU movement as the target PSMU.

5. The system according to claim 1, wherein the operation further comprises: The first boundary indicator corresponding to the P2L entry of the target PSMU is updated by inverting the binary value of the first boundary indicator.

6. The system of claim 1, wherein the operation further comprises: Perform the SMU movement operation.

7. The system of claim 6, wherein performing the SMU movement operation comprises: Identify multiple MUs referenced by the source PSMU; Read data referenced by a MU among the plurality of MUs; The second boundary indicator associated with the MU is updated by inverting its binary value; as well as The data is written to the target PSMU.

8. The system of claim 6, wherein the operation further comprises: In response to performing the SMU move operation, the L2P entry corresponding to the LSMU is updated to map to the target PSMU; as well as Update the P2L entry corresponding to the source PSMU to unmap the source PSMU; as well as Update the data movement status to indicate that the source PSMU is not associated with the SMU movement.

9. The system of claim 8, wherein the operation further comprises: Update the data movement status associated with the P2L entry corresponding to the target PSMU to indicate that the target PSMU is not associated with the SMU movement.

10. A method comprising: Perform a scan of the physical-to-logical P2L data structure of the memory subsystem, wherein the P2L data structure includes one or more P2L entries, wherein the P2L entries map the physical address of the super management unit (SMU) on the memory device to the corresponding logical address, and wherein the P2L entries include data movement status and boundary indicators. In response to identifying the first item in the P2L data structure, which includes an indication of a first data movement state associated with the first item as a target physical SMU movement, a first boundary indicator associated with the first item is identified; Identify a plurality of management unit MUs referenced by the SMU, wherein each of the plurality of MUs includes a second boundary indicator; Identify a subset of MUs among the plurality of MUs that have a corresponding second boundary indicator that does not match the first boundary indicator; as well as The SMU move is performed for each MU in the subset of MUs.

11. The method of claim 10, further comprising: In response to identifying the first item in the P2L data structure, which includes an indication that the first item is associated with the SMU movement as the target PSMU, the logical SMU, i.e., the LSMU address, associated with the first item is identified. Identify the second item corresponding to the LSMU in the logical-to-physical L2P data structure; Identify the third item corresponding to the PSMU in the second item in the P2L data structure; In response to determining that the data movement status of the third item does not indicate that the LSMU participates in the SMU movement as a source PSMU, a notification indicating that the P2L data structure is corrupted is sent to the memory subsystem controller.

12. The method of claim 11, wherein the L2P data structure and the P2L data structure are stored on a non-volatile memory device.

13. The method of claim 10, further comprising: Perform the second scan of the P2L data structure; In response to identifying a second item in the P2L data structure that includes a second data movement state indicating that the second item is associated with the SMU movement as a source PSMU, the second data movement state associated with the second item is updated to indicate that the second item is not associated with the SMU movement.

14. The method of claim 13, further comprising: Identify the logical SMU, i.e., LSMU address, associated with the second item; Identify the third item corresponding to the LSMU in the logical-to-physical L2P data structure; Update the third item in the L2P data structure to map it to the target PSMU; as well as Update the second item in the P2L data structure to unmap the source PSMU.

15. The method of claim 10, wherein the scan of the P2L data structure is performed upon power-on of the memory subsystem.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to perform operations including: On the first memory device of the memory subsystem, a logical-to-physical L2P data structure including multiple L2P entries is maintained, each L2P entry mapping a logical address to a physical address that identifies the super management unit (SMU) on the second memory device. A physical-to-logical P2L data structure including multiple P2L entries is maintained on the first memory device. Each P2L entry maps the physical address of the SMU on the second memory device to a corresponding logical address. The P2L entry includes data movement status, base address, and boundary indicator. Detect an SMU move operation, wherein the SMU move operation indicates that data referenced by the logical SMU, i.e., the LSMU, will be moved from the source physical SMU to the target PSMU; as well as In response to detecting the SMU movement operation, the data movement state associated with the source PSMU in the P2L data structure is updated.

17. The non-transitory computer-readable storage medium of claim 16, wherein the data movement state is updated to indicate that the source PSMU is associated with the SMU movement operation as the source PSMU.

18. The non-transitory computer-readable storage medium of claim 16, wherein the processing means is configured to perform operations further comprising: Update the P2L entry corresponding to the target PSMU to map it to the LSMU; Update the base address corresponding to the P2L entry of the target PSMU, wherein the updated base address is randomly selected; Update the data movement status of the P2L entry corresponding to the target PSMU, the data movement status indicating that the target PSMU is associated with the SMU movement as the target PSMU; as well as The first boundary indicator corresponding to the P2L entry of the target PSMU is updated by inverting the binary value of the first boundary indicator.

19. The non-transitory computer-readable storage medium of claim 16, wherein the processing means is configured to perform operations further comprising: Perform the SMU movement operation.

20. The non-transitory computer-readable storage medium of claim 19, wherein the processing means is configured to perform operations further comprising: In response to performing the SMU move operation, the L2P entry corresponding to the LSMU is updated to map to the target PSMU; as well as Update the P2L entry corresponding to the source PSMU to unmap the source PSMU; Update the data movement status to indicate that the source PSMU is not associated with the SMU movement; and Update the data movement status associated with the P2L entry corresponding to the target PSMU to indicate that the target PSMU is not associated with the SMU movement.

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