Control method of driving circuit, driving circuit and display device

Abstract

The present application provides a control method of a driving circuit, a driving circuit and a display device. The control method includes: detecting whether the refresh frequency of the display panel is reduced; if it is detected that the refresh frequency of the display panel is reduced, determining whether the current frequency reduction mode of the display panel is an adaptive frequency reduction mode or a normal frequency reduction mode; if the current frequency reduction mode of the display panel is a normal frequency reduction mode, controlling the power supply module to output a first shutdown voltage, wherein the voltage value of the first shutdown voltage is a fixed value; and if the current frequency reduction mode of the display panel is an adaptive frequency reduction mode, controlling the power supply module to output a second shutdown voltage according to the current refresh frequency of the display panel, wherein the voltage value of the second shutdown voltage decreases as the current refresh frequency of the display panel decreases, and is lower than the voltage value of the first shutdown voltage. The control method of the driving circuit provided in the present application can avoid flickering and abnormal images on the display panel when the frequency is adaptively reduced.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a control method of a drive circuit, a drive circuit and a display device. Background Art

[0002] With the continuous development of display technology, consumers have higher and higher requirements for liquid crystal displays (LCDs), which not only require higher resolution, color gamut, brightness and other display effects, but also high refresh rate, Freesync (adaptive frequency reduction mode), HDR (High-Dynamic Range) and other functions.

[0003] Most of the existing LCD displays are variable frequency displays, which support switching from high frequency to low frequency. When the display switches from high frequency to low frequency, there are two switching modes: true frequency reduction and false frequency reduction (i.e., adaptive frequency reduction mode). In true frequency reduction, the refresh frequency is reduced by amplifying the cycle of the image frame as a whole (i.e., amplifying the cycle of the timing signal as a whole). In false frequency reduction, the cycle of the image frame is kept unchanged, and the refresh frequency is reduced by extending the vertical blank interval (Vertical Blankinterval, V-Blank). In false frequency reduction, the lower the refresh frequency of the display screen, the longer the vertical blank interval, the more pixel electrode leakage, and the lower the brightness. Therefore, in false frequency reduction, the brightness of the display screen changes greatly, causing the human eye to feel obvious flickering and abnormal images, affecting the customer experience. Summary of the invention

[0004] In view of this, the main purpose of the present application is to propose a control method of a driving circuit, a driving circuit and a display device, aiming to solve the problem that the existing liquid crystal display is prone to flickering when pseudo-frequency reduction occurs.

[0005] The present application proposes a control method for a driving circuit, wherein the driving circuit is used to drive a display panel for display, and the driving circuit includes a power supply module for outputting a shutdown voltage, and the shutdown voltage is used to generate a scanning signal to scan the display panel. The control method of the driving circuit includes: detecting whether the refresh frequency of the display panel is reduced; if it is detected that the refresh frequency of the display panel is reduced, determining whether the current frequency reduction mode of the display panel is an adaptive frequency reduction mode or a normal frequency reduction mode; if the current frequency reduction mode of the display panel is the normal frequency reduction mode, controlling the power supply module to output a first shutdown voltage, wherein the voltage value of the first shutdown voltage is a constant value; and, if the current frequency reduction mode of the display panel is the adaptive frequency reduction mode, controlling the power supply module to output a second shutdown voltage according to the current refresh frequency of the display panel, wherein the voltage value of the second shutdown voltage decreases as the current refresh frequency of the display panel decreases, and is lower than the voltage value of the first shutdown voltage.

[0006] The control method of the driving circuit provided in the present application determines whether the current frequency reduction mode of the display panel is adaptive frequency reduction or normal frequency reduction, controls the power module to output a first shutdown voltage with a fixed voltage value when the display panel is normally frequency reduced, and controls the power module to output a second shutdown voltage according to the current refresh frequency of the display panel when the display panel is adaptively frequency reduced. This method not only allows the driving transistor in the display panel to always maintain a low leakage current during normal frequency reduction, thereby avoiding vertical crosstalk in the display panel during normal frequency reduction, but also allows the display panel to output a corresponding second shutdown voltage according to the refresh frequency after frequency reduction during adaptive frequency reduction, thereby avoiding flickering and abnormal images in the display panel during adaptive frequency reduction, thereby improving user experience.

[0007] Optionally, an image frame cycle includes an active display duration and a vertical blank gap duration. The determining whether the current frequency reduction mode of the display panel is an adaptive frequency reduction mode or a normal frequency reduction mode comprises: obtaining a vertical blank gap duration before frequency reduction and a vertical blank gap duration after frequency reduction; wherein the vertical blank gap duration before frequency reduction is a vertical blank gap duration in an image frame cycle before the refresh frequency is reduced, and the vertical blank gap duration after frequency reduction is a vertical blank gap duration in an image frame cycle after the refresh frequency is reduced; determining whether the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is greater than a preset duration difference threshold; if the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is greater than the preset duration difference threshold, determining that the current frequency reduction mode of the display panel is an adaptive frequency reduction mode; and if the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is less than or equal to the preset duration difference threshold, determining that the current frequency reduction mode of the display panel is a normal frequency reduction mode.

[0008] Optionally, the driving circuit further includes a timing control module, the timing control module is used to output a timing signal to the display panel, and the timing signal and the shutdown voltage are used together to generate the scanning signal. The determination of whether the current frequency reduction mode of the display panel is an adaptive frequency reduction mode or a normal frequency reduction mode comprises: obtaining a pre-frequency reduction period and a post-frequency reduction period of the timing signal output by the timing control module; wherein the pre-frequency reduction period is the period of the timing signal output by the timing control module before the refresh frequency is reduced, and the post-frequency reduction period is the period of the timing signal output by the timing control module after the refresh frequency is reduced; determining whether the pre-frequency reduction period and the post-frequency reduction period are the same; if the pre-frequency reduction period and the post-frequency reduction period are the same, determining that the current frequency reduction mode of the display panel is an adaptive frequency reduction mode; and if the pre-frequency reduction period and the post-frequency reduction period are not the same, determining that the current frequency reduction mode of the display panel is a normal frequency reduction mode.

[0009] Optionally, controlling the power module to output the second shutdown voltage according to the current refresh frequency of the display panel includes: obtaining a preset shutdown voltage calibration table, wherein the preset shutdown voltage calibration table pre-records a mapping relationship between multiple refresh frequency ranges and multiple shutdown voltages; determining the shutdown voltage corresponding to the current refresh frequency of the display panel as the second shutdown voltage according to the preset shutdown voltage calibration table; and controlling the power module to output the second shutdown voltage.

[0010] Optionally, the widths of the refresh frequency ranges in the preset shutdown voltage calibration table are equal.

[0011] The present application also provides a driving circuit, the driving circuit is used to drive a display panel for display, the driving circuit includes a power supply module for outputting a shutdown voltage, the shutdown voltage is used to generate a scanning signal to scan the display panel, the driving circuit also includes a shutdown voltage control module electrically connected to the power supply module, the shutdown voltage control module is used to detect whether the refresh frequency of the display panel is reduced, and when the refresh frequency of the display panel is detected to be reduced, it is determined whether the current frequency reduction mode of the display panel is an adaptive frequency reduction mode or a normal frequency reduction mode, and when the current frequency reduction mode of the display panel is a normal frequency reduction mode, the power supply module is controlled to output a first shutdown voltage, and when the current frequency reduction mode of the display panel is an adaptive frequency reduction mode, the power supply module is controlled to output a second shutdown voltage according to the current refresh frequency of the display panel. Wherein, the voltage value of the first shutdown voltage is a constant value. The voltage value of the second shutdown voltage decreases as the current refresh frequency of the display panel decreases, and is lower than the voltage value of the first shutdown voltage.

[0012] Optionally, an image frame cycle includes an active display duration and a vertical blank gap duration. The shutdown voltage control module is specifically used to obtain the vertical blank gap duration before frequency reduction and the vertical blank gap duration after frequency reduction, and to determine whether the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is greater than a preset duration difference threshold, and to determine that the current frequency reduction mode of the display panel is an adaptive frequency reduction mode when the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is greater than the preset duration difference threshold, and to determine that the current frequency reduction mode of the display panel is a normal frequency reduction mode when the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is less than or equal to the preset duration difference threshold. The vertical blank gap duration before frequency reduction is the vertical blank gap duration in an image frame cycle before the refresh frequency is reduced, and the vertical blank gap duration after frequency reduction is the vertical blank gap duration in an image frame cycle after the refresh frequency is reduced.

[0013] Optionally, the driving circuit further includes a timing control module, the timing control module is used to output a timing signal to the display panel, and the timing signal and the shutdown voltage are used together to generate the scanning signal. The timing control module includes the shutdown voltage control module. The shutdown voltage control module is specifically used to obtain the pre-frequency reduction period and the post-frequency reduction period of the timing signal output by the timing control module, and to determine whether the pre-frequency reduction period and the post-frequency reduction period are the same, and to determine that the current frequency reduction mode of the display panel is an adaptive frequency reduction mode when the pre-frequency reduction period and the post-frequency reduction period are the same, and to determine that the current frequency reduction mode of the display panel is a normal frequency reduction mode when the pre-frequency reduction period and the post-frequency reduction period are not the same. Among them, the pre-frequency reduction period is the period of the timing signal output by the timing control module before the refresh frequency is reduced, and the post-frequency reduction period is the period of the timing signal output by the timing control module after the refresh frequency is reduced.

[0014] Optionally, the driving circuit further includes a timing control module, and the timing control module further includes a memory for storing a preset shutdown voltage calibration table, wherein the preset shutdown voltage calibration table pre-records a mapping relationship between multiple refresh frequency ranges and multiple shutdown voltages. The shutdown voltage control module is electrically connected to the memory, and the shutdown voltage control module is further specifically used to obtain the preset shutdown voltage calibration table, and determine the shutdown voltage corresponding to the current refresh frequency of the display panel as the second shutdown voltage according to the preset shutdown voltage calibration table, and control the power supply module to output the second shutdown voltage.

[0015] The present application also provides a display device, which includes a display panel and the above-mentioned driving circuit, wherein the driving circuit is electrically connected to the display panel, and the driving circuit is used to drive the display panel to display.

[0016] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the structure of the display device provided in an embodiment of the present application.

[0018] Figure 2 It is a schematic diagram of the structure of the sub-pixel unit provided in an embodiment of the present application.

[0019] Figure 3 It is a schematic diagram of image frames at different refresh frequencies provided in an embodiment of the present application.

[0020] Figure 4 is a characteristic curve of the driving transistor provided in the embodiment of the present application.

[0021] Figure 5 It is a schematic diagram of the vertical crosstalk phenomenon occurring in the display panel provided by the embodiment of the present application.

[0022] Figure 6 It is a flow chart of a control method of a driving circuit provided in an embodiment of the present application.

[0023] Figure 7 yes Figure 6 A first detailed flowchart of step 620 in FIG.

[0024] Figure 8 yes Figure 6 A second detailed flowchart of step 620 in FIG.

[0025] Fig. 9 yes Figure 6 Detailed flowchart of step 640 in FIG.

[0026] Fig.10 It is a schematic diagram of a shutdown voltage calibration table provided in an embodiment of the present application.

[0027] Description of main component symbols:

[0028] Display device 1

[0029] Driving circuit 2

[0030] Display Panel 3

[0031] Sub-pixel unit 100

[0032] Gate driver 110

[0033] Source driver 120

[0034] Power module 130

[0035] Timing control module 140

[0036] Level conversion module 150

[0037] Scan line 111

[0038] Data line 121

[0039] Driving transistor TFT

[0040] Steps 610-630, 621-628, 641-643

[0041] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", etc. are based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0044] See also Figure 1 , Figure 1 1 is a schematic diagram of the structure of a display device 1 provided in an embodiment of the present application. The display device 1 includes a driving circuit 2 and a display panel 3, and the driving circuit 2 is used to drive the display panel 3 to display. A plurality of sub-pixel units 100 arranged in an array are defined in a display area of ​​the display panel 3. The driving circuit 2 includes a gate driver 110, a source driver 120, a power module 130, a timing control module 140, and a level conversion module 150.

[0045] Among them, the power supply module 130 is used to provide power supply voltage to each functional module, for example, to provide a common voltage VCOM to the common electrode of the display panel 3, and to provide a turn-on voltage VGH (also called a gate high level) and a turn-off voltage VGL (also called a gate low level) to the level conversion module 150.

[0046] The timing control module 140 is electrically connected to the level conversion module 150 and the source driver 120 , respectively. The timing control module 140 is used to provide a timing signal CK to the level conversion module 150 and provide a data control signal Source to the source driver 120 .

[0047] The level conversion module 150 generates a GOA timing control signal GOA_CK based on the received timing signal CK, the high level VGH, and the low level VGL, and outputs the signal to the gate driver 110 .

[0048] The gate driver 110 is electrically connected to each row of the sub-pixel units 100 through a plurality of scanning lines 111. The gate driver 110 generates a corresponding scanning signal for each row of the sub-pixel units 100 based on the received GOA timing control signal GOA_CK, so as to scan the display panel 3 row by row. The scanning signal includes a high level VDD and a low level VSS, wherein the high level VDD corresponds to the turn-on voltage VGH, and the low level VSS corresponds to the turn-off voltage VGL. The high level VDD is used to turn on the driving transistor TFT in the sub-pixel unit 100 in the row when scanning a row of the sub-pixel units 100, and the low level VSS is used to turn off the driving transistor TFT in the sub-pixel unit 100 in the row when the scanning is finished. In some embodiments, the difference between the low level VSS and the shutdown voltage VGL is fixed at 5V, and the low level VSS changes with the change of the shutdown voltage VGL. For example, when VSS=-5.5V, VGL=-10.5V; when VSS=-9V, VGL=-14V. This can avoid mutual pulling between the low level VSS and the shutdown voltage VGL.

[0049] The source driver 120 is electrically connected to each column of the sub-pixel units 100 through a plurality of data lines 121 . The source driver 120 generates a corresponding data voltage Vdata for each column of the sub-pixel units 100 based on the received data control signal Source.

[0050] Furthermore, if Figure 2 As shown, each sub-pixel unit 100 includes a pixel electrode 201, a driving transistor TFT, a storage capacitor Cst and a liquid crystal capacitor Clc, the control end of the driving transistor TFT is electrically connected to the scan line 111 of the row where it is located, the first end of the driving transistor TFT is electrically connected to the data line 121 of the column where it is located, the second end of the driving transistor TFT, the first end of the storage capacitor Cst and the first end of the liquid crystal capacitor Clc are all electrically connected to the pixel electrode. The second end of the storage capacitor Cst and the second end of the liquid crystal capacitor Clc are both used to receive the common voltage VCOM output by the power module.

[0051] The driving transistor TFT is turned on or off by the scanning signal of the row where it is located. Taking the driving transistor TFT as an NMOS tube as an example, in a frame image cycle, when the scanning signal is the high level VDD, the driving transistor TFT of the corresponding row is controlled to be turned on, so that the data line 121 can write the data voltage Vdata into the pixel electrode of the sub-pixel unit 100 (that is, charge the liquid crystal capacitor Clc and the storage capacitor Cst) through the turned-on driving transistor TFT, thereby making the sub-pixel unit 100 emit light. When the scanning signal is the low level VSS, the driving transistor TFT of the corresponding row is controlled to be turned off. During the period when the driving transistor TFT is turned off in the frame image cycle, the charge stored in the storage capacitor Cst can continue to drive the sub-pixel unit 100 to emit light.

[0052] Most of the existing LCD monitors are variable frequency monitors, which support switching from high frequency to low frequency. When the monitor switches from high frequency to low frequency, there are two switching modes: true frequency reduction (i.e. normal frequency reduction mode) and false frequency reduction (i.e. adaptive frequency reduction mode). Figure 3 As shown, an image frame cycle includes the active display duration and the vertical blank gap duration. Taking the display panel 3 down-converted from 120Hz to 60Hz as an example, in the normal down-converting mode, the refresh frequency is reduced by amplifying the cycle of the image frame by 2 times as a whole (i.e., amplifying the cycle of the timing signal CK by 2 times as a whole). In the adaptive down-converting mode, the cycle of the image frame is kept unchanged, and the refresh frequency is reduced by extending the vertical blank gap duration (V-Blank), that is, extending the vertical blank gap duration from Blank1 to Blank2. In the adaptive down-converting mode, the lower the refresh frequency of the display panel, the longer the vertical blank gap duration, the more the pixel electrode leaks, and the lower the brightness. Therefore, when the frequency is falsely reduced, the brightness of the display screen changes greatly, causing the human eye to be able to feel obvious flickering and abnormal images, and the lower the frequency after the false down-converting, the more serious the flickering and abnormal images.

[0053] See also Figure 4 , Figure 4 It is the characteristic curve of the driving transistor TFT. When the driving transistor TFT is turned off, there is still leakage current in the driving transistor TFT. When the gate-source voltage Vgs=VSS1, the leakage current reaches the minimum value Idsmin. In the embodiment of the present application, this point is called the optimal leakage point. During the period when the driving transistor TFT is turned off, the drain voltage of the driving transistor TFT can be regarded as 0V, so that the gate voltage of the driving transistor TFT in the off state is equal to the voltage value of VSS. At this time, the leakage current of the driving transistor TFT will vary within a certain value range according to the difference of VSS. It was found in the test that in the normal frequency reduction mode, if the voltage value of the shutdown voltage VGL is not selected properly, the following will occur: Figure 5 The vertical crosstalk phenomenon (V-Cross Talk) shown in FIG. 1 is analyzed and the reasons for the vertical crosstalk phenomenon are as follows: when the refresh frequency after normal frequency reduction is low, the cycle of the timing signal CK is extended, so the charging time of each row of sub-pixel units 100 is also extended accordingly. Figure 5 As shown, in one frame of displayed image, the brightness of the middle display area 301 is higher than the brightness of the surrounding edge display areas 302 and 303, wherein the edge display area 302 is located at the upper and lower sides of the middle display area 301, and the edge display area 303 is located at the left and right sides of the middle display area 301. Then, the data voltage Vdata written into the sub-pixel unit 100 of the middle display area 301 is higher than the data voltage Vdata written into the edge display areas 302 and 303. Therefore, taking the middle data line 121 as an example, when the data voltage Vdata is written row by row to the sub-pixel units 100 in the column through the data line 121, the driving transistor TFT of the sub-pixel unit 100 in the middle display area 301 will leak electricity to the sub-pixel unit 100 in the edge display area 302, and the charging time of each row of sub-pixel units 100 is longer, so that the actual voltage of the sub-pixel unit 100 in the edge display area 302 will be higher than the data voltage Vdata provided by the data line 121, which will cause the brightness of the edge display area 302 to be higher than the brightness of the edge display area 303, that is, vertical crosstalk will occur, and the greater the leakage current of the driving transistor TFT, the more serious the vertical crosstalk phenomenon.

[0054] See also Figure 6 In order to solve the problem that the existing liquid crystal display is prone to flickering in the adaptive frequency reduction mode and the problem that the vertical crosstalk is prone to occur in the normal frequency reduction mode, the embodiment of the present application proposes a control method of a driving circuit, the method comprising the following steps:

[0055] Step 610, detecting whether the refresh frequency of the display panel 3 is reduced. If it is detected that the refresh frequency of the display panel 3 is reduced, step 620 is executed, otherwise, step 610 is executed again. Exemplarily, it is possible to detect whether the refresh frequency of the display panel 3 is reduced by detecting the image period of the display panel. For example, when the refresh frequency of the display panel 3 is reduced from 120 Hz to 60 Hz, the image period will double. It is also possible to detect whether the refresh frequency of the display panel 3 is reduced by detecting the frame start signal STV output by the timing control module 140, which is not limited here.

[0056] Step 620, determine whether the current frequency reduction mode of the display panel 3 is the adaptive frequency reduction mode or the normal frequency reduction mode. If the current frequency reduction mode of the display panel 3 is the normal frequency reduction mode, execute step 630. If the current frequency reduction mode of the display panel 3 is the adaptive frequency reduction mode, execute step 640.

[0057] Step 630, control the power module 130 to output a first off-state voltage VGL1. The voltage value of the first off-state voltage VGL1 is a constant value. Preferably, the voltage value of the first off-state voltage VGL1 is a off-state voltage that minimizes the leakage current of the driving transistor TFT during the off-state period. In this way, the leakage current of the driving transistor TFT in the display panel 3 can be minimized, thereby avoiding the vertical crosstalk phenomenon of the display panel 3 during normal frequency reduction, thereby improving the user experience. Figure 4 As shown, the voltage value of the first turn-off voltage VGL1 can be determined according to the optimal leakage point in the characteristic curve of the driving transistor TFT. For example, if the low level VSS1 corresponding to the optimal leakage point is -5.5V, then VGL1 is -10.5V.

[0058] Step 640, according to the current refresh frequency of the display panel 3, the power module 130 is controlled to output the second turn-off voltage VGL2, wherein the voltage value of the second turn-off voltage VGL2 decreases as the current refresh frequency of the display panel 3 decreases, and is lower than the voltage value of the first turn-off voltage VGL1. It should be noted that the problem of flickering and abnormal display of the display panel 3 in the adaptive frequency reduction mode can be improved or eliminated by enhancing the driving capability of the gate driver 110, and the driving capability of the gate driver 110 is negatively correlated with the voltage value of the turn-off voltage, that is, the lower the voltage value of the second turn-off voltage VGL2, the stronger the driving capability of the gate driver 110. In this way, when the display panel 3 is in the adaptive frequency reduction mode, the lower the frequency after frequency reduction, the lower the second turn-off voltage VGL2 output by the power module 130 is controlled, thereby avoiding the flickering and abnormal display phenomenon of the display panel 3 in the adaptive frequency reduction mode, thereby improving the user experience.

[0059] The control method of the driving circuit provided in the present application determines whether the current frequency reduction mode of the display panel 3 is adaptive frequency reduction or normal frequency reduction, controls the power module to output a first shutdown voltage with a fixed voltage value when the display panel 3 is normally frequency reduced, and controls the power module to output a second shutdown voltage VGL2 according to the current refresh frequency of the display panel 3 when the display panel 3 is adaptive frequency reduced. This method can not only allow the driving transistor TFT in the display panel 3 to always maintain a low leakage current during normal frequency reduction, thereby avoiding the vertical crosstalk phenomenon of the display panel 3 during normal frequency conversion, but also allow the display panel 3 to output the corresponding second shutdown voltage VGL2 according to the refresh frequency after frequency reduction during adaptive frequency reduction, thereby avoiding the flickering phenomenon of the display panel 3 during adaptive frequency reduction, thereby improving the user experience.

[0060] See also Figure 7 In one embodiment, step 620 specifically includes the following steps:

[0061] Step 621, obtaining the vertical blank gap duration before frequency reduction and the vertical blank gap duration after frequency reduction, wherein the vertical blank gap duration before frequency reduction is the vertical blank gap duration in one image frame period before the refresh frequency is reduced, and the vertical blank gap duration after frequency reduction is the vertical blank gap duration in one image frame period after the refresh frequency is reduced.

[0062] Step 622, determining whether the difference between the vertical blank gap duration after the frequency reduction and the vertical blank gap duration before the frequency reduction is greater than a preset duration difference threshold t0. If the difference between the vertical blank gap duration after the frequency reduction and the vertical blank gap duration before the frequency reduction is greater than the preset duration difference threshold t0, executing step 623. If the difference between the vertical blank gap duration after the frequency reduction and the vertical blank gap duration before the frequency reduction is less than or equal to the preset duration difference threshold t0, executing step 624.

[0063] Step 623: Determine whether the current frequency reduction mode of the display panel 3 is an adaptive frequency reduction mode.

[0064] Step 624 , determining that the current frequency reduction mode of the display panel 3 is the normal frequency reduction mode.

[0065] by Figure 3For example, that is, the frequency is reduced from 120Hz to 60Hz, assuming that the display panel 3 includes 1440 scan lines n1, and the number of scan lines n2 corresponding to the vertical blank gap duration Blank1 is 50, then Blank1 = 1s / 120Hz / 1490*50≈0.28ms, Active1 = 1s / 120Hz / 1490*1440. When the frequency is reduced normally, Blank2 = 120Hz / 60Hz*Blank1≈0.56ms, at this time, the vertical blank gap duration increase value Δt1 = 0.56ms-0.28ms=0.28ms. When the frequency is adaptively changed, Blank3 = 1s / 60Hz-1s / 120Hz / 1490*1440≈8.6ms, at this time, the vertical blank gap duration increase value Δt2 = 8.6ms-0.28ms=8.32ms. Obviously, Δt2 is much smaller than Δt1. Therefore, by comparing the difference between the vertical blanking interval duration after frequency reduction and the vertical blanking interval duration before frequency reduction with the preset duration difference threshold t0, it can be determined whether the current frequency reduction mode is the adaptive frequency reduction mode or the normal frequency reduction mode. The preset duration difference threshold t0 can be determined according to the highest frequency fm1, the second highest frequency fm2 and the lowest frequency fn of the display panel 3. Specifically, 1 / fm1 / (n1+n2)*n1*(fm1-fn) / fn <t0<1 / fm2-1 / fm1 / (n1+n2)。

[0066] See also Figure 8 In another implementation, step 620 specifically includes the following steps:

[0067] Step 625, obtaining a pre-frequency reduction period and a post-frequency reduction period of the timing signal output by the timing control module 140. The pre-frequency reduction period is the period of the timing signal output by the timing control module 140 before the refresh frequency is reduced, and the post-frequency reduction period is the period of the timing signal output by the timing control module 140 after the refresh frequency is reduced.

[0068] Step 626, determining whether the pre-frequency reduction period and the post-frequency reduction period are the same. If the pre-frequency reduction period and the post-frequency reduction period are the same, executing step 627. If the pre-frequency reduction period and the post-frequency reduction period are not the same, executing step 628.

[0069] Step 627, determining that the current frequency reduction mode of the display panel 3 is an adaptive frequency reduction mode.

[0070] Step 628: Determine whether the current frequency reduction mode of the display panel 3 is a normal frequency reduction mode.

[0071] by Figure 3For example, the frequency is reduced from 120Hz to 60Hz. The period before the frequency reduction is T1. When the frequency is adaptively changed, the period after the frequency reduction is T2, that is, the period value of the timing signal increases. When the frequency is reduced normally, the period after the frequency reduction is still T1, that is, the period value of the timing signal remains unchanged. Therefore, by comparing the periods of the timing signals before and after the frequency reduction, it can be determined whether the current frequency reduction mode is the adaptive frequency reduction mode or the normal frequency reduction mode.

[0072] It should be noted that the method for identifying the frequency reduction mode may also be other methods, which are not listed one by one in the embodiments of the present application.

[0073] Please also read Figure 9-10 In one implementation, step 640 specifically includes the following steps:

[0074] Step 641, obtaining a preset shutdown voltage calibration table, wherein the preset shutdown voltage calibration table pre-records a mapping relationship between a plurality of refresh frequency ranges and a plurality of shutdown voltages. Fig.10 The shutdown voltage calibration table shown in the figure, where the refresh frequency range is divided into f1~f2, f2~f3...fn-1~fn, and the corresponding shutdown voltages are V1, V2...Vn-1, where f1 <f2<f3<……<fn-1<fn,V1<V2<……<Vn-1。

[0075] Step 642: According to the preset turn-off voltage calibration table, the turn-off voltage corresponding to the current refresh frequency of the display panel 3 is determined as the second turn-off voltage VGL2.

[0076] Step 643, control the power module 130 to output the second shutdown voltage VGL2. Exemplarily, the widths of the refresh frequency ranges in the preset shutdown voltage calibration table are equal. For example, f1 = 48Hz, f2 = 72Hz, f3 = 96Hz, f4 = 120Hz, f5 = 144Hz, f6 = 168Hz, V1 = -14V, V2 = -13.5V, V2 = -12.5V, V2 = -11.5V, V5 = -10.5V, then each refresh frequency range is 24Hz. If the refresh rate before frequency reduction is 165Hz and the current refresh frequency is 60Hz, then the corresponding shutdown voltage is -14V.

[0077] Please refer again Figure 1 Based on the same inventive concept, an embodiment of the present application also provides a driving circuit 2, which is used to drive the display panel 3 for display. The driving circuit 2 includes a power supply module 130 for outputting a shutdown voltage VGL, and the shutdown voltage VGL is used to generate a scanning signal to scan the display panel 3.

[0078] The driving circuit further includes a shutdown voltage control module electrically connected to the power module 130, the shutdown voltage control module is used to detect whether the refresh frequency of the display panel 3 is reduced, and when the refresh frequency of the display panel 3 is detected to be reduced, determine whether the current frequency reduction mode of the display panel 3 is an adaptive frequency reduction mode or a normal frequency reduction mode, and when the current frequency reduction mode of the display panel 3 is the normal frequency reduction mode, control the power module 130 to output a first shutdown voltage VGL1, and when the current frequency reduction mode of the display panel 3 is the adaptive frequency reduction mode, control the power module 130 to output a second shutdown voltage VGL2 according to the current refresh frequency of the display panel 3. The voltage value of the first shutdown voltage VGL1 is a constant value. The voltage value of the second shutdown voltage VGL2 decreases as the current refresh frequency of the display panel 3 decreases, and is lower than the voltage value of the first shutdown voltage VGL1. Furthermore, the driving circuit further includes a timing control module 140, and the timing control module 140 is used to output a timing signal CK to the display panel 3, and the timing signal CK and the shutdown voltage VGL are used together to generate the scanning signal. The timing control module 140 includes the shutdown voltage control module. In the embodiment of the present application, the shutdown voltage control module is the timing control module 140. Of course, in other implementations, the shutdown voltage control module can also be other independent control modules.

[0079] Further, an image frame cycle includes an active display duration and a vertical blank gap duration. In one embodiment, the shutdown voltage control module is specifically used to obtain the vertical blank gap duration before frequency reduction and the vertical blank gap duration after frequency reduction, and to determine whether the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is greater than a preset duration difference threshold t0, and to determine that the current frequency reduction mode of the display panel 3 is an adaptive frequency reduction mode when the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is greater than the preset duration difference threshold t0, and to determine that the current frequency reduction mode of the display panel 3 is a normal frequency reduction mode when the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is less than or equal to the preset duration difference threshold t0. Wherein, the vertical blank gap duration before frequency reduction is the vertical blank gap duration in an image frame cycle before the refresh frequency is reduced, and the vertical blank gap duration after frequency reduction is the vertical blank gap duration in an image frame cycle after the refresh frequency is reduced.

[0080] In another embodiment, the shutdown voltage control module is specifically used to obtain the pre-frequency reduction period and the post-frequency reduction period of the timing signal output by the timing control module 140, and to determine whether the pre-frequency reduction period and the post-frequency reduction period are the same, and to determine that the current frequency reduction mode of the display panel 3 is an adaptive frequency reduction mode when the pre-frequency reduction period and the post-frequency reduction period are the same, and to determine that the current frequency reduction mode of the display panel 3 is a normal frequency reduction mode when the pre-frequency reduction period and the post-frequency reduction period are not the same; wherein the pre-frequency reduction period is the period of the timing signal output by the timing control module 140 before the refresh frequency is reduced, and the post-frequency reduction period is the period of the timing signal output by the timing control module 140 after the refresh frequency is reduced.

[0081] Furthermore, the timing control module 140 also includes a memory for storing a preset shutdown voltage calibration table, wherein the preset shutdown voltage calibration table pre-records a mapping relationship between multiple refresh frequency ranges and multiple shutdown voltages. The shutdown voltage control module is electrically connected to the memory, and the shutdown voltage control module is also specifically used to obtain the preset shutdown voltage calibration table, and determine the shutdown voltage corresponding to the current refresh frequency of the display panel 3 as the second shutdown voltage VGL2 according to the preset shutdown voltage calibration table, and control the power supply module 130 to output the second shutdown voltage VGL2.

[0082] Based on the same inventive concept, an embodiment of the present application further provides a display device 1, which includes the above-mentioned driving circuit 2 and display panel 3, wherein the driving circuit 2 is electrically connected to the display panel 3, and the driving circuit 2 is used to drive the display panel 3 for display.

[0083] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A control method for a driving circuit, wherein the driving circuit is used to drive a display panel for display, the driving circuit comprises a power supply module for outputting a shutdown voltage, the shutdown voltage is used to generate a scanning signal to scan the display panel, characterized in that: The control method of the driving circuit comprises: Detecting whether the refresh frequency of the display panel decreases; If it is detected that the refresh frequency of the display panel is reduced, determining whether the current frequency reduction mode of the display panel is an adaptive frequency reduction mode or a normal frequency reduction mode; If the current frequency reduction mode of the display panel is the normal frequency reduction mode, controlling the power module to output a first shutdown voltage, wherein the voltage value of the first shutdown voltage is a constant value; and If the current frequency reduction mode of the display panel is an adaptive frequency reduction mode, the power supply module is controlled to output a second shutdown voltage according to the current refresh frequency of the display panel, wherein the voltage value of the second shutdown voltage decreases as the current refresh frequency of the display panel decreases and is lower than the voltage value of the first shutdown voltage; An image frame period includes the active display duration and the vertical blanking interval duration; The determining whether the current frequency reduction mode of the display panel is an adaptive frequency reduction mode or a normal frequency reduction mode includes: Obtaining a vertical blank gap duration before frequency reduction and a vertical blank gap duration after frequency reduction; wherein the vertical blank gap duration before frequency reduction is the vertical blank gap duration in an image frame cycle before the refresh frequency is reduced, and the vertical blank gap duration after frequency reduction is the vertical blank gap duration in an image frame cycle after the refresh frequency is reduced; Determine whether the difference between the vertical blank gap duration after the frequency reduction and the vertical blank gap duration before the frequency reduction is greater than a preset duration difference threshold; If the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is greater than the preset duration difference threshold, determining that the current frequency reduction mode of the display panel is an adaptive frequency reduction mode; and If the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is less than or equal to the preset duration difference threshold, it is determined that the current frequency reduction mode of the display panel is the normal frequency reduction mode.

2. The control method of the driving circuit according to claim 1, characterized in that: The driving circuit further comprises a timing control module, the timing control module is used to output a timing signal to the display panel, the timing signal and the shutdown voltage are used together to generate the scanning signal; The determining whether the current frequency reduction mode of the display panel is an adaptive frequency reduction mode or a normal frequency reduction mode includes: Obtaining a pre-frequency reduction period and a post-frequency reduction period of a timing signal output by the timing control module; wherein the pre-frequency reduction period is a period of the timing signal output by the timing control module before the refresh frequency is reduced, and the post-frequency reduction period is a period of the timing signal output by the timing control module after the refresh frequency is reduced; Determining whether the period before frequency reduction and the period after frequency reduction are the same; If the pre-frequency reduction period and the post-frequency reduction period are the same, determining that the current frequency reduction mode of the display panel is an adaptive frequency reduction mode; and If the pre-frequency reduction period and the post-frequency reduction period are different, it is determined that the current frequency reduction mode of the display panel is a normal frequency reduction mode.

3. The control method of the driving circuit according to any one of claims 1 to 2, characterized in that: The controlling the power module to output a second shutdown voltage according to the current refresh frequency of the display panel includes: Obtaining a preset shutdown voltage calibration table, wherein the preset shutdown voltage calibration table pre-records a mapping relationship between a plurality of refresh frequency ranges and a plurality of shutdown voltages; According to the preset shutdown voltage calibration table, determining the shutdown voltage corresponding to the current refresh frequency of the display panel as the second shutdown voltage; and Control the power supply module to output the second shutdown voltage.

4. The control method of the driving circuit according to claim 3, characterized in that: The widths of the refresh frequency ranges in the preset shutdown voltage calibration table are equal.

5. A driving circuit, the driving circuit is used to drive a display panel to display, the driving circuit comprises a power supply module for outputting a shutdown voltage, the shutdown voltage is used to generate a scanning signal to scan the display panel, characterized in that: The driving circuit further includes a shutdown voltage control module electrically connected to the power supply module, the shutdown voltage control module is used to detect whether the refresh frequency of the display panel is reduced, and when the refresh frequency of the display panel is detected to be reduced, determine whether the current frequency reduction mode of the display panel is an adaptive frequency reduction mode or a normal frequency reduction mode, and when the current frequency reduction mode of the display panel is the normal frequency reduction mode, control the power supply module to output a first shutdown voltage, and when the current frequency reduction mode of the display panel is the adaptive frequency reduction mode, control the power supply module to output a second shutdown voltage according to the current refresh frequency of the display panel; wherein the voltage value of the first shutdown voltage is a constant value; the voltage value of the second shutdown voltage decreases as the current refresh frequency of the display panel decreases, and is lower than the voltage value of the first shutdown voltage; An image frame period includes the active display duration and the vertical blanking interval duration; The shutdown voltage control module is specifically used to obtain the vertical blank gap duration before frequency reduction and the vertical blank gap duration after frequency reduction, and to determine whether the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is greater than a preset duration difference threshold, and to determine that the current frequency reduction mode of the display panel is an adaptive frequency reduction mode when the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is greater than the preset duration difference threshold, and to determine that the current frequency reduction mode of the display panel is a normal frequency reduction mode when the difference between the vertical blank gap duration after frequency reduction and the vertical blank gap duration before frequency reduction is less than or equal to the preset duration difference threshold; wherein, the vertical blank gap duration before frequency reduction is the vertical blank gap duration in an image frame period before the refresh frequency is reduced, and the vertical blank gap duration after frequency reduction is the vertical blank gap duration in an image frame period after the refresh frequency is reduced.

6. The driving circuit according to claim 5, characterized in that: The driving circuit further comprises a timing control module, the timing control module is used to output a timing signal to the display panel, the timing signal and the shutdown voltage are used together to generate the scanning signal; the timing control module comprises the shutdown voltage control module; The shutdown voltage control module is specifically used to obtain the pre-frequency reduction period and the post-frequency reduction period of the timing signal output by the timing control module, and to determine whether the pre-frequency reduction period and the post-frequency reduction period are the same, and to determine that the current frequency reduction mode of the display panel is an adaptive frequency reduction mode when the pre-frequency reduction period and the post-frequency reduction period are the same, and to determine that the current frequency reduction mode of the display panel is a normal frequency reduction mode when the pre-frequency reduction period and the post-frequency reduction period are not the same; wherein the pre-frequency reduction period is the period of the timing signal output by the timing control module before the refresh frequency is reduced, and the post-frequency reduction period is the period of the timing signal output by the timing control module after the refresh frequency is reduced.

7. The driving circuit according to any one of claims 5 to 6, characterized in that: The driving circuit further includes a timing control module, and the timing control module further includes a memory for storing a preset shutdown voltage calibration table, wherein the preset shutdown voltage calibration table pre-records a mapping relationship between a plurality of refresh frequency ranges and a plurality of shutdown voltages; The shutdown voltage control module is electrically connected to the memory, and the shutdown voltage control module is also specifically used to obtain the preset shutdown voltage calibration table, and determine the shutdown voltage corresponding to the current refresh frequency of the display panel as the second shutdown voltage according to the preset shutdown voltage calibration table, and control the power supply module to output the second shutdown voltage.

8. A display device, characterized in that: include: Display panel; as well as The driving circuit according to any one of claims 5 to 7, wherein the driving circuit is electrically connected to the display panel, and the driving circuit is used to drive the display panel to display.

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