Dispersion silicon interposer packaging method

Abstract

Embodiments of the present disclosure provide a chip packaging method, comprising: providing a substrate, a plurality of silicon wafers and a plurality of chips; forming a plurality of groups of conductive connection structures on the plurality of silicon wafers respectively, and obtaining a plurality of silicon interposer plates; cutting the plurality of silicon interposer plates respectively to obtain a plurality of silicon interposer blocks; selecting a plurality of target silicon interposer blocks from the plurality of silicon interposer blocks, and fixing back surfaces of the plurality of target silicon interposer blocks on the substrate; and respectively interconnecting the plurality of chips on the corresponding plurality of target silicon interposer blocks. The large silicon interposer plate is cut into small silicon interposer blocks, avoiding warping and cracking of the silicon interlayer during the thinning process. Different specifications of silicon interposer blocks are combined according to the mounting requirements of heterogeneous chips, and are mounted corresponding to each other between the heterogeneous chips and can be formed at one time, reducing the overall area of the silicon interlayer and the spacing of each chip, and greatly improving the integration of the overall package.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor packaging technology, and specifically relates to a method for packaging dispersed silicon interposer chips. Background Technology

[0002] In 2.5D packaging technology, the silicon interposer primarily connects the chip and the substrate, serving as an intermediate structure to amplify the chip's signals and transmit them to the substrate. Currently, chip packages are becoming increasingly thinner, and multiple chips may be connected to the silicon interposer. Therefore, when chips are mounted on the silicon interposer and the interposer is thinned, it can easily cause warping or even cracking of the interposer. Furthermore, the integration density of existing silicon interposers and chips still needs further improvement. Summary of the Invention

[0003] The embodiments disclosed herein are intended to at least address one of the technical problems existing in the prior art, and to provide a chip packaging method.

[0004] The encapsulation method includes:

[0005] It provides substrates, multiple silicon wafers, and multiple chips;

[0006] Multiple sets of conductive connection structures are formed on the multiple silicon wafers respectively, resulting in multiple silicon interposers; wherein at least one of the silicon interposers is different from the other silicon interposers;

[0007] The plurality of silicon interposers are cut into a plurality of silicon interposer blocks;

[0008] Multiple target silicon interposers are selected from the plurality of silicon interposers, and the back sides of the plurality of target silicon interposers are fixed on the substrate; wherein the thickness of the plurality of target silicon interposers is equal.

[0009] The plurality of chips are interconnected and disposed on the corresponding plurality of target silicon interposers.

[0010] Optionally, forming multiple sets of conductive connection structures on the multiple silicon wafers to obtain multiple silicon interposers includes:

[0011] Multiple sets of blind vias are formed on the front side of at least one of the silicon wafers;

[0012] The conductive connection structure is formed by filling the multiple sets of blind vias with conductive material, thereby obtaining the silicon interposer; or...

[0013] The process of forming multiple sets of conductive connection structures on the multiple silicon wafers to obtain multiple silicon interposers includes:

[0014] Multiple sets of blind vias are formed on the front side of at least one of the silicon wafers;

[0015] The conductive connection structure is formed by filling the multiple sets of blind holes with conductive material.

[0016] The back side of the silicon wafer is thinned until the conductive connection structure is exposed to form a through-silicon via, thereby obtaining the silicon interposer.

[0017] Optionally, forming multiple sets of conductive connection structures on the multiple silicon wafers to obtain multiple silicon interposers includes:

[0018] Multiple sets of blind vias are formed on the front side of at least one of the silicon wafers;

[0019] The multiple sets of blind holes are filled with conductive material;

[0020] A redistribution layer is formed on the front side of the silicon wafer to form the conductive connection structure, thereby obtaining the silicon interposer; or,

[0021] The process of forming multiple sets of conductive connection structures on the multiple silicon wafers to obtain multiple silicon interposers includes:

[0022] Multiple sets of blind vias are formed on the front side of at least one of the silicon wafers;

[0023] The multiple sets of blind holes are filled with conductive material;

[0024] A redistribution layer is formed on the front side of the silicon wafer to form the conductive connection structure;

[0025] The back side of the silicon wafer is thinned until the conductive connection structure is exposed to form a through-silicon via, thereby obtaining the silicon interposer.

[0026] Optionally, forming multiple sets of conductive connection structures on the multiple silicon wafers to obtain multiple silicon interposers includes:

[0027] Multiple sets of blind vias are formed on the front side of at least one of the silicon wafers;

[0028] The multiple sets of blind holes are filled with conductive material;

[0029] A redistribution layer is formed on the front side of at least one of the silicon wafers;

[0030] Solder balls are disposed on the redistribution layer to form the conductive connection structure, thereby obtaining the silicon interposer; or...

[0031] The process of forming multiple sets of conductive connection structures on the multiple silicon wafers to obtain multiple silicon interposers includes:

[0032] Multiple sets of blind vias are formed on the front side of at least one of the silicon wafers;

[0033] The multiple sets of blind holes are filled with conductive material;

[0034] A redistribution layer is formed on the front side of at least one of the silicon wafers;

[0035] Solder balls are disposed on the redistribution layer to form the conductive connection structure;

[0036] The back side of the silicon wafer is thinned until the conductive connection structure is exposed to form a through-silicon via, thereby obtaining the silicon interposer.

[0037] Preferably, a plurality of grooves are provided on one surface of the substrate; fixing the back sides of the plurality of target silicon interposers to the substrate includes fixing the back sides of each target silicon interposer into the corresponding groove.

[0038] Optionally, after fixing the back sides of the plurality of target silicon interposers onto the substrate, the method further includes:

[0039] A first bonding structure is formed on the front side of the plurality of target silicon interposers;

[0040] A second bonding structure corresponding to the first bonding structure is formed on the front side of the plurality of chips.

[0041] Optionally, the step of respectively interconnecting the plurality of chips on the corresponding plurality of target silicon interposers includes:

[0042] The first bonding structure and the second bonding structure are fixed together to complete the interconnection of the multiple chips on the multiple target silicon interposers.

[0043] Optionally, after fixing the back sides of the plurality of target silicon interposers onto the substrate, the method further includes:

[0044] Conductive bumps are formed on the front side of the plurality of chips.

[0045] Optional,

[0046] The step of interconnecting the plurality of chips on the corresponding plurality of target silicon interposers includes:

[0047] The conductive bumps are fixed to the front side of the plurality of target silicon interposers;

[0048] An underfill is filled between the plurality of chips and the plurality of target silicon interposers to complete the interconnection of the plurality of chips on the plurality of target silicon interposers.

[0049] Optionally, the multiple chips are fixed on a carrier board and encapsulated, and then the carrier board is removed to obtain a chip reconstituted body.

[0050] One chip packaging method disclosed herein involves cutting a large silicon interposer into smaller silicon interposer blocks, avoiding warping and cracking of the silicon interposer layer during the thinning process. Silicon interposer blocks of different specifications are combined according to the mounting requirements of heterogeneous chips, and these blocks are installed correspondingly to each other and can be formed in a single step. This reduces the overall area of ​​the silicon interposer layer and the spacing between individual chips, significantly improving the overall integration of the package. Attached Figure Description

[0051] Figure 1 This is a flowchart of a chip packaging method according to an embodiment of the present disclosure;

[0052] Figure 2 This is a schematic diagram of a method for forming a silicon interposer according to another embodiment of the present disclosure;

[0053] Figure 3 This is a schematic diagram of a method for forming a silicon interposer according to another embodiment of the present disclosure;

[0054] Figure 4 This is a schematic diagram of a method for forming a silicon interposer according to another embodiment of the present disclosure;

[0055] Figure 5 This is a schematic diagram of a chip interconnection method according to another embodiment of the present disclosure;

[0056] Figure 6 This is a schematic diagram of a chip interconnection method according to another embodiment of the present disclosure;

[0057] Figure 7 This is a schematic diagram of a chip interconnection method according to another embodiment of the present disclosure;

[0058] Figure 8 This is a schematic diagram of a chip interconnection method according to another embodiment of the present disclosure; Detailed Implementation

[0059] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] like Figure 1 As shown, a chip packaging method according to an embodiment of this disclosure includes:

[0061] S11 provides a substrate, multiple silicon wafers, and multiple chips.

[0062] Specifically, multiple silicon wafers are used to fabricate silicon interposers of various specifications. Multiple chips are the chips to be packaged in this embodiment of the disclosure, wherein the specifications of each individual chip can be arbitrary.

[0063] Preferably, one surface of the substrate provided in the embodiments of this disclosure is provided with a plurality of grooves.

[0064] This type of substrate with grooves can be prefabricated. The specific fabrication method is as follows: take a conventional planar substrate, and then etch multiple grooves at predetermined positions on one of its flat surfaces. For ease of description, the embodiments of this disclosure assume that the depth of all the multiple grooves is generally equal.

[0065] The chip packaging method provided by the embodiments of this disclosure is applicable to a variety of different substrates and chips of various specifications, and can meet various packaging requirements in modern chip packaging technology.

[0066] Preferably, the multiple chips are fixed on a carrier board and encapsulated, and then the carrier board is removed to obtain a reconstituted chip assembly. This allows multiple predetermined chips to be packaged into a single unit for subsequent bonding to the silicon interposer and substrate, saving steps, simplifying operation, and improving overall integration.

[0067] S12. Multiple sets of conductive connection structures are formed on the front side of the multiple silicon wafers respectively, and multiple silicon interposers are obtained; wherein, at least one of the silicon interposers is different from the other silicon interposers.

[0068] Specifically, embodiments of this disclosure provide six types of silicon interposers, distinguished by the formation steps. Each type of silicon interposer can be further subdivided into multiple different categories based on the different depths, widths, and densities of the formed holes. Typically, only one type of silicon interposer is processed from each silicon wafer.

[0069] like Figure 2 As shown, the method for forming the first type of silicon interposer is as follows: S21, forming multiple sets of blind vias on the front side of the silicon wafer. S22, filling the multiple sets of blind vias with conductive material to form the conductive connection structure, thereby obtaining the silicon interposer.

[0070] like Figure 2 As shown, based on the first type of silicon interposer, step S23 is added to thin the back side of the silicon wafer until the conductive connection structure is exposed to form a through hole, thus obtaining the silicon interposer. This forms the second type of silicon interposer.

[0071] like Figure 3 As shown, the method for forming the third type of silicon interposer is as follows: S31, forming multiple sets of blind vias on the front side of the silicon wafer. S32, filling the multiple sets of blind vias with conductive material. S33, forming a redistribution layer (RDL) on the front side of the silicon wafer to create the conductive connection structure, thereby obtaining the silicon interposer.

[0072] like Figure 3As shown, based on the third type of silicon interposer, step S34 is added to thin the back side of the silicon wafer until the conductive connection structure is exposed to form a through hole, thus obtaining the silicon interposer. This forms the fourth type of silicon interposer.

[0073] like Figure 4 As shown, the method for forming the fifth type of silicon interposer is as follows: S41, forming multiple sets of blind vias on the front side of the silicon wafer. S42, filling the multiple sets of blind vias with conductive material. S43, setting a redistribution layer on the front side of the silicon wafer. S44, setting solder bumps on the redistribution layer to form the conductive connection structure, thereby obtaining the silicon interposer.

[0074] like Figure 4 As shown, based on the fifth type of silicon interposer, step S45 is added to thin the back side of the silicon wafer until the conductive connection structure is exposed to form a through hole, thus obtaining the silicon interposer. This forms the sixth type of silicon interposer.

[0075] The embodiments of this disclosure provide silicon interposers with various conductive connection structures, which, together with the various substrates and chips described above, can meet various packaging requirements.

[0076] S13. Cut the plurality of silicon interposers into a plurality of silicon interposer blocks; wherein the thickness of the plurality of silicon interposer blocks is equal.

[0077] Specifically, by cutting the various silicon dielectric substrates obtained in the above steps, silicon dielectric blocks of various specifications can be obtained. That is to say, the conductive connection structure, as well as the depth, width, and density of the holes, are not the same for each silicon dielectric block. In the embodiments of this disclosure, all silicon dielectric blocks are cut to the same thickness.

[0078] The embodiments of this disclosure cut large silicon interposers into smaller silicon interposer blocks, avoiding warping and cracking of the silicon interposer layer during the thinning process. Different types of silicon interposer blocks can be arbitrarily combined according to packaging requirements, improving integration density.

[0079] S14. Select a plurality of target silicon interposers from the plurality of silicon interposers, and fix the back sides of the plurality of target silicon interposers onto the substrate.

[0080] Specifically, the silicon interposer blocks required for the packaging process are determined based on the pin layout of the chip to be packaged. This ensures that the conductive connection structures on the silicon interposer blocks can connect to the corresponding pins of the chip, facilitating conductivity. The silicon interposer blocks selected in this way are the target silicon interposer blocks. The back sides of these target silicon interposer blocks are then fixed to corresponding recesses on the substrate.

[0081] The embodiments of this disclosure allow for the arbitrary combination and mounting of silicon interposers of different specifications onto a substrate, enabling chips of different specifications to be mounted onto the corresponding silicon interposers as needed, thereby improving the overall integration.

[0082] S15. The plurality of chips are interconnected and disposed on the corresponding plurality of target silicon interposers.

[0083] Specifically, before and after this step, several different implementation processes need to be completed, depending on the substrate style, the type of target silicon interposer, and its placement in the groove. To enable those skilled in the art to achieve the technical effects of this disclosure, and to make the technical solution of this disclosure clear and complete, some different implementation processes are illustrated below.

[0084] Example 1:

[0085] like Figure 5 As shown, multiple target silicon interposers 51 with blind vias of the same height and a substrate 52 with corresponding grooves etched at their positions are taken. First, all the target silicon interposers 51 are fixed in the corresponding grooves on the substrate 52 with the blind via openings facing outwards. The height of all the target silicon interposers 51 is exactly equal to the depth of the groove, that is, the outer surface of all the target silicon interposers 51 is flush with the surface of the substrate 52 outside the groove.

[0086] Subsequently, a first bonding structure 54 is formed on the flush surface, and a second bonding structure 55 is formed on the side of the chip recombinant 53 described above that has a chip.

[0087] Finally, the first bonding structure 54 and the second bonding structure 55 are fixed together to complete the interconnection setup of multiple chips on multiple target silicon interposers.

[0088] Additionally, the side of the substrate away from the groove can be thinned until all the blind vias of the target silicon interposers are exposed, and redistribution lines (RDLs) and bumping can be performed on the thinned plane for further possible process operations, such as chip stacking.

[0089] Example 2:

[0090] like Figure 6 As shown, multiple target silicon interposers 61 with through holes and a substrate 62 with pre-etched grooves are taken, and the depth of the grooves is consistent with the height of the target silicon interposers 61.

[0091] First, fix the target silicon interposer 61 in the corresponding groove.

[0092] The side of the substrate 62 facing away from the groove is then ground and thinned until the target silicon interposer 61 is exposed.

[0093] Finally, multiple chips 63 of different specifications are fixed onto the corresponding target silicon interposers. The chips 63 can be fixed on the side of the target silicon interposer 61 that originally has a conductive connection structure, or they can be fixed on the side of the target silicon interposer 61 that is newly exposed after thinning, thus completing the interconnection of multiple chips 63 on multiple target silicon interposers 61.

[0094] Additionally, redistribution and balling can be performed on the surface of the substrate and the side of the target silicon interposer that is not bonded to the chip, for further possible operations in the process, such as chip stacking.

[0095] Example three:

[0096] like Figure 7 As shown, multiple target silicon interposers 71 with blind vias and target silicon interposers 72 with through vias are respectively taken, as well as a substrate 73 with grooves pre-etched. The depth of the grooves is consistent with the height of all target silicon interposers.

[0097] First, with the blind hole openings of the target silicon interposer 71 facing outwards, fix all the target silicon interposers in the corresponding grooves pre-etched on the substrate 73.

[0098] The side of substrate 73 facing away from the groove is then ground and thinned until all blind vias are exposed. At this point, all target silicon interposers have through-holes.

[0099] Finally, multiple chips 74 of different specifications are fixed onto the corresponding target silicon interposers. The chips 74 can be fixed on the side of the substrate 73 where there is originally a groove, or on the side of the substrate 73 that is newly exposed after thinning, thus completing the interconnection of multiple chips 74 on multiple target silicon interposers.

[0100] Additionally, redistribution and balling can be performed on the surface of the substrate and the side of the target silicon interposer that is not bonded to the chip, for further possible operations in the process, such as chip stacking.

[0101] Example 4:

[0102] like Figure 8 As shown, multiple target silicon interposers 81 with through holes are taken, and a substrate 82 with grooves pre-etched is taken; the height of a single target silicon interposer 81 is lower than or equal to the height of the groove on the substrate 82.

[0103] First, fix the target silicon interposer 81 with the blind via opening facing outwards in the corresponding groove on the substrate 82.

[0104] Subsequently, a bonding structure 84 is set on the chip reconstituted body 83 as described above at a position corresponding to the silicon interposer 81 whose height is lower than that of the groove. The height of this bonding structure 84 is exactly equal to the height difference between the target silicon interposer 81 and the groove.

[0105] Finally, the chip recombinant 83 is interconnected on multiple target silicon interposers 81 via bonding structure 84.

[0106] Additionally, the side of the substrate away from the groove can be thinned until the target silicon interposer is exposed, and redistribution and ball-mounting can be performed on the thinned plane for further possible operations in the process, such as chip stacking.

[0107] It should be noted that the bonding structure described in the embodiments of this disclosure typically includes conductive bumps (which may be copper bumps) located on the surface of its carrier (substrate, chip, or silicon interposer), and a SiO2 layer or SiCN layer (collectively referred to as a passivation layer) of equal height surrounding the conductive bumps. Alternatively, in the embodiments of this disclosure, if the method of combining multiple chips into a chip assembly and then interconnecting them as a whole is not used, a bonding method of flip-chip bonding of individual chips followed by overall underfill (FC) bonding can also be used. All "front side" refers to the functional surface; the "front side" of the target silicon interposer is the surface with blind via openings and the conductive connection structure formed.

[0108] In chip packaging processes, various types of substrates and target silicon interposers may be required depending on the specific packaging requirements. Embodiments of this disclosure provide packaging operation steps for specific combinations of target silicon interposers and substrates in certain scenarios. Therefore, the chip packaging method of this disclosure has high versatility.

[0109] One chip packaging method disclosed herein involves cutting a large silicon interposer into smaller silicon interposer blocks, avoiding warping and cracking of the silicon interposer layer during the thinning process. Silicon interposer blocks of different specifications are combined according to the mounting requirements of heterogeneous chips, and these blocks are installed correspondingly to each other and can be formed in a single step. This reduces the overall area of ​​the silicon interposer layer and the spacing between individual chips, significantly improving the overall integration of the package.

[0110] It is understood that the above description of the embodiments does not exhaustively cover all possible situations. The purpose of the specific embodiments is to illustrate the principles of this disclosure in detail and to provide some reproducible reference methods. However, this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements will also be considered within the scope of protection of this invention.

Claims

1. A chip packaging method, characterized in that, The encapsulation method includes: A substrate, multiple silicon wafers, and multiple chips are provided; wherein, a plurality of grooves are provided on one surface of the substrate; Multiple sets of conductive connection structures are formed on the multiple silicon wafers respectively, resulting in multiple silicon interposers; wherein at least one of the silicon interposers is different from the other silicon interposers; The plurality of silicon interposers are cut into a plurality of silicon interposer blocks; Multiple target silicon interposers are selected from the plurality of silicon interposers, and the back sides of the plurality of target silicon interposers are fixed in the corresponding grooves on the substrate; wherein the thickness of the plurality of target silicon interposers is equal. The plurality of chips are interconnected and disposed on the corresponding plurality of target silicon interposers.

2. The chip packaging method according to claim 1, characterized in that, The process of forming multiple sets of conductive connection structures on the multiple silicon wafers to obtain multiple silicon interposers includes: Multiple sets of blind vias are formed on the front side of at least one of the silicon wafers; The conductive connection structure is formed by filling the multiple sets of blind vias with conductive material, thereby obtaining the silicon interposer; or... The process of forming multiple sets of conductive connection structures on the multiple silicon wafers to obtain multiple silicon interposers includes: Multiple sets of blind vias are formed on the front side of at least one of the silicon wafers; The conductive connection structure is formed by filling the multiple sets of blind holes with conductive material. The back side of the silicon wafer is thinned until the conductive connection structure is exposed to form a through-silicon via, thereby obtaining the silicon interposer.

3. The chip packaging method according to claim 1, characterized in that, The process of forming multiple sets of conductive connection structures on the multiple silicon wafers to obtain multiple silicon interposers includes: Multiple sets of blind vias are formed on the front side of at least one of the silicon wafers; The multiple sets of blind holes are filled with conductive material; A redistribution layer is formed on the front side of the silicon wafer to form the conductive connection structure, thereby obtaining the silicon interposer; or, The process of forming multiple sets of conductive connection structures on the multiple silicon wafers to obtain multiple silicon interposers includes: Multiple sets of blind vias are formed on the front side of at least one of the silicon wafers; The multiple sets of blind holes are filled with conductive material; A redistribution layer is formed on the front side of the silicon wafer to form the conductive connection structure; The back side of the silicon wafer is thinned until the conductive connection structure is exposed to form a through-silicon via, thereby obtaining the silicon interposer.

4. The chip packaging method according to claim 1, characterized in that, The process of forming multiple sets of conductive connection structures on the multiple silicon wafers to obtain multiple silicon interposers includes: Multiple sets of blind vias are formed on the front side of at least one of the silicon wafers; The multiple sets of blind holes are filled with conductive material; A redistribution layer is formed on the front side of the silicon wafer; Solder balls are disposed on the redistribution layer to form the conductive connection structure, thereby obtaining the silicon interposer; or... The process of forming multiple sets of conductive connection structures on the multiple silicon wafers to obtain multiple silicon interposers includes: Multiple sets of blind vias are formed on the front side of at least one of the silicon wafers; The multiple sets of blind holes are filled with conductive material; A redistribution layer is formed on the front side of the silicon wafer; Solder balls are disposed on the redistribution layer to form the conductive connection structure; The back side of the silicon wafer is thinned until the conductive connection structure is exposed to form a through-silicon via, thereby obtaining the silicon interposer.

5. The chip packaging method according to claim 1, characterized in that, After fixing the back sides of the plurality of target silicon interposers into the corresponding grooves on the substrate, the method further includes: A first bonding structure is formed on the front side of the plurality of target silicon interposers; A second bonding structure corresponding to the first bonding structure is formed on the front side of the plurality of chips.

6. The chip packaging method according to claim 5, characterized in that, The step of interconnecting the plurality of chips on the corresponding plurality of target silicon interposers includes: The first bonding structure and the second bonding structure are fixed together to complete the interconnection of the multiple chips on the multiple target silicon interposers.

7. The chip packaging method according to claim 1, characterized in that, After fixing the back sides of the plurality of target silicon interposers into the corresponding grooves on the substrate, the method further includes: Conductive bumps are formed on the front side of the plurality of chips.

8. The chip packaging method according to claim 7, characterized in that, The step of interconnecting the plurality of chips on the corresponding plurality of target silicon interposers includes: The conductive bumps are fixed to the front side of the plurality of target silicon interposers; An underfill is filled between the plurality of chips and the plurality of target silicon interposers to complete the interconnection of the plurality of chips on the plurality of target silicon interposers.

9. The chip packaging method according to claim 1, characterized in that, The multiple chips are fixed on a carrier board and encapsulated, and then the carrier board is removed to obtain a chip reconstituted body.

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