Highly integrated gated resistors and methods of making the same
By combining MOSFET transistors and ferroelectric tunnel junctions, and utilizing polarization switching to achieve data writing and reading, the problems of complex existing memory structures and crosstalk-induced write/erase errors are solved, realizing a highly integrated and efficient memory device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIANGTAN UNIV
- Filing Date
- 2022-11-29
- Publication Date
- 2026-07-21
AI Technical Summary
Existing 1T1R memory structures are complex, have limited area, suffer from crosstalk and accidental erasure/write phenomena, and traditional ferroelectric tunnel junctions have limited functionality, restricting storage density and integration.
By combining MOSFET transistors and ferroelectric tunnel junctions, data writing and reading are achieved through polarization switching. The use of graphene layer and gate dielectric layer structure simplifies the connection lines and improves the integration density.
A highly integrated gating memristor has been implemented, featuring high switching speed, low power consumption, non-volatility, and compatibility with CMOS processes. It suppresses bypass current in the cross-switch matrix array and is suitable for novel memory and artificial neural network accelerators.
Smart Images
Figure CN115734615B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of microelectronic device technology, and in particular to a highly integrated gating memristor and its fabrication method. Background Technology
[0002] Currently, memory structures based on the 1T1R architecture are complex: the memory and transistors are discrete, and the two units are connected by metal interconnects, making the manufacturing process relatively complex. At the same time, the area of the memory structure based on the 1T1R architecture mainly depends on the area of the transistors and the memory. The complexity of the traditional 1T1R structure prevents the memory structure area from being reduced, thus limiting the storage density. In addition, the traditional ferroelectric tunnel junction has a relatively simple function, and crosstalk and accidental erasure only occur when the ferroelectric tunnel structure is arranged in a cross array. Therefore, matching transistors must be used to perform the selection function to realize the 1T1R structure. Summary of the Invention
[0003] The present invention aims to provide a highly integrated gating memristor and its fabrication method to overcome the shortcomings of the prior art. The technical problem to be solved by the present invention is achieved through the following technical solution.
[0004] The highly integrated gating memristor provided by this invention includes:
[0005] A MOSFET transistor and a ferroelectric tunnel junction;
[0006] The MOSFET transistor includes a substrate, a common semiconductor layer disposed on the substrate, and a first common electrode, a gate, and a second common electrode formed on the common semiconductor layer.
[0007] The ferroelectric tunnel junction includes a ferroelectric semiconductor layer, a common semiconductor layer disposed below the ferroelectric semiconductor layer, a first graphene layer disposed on the common semiconductor layer and a second common electrode disposed on the first graphene layer, a second graphene layer disposed above the ferroelectric semiconductor layer and a first common electrode disposed on the second graphene layer.
[0008] The MOSFET transistor further includes the ferroelectric semiconductor layer, the first graphene layer, the second graphene layer, and the gate dielectric layer. The ferroelectric semiconductor layer and the second graphene layer are sequentially disposed between the common semiconductor layer and the first common electrode. The first graphene layer is disposed between the common semiconductor layer and the second common electrode. The gate dielectric layer surrounds the left, right, and lower sides of the gate.
[0009] The first common electrode is electrically connected to the bit line, the gate is electrically connected to the word line, and the second common electrode is electrically connected to the ground line.
[0010] In the above scheme, a voltage is applied to the gate to open the channel, and a voltage greater than the coercive electric field is applied to the first common electrode to cause the ferroelectric semiconductor layer to undergo a downward polarization reversal or an upward polarization reversal, thereby electrostatically controlling the common semiconductor layer below the ferroelectric semiconductor layer to accumulate charge carriers, and writing the data "0" to the highly integrated gating memristor.
[0011] In the above scheme, a voltage is applied to the gate to open the channel, and a voltage greater than the coercive electric field is applied to the first common electrode to cause the ferroelectric semiconductor layer to undergo an upward or downward polarization reversal, thereby electrostatically controlling the common semiconductor layer below the ferroelectric semiconductor layer to deplete its charge carriers, and writing the data "1" to the highly integrated gating memristor.
[0012] In the above scheme, applying a voltage to the gate turns on the channel. When a read voltage less than the coercive electric field is applied to the first common electrode, the polarization state of the ferroelectric semiconductor layer is not changed, thereby reading the stored data of the highly integrated gating memristor.
[0013] In the above scheme, the substrate is a silicon substrate or a silicon oxide substrate.
[0014] In the above scheme, the common semiconductor layer is a molybdenum sulfide layer, a carbon nanotube layer, a silicon layer, a MoTe2 layer, a WS2 layer, or a WSe2 layer.
[0015] In the above scheme, the ferroelectric semiconductor layer is an indium selenide layer, a hafnium zirconium oxide layer, a WTe2 layer, a SnS layer, a SnSe layer, or a CIPS layer.
[0016] The method for fabricating a highly integrated gating memristor provided by this invention includes:
[0017] A substrate is provided on which a MoS2 layer is grown;
[0018] A ferroelectric semiconductor layer, a first graphene layer, a first metal electrode layer and a first hard mask layer are sequentially formed on the left side of the upper surface of the MoS2 layer, and a second graphene layer, a second metal electrode layer and a second hard mask layer are sequentially formed on the right side of the upper surface of the MoS2 layer, and a groove is formed on the upper surface of the MoS2 layer.
[0019] A gate dielectric layer is grown on the inner ring sidewall of the groove, the upper surface of the first hard mask layer, and the upper surface of the second hard mask layer, and a third metal electrode layer is grown on the gate dielectric layer.
[0020] The third metal electrode layer is polished to remove the gate dielectric layer and the third metal electrode layer on the upper surface of the first hard mask layer, and the gate dielectric layer and the third metal electrode layer on the upper surface of the second hard mask layer are removed to obtain the gate.
[0021] A third hard mask layer is formed on the upper surface of the first hard mask layer, the upper surface of the second hard mask layer, and the gate.
[0022] A photoresist layer is coated on the third hard mask layer. The third hard mask layer, the first hard mask layer, and the second hard mask layer are patterned by photolithography using the photoresist layer as a barrier layer, and a connection via is etched out.
[0023] Remove the photoresist layer;
[0024] Tungsten pillars are PVD sputtered onto the connecting vias and the patterned third hard mask layer.
[0025] The tungsten pillar is CMP polished to form peripheral leads.
[0026] In the above scheme, a ferroelectric semiconductor layer, a first graphene layer, a first metal electrode layer, and a first hard mask layer are sequentially formed on the left side of the upper surface of the MoS2 layer, and a second graphene layer, a second metal electrode layer, and a second hard mask layer are sequentially formed on the right side of the upper surface of the MoS2 layer. The formation of grooves on the upper surface of the MoS2 layer includes:
[0027] A ferroelectric semiconductor layer, a first graphene layer, and a first metal electrode layer are sequentially formed on the MoS2 layer, and a first hard mask layer is deposited on the first metal electrode layer.
[0028] A photoresist layer is coated on the first hard mask layer, and the first hard mask layer is etched and patterned using the photoresist layer as a barrier layer.
[0029] Remove the photoresist layer;
[0030] The first hard mask layer, patterned as a barrier layer, is used to etch the ferroelectric semiconductor layer, the first graphene layer, and the first metal electrode layer to expose the MoS2 layer.
[0031] A second graphene layer is formed on the upper surface of the patterned first hard mask layer, the right side of the ferroelectric semiconductor layer, the right side of the first graphene layer, the right side of the first metal electrode layer, and the exposed upper surface of the MoS2 layer, and a second metal electrode layer is grown on the second graphene layer.
[0032] A second hard mask layer is formed on the second metal electrode layer;
[0033] A photoresist layer is coated on the second hard mask layer, and the second hard mask layer is etched and patterned using the photoresist layer as a barrier layer.
[0034] Remove the photoresist layer;
[0035] The patterned second hard mask layer is used as a barrier layer to etch the second graphene layer and the second metal electrode layer, exposing the MoS2 layer and forming a groove on the upper surface of the MoS2 layer.
[0036] The embodiments of the present invention have the following advantages:
[0037] The highly integrated gating memristor and its fabrication method provided in this invention combine a MOSFET transistor and a ferroelectric tunnel junction, enabling the suppression of bypass current in a cross-switch matrix array. Simultaneously, the hybrid MOSFET and ferroelectric tunnel junction exhibit high switching speed, non-volatility, low power consumption, high scalability, and compatibility with CMOS processes, making it widely applicable in novel memory, artificial neural network accelerators, and in-memory computing processors. Furthermore, the highly integrated gating memristor and its fabrication method omit the source metal electrode of the MOSFET transistor, directly using the extended portion of the semiconductor source terminal of the MOSFET transistor as one end of the ferroelectric tunnel junction. That is, the source of the MOSFET becomes the data write port of the ferroelectric tunnel junction, forming the two ends of the ferroelectric tunnel junction with the drain. This fully realizes the 1T1R memory function, significantly improving the device's integration. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of the structure of a highly integrated gating memristor according to the present invention.
[0039] Figure 2 This is a schematic diagram of one embodiment of the data writing method of the present invention.
[0040] Figure 3 This is a schematic diagram of another embodiment of the data writing method of the present invention.
[0041] Figure 4 This is a schematic diagram of one embodiment of the present invention for reading data.
[0042] Figure 5 This is a schematic diagram of the first process of a method for fabricating a highly integrated gating memristor according to the present invention.
[0043] Figure 6 This is a schematic diagram of the second process of a method for fabricating a highly integrated gating memristor according to the present invention.
[0044] Figure 7 This is a schematic diagram of the third process in the fabrication method of a highly integrated gating memristor according to the present invention.
[0045] Figure 8 This is a schematic diagram of the fourth process in the fabrication method of a highly integrated gating memristor according to the present invention.
[0046] Figure 9 This is a schematic diagram of the fifth process in the fabrication method of a highly integrated gating memristor according to the present invention.
[0047] Figure 10 This is a schematic diagram of the sixth process in the fabrication method of a highly integrated gating memristor according to the present invention.
[0048] Figure 11 This is a schematic diagram of the seventh process in the fabrication method of a highly integrated gating memristor according to the present invention.
[0049] Figure 12 This is a schematic diagram of the eighth process in the fabrication method of a highly integrated gating memristor according to the present invention.
[0050] Figure 13 This is a schematic diagram of the ninth process in the fabrication method of a highly integrated gating memristor according to the present invention.
[0051] Figure 14 This is the tenth process diagram of the fabrication method of a highly integrated selected memristor according to the present invention.
[0052] Figure 15 This is a schematic diagram of the eleventh process in the fabrication method of a highly integrated selected memristor according to the present invention.
[0053] Figure 16 This is a schematic diagram of the twelfth process in the fabrication method of a highly integrated gating memristor according to the present invention. Detailed Implementation
[0054] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0055] like Figure 1 As shown, the present invention provides a highly integrated gating memristor, the gating memristor comprising:
[0056] A MOSFET transistor and a ferroelectric tunnel junction;
[0057] The MOSFET transistor includes a substrate 1, a common semiconductor layer 2 disposed on the substrate 1, and a first common electrode 3, a gate 4, and a second common electrode 5 formed on the common semiconductor layer 2.
[0058] The ferroelectric tunnel junction includes a ferroelectric semiconductor layer 6, a common semiconductor layer 2 disposed below the ferroelectric semiconductor layer 6, a first graphene layer 7 disposed on the common semiconductor layer 2, a second common electrode 5 disposed on the first graphene layer 7, a second graphene layer 8 disposed above the ferroelectric semiconductor layer 6, and a first common electrode 3 disposed on the second graphene layer 8.
[0059] The MOSFET transistor further includes the ferroelectric semiconductor layer 6, the first graphene layer 7, the second graphene layer 8, and the gate dielectric layer 9. The ferroelectric semiconductor layer 6 and the second graphene layer 8 are sequentially disposed between the common semiconductor layer 2 and the first common electrode 3. The first graphene layer 7 is disposed between the common semiconductor layer 2 and the second common electrode 5. The gate dielectric layer 9 surrounds the left, right, and lower sides of the gate 4.
[0060] The first common electrode 3 is electrically connected to the bit line, the gate 4 is electrically connected to the word line, and the second common electrode 5 is electrically connected to the ground line.
[0061] In this embodiment, the source of the MOSFET transistor and the data write port of the ferroelectric tunnel junction share the same electrode.
[0062] In this embodiment, the substrate 1 is a silicon substrate or a silicon oxide substrate.
[0063] In this embodiment, the common semiconductor layer 2 is a molybdenum sulfide layer, a carbon nanotube layer, a silicon layer, a MoTe2 layer, a WS2 layer, or a WSe2 layer, or it can be replaced with other low-dimensional semiconductor layers. When the common semiconductor layer 2 is a molybdenum sulfide layer, the number of molybdenum sulfide layers is 5 or less.
[0064] In this embodiment, the ferroelectric semiconductor layer 6 is an indium selenide layer, a hafnium zirconium oxide layer, a WTe2 layer, a SnS layer, a SnSe layer, or a CIPS layer, or it can be other low-dimensional ferroelectric semiconductor layers.
[0065] In this embodiment, the gate dielectric layer 9 can be any high-k material or existing silicon dioxide material.
[0066] In this embodiment, the working principle of the selected memristor provided by the present invention is as follows: when a high level is applied to one end of the word line, the device switch of the selected memristor is turned on; when a voltage is applied to one end of the bit line, the polarization of the ferroelectric semiconductor is reversed, and the electrons in the ferroelectric semiconductor are accumulated or depleted, causing the conduction current of the selected memristor to change, thereby changing the stored information.
[0067] like Figure 2As shown, taking an NMOSFET transistor as an example, a voltage is applied to the gate 4 to turn on the channel. Specifically, a positive voltage is applied to the gate 4, and a voltage greater than the coercive electric field is applied to the first common electrode 3 to cause the ferroelectric semiconductor layer 6 to undergo a downward polarization reversal. This, in turn, electrostatically controls the common semiconductor layer 2 below the ferroelectric semiconductor layer 6 to accumulate charge carriers, and writes the data "0" to the highly integrated gating memristor.
[0068] Furthermore, taking a PMOSFET transistor as an example, a voltage is applied to the gate 4 to turn on the channel. Specifically, a negative voltage is applied to the gate 4, and a voltage greater than the coercive electric field is applied to the first common electrode 3 to cause the ferroelectric semiconductor layer 6 to undergo an upward polarization reversal. This, in turn, electrostatically modulates the common semiconductor layer 2 below the ferroelectric semiconductor layer 6 to accumulate charge carriers, and writes the data "0" to the highly integrated gating memristor.
[0069] like Figure 3 As shown, taking an NMOSFET transistor as an example, a voltage is applied to the gate 4 to open the channel. Specifically, a positive voltage is applied to the gate 4, and a voltage greater than the coercive electric field is applied to the first common electrode 3 to cause the ferroelectric semiconductor layer 6 to undergo an upward polarization reversal. This then electrostatically controls the common semiconductor layer 2 below the ferroelectric semiconductor layer 6 to deplete its charge carriers, and writes the data "1" to the highly integrated gating memristor.
[0070] Furthermore, taking a PMOSFET transistor as an example, a voltage is applied to the gate 4 to turn on the channel. Specifically, a negative voltage is applied to the gate 4, and a voltage greater than the coercive electric field is applied to the first common electrode 3 to cause the ferroelectric semiconductor layer 6 to undergo a downward polarization reversal. This then electrostatically controls the common semiconductor layer 2 below the ferroelectric semiconductor layer 6 to deplete its charge carriers, and writes the data "1" to the highly integrated gating memristor.
[0071] like Figure 4 As shown, taking an NMOSFET transistor as an example, a voltage is applied to the gate 4 to turn on the channel, and a read voltage less than the coercive field is applied to the first common electrode 3 to read the stored data of the highly integrated memristor. Specifically, a positive voltage is applied to the gate 4, causing electrons to accumulate in the region of the common semiconductor layer 2 to form an inversion layer, and the device switch of the memristor is turned on. At this time, a read voltage less than the coercive field is applied to the first common electrode 3 without changing the polarization state of the ferroelectric semiconductor layer 6. Then, the output current at the drain terminal is measured, and the stored data can be read non-destructively.
[0072] Furthermore, taking a PMOSFET transistor as an example, a voltage is applied to the gate 4 to turn on the channel, and a read voltage less than the coercive field is applied to the first common electrode 3 to read the stored data of the highly integrated gating memristor. Specifically, a negative voltage is applied to the gate 4, causing electrons to accumulate in the region of the common semiconductor layer 2 to form an inversion layer, and the device switch of the gating memristor is turned on. At this time, a read voltage less than the coercive field is applied to the first common electrode 3 without changing the polarization state of the ferroelectric semiconductor layer 6. Then, the output current at the drain terminal is measured, and the stored data can be read non-destructively.
[0073] like Figures 5-16 As shown, the present invention provides a method for fabricating a highly integrated gating memristor, comprising:
[0074] A substrate 21 is provided, on which a MoS2 layer 22 is grown;
[0075] A ferroelectric semiconductor layer 23, a first graphene layer 24, and a first metal electrode layer 25 are sequentially formed on the MoS2 layer 22, and a first hard mask layer 26 is deposited on the first metal electrode layer 25.
[0076] A photoresist layer 27 is coated on the first hard mask layer 26, and the first hard mask layer 26 is etched and patterned using the photoresist layer 27 as a barrier layer.
[0077] Remove the photoresist layer 27;
[0078] The first hard mask layer 26, which is patterned, is used as a barrier layer to etch the ferroelectric semiconductor layer 23, the first graphene layer 24, and the first metal electrode layer 25, thereby exposing the MoS2 layer 22.
[0079] A second graphene layer 28 is formed on the upper surface of the patterned first hard mask layer 26, the right side of the ferroelectric semiconductor layer 23, the right side of the first graphene layer 24, the right side of the first metal electrode layer 25, and the exposed upper surface of the MoS2 layer 22, and a second metal electrode layer 29 is grown on the second graphene layer 28.
[0080] A second hard mask layer 30 is formed on the second metal electrode layer 29;
[0081] A photoresist layer 31 is coated on the second hard mask layer 30, and the second hard mask layer 30 is etched and patterned using the photoresist layer 31 as a barrier layer.
[0082] Remove the photoresist layer 31;
[0083] The patterned second hard mask layer 30 is used as a barrier layer to etch the second graphene layer 28 and the second metal electrode layer 29 to expose the MoS2 layer 22, and a groove 32 is formed on the upper surface of the MoS2 layer 22.
[0084] A gate dielectric layer 33 is grown on the inner ring sidewall of the groove 32, the upper surface of the first hard mask layer 26, and the upper surface of the second hard mask layer 30, and a third metal electrode layer 34 is grown on the gate dielectric layer 33.
[0085] The third metal electrode layer 34 is polished to remove the gate dielectric layer and the third metal electrode layer on the upper surface of the first hard mask layer 26, and the gate dielectric layer and the third metal electrode layer on the upper surface of the second hard mask layer 30 are removed to obtain the gate 35.
[0086] A third hard mask layer 36 is formed on the upper surface of the first hard mask layer 26, the upper surface of the second hard mask layer 30, and the gate 35;
[0087] A photoresist layer 37 is coated on the third hard mask layer 36. The third hard mask layer 36, the first hard mask layer 26 and the second hard mask layer 30 are patterned by photolithography using the photoresist layer 37 as a barrier layer, and the connecting vias are etched out.
[0088] Remove the photoresist layer 37;
[0089] Tungsten pillars 38 are PVD sputtered onto the connecting vias and the patterned third hard mask layer 36;
[0090] The tungsten pillar 38 is CMP polished to form peripheral leads.
[0091] In this embodiment, a MoS2 layer 22 is grown by CVD, ALD or MBE method, and the number of MoS2 layers 22 is 1-5.
[0092] In this embodiment, a ferroelectric semiconductor layer 23 of 1-10 nm is formed by CVD, ALD or MBE methods.
[0093] In this embodiment, the first graphene layer 24 and the second graphene layer 28 are formed by CVD, ALD or MBE methods.
[0094] In this embodiment, the first hard mask layer 26, the second hard mask layer 30, and the third hard mask layer 36 are grown by CVD or PECVD methods.
[0095] In this embodiment, the ferroelectric semiconductor layer 23, the first graphene layer 24, the first metal electrode layer 25, the second graphene layer 28, and the second metal electrode layer 29 are etched by means of ICP, ion beam bombardment, etc.
[0096] In this embodiment, the first metal electrode layer 25, the second metal electrode layer 29, and the third metal electrode layer 34 are grown by PVD.
[0097] In this embodiment, a gate dielectric layer 33 is formed by a method, wherein the gate dielectric layer 33 is a High-k dielectric layer.
[0098] In this embodiment, the interconnect vias are etched using the ICP method.
[0099] It should be noted that the above detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0100] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0101] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.
[0102] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.
[0103] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatial relative descriptions used herein will be interpreted accordingly.
[0104] In the detailed description above, reference has been made to the accompanying drawings, which form part of this document. In the drawings, similar symbols typically identify similar parts unless the context otherwise indicates otherwise. The illustrated embodiments described in the detailed specification, drawings, and claims are not intended to be limiting. Other embodiments may be used and other changes may be made without departing from the spirit or scope of the subject matter presented herein.
[0105] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A highly integrated gating memristor, characterized in that, The selected memristor includes: A MOSFET transistor and a ferroelectric tunnel junction; The MOSFET transistor includes a substrate (1), a common semiconductor layer (2) disposed on the substrate (1), and a first common electrode (3), a gate (4), and a second common electrode (5) formed on the common semiconductor layer (2); The ferroelectric tunnel junction includes a ferroelectric semiconductor layer (6), a common semiconductor layer (2) disposed below the ferroelectric semiconductor layer (6), a first graphene layer (7) disposed on the common semiconductor layer (2) and a second common electrode (5) disposed on the first graphene layer (7), a second graphene layer (8) disposed above the ferroelectric semiconductor layer (6) and a first common electrode (3) disposed on the second graphene layer (8); The MOSFET transistor further includes the ferroelectric semiconductor layer (6), the first graphene layer (7), the second graphene layer (8), and the gate dielectric layer (9). The ferroelectric semiconductor layer (6) and the second graphene layer (8) are sequentially disposed between the common semiconductor layer (2) and the first common electrode (3). The first graphene layer (7) is disposed between the common semiconductor layer (2) and the second common electrode (5). The gate dielectric layer (9) surrounds the left, right, and lower sides of the gate (4). The first common electrode (3) is electrically connected to the bit line, the gate (4) is electrically connected to the word line, and the second common electrode (5) is electrically connected to the ground line.
2. The highly integrated gating memristor according to claim 1, characterized in that, A voltage is applied to the gate (4) to open the channel, and a voltage greater than the coercive field is applied to the first common electrode (3) to cause the ferroelectric semiconductor layer (6) to undergo a downward polarization reversal or an upward polarization reversal. Then, the common semiconductor layer (2) below the ferroelectric semiconductor layer (6) is electrostatically controlled to accumulate its charge carriers, and the data "0" is written to the highly integrated gating memristor.
3. The highly integrated gating memristor according to claim 2, characterized in that, A voltage is applied to the gate (4) to open the channel, and a voltage greater than the coercive field is applied to the first common electrode (3) to cause the ferroelectric semiconductor layer (6) to undergo an upward polarization reversal or a downward polarization reversal, thereby electrostatically controlling the common semiconductor layer (2) below the ferroelectric semiconductor layer (6) to deplete its charge carriers, and writing data "1" to the highly integrated gating memristor.
4. The highly integrated gating memristor according to claim 2, characterized in that, When a voltage is applied to the gate (4) to open the channel, and a read voltage less than the coercive field is applied to the first common electrode (3), the polarization state of the ferroelectric semiconductor layer (6) is not changed, thereby reading the stored data of the highly integrated gating memristor.
5. The highly integrated gating memristor according to claim 1, characterized in that, The substrate (1) is a silicon substrate or a silicon oxide substrate.
6. The highly integrated gating memristor according to claim 5, characterized in that, The common semiconductor layer (2) is a molybdenum sulfide layer, a carbon nanotube layer, a silicon layer, a MoTe2 layer, a WS2 layer, or a WSe2 layer.
7. The highly integrated gating memristor according to claim 6, characterized in that, The ferroelectric semiconductor layer (6) is an indium selenide layer, a hafnium zirconium oxide layer, a WTe2 layer, a SnS layer, a SnSe layer, or a CIPS layer.
8. A method for fabricating a highly integrated gating memristor, characterized in that, The method includes: A substrate is provided on which a MoS2 layer is grown; A ferroelectric semiconductor layer, a first graphene layer, a first metal electrode layer and a first hard mask layer are sequentially formed on the left side of the upper surface of the MoS2 layer, and a second graphene layer, a second metal electrode layer and a second hard mask layer are sequentially formed on the right side of the upper surface of the MoS2 layer, and a groove is formed on the upper surface of the MoS2 layer. A gate dielectric layer is grown on the inner ring sidewall of the groove, the upper surface of the first hard mask layer, and the upper surface of the second hard mask layer, and a third metal electrode layer is grown on the gate dielectric layer. The third metal electrode layer is polished to remove the gate dielectric layer and the third metal electrode layer on the upper surface of the first hard mask layer, and the gate dielectric layer and the third metal electrode layer on the upper surface of the second hard mask layer are removed to obtain the gate. A third hard mask layer is formed on the upper surface of the first hard mask layer, the upper surface of the second hard mask layer, and the gate. A photoresist layer is coated on the third hard mask layer, and the third hard mask layer, the first hard mask layer, and the second hard mask layer are etched and patterned using the photoresist layer 37 as a barrier layer. Remove the photoresist layer; Tungsten pillars are PVD sputtered onto the patterned third hard mask layer; The tungsten pillar is CMP polished to form peripheral leads.
9. The method for fabricating a highly integrated gating memristor according to claim 8, characterized in that, A ferroelectric semiconductor layer, a first graphene layer, a first metal electrode layer, and a first hard mask layer are sequentially formed on the left side of the upper surface of the MoS2 layer. A second graphene layer, a second metal electrode layer, and a second hard mask layer are sequentially formed on the right side of the upper surface of the MoS2 layer. The groove formed on the upper surface of the MoS2 layer includes: A ferroelectric semiconductor layer, a first graphene layer, and a first metal electrode layer are sequentially formed on the MoS2 layer, and a first hard mask layer is deposited on the first metal electrode layer. A photoresist layer is coated on the first hard mask layer, and the first hard mask layer is etched and patterned using the photoresist layer as a barrier layer. Remove the photoresist layer; The first hard mask layer, patterned as a barrier layer, is used to etch the ferroelectric semiconductor layer, the first graphene layer, and the first metal electrode layer to expose the MoS2 layer. A second graphene layer is formed on the upper surface of the patterned first hard mask layer, the right side of the ferroelectric semiconductor layer, the right side of the first graphene layer, the right side of the first metal electrode layer, and the exposed upper surface of the MoS2 layer, and a second metal electrode layer is grown on the second graphene layer. A second hard mask layer is formed on the second metal electrode layer; A photoresist layer is coated on the second hard mask layer, and the second hard mask layer is etched and patterned using the photoresist layer as a barrier layer. Remove the photoresist layer; The patterned second hard mask layer is used as a barrier layer to etch the second graphene layer and the second metal electrode layer, exposing the MoS2 layer and forming a groove on the upper surface of the MoS2 layer.