Computing devices, methods of operation, and machine readable storage media

Abstract

A computing device, a method of operation thereof, and a machine-readable storage medium are provided. The computing device includes execution unit (EU) circuitry and instruction scheduler (IS) circuitry. The IS circuitry can issue instructions to the EU circuitry for execution. The IS circuitry includes a descriptor address register (DAR). The DAR is used to store address information of a resource descriptor. In a case where a current instruction being processed by the IS circuitry uses the resource descriptor, the IS circuitry accesses the address information stored in the DAR local to the IS circuitry without triggering the EU circuitry to read the address information of the resource descriptor from a scalar register file external to the IS circuitry to the IS circuitry. After obtaining the address information of the resource descriptor, the IS circuitry issues the current instruction using the resource descriptor to the EU circuitry for execution based on the address information.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a computing device, a method of operation, and a machine-readable storage medium. Background Technology

[0002] Generally, a resource descriptor describes information about a resource (such as an image or texture), such as its size. Instructions can access resources in memory based on resource descriptors. An instruction may use one or more resource descriptors. For example, a load instruction, store instruction, or atomic instruction (i.e., a minimal operation instruction) uses one resource descriptor, while a texture instruction typically uses two. Unbound resource descriptors are not pre-bound to any on-chip addressable memory. Unbound resource descriptors are usually dynamically fetched by resource access instructions. For example, a memory access instruction must fetch the resource descriptor before performing a memory access on the resource.

[0003] The scalar register file (SRF) pre-stores either the complete 64-bit memory address of the resource descriptor (the address of the target resource in memory) or the 32-bit offset of the resource descriptor in the descriptor set. When an instruction accesses memory using an unbound resource descriptor, the instruction scheduler (IS) retrieves the complete memory address of the unbound resource descriptor from the SRF based on the address provided by the instruction. In the first step of retrieving the resource descriptor's address / offset, the instruction scheduler issues an additional hidden instruction to the execution unit (EU) to read the value (resource descriptor address / offset) from the SRF. In the second step, the execution unit executes the hidden instruction issued by the instruction scheduler to read the resource descriptor's address / offset from the SRF. In the third step, the execution unit returns the value (resource descriptor address / offset) from the SRF back to the instruction scheduler. If the value returned to the instruction scheduler is the offset of the resource descriptor within the descriptor set, the instruction scheduler can use the descriptor set identifier (ID) (or the base memory address of the descriptor set) and the offset returned by the execution unit to calculate the complete memory address of the resource descriptor. Regardless of whether the instruction scheduler calculates the complete memory address of the resource descriptor or the execution unit directly returns the complete memory address of the resource descriptor to the instruction scheduler, after determining the complete memory address of the resource descriptor, the instruction can use the resource descriptor to access memory based on the execution unit's execution.

[0004] The problem is that the instruction scheduler must issue additional hidden instructions to the execution unit, which causes pipeline latency. Hidden instructions are extra instructions dynamically generated by the instruction scheduler, not instructions from the instruction set. Since hidden instructions are not in the program source code, they cannot be optimized during the compilation process. Furthermore, forcing the execution of hidden instructions for each descriptor ignores descriptor reuse within the instruction scheduler and burdens the hardware. Summary of the Invention

[0005] The present invention provides a computing device and a method for operating the same, as well as a machine-readable storage medium, for more efficient acquisition of address information of resource descriptors.

[0006] In an embodiment of the present invention, the computing device includes an execution unit (EU) circuit and an instruction scheduler (IS) circuit. The instruction scheduler circuit is coupled to the execution unit circuit and is used to issue instructions to the execution unit circuit for execution. The instruction scheduler circuit includes descriptor address registers (DARs). The descriptor address registers are used to store the first address information of a first resource descriptor. When the current instruction processed by the instruction scheduler circuit uses the first resource descriptor, the instruction scheduler circuit retrieves the first address information stored in the descriptor address registers locally on the instruction scheduler circuit, without triggering the execution unit circuit to read the first address information of the first resource descriptor from a scalar register file (SRF) outside the instruction scheduler circuit and provide it to the instruction scheduler circuit. After obtaining the first address information of the first resource descriptor, the instruction scheduler circuit issues the current instruction using the first resource descriptor to the execution unit circuit for execution based on the first address information.

[0007] In an embodiment of the present invention, the operation method includes: storing first address information of a first resource descriptor in a descriptor address register of an instruction scheduler circuit of a computing device; when the current instruction being processed by the instruction scheduler circuit uses the first resource descriptor, retrieving the first address information stored in the descriptor address register locally in the instruction scheduler circuit, without triggering the execution unit circuit of the computing device to read the first address information of the first resource descriptor from a scalar register file outside the instruction scheduler circuit and provide it to the instruction scheduler circuit; and after obtaining the first address information of the first resource descriptor, the instruction scheduler circuit, based on the first address information, issues the current instruction using the first resource descriptor to the execution unit circuit for execution.

[0008] In an embodiment of the invention, the machine-readable storage medium is used to store non-transitory machine-readable instructions. When the non-transitory machine-readable instructions are executed by a computer, the operation method of the computing device can be implemented.

[0009] Based on the above, the instruction scheduler circuit is locally configured with a descriptor address register. The instruction scheduler circuit can directly access the address information stored in the local descriptor address register, thus obtaining the resource descriptor address information more efficiently. Depending on the actual design and application scenario, in some embodiments, the address information may include the complete memory address of the resource descriptor or the offset of the resource descriptor in the descriptor set. Therefore, the instruction scheduler avoids issuing additional hidden instructions to the execution unit, thereby avoiding pipeline latency caused by hidden instructions. If the address information of the second resource descriptor used by a subsequent instruction is the same as the address information of the resource descriptor used by the currently used instruction, the instruction scheduler circuit can reuse the address information stored in the descriptor address register. Therefore, the instruction scheduler circuit can more efficiently utilize the address information stored in the descriptor address register locally within the instruction scheduler circuit. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a circuit block of a computing device according to an embodiment of the present invention.

[0011] Figure 2 This is a flowchart illustrating an operation method of a computing device according to an embodiment of the present invention.

[0012] Explanation of reference numerals in the attached figures

[0013] 100: Computing device

[0014] 110: Instruction Scheduler (IS) Circuit

[0015] 111: Descriptor Address Register (DAR)

[0016] 112: Base Address Register (BAR)

[0017] 120: Execution Unit (EU) Circuit

[0018] 130: Scalar Register File

[0019] S210, S220, S230: Steps Detailed Implementation

[0020] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0021] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components, and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0022] Figure 1 This is a schematic diagram of a circuit block of a computing device 100 according to an embodiment of the present invention. Figure 1 The computing device 100 shown includes an instruction scheduler (IS) circuit 110, an execution unit (EU) circuit 120, and a scalar register file (SRF) 130. The EU circuit 120 is coupled to the IS circuit 110 and the scalar register file 130. The IS circuit 110 can issue instructions to the EU circuit 120 for execution. Depending on different design requirements, in some embodiments, the IS circuit 110 and / or the EU circuit 120 can be implemented as hardware circuits. In other embodiments, the IS circuit 110 and / or the EU circuit 120 can be implemented as firmware, software (i.e., a program), or a combination of both. In still other embodiments, the IS circuit 110 and / or the EU circuit 120 can be implemented as a combination of hardware, firmware, and software.

[0023] In hardware terms, the IS circuit 110 and / or EU circuit 120 described above can be implemented as logic circuits on an integrated circuit. For example, the functions of the IS circuit 110 and / or EU circuit 120 can be implemented in various logic blocks, modules, and circuits within one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and / or other processing units. The functions of the IS circuit 110 and / or EU circuit 120 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in an integrated circuit, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0024] In software and / or firmware form, the functions of the IS circuit 110 and / or EU circuit 120 can be implemented as programming codes. For example, the IS circuit 110 and / or EU circuit 120 can be implemented using common programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming code can be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the machine-readable storage medium includes, for example, semiconductor memory and / or storage devices. The semiconductor memory includes memory cards, read-only memory (ROM), flash memory, programmable logic circuits, or other semiconductor memory. The storage device includes tape, disk, hard disk drive (HDD), solid-state drive (SSD), or other storage devices. An electronic device (e.g., a central processing unit (CPU), controller, microcontroller, or microprocessor) can read and execute the programming code from the machine-readable storage medium to implement the relevant functions of the IS circuit 110 and / or EU circuit 120. Alternatively, the programming code can be provided to the electronic device via any transmission medium (e.g., a communication network or broadcast radio waves). The communication network is, for example, the Internet, a wired communication network, a wireless communication network, or other communication media.

[0025] Figure 2 This is a flowchart illustrating an operation method of a computing device according to an embodiment of the present invention. In some embodiments, Figure 2 The operation method of the computing device shown can be implemented in firmware or software (i.e., a program). For example, Figure 2 The operations of the computing device shown can be implemented as non-transitory machine-readable instructions (programming code or program), which can be stored in a machine-readable storage medium. When the non-transitory machine-readable instructions are executed by a computer, they can be implemented... Figure 2 The illustrated method of operating the computing device. In other embodiments, Figure 2 The operation method of the computing device shown can be implemented in hardware, for example, implemented in... Figure 1 The computing device 100 shown.

[0026] Please refer to Figure 1 and Figure 2The IS circuit 110 includes a descriptor address register (DAR) 111 and a base address register (BAR) 112. The base address register 112 stores the base memory address of the descriptor set. The base memory address of the descriptor set can be, for example, 64 bits. Each descriptor set corresponds to one base address register 112. For example, when supporting 4 or 8 descriptor sets, 4 or 8 base address registers 112 are required respectively. The specific number of base address registers 112 can be determined according to the actual design. The descriptor set identifier (Descriptor set ID) is an immediate number embedded in the current instruction. The base address register 112 can be selected using the descriptor set identifier, thereby determining the base memory address of the descriptor set corresponding to the identifier. The number of identifiers is determined by the current instruction; for example, when 2 resource descriptors are required, the current instruction will provide 2 corresponding identifiers. The descriptor address register 111 can store the address information of resource descriptors. Based on actual design and application scenarios, in some embodiments, the address information may include the complete memory address of the resource descriptor or the offset of the resource descriptor within the descriptor set. The complete memory address of the resource descriptor is the sum of the base memory address of the descriptor set and the offset of the resource descriptor within the descriptor set. The specific number of descriptor address registers 111 can be determined according to the actual design. For example, descriptor address register 111 may contain a 32-bit register dar0 (not shown, or a register of other bit count) to store the offset of a resource descriptor within the descriptor set. Alternatively, descriptor address register 111 may contain two 32-bit registers dar0 and dar1 (not shown, or a register of other bit count). When the address information is an offset, the offset of the resource descriptor can be stored in register dar0. When the address information is the complete memory address of the resource descriptor, the complete memory address of the resource descriptor can be stored in both registers dar0 and dar1. Alternatively, the descriptor address register 111 can contain four 32-bit registers dar0, dar1, dar2, and dar3 (not shown, or registers of other bit counts). When an instruction uses a resource descriptor, the offset of the resource descriptor can be stored in register dar0, or the complete memory address of the resource descriptor can be stored in registers dar0 and dar1.When an instruction uses two resource descriptors, the complete memory address (or offset) of one resource descriptor can be stored in registers dar0 and dar1, while the complete memory address (or offset) of the other resource descriptor can be stored in registers dar2 and dar3.

[0027] For example (but not limited to), a warp can have four 32-bit registers: dar0, dar1, dar2, and dar3, and the IS circuit 110 can directly read registers dar0 to dar3 of the descriptor address register 111. Generally, a thread group can include multiple warps, and a warp can also be called a thread bundle. Load instructions or store instructions can use registers dar0 and dar1 of the descriptor address register 111 to store the offset or address of the descriptor. Texture instructions can use registers dar0 and dar1 of the descriptor address register 111 to store the offset or address of the texture descriptor, and use registers dar2 and dar3 of the descriptor address register 111 to store the offset or address of the sampler descriptor.

[0028] Here, it is assumed that the descriptor address register 111 stores the first address information of the first resource descriptor (step S210). When the current instruction processed by the IS circuit 110 uses the first resource descriptor, the IS circuit 110 can retrieve the first address information stored in the descriptor address register 111 locally (step S220) without triggering the EU circuit 120 to read the first address information of the first resource descriptor from the scalar register file 130 outside the IS circuit 110 and provide it to the IS circuit 110. After obtaining the first address information of the first resource descriptor, the IS circuit 110 can issue the current instruction using the first resource descriptor to the EU circuit 120 for execution based on the first address information (step S230).

[0029] When the address information of the second resource descriptor used by the next instruction is the same as the first address information of the first resource descriptor used by the current instruction, that is, when the resource descriptor used by the next instruction is the same as the resource descriptor used by the current instruction, the IS circuit 110 can reuse the first address information stored in the descriptor address register 111 to access the resource in memory (not shown) without triggering the EU circuit 120 to read the address information of the second resource descriptor from the scalar register file 130 for the IS circuit 110. After obtaining the address information of the second resource descriptor (i.e., the first address information), the IS circuit 110 can issue the current instruction using the second resource descriptor to the EU circuit 120 for execution based on the first address information (step S230).

[0030] Based on practical design and application scenarios, in some embodiments, the address information may include the complete memory address of the resource descriptor or the offset of the resource descriptor within the descriptor set. If the address information includes the offset of the resource descriptor within the descriptor set, the IS circuit 110 can select the corresponding base address register 112 based on the descriptor set identifier carried in the current instruction, and then use the base memory address of the descriptor set stored in the base address register 112 and the offset stored in the descriptor address register 111 to calculate the complete memory address of the first resource descriptor. The IS circuit 110 can issue the complete memory address and the current instruction using the first resource descriptor to the EU circuit 120 for execution. If the address information includes the complete memory address of the first resource descriptor in memory, the IS circuit 110 can issue the complete memory address stored in the descriptor address register 111 and the current instruction using the first resource descriptor to the EU circuit 120 for execution.

[0031] In summary, the descriptor address register 111 can be added to the IS circuit 110. The IS circuit 110 can directly access the address information stored in the local descriptor address register 111, thus obtaining the address information of the resource descriptor (e.g., the complete memory address of the resource descriptor or the offset of the resource descriptor within the descriptor set) more efficiently. Based on this, the IS circuit 110 avoids issuing additional hidden instructions to the EU circuit 120, thereby avoiding pipeline latency caused by hidden instructions and reducing the hardware burden. When the address information of the second resource descriptor used by a subsequent instruction is the same as the first address information of the first resource descriptor used by the current instruction, the IS circuit 110 can reuse the address information stored in the descriptor address register 111. Therefore, the IS circuit 110 can utilize the address information stored in the descriptor address register 111 locally within the IS circuit 110 more efficiently.

[0032] In contrast, prior art instruction schedulers must issue additional hidden instructions to the execution unit for each boundless resource descriptor to trigger the execution unit to read the value (the address / offset of the resource descriptor) in the scalar register file. The problem is that these hidden instructions issued by prior art instruction schedulers cause pipeline delays in the execution unit. Furthermore, hidden instructions are additional instructions dynamically generated by the instruction scheduler, rather than instructions from the instruction set. Since hidden instructions are not in the program source code, they cannot be optimized during the compilation process. Moreover, prior art forces the issuance / execution of hidden instructions for each descriptor, thus ignoring the reuse of descriptors within the instruction scheduler and burdening the hardware.

[0033] Please refer to Figure 1The embodiment of the present invention is shown. In this embodiment, a new move instruction SMOVD can be added to the instruction set to move a value (the full memory address of the resource descriptor or the offset of the resource descriptor within the descriptor set) from the scalar register file 130 to the descriptor address register 111. For example, depending on the actual operating scenario, the move instruction SMOVD can be the following pseudo code [1]. In the following pseudo code [1], dest represents the descriptor address register 111, and source can represent the scalar register file 130, constant random access memory (RAM), a constant register, or an immediate value. Programs or shaders can use the move instruction SMOVD to update the descriptor address register 111.

[0034] smovd dest,source; pseudocode[1]

[0035] The SMOVD instruction is a set-of instruction. Since the SMOVD instruction resides in the program source code, it can be optimized during the compilation process. When the second address information of the second resource descriptor used by a subsequent instruction differs from the first address information of the first resource descriptor used by the current instruction—that is, when the resource descriptor used by the next instruction is not the same as the resource descriptor used by the current instruction—IS circuit 110 can issue the SMOVD instruction to EU circuit 120. Based on the SMOVD instruction, EU circuit 120 can move the second address information of the second resource descriptor from the scalar register file 130 outside IS circuit 110 to the descriptor address register 111 local to IS circuit 110. Therefore, when IS circuit 110 processes the subsequent instruction using the second resource descriptor, IS circuit 110 can retrieve the second address information stored in descriptor address register 111. After obtaining the second address information of the second resource descriptor, the IS circuit 110 can issue the subsequent instructions using the second resource descriptor to the EU circuit 120 for execution based on the second address information.

[0036] In contrast, prior art instruction schedulers issued additional hidden instructions to the execution unit for each unbound resource descriptor, triggering the execution unit to read the value (the address / offset of the resource descriptor) in the scalar register file. The problem is that these hidden instructions are extra instructions dynamically generated by the instruction scheduler, not instructions from the instruction set. Since these hidden instructions are not in the program source code, they cannot be optimized during the compilation process.

[0037] Please refer to Figure 1The embodiments of the present invention are shown. In some practical operating scenarios, the address information of the resource descriptors generated by scalar operations can be directly stored in the descriptor address register 111 local to the IS circuit 110. In other practical operating scenarios, the address information of the resource descriptors generated by scalar operations can be stored in the scalar register file 130 outside the IS circuit 110 for use by the IS circuit 110.

[0038] For example, before IS circuit 110 processes the current instruction, IS circuit 110 processes scalar operation instructions to generate the first address information of the first resource descriptor. At this time, when IS circuit 110 needs to reuse the first address information, IS circuit 110 can directly store the first address information in its local descriptor address register 111, instead of storing it in the external scalar register file 130 via EU circuit 120. When IS circuit 110 processes the current instruction using the first resource descriptor, IS circuit 110 can retrieve the first address information stored in descriptor address register 111. Therefore, IS circuit 110 can issue the current instruction using the first resource descriptor to EU circuit 120 for execution based on the first address information. When IS circuit 110 does not need to reuse the first address information, IS circuit 110 can store the first address information in the external scalar register file 130 via EU circuit 120.

[0039] For example, when the second address information of the second resource descriptor used by the next instruction is different from the first address information of the first resource descriptor used by the current instruction—that is, when the resource descriptor used by the next instruction is not the resource descriptor used by the current instruction—IS circuit 110 processes scalar operation instructions to generate the second address information of the second resource descriptor. In this case, IS circuit 110 can directly store the second address information in its local descriptor address register 111, instead of storing it in the external scalar register file 130 (e.g., when IS circuit 110 does not need to reuse the second address information). Therefore, when IS circuit 110 processes the next instruction using the second resource descriptor, IS circuit 110 can retrieve the second address information stored in descriptor address register 111. After obtaining the second address information of the second resource descriptor, IS circuit 110 can issue the next instruction using the second resource descriptor to EU circuit 120 for execution based on the second address information.

[0040] For another example, after the scalar operation instruction processed by IS circuit 110 generates the first address information of the first resource descriptor, IS circuit 110 can store the first address information in the scalar register file 130 outside IS circuit 110. Before IS circuit 110 processes the current instruction using the first resource descriptor, IS circuit 110 can issue a move instruction SMOVD to EU circuit 120 to move the first address information of the first resource descriptor from scalar register file 130 to descriptor address register 111 of IS circuit 110. When IS circuit 110 processes the current instruction using the first resource descriptor, IS circuit 110 can retrieve the first address information stored in descriptor address register 111. Therefore, IS circuit 110 can issue the current instruction using the first resource descriptor to EU circuit 120 for execution based on the first address information.

[0041] Based on practical design, in some embodiments, the descriptor address register 111 can be added to the address space of the scalar register file 130. A program or shader can update the descriptor address register 111 using a target address in the address space of the scalar register file 130. For example, a first interval of the address space can correspond to the scalar register file 130 outside the IS circuit 110, while a second interval of the address space can correspond to the descriptor address register 111 local to the IS circuit 110. After a scalar operation instruction processed by the IS circuit 110 generates the first address information of the first resource descriptor, the IS circuit 110 can use the address space to selectively store the first address information in either the scalar register file 130 or the descriptor address register 111. As a concrete example of adding descriptor address register 111 to the address space of scalar register file 130, it is assumed that the address space of scalar register file 130 is a 7-bit address space, where each address from 0 to 63 (the first interval of the address space) can be used to represent a regular scalar register in scalar register file 130, and each address from 64 to 67 (the second interval of the address space) can be used to represent one of the registers dar0 to dar3 in descriptor address register 111. IS circuit 110 can use the address space of scalar register file 130 to specify that the result of a scalar operation should be written to descriptor address register 111.

[0042] In summary, the IS circuit 110 can directly access the descriptor address register 111 local to the IS circuit 110, thus eliminating the hidden instructions that cause EU pipeline delays. Because the IS circuit does not need to prepare and issue hidden instructions, its complexity is reduced. When the address information of the second resource descriptor used by a subsequent instruction is the same as the address information of the resource descriptor used by the current instruction, the IS circuit 110 can reuse the address information stored in the descriptor address register 111, that is, reuse resource descriptors with the same offset (or address) (which was impossible in the prior art). Therefore, the IS circuit 110 can achieve better performance when a series of instructions use the same resource descriptor.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A computing device, characterized in that, The computing device includes: Execution unit circuit; and An instruction scheduler circuit, coupled to the execution unit circuit, is used to issue instructions to the execution unit circuit for execution. The instruction scheduler circuit includes a descriptor address register, which stores the first address information of a first resource descriptor. When the instruction being processed by the instruction scheduler circuit uses the first resource descriptor, the instruction scheduler circuit retrieves the first address information stored in the descriptor address register locally within the instruction scheduler circuit, without triggering the execution unit circuit to read the first address information of the first resource descriptor from the scalar register file outside the instruction scheduler circuit and provide it to the instruction scheduler circuit. After obtaining the first address information of the first resource descriptor, the instruction scheduler circuit issues the current instruction using the first resource descriptor to the execution unit circuit for execution based on the first address information.

2. The computing device according to claim 1, characterized in that, If the address information of the second resource descriptor used in the subsequent instruction is the same as the first address information of the first resource descriptor used in the current instruction, the instruction scheduler circuit reuses the first address information stored in the descriptor address register without triggering the execution unit circuit to read the first address information from the scalar register file for the instruction scheduler circuit.

3. The computing device according to claim 1, characterized in that, If the second address information of the second resource descriptor used in the subsequent instruction is not the first address information of the first resource descriptor used in the current instruction: the instruction scheduler circuit issues a move instruction of the instruction set to the execution unit circuit to move the second address information of the second resource descriptor from the scalar register file outside the instruction scheduler circuit to the descriptor address register local to the instruction scheduler circuit; or the instruction scheduler circuit processes the scalar operation instruction to generate the second address information of the second resource descriptor; or the instruction scheduler circuit directly stores the second address information in the descriptor address register local to the instruction scheduler circuit, instead of storing the second address information in the scalar register file outside the instruction scheduler circuit. When the instruction scheduler circuit processes the next instruction using the second resource descriptor, the instruction scheduler circuit retrieves the second address information stored in the descriptor address register; as well as After obtaining the second address information of the second resource descriptor, the instruction scheduler circuit issues the next instruction using the second resource descriptor to the execution unit circuit for execution based on the second address information.

4. The computing device according to claim 1, characterized in that, Before the instruction scheduler circuit processes the current instruction, the instruction scheduler circuit processes scalar operation instructions to generate the first address information of the first resource descriptor, and the instruction scheduler circuit directly stores the first address information in the descriptor address register local to the instruction scheduler circuit, instead of storing the first address information in the scalar register file outside the instruction scheduler circuit.

5. The computing device according to claim 1, characterized in that, After the scalar operation instruction processed by the instruction scheduler circuit generates the first address information of the first resource descriptor, the instruction scheduler circuit stores the first address information in the scalar register file outside the instruction scheduler circuit. as well as Before the instruction scheduler circuit processes the current instruction, the instruction scheduler circuit issues a move instruction for the instruction set to the execution unit circuit to move the first address information of the first resource descriptor from the scalar register file to the descriptor address register of the instruction scheduler circuit.

6. The computing device according to claim 1, characterized in that, The descriptor address register is added to the address space of the scalar register file. The first interval of the address space corresponds to the scalar register file outside the instruction scheduler circuit, and the second interval of the address space corresponds to the descriptor address register local to the instruction scheduler circuit. After the scalar operation instruction processed by the instruction scheduler circuit generates the first address information of the first resource descriptor, the instruction scheduler circuit uses the address space to selectively store the first address information in either the scalar register file or the descriptor address register.

7. The computing device according to claim 1, characterized in that, The first address information includes the offset of the first resource descriptor within the descriptor set, and the instruction scheduler circuit further includes: The base address register is used to store the base memory address of the descriptor set. The instruction scheduler circuit uses the base memory address stored in the base address register and the offset stored in the descriptor address register to calculate the complete memory address of the first resource descriptor, and the instruction scheduler circuit issues the complete memory address and the current instruction using the first resource descriptor to the execution unit circuit for execution.

8. The computing device according to claim 1, characterized in that, The first address information includes the complete memory address of the first resource descriptor in the memory, and the instruction scheduler circuit issues the complete memory address stored in the descriptor address register and the current instruction using the first resource descriptor to the execution unit circuit for execution.

9. A method for operating a computing device, characterized in that, The operation method includes: The first address information of the first resource descriptor is stored in the descriptor address register of the instruction scheduler circuit of the computing device; When the instruction being processed by the instruction scheduler circuit uses the first resource descriptor, the first address information stored in the descriptor address register local to the instruction scheduler circuit is retrieved without triggering the execution unit circuit of the computing device to read the first address information of the first resource descriptor from the scalar register file outside the instruction scheduler circuit and provide it to the instruction scheduler circuit; and After obtaining the first address information of the first resource descriptor, the instruction scheduler circuit issues the current instruction using the first resource descriptor to the execution unit circuit for execution based on the first address information.

10. The operating method according to claim 9, characterized in that, The operation method further includes: If the address information of the second resource descriptor used in the next instruction is the same as the first address information of the first resource descriptor used in the current instruction, the first address information stored in the descriptor address register is reused without triggering the execution unit circuit to read the first address information from the scalar register file to the instruction scheduler circuit.

11. The operating method according to claim 9, characterized in that, The operation method further includes: If the second address information of the second resource descriptor used in the subsequent instruction is not the first address information of the first resource descriptor used in the current instruction: the instruction scheduler circuit issues a move instruction of the instruction set to the execution unit circuit to move the second address information of the second resource descriptor from the scalar register file outside the instruction scheduler circuit to the descriptor address register local to the instruction scheduler circuit; or the instruction scheduler circuit processes the scalar operation instruction to generate the second address information of the second resource descriptor; or the instruction scheduler circuit directly stores the second address information in the descriptor address register local to the instruction scheduler circuit, instead of storing the second address information in the scalar register file outside the instruction scheduler circuit. When the instruction scheduler circuit processes the subsequent instruction using the second resource descriptor, it retrieves the second address information stored in the descriptor address register; and After obtaining the second address information of the second resource descriptor, the instruction scheduler circuit issues the subsequent instruction using the second resource descriptor to the execution unit circuit for execution based on the second address information.

12. The operating method according to claim 9, characterized in that, The operation method further includes: Before the instruction scheduler circuit processes the current instruction, the instruction scheduler circuit processes scalar operation instructions to generate the first address information of the first resource descriptor; and The first address information is stored directly in the descriptor address register local to the instruction scheduler circuit, instead of being stored in the scalar register file outside the instruction scheduler circuit.

13. The operating method according to claim 9, characterized in that, The operation method further includes: After the scalar operation instruction processed by the instruction scheduler circuit generates the first address information of the first resource descriptor, the first address information is stored in the scalar register file outside the instruction scheduler circuit; and Before the instruction scheduler circuit processes the current instruction, the instruction scheduler circuit issues a move instruction for the instruction set to the execution unit circuit, so as to move the first address information of the first resource descriptor from the scalar register file to the descriptor address register of the instruction scheduler circuit.

14. The operating method according to claim 9, characterized in that, The descriptor address register is added to the address space of the scalar register file, the first interval of the address space corresponds to the scalar register file outside the instruction scheduler circuit, the second interval of the address space corresponds to the descriptor address register local to the instruction scheduler circuit, and the operation method further includes: After the scalar operation instruction processed by the instruction scheduler circuit generates the first address information of the first resource descriptor, the address space is used to selectively store the first address information in either the scalar register file or the descriptor address register.

15. The operating method according to claim 9, characterized in that, The first address information includes the offset of the first resource descriptor within the descriptor set, and the operation method further includes: The base address register of the instruction scheduler circuit stores the basic memory address of the descriptor set; The complete memory address of the first resource descriptor is calculated using the base memory address stored in the base address register and the offset stored in the descriptor address register; and The instruction scheduler circuit issues the complete memory address and the current instruction using the first resource descriptor to the execution unit circuit for execution.

16. The operating method according to claim 9, characterized in that, The first address information includes the complete memory address of the first resource descriptor in memory, and the operation method further includes: The instruction scheduler circuit sends the complete memory address stored in the descriptor address register and the current instruction using the first resource descriptor to the execution unit circuit for execution.

17. A machine-readable storage medium for storing non-transitory machine-readable instructions that, when executed by a computer, can implement the operation method of the computing device according to any one of claims 9-16.

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