Shift register unit, gate drive circuit and touch display device

Abstract

Embodiments of the present application provide a shift register unit, a gate drive circuit and a touch display device. The shift register unit comprises an input module, an output module, an energy storage module, a first pull-down module and a first reset module. The input module is connected with an input end, a first signal end and a pull-up node respectively; the output module is connected with a clock signal end, an output end and the pull-up node respectively; one end of the energy storage module is connected with the pull-up node, and the other end of the energy storage module is connected with the output end; the first pull-down module is connected with the pull-up node, a pull-down node, a second signal end and a third signal end respectively; and the first reset module is connected with the pull-up node, a first reset signal end and a fourth signal end respectively. By eliminating the leakage path on the basis of maintaining the original process, the embodiments of the present application can avoid the voltage of the pull-up node from being reduced after the LHB pit is output, thereby reducing the horizontal stripe defect in the LH drive mode.

Description

TECHNICAL FIELD

[0001] The present application relates to the display technical field, and in particular, the present application relates to a shift register unit, a gate drive circuit and a touch display device. BACKGROUND

[0002] Currently, the development trend of electronic products is light and thin, and the design challenge of display products is also higher and higher. With the continuous popularization of active pen in NB (notebook computer), TPC (tablet computer), Mobile (mobile phone) and other display products, the advantages of In-cell (in-cell touch screen) technology are increasingly prominent. The in-cell touch screen has the advantages of simple process, high product characteristic compatibility, excellent touch performance, low cost, lightness and thinness.

[0003] Currently, some in-cell touch display devices (such as the current mainstream a-Si Mobile In-cell display products) have horizontal stripe defects in the LH driving mode (the LH driving mode refers to a driving mode in which touch signals are inserted during screen display time), which limits the application of the LH driving mode in TPC (tablet computer), NB (notebook computer) and other display products. SUMMARY

[0004] The present application proposes a shift register unit, a gate drive circuit and a touch display device to solve the technical problem of horizontal stripe defects of the in-cell touch display device in the LH driving mode in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a shift register unit, comprising:

[0006] An input module is connected with an input end, a first signal end and a pull-up node respectively;

[0007] An output module is connected with a clock signal end, an output end and the pull-up node respectively;

[0008] An energy storage module, one end of the energy storage module is connected with the pull-up node, and the other end of the energy storage module is connected with the output end;

[0009] A first pull-down module is connected with the pull-up node, a pull-down node, a second signal end and a third signal end respectively;

[0010] A first reset module is connected with the pull-up node, a first reset signal end and a fourth signal end respectively;

[0011] In the touch phase, the signal of the first signal end keeps a high level signal, the signal of the second signal end is pulled to a low level signal, the signal of the third signal end keeps a low level signal, and the signal of the fourth signal end is pulled to a high level signal.

[0012] In a possible implementation, the circuit further includes:

[0013] a second pull-down module connected with the pull-up node, the pull-down node and the fourth signal terminal respectively;

[0014] a third pull-down module connected with the output terminal, the pull-down node and the third signal terminal respectively.

[0015] In a possible implementation, the circuit further includes:

[0016] a second reset module connected with the pull-up node, the second reset signal terminal and the fourth signal terminal respectively;

[0017] a third reset module connected with the output terminal, the second reset signal terminal and the third signal terminal respectively.

[0018] In a possible implementation, the circuit further includes:

[0019] a first noise reduction module connected with the pull-down node, the fourth signal terminal and the third signal terminal respectively;

[0020] a second noise reduction module connected with the output terminal, the fourth signal terminal and the third signal terminal respectively.

[0021] In a possible implementation, the first noise reduction module includes a first transistor, and the second noise reduction module includes a second transistor.

[0022] a first electrode of the first transistor is connected with the pull-down node, a second electrode of the first transistor is connected with the third signal terminal, and a control electrode of the first transistor is connected with the fourth signal terminal;

[0023] a first electrode of the second transistor is connected with the output terminal, a second electrode of the second transistor is connected with the third signal terminal, and a control electrode of the second transistor is connected with the fourth signal terminal.

[0024] In a possible implementation, the input module includes a third transistor, the output module includes a fourth transistor, the first pull-down module includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, and the first reset module includes a ninth transistor.

[0025] a control electrode of the third transistor is connected with the input terminal, a first electrode of the third transistor is connected with the first signal terminal, and a second electrode of the third transistor is connected with the pull-up node;

[0026] a control electrode of the fourth transistor is connected with the pull-up node, a first electrode of the fourth transistor is connected with the clock signal terminal, and a second electrode of the fourth transistor is connected with the output terminal.

[0027] The first electrode of the fifth transistor, the first electrode of the eighth transistor and the control electrode are connected with a second signal terminal, the second electrode of the fifth transistor is connected with the first electrode of the sixth transistor, the control electrode of the fifth transistor and the second electrode of the eighth transistor are connected with a first node, and the first electrode of the seventh transistor is connected with the first node; the second electrode of the sixth transistor and the second electrode of the seventh transistor are connected with a third signal terminal; the control electrode of the sixth transistor and the control electrode of the seventh transistor are connected with a pull-up node.

[0028] The first electrode of the ninth transistor is connected with the pull-up node, the second electrode of the ninth transistor is connected with a fourth signal terminal, and the control electrode of the ninth transistor is connected with a first reset signal terminal.

[0029] In a possible implementation, the second pull-down module includes a tenth transistor, and the third pull-down module includes an eleventh transistor.

[0030] The first electrode of the tenth transistor is connected with the pull-up node, the second electrode of the tenth transistor is connected with the fourth signal terminal, and the control electrode of the tenth transistor is connected with a pull-down node.

[0031] The first electrode of the eleventh transistor is connected with an output terminal, the second electrode of the eleventh transistor is connected with the third signal terminal, and the control electrode of the eleventh transistor is connected with the pull-down node.

[0032] In a possible implementation, the second reset module includes a twelfth transistor, and the third reset module includes a thirteenth transistor.

[0033] The first electrode of the twelfth transistor is connected with the pull-up node, the second electrode of the twelfth transistor is connected with the fourth signal terminal, and the control electrode of the twelfth transistor is connected with a second reset signal terminal.

[0034] The first electrode of the thirteenth transistor is connected with the output terminal, the second electrode of the thirteenth transistor is connected with the third signal terminal, and the control electrode of the thirteenth transistor is connected with the second reset signal terminal.

[0035] In a second aspect, an embodiment of the present application provides a gate drive circuit, including at least two cascaded shift register units as any of the first aspect.

[0036] The output terminal of each shift register unit is electrically connected with the input terminal of the next shift register unit.

[0037] The first reset signal terminal of each shift register unit is electrically connected with the output terminal of the next shift register unit.

[0038] In a third aspect, an embodiment of the present application provides a touch display device, including the gate drive circuit as the second aspect.

[0039] The technical scheme provided by the embodiments of the present application has the beneficial technical effects of:

[0040] The shift register unit provided by the embodiments of the present application is connected with the input module through the first signal end, and in the touch stage, the two ends of the input module are both high-level signals because the first signal end and the pull-up node are both high-level signals, the two ends of the input module are consistent in level, and the leakage path of the pull-up node is blocked. The first reset module is connected with the fourth signal end, and in the touch stage, the two ends of the first reset module are both high-level signals because the pull-up node and the fourth signal end are both high-level signals, the two ends of the first reset module are consistent in level, the first reset module is ensured to be closed, the leakage path of the pull-up node is blocked, and therefore the touch display device, especially the touch display device supporting the active pen, can maintain the pull-up node at a high level after the pull-up node goes out of the LHB pit in the touch stage until the display stage.

[0041] The embodiments of the present application can avoid the voltage of the pull-up node from being reduced after the pull-up node goes out of the LHB pit by eliminating the leakage path on the basis of maintaining the original process, thereby reducing the horizontal stripe defect in the LH driving mode, avoiding the abnormal display problem of the touch display device, especially the a-Si (amorphous silicon) touch display device, caused by too long LHB time, and supporting longer LHB time requirement due to the elimination of the leakage path.

[0042] Additional aspects and advantages of the present application will be made apparent from the following description, which, taken in conjunction with the accompanying drawings, which illustrate by way of example the principles of the application. BRIEF DESCRIPTION OF DRAWINGS

[0043] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken in conjunction with the accompanying drawings, in which:

[0044] Figure 1 The waveform schematic diagram of the pull-up node PU before the LHB pit of the prior art is shown in FIG. 1;

[0045] Figure 2 The waveform schematic diagram of the pull-up node PU after the LHB pit of the prior art is shown in FIG. 2;

[0046] Figure 3 The circuit principle schematic diagram of the shift register unit provided by the embodiments of the present application is shown in FIG. 3;

[0047] Figure 4 The timing schematic diagram of the shift register unit provided by the embodiments of the present application is shown in FIG. 4;

[0048] Figure 5 The output waveform schematic diagram of the shift register unit for the pixel row going into the LHB pit provided by the embodiments of the present application is shown in FIG. 5;

[0049] Figure 6 An output waveform diagram of a shift register unit for a non-LHB pit pixel row provided by an embodiment of the present application is shown.

[0050] Reference signs:

[0051] 100 - shift register unit, 10 - input module, 20 - output module, 30 - storage module, 40 - first pull-down module, 41 - second pull-down module, 61 - first noise reduction module, 62 - second noise reduction module, 42 - third pull-down module, 50 - first reset module, 51 - second reset module, 52 - third reset module. DETAILED DESCRIPTION

[0052] The present application is described in detail below, examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or like reference numerals represent the same or like parts or parts having the same or similar functions throughout. In addition, if a detailed description of known technology is unnecessary for the features of the present application shown, it is omitted. The embodiments described below by reference to the accompanying drawings are exemplary and are for the purpose of explaining the present application only, and cannot be interpreted as limiting the present application.

[0053] Those skilled in the art can understand that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs. It should also be understood that terms such as those defined in a general dictionary should be understood to have meanings consistent with meanings in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as such herein.

[0054] Those skilled in the art can understand that, unless otherwise stated, the singular forms "a", "an" and "the" used herein also include the plural forms. It should be further understood that the phrase "comprising" used in the specification of the present application means that the stated features, integers, steps, operations, elements and / or components exist, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connected" or "coupled" used herein can include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any single unit and all combinations of the associated listed items.

[0055] The in-cell touch display device generally adopts a time-sharing driving mode, i.e., time of each frame (V-sync) is divided into a display time period and a touch time period to realize touch function and display function. The display time period can include a plurality of display stages (Display), and the touch time period can include a plurality of touch stages (Touch). The display stage and the touch stage work alternately.

[0056] The inventors of the present application have found that the horizontal stripe problem in the background art is mainly caused by the signal of the pull-up node PU in the shift register unit decaying after the LHB (Long Horizontal Blanking) pit, resulting in insufficient Gate voltage of the scan signal output by the shift register unit, insufficient charging of the corresponding pixels, and thus causing the display panel to have horizontal stripe defects.

[0057] In the existing shift register unit (i.e., GOA unit), the pull-up node PU is in a floating state during the touch stage (LHB period). Since the Vgs of the transistor M1 included in the input module and the transistor M2 included in the first reset module is 0, especially for a-Si (amorphous silicon) touch display devices, the leakage current of the TFT (Thin Film Transistor) at 0V is large. When the pull-up node PU is held for a long time, it will continuously leak to the transistors M1 and M2, so that the voltage of the pull-up node PU after the LHB pit is lower than that of the normal pixel row, resulting in a decrease in the Gate voltage output by the shift register unit after the LHB pit, insufficient charging of the pixels, and thus LHB horizontal stripe defects.

[0058] Figure 1 And Figure 2 To simulate the difference between the waveforms of the pull-up node PU before and after the Touch LHB pit. From Figure 2 It can be seen that the voltage of the pull-up node PU gradually decreases after the LHB pit in the long floating state, and it is difficult for the pull-up node PU to maintain a high voltage all the time.

[0059] The existing improvement measures include: ① by adjusting the process to reduce the threshold voltage Vth of the transistor of the GOA unit by 0V leakage, but the improvement effect is not obvious, and at the same time, the anti-noise ability of the GOA unit is reduced, and the reliability of the product cannot be effectively guaranteed; ② reduce the LHB time, usually 180us is better, but the use of active pen is limited, and cannot support the demand of mainstream active pen for LHB time (for example, Microsoft usually requires 450us).

[0060] The application provides a shift register unit, a gate drive circuit and a touch display device, and aims to solve the technical problem of horizontal stripe defects of an in-cell touch display device in an LH driving mode.

[0061] The technical solutions of the application and how the technical solutions solve the above technical problems are described in detail below with specific examples.

[0062] The application provides a shift register unit 100 applied to a gate drive circuit of a touch display device, wherein the gate drive circuit comprises at least two cascaded shift register units 100. The touch display device further comprises a touch display panel, and the shift register unit 100 is configured to provide a scanning signal Gate to a pixel row of the touch display panel. The touch display device is an in-cell touch display device, adopts an LH driving mode, and is in a display stage when normally displaying.

[0063] As shown in Figure 3 The shift register unit 100 comprises an input module 10, an output module 20, an energy storage module 30, a first pull-down module 40 and a first reset module 50.

[0064] Specifically, the input module 10 is connected with an input end INPUT, a first signal end VDS and a pull-up node PU respectively.

[0065] The output module 20 is connected with a clock signal end CLK, an output end OUTPUT and the pull-up node PU respectively.

[0066] The energy storage module 30 is connected with the pull-up node PU at one end and the output end OUTPUT at the other end.

[0067] The first pull-down module 40 is connected with the pull-up node PU, a pull-down node PD, a second signal end VGH and a third signal end VGL1 respectively.

[0068] The first reset module 50 is connected with the pull-up node PU, a first reset signal end RESET and a fourth signal end VGL2 respectively.

[0069] In the touch stage, the pull-up node PU is at a high level, the signal of the first signal end VDS remains a high level signal, the signal of the second signal end VGH is pulled to a low level signal, the signal of the third signal end VGL1 remains a low level signal, and the signal of the fourth signal end VGL2 is pulled to a high level signal.

[0070] The technical solutions of the application and how the technical solutions solve the above technical problems are described in detail below with specific examples. Figure 3 and Figure 4As shown, the working principle of the shift register unit 100 provided by the embodiment of the present application is described in detail.

[0071] In the display stage (Display), the signal of the first signal end VDS and the signal of the second signal end VGH are both high-level signals, and the signal of the third signal end VGL1 and the signal of the fourth signal end VGL2 are both low-level signals; under the control of the high-level signal at the input end INPUT, the input module 10 is turned on, and the high-level signal at the first signal end VDS is transmitted to the pull-up node PU, that is, the pull-up node PU is pulled high to the high level; under the control of the pull-up node PU, the output module 20 is turned on, and the high-level clock signal from the clock signal end CLK is transmitted to the output end OUTPUT as the scanning signal Gate output to the corresponding pixel row. The specific implementation of this display stage is similar to the prior art.

[0072] When the AA area (display area) of the touch display panel receives a touch signal, it enters the touch stage. In the touch stage (Touch), the signal of the first signal end VDS remains a high-level signal, the signal of the second signal end VGH is pulled to a low-level signal, and the signal of the third signal end VGL1 remains a low-level signal; the signal of the fourth signal end VGL2 is pulled to a high-level signal. The signal of the clock signal end CLK and the signal of the first reset signal end RESET are both low-level signals. The pull-up node PU always remains high until the end of the touch stage (Touch).

[0073] Exemplarily, when the touch display panel displays the 20th pixel row, if the touch display panel receives a touch signal at this time, it enters the touch stage, and the 20th pixel row enters the LHB pit pixel row, and other pixel rows are non-LHB pit pixel rows. Of course, the LHB pit pixel row can be multiple rows, which needs to be set according to the actual situation. This example is only used to explain the LHB pit pixel row and the non-LHB pit pixel row.

[0074] In the touch stage, for the LHB pit pixel row, such as Figure 5As shown, the input module 10 is turned on under the control of the high level signal of the input end INPUT, and transmits the high level signal of the first signal end VDS to the pull-up node PU, that is, the pull-up node PU is pulled high to the high level, and then enters the touch stage, and the signals of the clock signal end CLK and the first reset signal end RESET are low level signals. In the touch stage (during LHB), (1) since the signal of the first signal end VDS is a high level signal, the signal of the pull-up node PU is a high level signal, and the two ends of the input module 10 are both high level signals, that is, the two ends of the input module 10 are consistent in level, so that the input module 10 is closed, and thus the pull-up node PU cannot leak through the input module 10, and the leakage path of the pull-up node PU is blocked. (2) Since the signal of the fourth signal end VGL2 is a high level signal, the signal of the pull-up node PU is a high level signal, and the two ends of the first reset module 50 are both high level signals, that is, the two ends of the first reset module 50 are consistent in level, so that the pull-up node PU cannot leak through the first reset module 50, and the leakage path of the pull-up node PU is blocked. Since the pull-up node PU has no leakage path, it can support longer LHB time requirements.

[0075] The shift register unit 100 provided by the embodiment of the present application is connected with the input module 10 through the first signal end VDS. In the touch stage, since the first signal end VDS and the pull-up node PU are both high level signals, the two ends of the input module 10 are both high level signals, the two ends of the input module 10 are consistent in level, and the leakage path of the pull-up node PU is blocked. The shift register unit 100 is connected with the first reset module 50 through the fourth signal end VGL2. In the touch stage, since the pull-up node PU and the fourth signal end VGL2 are both high level signals, the two ends of the first reset module 50 are both high level signals, the two ends of the first reset module 50 are consistent in level, the first reset module 50 is closed, the leakage path of the pull-up node PU is blocked, and thus the touch display device, especially the touch display device supporting the active pen, can maintain the pull-up node PU at a high level after the pull-up node PU gets out of the LHB pit in the touch stage, until entering the display stage (the signal of the clock signal end CLK is pulled high, and the shift register unit 100 normally outputs the scanning signal Gate).

[0076] The embodiment of the present application can avoid the voltage of the pull-up node PU from decreasing after getting out of the LHB pit by eliminating the leakage path on the basis of maintaining the original process, so as to reduce the horizontal stripe defect in the LH driving mode, avoid the abnormal display problem of the touch display device, especially the a-Si (amorphous silicon) touch display device, caused by too long LHB time, and support longer LHB time requirements due to the elimination of the leakage path.

[0077] In some embodiments, as Figure 3As shown, the shift register unit 100 also includes a second pull-down module 41. Specifically, the second pull-down module 41 is connected to the pull-up node PU, the pull-down node PD, and the fourth signal terminal VGL2, respectively.

[0078] Continuing the analysis above, during the touch phase, for the LHB pit pixel row, such as Figure 5 As shown, the input module 10 is turned on under the control of the high-level signal of the input terminal I NPUT, and transmits the high-level signal of the first signal terminal VDS to the pull-up node PU, that is, the pull-up node PU is pulled high, and then enters the touch stage. The signal of the clock signal terminal CLK and the signal of the first reset signal terminal RESET are both low-level signals. During the touch stage (LHB period), (3) since the signal of the fourth signal terminal VGL2 is a high-level signal, the signal of the pull-up node PU is a high-level signal, and both ends of the second pull-down module 41 are high-level signals, that is, the levels of both ends of the second pull-down module 41 are consistent, so the pull-up node PU cannot leak through the second pull-down module 41, thus blocking the leakage path of the pull-up node PU. Since the pull-up node PU has no leakage path, it can support longer LHB time requirements.

[0079] The shift register unit 100 provided in this application embodiment, by setting the fourth signal terminal VGL2 connected to the second pull-down module 41, ensures that during the touch phase, since both the pull-up node PU and the fourth signal terminal VGL2 are high-level signals, both ends of the second pull-down module 41 are also high-level signals. The consistent level at both ends of the second pull-down module 41 ensures that the second pull-down module 41 is closed, blocking the leakage path of the pull-up node PU. This allows the touch display device, especially the touch display device supporting an active pen, to maintain a high level after the pull-up node PU exits the LHB pit during the touch phase, until entering the display phase (the clock signal terminal CLK is pulled high, and the shift register unit 100 normally outputs the scan signal Gate).

[0080] In some embodiments, such as Figure 3 As shown, the shift register unit 100 also includes a second reset module 51. Specifically, the second reset module 51 is connected to the pull-up node PU, the second reset signal terminal TRST, and the fourth signal terminal VGL2, respectively.

[0081] Continuing the analysis above, during the touch phase, for the LHB pit pixel row, such as Figure 5As shown, the input module 10 is turned on under the control of the high level signal of the input terminal INPUT, and transmits the high level signal of the first signal terminal VDS to the pull-up node PU, that is, the pull-up node PU is pulled high to the high level, and then enters the touch stage, and the signals of the clock signal terminal CLK, the first reset signal terminal RESET and the second reset signal terminal TRST are all low level signals. In the touch stage (during LHB), (4) because the signal of the fourth signal terminal VGL2 is a high level signal, the signal of the pull-up node PU is a high level signal, and the two ends of the second reset module 51 are both high level signals, that is, the two ends of the second reset module 51 are consistent in level, so that the pull-up node PU cannot leak through the second reset module 51, and the leakage path of the pull-up node PU is blocked. Because the pull-up node PU has no leakage path, it can support longer LHB time requirements.

[0082] The shift register unit 100 provided by the embodiment of the present application is connected between the fourth signal terminal VGL2 and the second reset module 51, and in the touch stage, because the pull-up node PU and the fourth signal terminal VGL2 are both high level signals, the two ends of the second reset module 51 are both high level signals, the two ends of the second reset module 51 are consistent in level, the second reset module 51 is closed, the leakage path of the pull-up node PU is blocked, so that the touch display device, especially the touch display device supporting the active pen, can maintain the pull-up node PU at a high level after the pull-up node PU gets out of the LHB pit in the touch stage, until entering the display stage (the signal of the clock signal terminal CLK is pulled high, and the shift register unit 100 normally outputs the scanning signal Gate).

[0083] In some embodiments, as shown in Figure 3 The shift register unit 100 further includes a first noise reduction module 61. Specifically, the first noise reduction module 61 is connected with the pull-down node PD, the fourth signal terminal VGL2 and the third signal terminal VGL1 respectively.

[0084] Continuing the above analysis, in the touch stage, for non-LHB pit pixel rows, as shown in Figure 3 、 Figure 4 、 Figure 6 As shown, when entering the touch stage, (1) although the signal of the second signal terminal VGH is pulled low, the pull-down node PD may have residual charge and be at a high level, so that the second pull-down module 41 (including the transistor M10) is turned on, and the high level signal of the fourth signal terminal VGL2 is easily transmitted to the pull-up node PU, and the pull-up node PU is easily pulled high. Therefore, by adding the first noise reduction module 61 to reduce the noise of the pull-down node PD, the output of the non-LHB pit pixel row is ensured to be free of noise.

[0085] The shift register unit 100 provided by the embodiment of the present application increases the first noise reduction module 61 and connects the first noise reduction module 61 with the fourth signal end VGL2. In the touch stage, since the fourth signal end VGL2 is a high level signal, the first noise reduction module 61 is turned on under the control of the high level signal of the fourth signal end VGL2, and the low level signal of the third signal end VGL1 is transmitted to the pull-down node PD to reduce the noise of the pull-down node PD.

[0086] In some embodiments, as shown in Figure 3 The shift register unit 100 further includes a second noise reduction module 62. Specifically, the second noise reduction module 62 is connected with the output end OUTPUT, the fourth signal end VGL2 and the third signal end VGL1 respectively.

[0087] Continuing the analysis above, in the touch stage, for the non-LHB pit pixel row, as shown in Figure 6 When entering the touch stage, (2) since the signal of the fourth signal end VGL2 is pulled high instantaneously, due to the existence of the coupling capacitance of the first reset module 50 (including the transistor M2), the second pull-down module 41 (including the transistor M10) and the second reset module 51 (including the transistor M7), the voltage of the pull-up node PU is slightly pulled high, and noise may exist. Therefore, by increasing the second noise reduction module 62 to reduce the noise of the output end OUTPUT, it is ensured that the output of the non-LHB pit pixel row has no noise.

[0088] The shift register unit 100 provided by the embodiment of the present application increases the second noise reduction module 62 and connects the second noise reduction module 62 with the fourth signal end VGL2. In the touch stage, since the fourth signal end VGL2 is a high level signal, the second noise reduction module 62 is turned on under the control of the high level signal of the fourth signal end VGL2, and the low level signal of the third signal end VGL1 is transmitted to the output end OUTPUT to reduce the noise of the output end OUTPUT.

[0089] In some embodiments, as shown in Figure 3 The shift register unit 100 further includes a third pull-down module 42 and a third reset module 52. Specifically, the third pull-down module 42 is connected with the output end OUTPUT, the pull-down node PD and the third signal end VGL1 respectively. The third reset module 52 is connected with the output end OUTPUT, the second reset signal end TRST and the third signal end VGL1 respectively.

[0090] It should be noted that the first reset signal end RESET is used for cascading the shift register unit 100. The second reset signal end TRST is used for resetting the shift register unit 100. Specifically, after a frame of picture ends, the signals of the pull-up node PU and the output end OUTPUT are both pulled low under the control of the second reset signal end TRST, so as to reset the shift register unit 100.

[0091] As shown in the figure, Figure 3 The first noise reduction module 61 includes a first transistor M16. The first electrode of the first transistor M16 is connected with the pull-down node PD. The second electrode of the first transistor M16 is connected with the third signal end VGL1. The control electrode of the first transistor M16 is connected with the fourth signal end VGL2.

[0092] As shown in the figure, Figure 3 The second noise reduction module 62 includes a second transistor M15. The first electrode of the second transistor M15 is connected with the output end OUTPUT. The second electrode of the second transistor M15 is connected with the third signal end VGL1. The control electrode of the second transistor M15 is connected with the fourth signal end VGL2.

[0093] As shown in the figure, Figure 3 The input module 10 includes a third transistor M1. The control electrode of the third transistor M1 is connected with the input end INPUT. The first electrode of the third transistor M1 is connected with the first signal end VDS. The second electrode of the third transistor M1 is connected with the pull-up node PU.

[0094] As shown in the figure, Figure 3 The output module 20 includes a fourth transistor M3. The control electrode of the fourth transistor M3 is connected with the pull-up node PU. The first electrode of the fourth transistor M3 is connected with the clock signal end CLK. The second electrode of the fourth transistor M3 is connected with the output end OUTPUT.

[0095] As shown in the figure, Figure 3 The storage module 30 includes a capacitor C1. One end of the capacitor C1 is connected with the pull-up node PU. The other end of the capacitor C1 is connected with the output end OUTPUT.

[0096] As shown in the figure, Figure 3As shown, the first pull-down module 40 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M8 and an eighth transistor M9. The first electrode, the first electrode and the control electrode of the eighth transistor M9 are all connected with the second signal end VGH, the second electrode of the fifth transistor M5 is connected with the first electrode of the sixth transistor M6, the control electrode of the fifth transistor M5 and the second electrode of the eighth transistor M9 are all connected with the first node PD_CN, the first electrode of the seventh transistor M8 is connected with the first node PD_CN; the second electrode of the sixth transistor M6 and the second electrode of the seventh transistor M8 are all connected with the third signal end VGL1; the control electrode of the sixth transistor M6 and the control electrode of the seventh transistor M8 are all connected with the pull-up node PU.

[0097] As shown in the figure, Figure 3 The first reset module 50 includes a ninth transistor M2, the first electrode of the ninth transistor M2 is connected with the pull-up node PU, the second electrode of the ninth transistor M2 is connected with the fourth signal end VGL2, and the control electrode of the ninth transistor M2 is connected with the first reset signal end RESET.

[0098] As shown in the figure, Figure 3 The second pull-down module 41 includes a tenth transistor M10, the first electrode of the tenth transistor M10 is connected with the pull-up node PU, the second electrode of the tenth transistor M10 is connected with the fourth signal end VGL2, and the control electrode of the tenth transistor M10 is connected with the pull-down node PD.

[0099] As shown in the figure, Figure 3 The third pull-down module 42 includes an eleventh transistor M12, the first electrode of the eleventh transistor M12 is connected with the output end OUTPUT, the second electrode of the eleventh transistor M12 is connected with the third signal end VGL1, and the control electrode of the eleventh transistor M12 is connected with the pull-down node PD.

[0100] As shown in the figure, Figure 3 The second reset module 51 includes a twelfth transistor M7, the first electrode of the twelfth transistor M7 is connected with the pull-up node PU, the second electrode of the twelfth transistor M7 is connected with the fourth signal end VGL2, and the control electrode of the twelfth transistor M7 is connected with the second reset signal end TRST.

[0101] As shown in the figure, Figure 3 The third reset module 52 includes a thirteenth transistor M11, the first electrode of the thirteenth transistor M11 is connected with the output end OUTPUT, the second electrode of the thirteenth transistor M11 is connected with the third signal end VGL1, and the control electrode of the thirteenth transistor M11 is connected with the second reset signal end TRST.

[0102] In combination with Figures 3-6The application makes the following improvements on the basis of the original shift register unit architecture model.

[0103] 1. For the pixel row entering the LHB pit, a first signal terminal VDS is newly added and connected with the third transistor M1, so that the original diode becomes a triode. In the touch phase, since the signal of the first signal terminal VDS is a high-level signal, the signal of the pull-up node PU is a high-level signal, and the first and second poles of the third transistor M1 are both high-level signals, that is, the two poles of the third transistor M1 are consistent in level, which ensures that the third transistor M1 is closed, so that the pull-up node PU cannot leak through the third transistor M1, and the leakage path of the pull-up node PU is blocked (as shown in Figure 5 ).

[0104] 2. For the pixel row entering the LHB pit, a fourth signal terminal VGL2 is newly added and connected with the ninth transistor M2, the tenth transistor M10 and the twelfth transistor M7. In the touch phase, since the signal of the fourth signal terminal VGL2 is a high-level signal, the signal of the pull-up node PU is a high-level signal, and the two poles of the ninth transistor M2, the two poles of the tenth transistor M10 and the two poles of the twelfth transistor M7 are all high-level signals, that is, the two poles of the ninth transistor M2, the two poles of the tenth transistor M10 and the two poles of the twelfth transistor M7 are consistent in level, so that the pull-up node PU cannot leak through the ninth transistor M2, the tenth transistor M10 and the twelfth transistor M7, and the leakage path of the pull-up node PU is blocked. Since the pull-up node PU has no leakage path, it can support longer LHB time requirements (as shown in Figure 5 ).

[0105] In combination with Figure 5 and Figure 2 , for the pixel row entering the LHB pit, after the pull-up node PU is pulled up to a high level and enters the touch phase, compared with Figure 2 , in which the voltage of the pull-up node PU gradually decreases after the LHB pit, the pull-up node PU is difficult to maintain a relatively high voltage all the time, Figure 5 , in which, since the leakage path of the pull-up node PU is blocked, the voltage of the pull-up node PU maintains a relatively high voltage all the time after the LHB pit, until the display phase (the signal of the clock signal terminal CLK is pulled up, the output terminal OUTPUT of the shift register unit 100 outputs a high-level clock signal, which is output as a scanning signal Gate to the corresponding pixel row. The level of the pull-down node PD is opposite to that of the pull-up node PU.

[0106] 3. A first transistor M16 and a second transistor M15 are newly added, the second pole of the first transistor M16 and the second pole of the second transistor M15 are both connected with the third signal terminal VGL1, the first pole of the first transistor M16 is connected with the pull-down node PD, and the first pole of the second transistor M15 is connected with the output terminal OUTPUT (as shown inFigure 6 (As shown).

[0107] 3.1 For non-LHB pit pixel rows, during the touch phase, when the signal at the fourth signal terminal VGL2 is pulled high, due to the coupling capacitors of the ninth transistor M2, the tenth transistor M10, and the twelfth transistor M7, the voltage of the pull-up node PU is slightly pulled up (e.g., ...). Figure 6 The PU waveform shown may contain noise. Therefore, by adding a second transistor M15 to reduce noise at the output terminal OUTPUT, noise-free output of non-LHB pit pixel rows is ensured.

[0108] 3.2 For non-LHB pit pixel rows, when entering the touch phase, although the signal at the second signal terminal VGH is pulled low, the pull-down node PD may have residual charge and remain at a high level (e.g. Figure 6 The PD waveform shown makes the tenth transistor M10 turn on, which makes it easy to transmit the high-level signal of the fourth signal terminal VGL2 to the pull-up node PU. The pull-up node PU is easily pulled high. Therefore, by adding the first transistor M16 to reduce noise for the pull-down node PD, it is ensured that the non-LHB pit pixel row output is noiseless.

[0109] It should be noted that, Figure 5 and Figure 6 In the process, the bootstrap effect of capacitor C1 further pulls up the voltage of the pull-up node PU.

[0110] Optionally, the aforementioned transistor can be an N-type transistor, or of course, a P-type transistor, as those skilled in the art will understand. Figure 3 The circuit connection shown is only an example of the shift register unit 100 provided in the embodiments of this application. When the type of each transistor changes, the electrical connection of each component in the shift register unit provided in the embodiments of this application can be adjusted accordingly. The adjusted electrical connection still falls within the protection scope of the embodiments of this application.

[0111] In specific implementations, each transistor can be a thin-film transistor (TFT) or a metal-oxide-semiconductor field-effect transistor (MOS), without limitation. In specific implementations, the first and second terminals of these transistors can be the source or drain of the transistor. Depending on the type of transistor and the input signal, their functions can be interchanged, without specific distinction here.

[0112] Based on the same inventive concept, this application provides a gate driving circuit, which includes at least two cascaded shift register units 100 as provided in any of the above embodiments.

[0113] The output end OUTPUT of each stage of the shift register unit 100 is electrically connected with the input end INPUT of the next stage of the shift register unit 100;

[0114] The first reset signal end RESET of each stage of the shift register unit 100 is electrically connected with the output end OUTPUT of the next stage of the shift register unit 100.

[0115] The gate drive circuit provided by the embodiments of the present application has the same inventive concept and the same beneficial effects as the previous embodiments, and the contents not shown in detail in the gate drive circuit can refer to the previous embodiments, which will not be described here again.

[0116] Based on the same inventive concept, the embodiments of the present application provide a touch display device, which comprises the gate drive circuit provided by the above embodiments.

[0117] The touch display device provided by the embodiments of the present application has the same inventive concept and the same beneficial effects as the previous embodiments, and the contents not shown in detail in the touch display device can refer to the previous embodiments, which will not be described here again.

[0118] By using the embodiments of the present application, the following beneficial effects can be achieved at least:

[0119] (1) The shift register unit 100 provided by the embodiments of the present application is connected with the input module 10 through the first signal end VDS, and in the touch stage, since the first signal end VDS and the pull-up node PU are both high-level signals, the two ends of the input module 10 are both high-level signals, the levels of the two ends of the input module 10 are consistent, and the leakage path of the pull-up node PU is blocked. The fourth signal end VGL2 is connected with the first reset module 50, and in the touch stage, since the pull-up node PU and the fourth signal end VGL2 are both high-level signals, the two ends of the first reset module 50 are both high-level signals, the levels of the two ends of the first reset module 50 are consistent, the first reset module 50 is ensured to be closed, the leakage path of the pull-up node PU is blocked, so that the touch display device, especially the touch display device supporting an active pen, maintains the pull-up node PU at a high level after the pull-up node PU goes out of the LHB pit in the touch stage, until entering the display stage (the signal of the clock signal end CLK is pulled up, and the shift register unit 100 normally outputs the scanning signal Gate). By eliminating the leakage path on the basis of maintaining the original process, the embodiments of the present application can avoid the voltage of the pull-up node PU from being reduced after the pull-up node PU goes out of the LHB pit, so as to reduce the horizontal stripe defect in the LH driving mode, avoid the abnormal display problem of the touch display device, especially the a-Si (amorphous silicon) touch display device, caused by too long LHB time, and support longer LHB time requirement due to the elimination of the leakage path.

[0120] (2) The shift register unit 100 provided by the embodiment of the present application, by setting the connection between the fourth signal terminal VGL2 and the second pull-down module 41, in the touch stage, since the pull-up node PU and the fourth signal terminal VGL2 are both high-level signals, the two ends of the second pull-down module 41 are both high-level signals, the levels of the two ends of the second pull-down module 41 are consistent, the second pull-down module 41 is guaranteed to be closed, and the leakage path of the pull-up node PU is blocked, so that the touch display device, especially the touch display device supporting the active pen, maintains the pull-up node PU at a high level after the pull-up node PU goes out of the LHB pit in the touch stage, until entering the display stage (the signal of the clock signal terminal CLK is pulled up, and the shift register unit 100 normally outputs the scanning signal Gate).

[0121] (3) The shift register unit 100 provided by the embodiment of the present application, by setting the connection between the fourth signal terminal VGL2 and the second reset module 51, in the touch stage, since the pull-up node PU and the fourth signal terminal VGL2 are both high-level signals, the two ends of the second reset module 51 are both high-level signals, the levels of the two ends of the second reset module 51 are consistent, the second reset module 51 is guaranteed to be closed, and the leakage path of the pull-up node PU is blocked, so that the touch display device, especially the touch display device supporting the active pen, maintains the pull-up node PU at a high level after the pull-up node PU goes out of the LHB pit in the touch stage, until entering the display stage (the signal of the clock signal terminal CLK is pulled up, and the shift register unit 100 normally outputs the scanning signal Gate).

[0122] (4) The shift register unit 100 provided by the embodiment of the present application, by increasing the first noise reduction module 61 and connecting the first noise reduction module 61 with the fourth signal terminal VGL2, in the touch stage, since the fourth signal terminal VGL2 is a high-level signal, the first noise reduction module 61 is turned on under the control of the high-level signal of the fourth signal terminal VGL2, and the low-level signal of the third signal terminal VGL1 is transmitted to the pull-down node PD to reduce the noise of the pull-down node PD.

[0123] (5) The shift register unit 100 provided by the embodiment of the present application, by increasing the second noise reduction module 62 and connecting the second noise reduction module 62 with the fourth signal terminal VGL2, in the touch stage, since the fourth signal terminal VGL2 is a high-level signal, the second noise reduction module 62 is turned on under the control of the high-level signal of the fourth signal terminal VGL2, and the low-level signal of the third signal terminal VGL1 is transmitted to the output terminal OUTPUT to reduce the noise of the output terminal OUTPUT.

[0124] Those skilled in the art can understand that the steps, measures, and schemes in various operations, methods, and processes discussed in the present application can be alternated, changed, combined, or deleted. Further, other steps, measures, and schemes in various operations, methods, and processes discussed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted. Further, steps, measures, and schemes in various operations, methods, and processes in the prior art can also be alternated, changed, rearranged, decomposed, combined, or deleted.

[0125] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0126] The terms "first", "second", are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0127] In the description of the present application, it should be noted that unless otherwise specified and limited, the terms "mounting", "connecting", "connection" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integral connection; it can be directly connected, or indirectly connected through an intermediate medium, or the communication between the two elements inside. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0128] In the description of the present application, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0129] It should be understood that although the steps in the flowcharts of the drawings are shown in a sequential order following the arrows, the steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated otherwise herein, the execution of the steps is not strictly limited to the order indicated by the arrows, and can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the drawings can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of which is not necessarily sequential, but can be round-robin or alternating with at least some of the other steps or sub-steps or stages of other steps.

[0130] The above only describes some embodiments of the present application, and it should be pointed out that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which should also be considered as the protection scope of the present application.

Claims

1. A shift register unit, characterized in that, include: The input module is connected to the input terminal, the first signal terminal, and the pull-up node, respectively. The output module is connected to the clock signal terminal, the output terminal, and the pull-up node, respectively. An energy storage module, one end of which is connected to the pull-up node, and the other end of which is connected to the output terminal; The first pull-down module is connected to the pull-up node, the pull-down node, the second signal terminal, and the third signal terminal, respectively. The first reset module is connected to the pull-up node, the first reset signal terminal, and the fourth signal terminal, respectively. During the touch control phase, the signal at the first signal terminal remains at a high level, the signal at the second signal terminal is pulled to a low level, the signal at the third signal terminal remains at a low level, and the signal at the fourth signal terminal is pulled to a high level. The shift register unit also includes a second reset module; The second reset module is connected to the pull-up node, the second reset signal terminal and the fourth signal terminal respectively, and is used to control the pull-up node to disconnect from the fourth signal terminal under the control of the potential of the pull-up node and the fourth signal provided by the fourth signal terminal during the touch phase; The shift register unit further includes a first noise reduction module and a second noise reduction module; The first noise reduction module is connected to the drop-down node, the fourth signal terminal and the third signal terminal respectively, and is used to transmit the low-level signal provided by the third signal terminal to the drop-down node under the control of the fourth signal during the touch phase. The second noise reduction module is connected to the output terminal, the fourth signal terminal and the third signal terminal respectively, and is used to transmit the low-level signal provided by the third signal terminal to the output terminal under the control of the fourth signal during the touch stage.

2. The shift register unit according to claim 1, characterized in that, Also includes: The second pull-down module is connected to the pull-up node, the pull-down node, and the fourth signal terminal, respectively. The third pull-down module is connected to the output terminal, the pull-down node, and the third signal terminal, respectively.

3. The shift register unit according to claim 1, characterized in that, Also includes: The third reset module is connected to the output terminal, the second reset signal terminal, and the third signal terminal, respectively.

4. The shift register unit according to claim 1, characterized in that, The first noise reduction module includes a first transistor; the second noise reduction module includes a second transistor; The first terminal of the first transistor is connected to the pull-down node, the second terminal of the first transistor is connected to the third signal terminal, and the control terminal of the first transistor is connected to the fourth signal terminal. The first terminal of the second transistor is connected to the output terminal, the second terminal of the second transistor is connected to the third signal terminal, and the control terminal of the second transistor is connected to the fourth signal terminal.

5. The shift register unit according to claim 1, characterized in that, The input module includes a third transistor; The output module includes a fourth transistor; the first pull-down module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the first reset module includes a ninth transistor; The control electrode of the third transistor is connected to the input terminal, the first electrode of the third transistor is connected to the first signal terminal, and the second electrode of the third transistor is connected to the pull-up node. The control electrode of the fourth transistor is connected to the pull-up node, the first electrode of the fourth transistor is connected to the clock signal terminal, and the second electrode of the fourth transistor is connected to the output terminal. The first terminal of the fifth transistor, the first terminal of the eighth transistor, and the control terminal are all connected to the second signal terminal. The second terminal of the fifth transistor is connected to the first terminal of the sixth transistor. The control terminal of the fifth transistor and the second terminal of the eighth transistor are both connected to the first node. The first terminal of the seventh transistor is connected to the first node. The second terminals of the sixth transistor and the seventh transistor are both connected to the third signal terminal. The control terminals of the sixth transistor and the seventh transistor are both connected to the pull-up node. The first terminal of the ninth transistor is connected to the pull-up node, the second terminal of the ninth transistor is connected to the fourth signal terminal, and the control terminal of the ninth transistor is connected to the first reset signal terminal.

6. The shift register unit according to claim 2, characterized in that, The second pull-down module includes a tenth transistor, and the third pull-down module includes an eleventh transistor; The first terminal of the tenth transistor is connected to the pull-up node, the second terminal of the tenth transistor is connected to the fourth signal terminal, and the control terminal of the tenth transistor is connected to the pull-down node. The first terminal of the eleventh transistor is connected to the output terminal, the second terminal of the eleventh transistor is connected to the third signal terminal, and the control terminal of the eleventh transistor is connected to the pull-down node.

7. The shift register unit according to claim 3, characterized in that, The second reset module includes a twelfth transistor, and the third reset module includes a thirteenth transistor; The first terminal of the twelfth transistor is connected to the pull-up node, the second terminal of the twelfth transistor is connected to the fourth signal terminal, and the control terminal of the twelfth transistor is connected to the second reset signal terminal. The first terminal of the thirteenth transistor is connected to the output terminal, the second terminal of the thirteenth transistor is connected to the third signal terminal, and the control terminal of the thirteenth transistor is connected to the second reset signal terminal.

8. A gate driving circuit, characterized in that, Includes at least two cascaded shift register units as described in any one of claims 1 to 7; The output of each shift register unit is electrically connected to the input of the next shift register unit. The first reset signal terminal of each shift register unit is electrically connected to the output terminal of the next-level shift register unit.

9. A touch display device, characterized in that, Includes the gate drive circuit as described in claim 8.

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