Stacked nanosheet ring gate transistor and method of making the same
By employing low-temperature dry plasma processing technology, the risk of breakdown due to excessively high corner electric fields in stacked nanosheet GAA-FET channel structures was solved, resulting in higher-performance nanosheet gate-around transistors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2022-11-15
- Publication Date
- 2026-07-24
AI Technical Summary
In the existing technology, the channel structure of stacked nanosheet GAA-FET has the problem of excessively high corner electric fields, which may lead to device breakdown.
By using a low-temperature dry plasma treatment method to surface-treat the nanosheet channels during the preparation process, surface defects such as sharp edges and etched superlattice stacked nanosheet fin sidewalls are eliminated, forming a smooth channel surface.
It eliminates the risk of breakdown caused by excessively high electric fields at sharp edges, improves device performance, and reduces interface state defect density.
Smart Images
Figure CN115763254B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a stacked nanosheet ring gate transistor and its fabrication method. Background Technology
[0002] GAAFET (Gate all around Field Effect Transistors), also known as gate-all-around transistors, is an emerging technology that continues the existing semiconductor technology roadmap, further enhancing gate control capabilities and overcoming the physical scaling and performance limitations of current technologies.
[0003] One implementation structure of GAA-FET is in the form of stacked nanosheets. In the CMOS integration process of conventional stacked nanosheet GAA-FET, after the nanosheet channel is formed by gate release, the channel structure is a square structure with sharp edges, which poses a risk of device breakdown due to excessively high electric fields at the edges. Summary of the Invention
[0004] To address the aforementioned problems, this invention provides a stacked nanosheet ring gate transistor and its fabrication method, which can eliminate the risk of device breakdown caused by excessively high electric fields at the edges.
[0005] On one hand, the present invention provides a method for fabricating a stacked nanosheet ring gate transistor, comprising:
[0006] A substrate is provided, one side of which has a support portion, and the support portion has alternating layers of sacrificial layers and channel layers, the support portion, the sacrificial layers and the channel layers constituting fins, and a shallow trench isolation region is formed between two adjacent fins;
[0007] Forming a false grid across the fins;
[0008] Sidewalls are formed on both sides of the dummy fence;
[0009] The fins are etched, and the etching stops at the surface of the support portion, forming source / drain regions on both sides of the sidewall for fabricating source / drain electrodes;
[0010] Inner sidewalls are formed at both ends of the sacrificial layer;
[0011] The channel layer is epitaxially grown to form source / drain electrodes in the source / drain region;
[0012] Deposit interlayer medium, and perform chemical mechanical polishing on the interlayer medium until the dummy gate is exposed;
[0013] Remove the spurious gate;
[0014] Remove the sacrificial layer to release the channel layer and form a nanosheet channel;
[0015] The nanosheet channels are surface treated to make the surface of the nanosheet channels smooth.
[0016] A metal gate is formed around the nanosheet channel.
[0017] Optionally, the surface treatment of the nanosheet channels to make the surface of the nanosheet channels smooth includes:
[0018] The nanosheet channels are surface-treated using a low-temperature dry plasma treatment method.
[0019] Optionally, forming inner sidewalls at both ends of the sacrificial layer includes:
[0020] The edge portion of the sacrificial layer is etched away from the source / drain region toward the center to form an embedded groove;
[0021] Deposit inner wall medium, the inner wall medium covering the entire surface and filling the groove;
[0022] Anisotropic etching is used to remove the portion of the inner wall medium located in the horizontal direction;
[0023] Isotropic etching is used to remove the portion of the inner wall medium located in the vertical direction, leaving only the inner wall medium located in the groove, thus forming the inner wall.
[0024] Optionally, after forming the metal grid, the method further includes:
[0025] Contact holes are formed to contact the source / drain and the metal gate respectively, and conductive channels are formed in the contact holes.
[0026] On the other hand, the present invention provides a stacked nanosheet ring gate transistor, comprising:
[0027] A substrate, wherein one side of the substrate has a support portion;
[0028] The nanosheet channel is located on the support and includes multiple channel layers, each of which has a smooth surface;
[0029] A metal grid surrounds the nanosheet channel;
[0030] The source / drain electrodes are connected to the nanosheet channel.
[0031] Optionally, it also includes:
[0032] Interlayer dielectric, located above the source / drain electrodes;
[0033] Conductive channels formed within the interlayer dielectric are respectively connected to the source / drain and the metal gate.
[0034] The stacked nanosheet gate-around transistor and its fabrication method provided by this invention, after releasing the nanosheet channel in the post-gate process, eliminates the sharp corners of the gate-around nanosheet channel and the surface defects of the etched superlattice stacked nanosheet fin sidewalls through low-temperature dry plasma treatment. This morphology control of the sharp corners and surface of the stacked silicon channel results in a smooth channel surface. This not only eliminates the problem of device breakdown risk caused by excessively high electric fields at the sharp corners, but also obtains interface states with lower defect density, thereby improving the overall device performance. Attached Figure Description
[0035] Figure 1 This is a three-dimensional structural diagram of a substrate after fins have been formed on it, according to an embodiment of the present invention.
[0036] Figure 2 for Figure 1 The cross-sectional view of the structure shown along the X-X' direction;
[0037] Figure 3 A schematic diagram of the three-dimensional structure after the formation of the dummy gate;
[0038] Figure 4 for Figure 3 The cross-sectional view of the structure shown along the Y-Y' direction;
[0039] Figure 5 A schematic diagram of the three-dimensional structure after the side walls are formed;
[0040] Figure 6 for Figure 5 The cross-sectional view of the structure shown along the Y-Y' direction;
[0041] Figure 7 A schematic diagram of the three-dimensional structure after etching the fins to form the source / drain regions;
[0042] Figure 8 for Figure 7 The cross-sectional view of the structure shown along the Y-Y' direction;
[0043] Figure 9 This is a cross-sectional view along the Y-Y' direction after the edge of the sacrificial layer has been etched;
[0044] Figure 10 This is a cross-sectional view along the Y-Y' direction after the deposition of the inner wall medium;
[0045] Figure 11 This is a cross-sectional view along the Y-Y' direction after removing the horizontal portion of the inner wall medium;
[0046] Figure 12This is a cross-sectional view along the Y-Y' direction after removing the vertical portion of the inner wall medium;
[0047] Figure 13 A cross-sectional view along the Y-Y' direction after the source / drain electrodes have been formed;
[0048] Figure 14 A cross-sectional view along the Y-Y' direction after the interlayer medium is deposited above the source / drain electrodes;
[0049] Figure 15 This is a cross-sectional view along the Y-Y' direction after removing the dummy grid;
[0050] Figure 16 This is a cross-sectional view along the Y-Y' direction after the sacrificial layer has been removed.
[0051] Figure 17 This is a cross-sectional view along the X-X' direction after the sacrificial layer has been removed.
[0052] Figure 18 This is a cross-sectional view along the X-X' direction after plasma treatment of the nanosheet channel;
[0053] Figure 19 This is a cross-sectional view along the Y-Y' direction after the metal grid has been formed;
[0054] Figure 20 This is a cross-sectional view along the Y-Y' direction after the conductive channel has been formed. Detailed Implementation
[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. Furthermore, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of this disclosure.
[0056] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0057] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0058] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0059] An embodiment of the present invention provides a method for fabricating a stacked nanosheet ring gate transistor, comprising the following steps:
[0060] S1 provides a substrate with a support portion on one side, and alternating layers of sacrificial layers and channel layers on the support portion. The support portion, sacrificial layers and channel layers constitute a fin, and a shallow trench isolation region is formed between two adjacent fins.
[0061] S2, forming a false grid across the fins;
[0062] S3, forming sidewalls on both sides of the dummy fence;
[0063] S4, etch the fins, the etching stops at the surface of the support, and form source / drain regions on both sides of the sidewall for fabricating source / drain electrodes;
[0064] S5, forming inner walls at both ends of the sacrificial layer;
[0065] S6, epitaxially grow the channel layer to form source / drain electrodes in the source / drain region;
[0066] S7, deposit interlayer medium, perform chemical mechanical polishing on the interlayer medium until the dummy gate is exposed;
[0067] S8, removes spurious gates;
[0068] S9, remove the sacrificial layer to release the channel layer to form nanosheet channels;
[0069] S10, surface treatment is performed on the nanosheet channels to make the surface of the nanosheet channels smooth;
[0070] S11 forms a metal gate surrounding the nanosheet channel.
[0071] The steps described above are described in more detail below.
[0072] In step S1, refer to Figure 1 and Figure 2 , Figure 1 This diagram shows a three-dimensional structure after the fin structure is formed on the substrate 101. Figure 2It shows Figure 1 A cross-sectional view of the three-dimensional structure along the X-X' direction. First, a substrate 101 is provided, typically a silicon substrate. One side of the substrate 101 has a support portion 1011, on which alternately stacked sacrificial layers 102 and channel layers 103 are provided. Figure 1 The diagram illustrates an alternating stack of three sacrificial layers 102 and three channel layers 103. The sacrificial layers 102 are typically made of SiGe, while the channel layers 103 are typically made of Si. The sacrificial layers 102 and 103 form a superlattice structure. The support 1011, sacrificial layers 102, and channel layers 103 constitute fins. Shallow trench isolation (STI) regions 104 are formed between adjacent fins. The fabrication process of the above structure can be achieved using existing techniques and will not be described in detail here.
[0073] In step S2, a dummy gate is formed across the fins. (See reference) Figure 3 and Figure 4 , Figure 3 A schematic diagram of the three-dimensional structure after forming the pseudo-gate across the fins is shown. Figure 4 It shows Figure 3 The three-dimensional structure is shown in a cross-sectional view along the Y-Y' direction. The specific steps are as follows: depositing a dummy gate material layer (polycrystalline silicon or amorphous silicon), and then depositing a dummy gate hard mask layer. The material of this dummy gate hard mask layer can be oxide, carbide, organic material, etc. A dummy gate 105 spanning the fins is formed through photolithography and etching processes. After etching, the dummy gate hard mask layer 106 above the dummy gate 105 is retained.
[0074] In step S3, sidewalls are formed on both sides of the dummy gate. (See reference) Figure 5 and Figure 6 , Figure 5 A three-dimensional structural diagram showing the formation of the sidewalls is shown. Figure 6 It shows Figure 5 The three-dimensional structure is a cross-sectional view along the Y-Y' direction. The specific steps are as follows: deposit a layer of sidewall dielectric, which can be silicon nitride or doped silicon oxide, etc., and then etch the sidewall dielectric in the horizontal direction, retaining only the dielectric of the dummy gate 105 and the sidewall of the dummy gate hard mask layer 106 to form the sidewall 107.
[0075] In step S4, the fins are etched, stopping at the surface of the support, forming source / drain regions on both sides of the sidewalls for fabricating the source / drain electrodes. (Reference) Figure 7 and Figure 8 , Figure 7 A schematic diagram of the three-dimensional structure after the source / drain region is formed is shown. Figure 8 It shows Figure 7A cross-sectional view of the three-dimensional structure along the Y-Y' direction. The specific steps are as follows: using a dummy gate hard mask layer 106 and sidewall 107 as a mask, the source and drain of the fins are etched by an etching process until the etching stops at the surface of the support portion 1011.
[0076] In step S5, inner sidewalls are formed at both ends of the sacrificial layer. (See reference) Figures 9 to 12 The specific steps include: Figure 9 As shown, in Figure 8 Based on this, the edge portion of the sacrificial layer (SiGe layer in this embodiment) 102 is etched away from the source / drain region towards the center, forming an embedded groove. During etching, a relatively large etch selectivity ratio is considered between the sacrificial layer (SiGe layer) 102 and the channel layer (Si layer) 103 to ensure the integrity of the channel layer 103. Figure 10 As shown, the deposited inner sidewall medium 1081 can be the same as the previously deposited sidewall medium, such as silicon nitride, doped silicon oxide, or doped silicon carbide (NDC). This inner sidewall medium 1081 covers the entire surface and fills the embedded grooves. Figure 11 As shown, anisotropic etching is used to remove the portion of the inner wall medium 1081 located in the horizontal direction. The inner wall medium of the horizontal source / drain region and the inner wall medium of the top surface are etched away. Figure 12 As shown, isotropic etching is used to remove the portion of the inner wall medium 1081 located in the vertical direction, and the remaining inner wall medium constitutes the inner wall 108.
[0077] In step S6, Figure 13 A schematic diagram of the structure after the formation of source / drain 110 is shown. The two ends of the channel layer 103 are exposed. The channel layer 103 is epitaxially grown to form the source / drain regions. Specifically, the source / drain regions can be formed using suitable methods such as metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth (SEG), similar methods, or combinations thereof. Simultaneously, the source / drain regions are doped. For P-type FETs, the source / drain region material is boron (B)-doped SiGe (SiGe:B); for N-type FETs, the source / drain region material is phosphorus (P)-doped silicon (Si) (Si:P).
[0078] In step S7, refer to Figure 14 After forming the source / drain 110, an interlayer dielectric 111 is deposited, the interlayer dielectric 111 is chemically and mechanically polished, and the dummy gate hard mask layer 106 is removed to expose the dummy gate 105.
[0079] In step S8, refer to Figure 15The dummy gate 105 is removed by selective etching or etching processes to remove the dummy gate 105 formed by the aforementioned polysilicon (p-si) or amorphous silicon (a-si).
[0080] In step S9, refer to Figure 16 and Figure 17 The sacrificial layer 102 is removed to release the channel layer 103, thereby forming a nanosheet channel. Figure 16 A cross-sectional view along the Y-Y' direction is shown after the formation of nanosheet channels. Figure 17 A cross-sectional view along the X-X' direction is shown after the nanosheet channels have been formed.
[0081] In step S10, the nanosheet channels are surface-treated to make the surface of the nanosheet channels smooth. To illustrate the surface morphology, a cross-sectional view along the X-X' direction is used. Figure 18 A schematic diagram of the nanosheet channel structure after surface treatment is shown. (Reference) Figure 18 One approach is to use low-temperature dry plasma treatment to surface-treat nanosheet channels. For example, in-situ treatment with H2 and N2 plasma can be used. A feasible process parameter is as follows: RF power 400-750W; treatment time 20-35 seconds; H2 flow rate 450 sccm; N2 flow rate 300 sccm; treatment temperature 400℃; chamber pressure 1.3 Torr. Plasma surface treatment can eliminate the sharp edges of nanosheet channels and surface defects caused by the sidewalls of the superlattice stack of the sacrificial layer / channel layer during fin etching. It can also control the morphology of the sharp corners and surface of the stacked silicon channel layer, obtaining a smooth channel surface. This not only eliminates the risk of device breakdown due to excessively high electric fields at the edges, but also achieves a lower defect density interface state, thereby improving overall device performance.
[0082] In step S11, refer to Figure 19 A metal gate 112 is formed around the nanosheet channel. A high-k metal gate is then deposited sequentially, followed by CMP.
[0083] Furthermore, after forming the metal grid 112, it also includes:
[0084] Step S12, refer to Figure 20 Interlayer dielectric is deposited on top and dielectric CMP is performed. Then, contact hole photolithography and etching are performed to form contact holes that contact the source / drain 110 and the metal gate 112 respectively, and conductive channels 113 are formed in the contact holes.
[0085] As can be seen from the above preparation process, the method for preparing the stacked nanosheet ring gate transistor provided in this embodiment of the invention, after releasing the nanosheet channel in the post-gate process, eliminates the sharp corners of the ring gate nanosheet channel and the surface defects of the etched superlattice stacked nanosheet fin sidewalls through low-temperature dry plasma treatment, thereby controlling the morphology of the sharp corners and surface of the stacked silicon channel to obtain a smooth channel surface. This not only eliminates the problem of device breakdown risk caused by excessively high electric field at the sharp corners, but also obtains interface states with lower defect density, thereby improving the overall device performance.
[0086] On the other hand, another embodiment of the present invention also provides a stacked nanosheet ring gate transistor, which can be referred to Figure 18 and Figure 20 ,include:
[0087] Substrate 101, with a support portion on one side;
[0088] The nanosheet channel, located on the support, includes multiple channel layers 103, each channel layer having a smooth surface;
[0089] Metal gate 112 surrounds the nanosheet channel;
[0090] Source / drain 110, connected to the nanosheet channel.
[0091] In addition, it also includes:
[0092] Interlayer dielectric 111 is located above source / drain electrode 110;
[0093] Conductive channels 113 are formed within the interlayer dielectric 111 and are respectively connected to the source / drain electrode 110 and the metal gate 112.
[0094] The stacked nanosheet ring gate transistor of this invention is formed by the aforementioned method embodiments. The materials and characteristics of each part can be referred to the above method embodiments, and will not be discussed further here.
[0095] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0096] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method for fabricating a stacked nanosheet ring gate transistor, characterized in that, The method includes: A substrate is provided, one side of which has a support portion, and the support portion has alternating layers of sacrificial layers and channel layers, the support portion, the sacrificial layers and the channel layers constituting fins, and a shallow trench isolation region is formed between two adjacent fins; Forming a false grid across the fins; Side walls are formed on both sides of the dummy fence; The fins are etched, and the etching stops at the surface of the support portion, forming source / drain regions on both sides of the sidewall for fabricating source / drain electrodes; Inner sidewalls are formed at both ends of the sacrificial layer; The channel layer is epitaxially grown to form source / drain electrodes in the source / drain region; Deposit interlayer medium, and perform chemical mechanical polishing on the interlayer medium until the dummy gate is exposed; Remove the spurious gate; Remove the sacrificial layer to release the channel layer and form a nanosheet channel; The nanosheet channel is surface-treated to make its surface smooth. Specifically, this includes in-situ treatment of the nanosheet channel surface using H2 and N2 plasma, with the following process parameters: RF power of 400-750W; treatment time of 20-35 seconds; H2 flow rate of 450 sccm; N2 flow rate of 300 sccm; treatment temperature of 400℃; and chamber pressure of 1.3 Torr. A metal gate is formed around the nanosheet channel.
2. The method according to claim 1, characterized in that, The formation of inner sidewalls at both ends of the sacrificial layer includes: The edge portion of the sacrificial layer is etched away from the source / drain region toward the center to form an embedded groove; Deposit inner wall medium, the inner wall medium covering the entire surface and filling the groove; Anisotropic etching is used to remove the portion of the inner wall medium located in the horizontal direction; Isotropic etching is used to remove the portion of the inner wall medium located in the vertical direction, leaving only the inner wall medium located in the groove, thus forming the inner wall.
3. The method according to claim 1, characterized in that, After forming the metal grid, the method further includes: Contact holes are formed to contact the source / drain and the metal gate respectively, and conductive channels are formed in the contact holes.