Etching method of floating gate of flash memory device
By controlling the etching rate through a two-stage oxide layer deposition and etching process during the etching of the floating gate polysilicon layer, a sharp corner is formed above the floating gate, which solves the problem of poor durability caused by the indistinct floating gate sharp corner in the prior art and improves the erase operation performance of flash memory devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2022-08-30
- Publication Date
- 2026-06-02
AI Technical Summary
In the prior art, the lack of distinct sharp corners of the floating gate leads to poor erase operation performance of flash memory devices, which in turn affects the durability of the memory devices.
A two-stage oxide deposition and etching process is employed to form a structure with sharp corners above the floating gate by controlling the difference in etching rate of the floating gate polysilicon layer. The specific steps include depositing the first and second oxide layers and forming etching openings by dry etching to control the etching rate.
It improves the durability of flash memory devices and enhances the performance of erase operations.
Smart Images
Figure CN115763545B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to an etching method for the floating gate of a flash memory device. Background Technology
[0002] Embedded flash memory (eflash) is playing an increasingly important role in the field of non-volatile memory due to its advantages such as low cost, low power consumption, and fast access speed. Typically, the eflash memory structure consists of a floating gate and a control gate stacked together, with a gate dielectric layer forming between them. Read, write, and erase operations are controlled by applying different operating voltages to the electrodes such as the control gate. The stored content of eflash depends on the state of the electrons in the floating gate; if the floating gate is in a state without electrons, the data in eflash is 1; if the floating gate is in a state with electrons, the data in eflash is 0.
[0003] Currently, when forming a floating gate by etching a polysilicon layer, the lateral etching rates of the upper portion (the side furthest from the semiconductor substrate) and the lower portion (the side closest to the semiconductor substrate) of the polysilicon layer are basically the same. This prevents the formation of a prominent sharp corner (such as...) in the floating gate. Figure 1 The circled area shows a relatively smooth sharp corner. However, if the sharp corner on the floating gate is not obvious (smooth), it will result in poor erase operation performance of eflash, which will lead to weak current representing data 1, and thus poor durability of the memory device. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an etching method for the floating gate of a flash memory device, which solves the problem that the sharp corners above the floating gate formed by existing processes are not obvious, resulting in poor durability of the flash memory device.
[0005] To achieve the above and other related objectives, the present invention provides a method for etching the floating gate of a flash memory device, the method comprising:
[0006] Step 1) Provide a memory region structure for a flash memory device, the memory region structure including a gate oxide layer, a floating gate polysilicon layer, a gate dielectric layer and a control gate polysilicon layer stacked sequentially from bottom to top, wherein the control gate polysilicon layer and the gate dielectric layer form a first etching window, and the sidewall of the first etching window forms a sidewall structure.
[0007] Step 2) Form a first oxide layer on the surface of the storage area structure;
[0008] Step 3) The first oxide layer is etched using the first etching process, and the floating gate polysilicon layer at a preset depth is etched at the first etching window to form an etching opening;
[0009] Step 4) Form a second oxide layer on the surface of the structure formed in step 3);
[0010] Step 5) Use the second etching process to etch the second oxide layer until the floating gate polysilicon layer at the bottom of the etching opening is exposed, and the sidewall of the etching opening is still covered by the second oxide layer.
[0011] Step 6) The floating gate polysilicon layer is etched at the etched opening using a third etching process to form a floating gate.
[0012] Optionally, the preset depth ranges from 30 Å to 80 Å.
[0013] Optionally, the thickness of the second oxide layer ranges from 70 Å to 200 Å.
[0014] Optionally, the first oxide layer and the second oxide layer are formed using a deposition process.
[0015] Optionally, the first etching process, the second etching process, and the third etching process are all dry etching processes.
[0016] Optionally, in step 6), an etching gas with a high selectivity for the second oxide layer is selected.
[0017] Optionally, a mask layer is formed on the surface of the control gate polysilicon layer, and the mask layer forms a second etching window. The second etching window is connected to the first etching window and is larger than the first etching window. In this case, the sidewall structure is also formed on the sidewall of the second etching window.
[0018] Optionally, the gate dielectric layer includes a bottom oxide layer, an intermediate nitride layer, and a top oxide layer, wherein the bottom oxide layer is formed on the surface of the floating gate polysilicon layer, and the intermediate nitride layer is formed between the bottom oxide layer and the top oxide layer.
[0019] As described above, the method for etching the floating gate of the flash memory device of the present invention involves performing two oxide layer deposition and etching processes, so that the upper part of the floating gate polysilicon layer (where the sharp corner is subsequently formed) is covered by the oxide layer. Therefore, when etching the floating gate polysilicon to form the floating gate, the etching rate of the upper part of the floating gate polysilicon is lower than the etching rate of the lower part, thereby enabling the formed floating gate to have sharp corners, thereby improving the durability of the flash memory device. Attached Figure Description
[0020] Figure 1 The image shown is a scanning electron microscope image of a floating grating formed using existing processes.
[0021] Figure 2 The diagram shown is a cross-sectional view of the storage area structure with a mask layer formed according to the present invention.
[0022] Figure 3 The diagram shown is a cross-sectional view of the structure after the formation of the first oxide layer according to the present invention.
[0023] Figure 4 The diagram shown is a cross-sectional view of the structure after the first etching process of the present invention.
[0024] Figure 5 The diagram shown is a cross-sectional view of the structure after the formation of the second oxide layer according to the present invention.
[0025] Figure 6 The diagram shown is a cross-sectional view of the structure after the second etching process of the present invention.
[0026] Figure 7 The diagram shows a cross-sectional structure of the floating gate formed by the third etching process of the present invention.
[0027] Figure 8 Displayed as Figure 7 Scanning electron microscope image of the structure shown.
[0028] Explanation of icon numbers
[0029] 10: Memory region structure; 11: Gate oxide layer; 12: Floating gate polysilicon layer; 13: Gate dielectric layer; 13a: Bottom oxide layer; 13b: Intermediate nitride layer; 13c: Top oxide layer; 14: Control gate polysilicon layer; 15: First etching window; 16: Sidewall structure; 16a: First silicon oxide layer; 16b: Second silicon nitride layer; 20: Semiconductor substrate; 30: Mask layer; 31: Second etching window; 40: First oxide layer; 41: Etching opening; 50: Second oxide layer Detailed Implementation
[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0031] Please see Figures 1 to 8It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.
[0032] This embodiment provides a method for etching the floating gate of a flash memory device, the method including: step 1), step 2), step 3), step 4), step 5), and step 6).
[0033] In step 1), a memory region structure 10 of a flash memory device is provided. The memory region structure 10 includes a gate oxide layer 11, a floating gate polysilicon layer 12, a gate dielectric layer 13 and a control gate polysilicon layer 14 stacked sequentially from bottom to top. The control gate polysilicon layer 14 and the gate dielectric layer 13 form a first etching window 15, and the sidewall of the first etching window 15 forms a sidewall structure 16.
[0034] like Figure 2 As shown, in this embodiment, the storage region structure 10 is formed on the surface of the semiconductor substrate 20, which includes, but is not limited to, a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate. The sidewall structure 16 includes a first silicon oxide layer 16a and a second silicon nitride layer 16b, and the second silicon nitride layer 16b is formed on the surface of the first silicon oxide layer 16a.
[0035] Specifically, the gate dielectric layer 13 includes a bottom oxide layer 13a, an intermediate nitride layer 13b, and a top oxide layer 13c, wherein the bottom oxide layer 13a is formed on the surface of the floating gate polysilicon layer 12, and the intermediate nitride layer 13b is formed between the bottom oxide layer 13a and the top oxide layer 13b.
[0036] Specifically, a mask layer 30 is formed on the surface of the control gate polysilicon layer 14, and the mask layer 30 has a second etching window 31. The second etching window 31 communicates with the first etching window 15 and is larger than the first etching window 15. At this time, the sidewall structure 16 is also formed on the sidewall of the second etching window 31. In this embodiment, the material of the mask layer 30 includes silicon nitride.
[0037] In step 2), a first oxide layer 40 is formed on the surface of the storage area structure 10. For example... Figure 3 As shown, in this embodiment, the first oxide layer 40 covers the bottom of the first etched window 15, the sidewall structure 16, and the surface of the mask layer 30.
[0038] Specifically, the first oxide layer 40 is formed using a deposition process. In this embodiment, the first oxide layer 40 is made of silicon oxide and can be formed using a CVD deposition process.
[0039] In step 3), the first oxide layer 40 is etched using the first etching process, and the floating gate polysilicon layer 12 at a preset depth is etched at the first etching window 15 to form an etching opening 41.
[0040] Specifically, the preset depth ranges from 30 Å to 80 Å.
[0041] like Figure 4 As shown, in this embodiment, the floating gate polysilicon layer 12 is etched to a preset depth using the first etching process to form the etching opening 41. The depth of the etching opening 41 can be used to define the upper portion of the floating gate polysilicon layer 12. When the third etching process is performed to form the floating gate, the sidewalls of the etching opening 41 are covered by the second oxide layer 50, thus ensuring that the upper portion of the formed floating gate has a prominent and obvious sharp corner. Optionally, the preset depth is 50 Å. Of course, in the specific etching process, the preset depth can be selected within this range as needed.
[0042] In step 4), a second oxide layer 50 is formed on the surface of the structure formed in step 3).
[0043] like Figure 5 As shown, in this embodiment, the material of the second oxide layer 50 includes silicon oxide. Furthermore, the second oxide layer 50 covers the bottom and sidewalls of the etched opening, as well as the surfaces of the sidewall structure 16 and the mask layer 30.
[0044] Specifically, the second oxide layer 50 is formed using a deposition process.
[0045] Specifically, the thickness of the second oxide layer 50 ranges from 70 Å to 200 Å.
[0046] In step 5), the second oxide layer 50 is etched using a second etching process until the floating gate polysilicon layer 12 at the bottom of the etched opening 41 is exposed, while the sidewalls of the etched opening 41 are still covered by the second oxide layer 50 (e.g., Figure 6 (As shown).
[0047] In step 6), the floating gate polysilicon layer 12 is etched at the etched opening using a third etching process to form a floating gate.
[0048] In this embodiment, since the sidewall of the etching opening 41 is covered by the second oxide layer 50, and the second oxide layer 50 and the floating gate polysilicon layer 12 have a high selectivity, when the floating gate polysilicon layer 12 is etched in the third etching process, the floating gate polysilicon layer 12 (the lower part of the floating gate polysilicon layer 12) not covered by the second oxide layer 50 at the etching opening 41 is etched at a fast rate, while the floating gate polysilicon layer 12 (the lower part of the floating gate polysilicon layer 12) covered by the second oxide layer 50 is etched at a slow rate. This results in the floating gate forming a prominent sharp corner in the upper part (e.g., Figure 7 (As shown).
[0049] Specifically, in step 6), an etching gas with a high selectivity for the second oxide layer 50 is selected. In this embodiment, the etching gas includes SF6 and CH2F2.
[0050] Specifically, the first etching process, the second etching process, and the third etching process are all dry etching processes.
[0051] In summary, the floating gate etching method for the flash memory device of the present invention, through a two-stage oxide layer deposition and etching process, ensures that the portion above the polysilicon layer of the floating gate (where sharp corners will subsequently form) is covered by an oxide layer. Therefore, during the etching of the polysilicon to form the floating gate, the etching rate of the portion above the polysilicon is lower than the etching rate of the portion below it, thereby enabling the formed floating gate to have sharp corners and improving the durability of the flash memory device. Thus, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0052] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for etching the floating gate of a flash memory device, characterized in that, The method includes: Step 1) Provide a memory region structure for a flash memory device, the memory region structure including a gate oxide layer, a floating gate polysilicon layer, a gate dielectric layer and a control gate polysilicon layer stacked sequentially from bottom to top, wherein the control gate polysilicon layer and the gate dielectric layer form a first etching window, and the sidewall of the first etching window forms a sidewall structure. Step 2) Form a first oxide layer on the surface of the storage area structure; Step 3) The first oxide layer is etched using the first etching process, and the floating gate polysilicon layer at a preset depth is etched at the first etching window to form an etching opening; Step 4) Form a second oxide layer on the surface of the structure formed in step 3); Step 5) Use the second etching process to etch the second oxide layer until the floating gate polysilicon layer at the bottom of the etching opening is exposed, and the sidewall of the etching opening is still covered by the second oxide layer. Step 6) The floating gate polysilicon layer is etched at the etched opening using a third etching process to form a floating gate.
2. The etching method for the floating gate of a flash memory device according to claim 1, characterized in that, The preset depth ranges from 30 Å to 80 Å.
3. The etching method for the floating gate of a flash memory device according to claim 1, characterized in that, The thickness of the second oxide layer ranges from 70 Å to 200 Å.
4. The etching method for the floating gate of a flash memory device according to claim 1, characterized in that, The first oxide layer and the second oxide layer are formed using a deposition process.
5. The etching method for the floating gate of a flash memory device according to claim 1, characterized in that, The first etching process, the second etching process, and the third etching process are all dry etching processes.
6. The etching method for the floating gate of a flash memory device according to claim 1, characterized in that, In step 6), an etching gas with a high selectivity for the second oxide layer is selected.
7. The etching method for the floating gate of a flash memory device according to any one of claims 1 to 6, characterized in that, A mask layer is formed on the surface of the control gate polysilicon layer, and a second etching window is formed on the mask layer. The second etching window is connected to the first etching window and is larger than the first etching window. At this time, the sidewall structure is also formed on the sidewall of the second etching window.
8. The etching method for the floating gate of a flash memory device according to claim 1, characterized in that, The gate dielectric layer includes a bottom oxide layer, an intermediate nitride layer, and a top oxide layer, wherein the bottom oxide layer is formed on the surface of the floating gate polysilicon layer, and the intermediate nitride layer is formed between the bottom oxide layer and the top oxide layer.