A high electron mobility transistor resistant to single event burnout and a method of manufacturing the same

Abstract

The embodiment of the present application relates to the technical field of semiconductor devices, in particular to a high electron mobility transistor (HEMT) resistant to single event burnout (SEB) and a preparation method thereof, comprising: a substrate, a buffer layer, a channel layer and a barrier layer stacked on the substrate in sequence, a source and a drain respectively located on two sides of the barrier layer, a doped layer located between the source and the drain, a nitride layer located on the barrier layer, and a gate located on the nitride layer; wherein the bottom of the gate is in contact with the nitride layer; the source and the drain are in contact with the barrier layer respectively; the doped layer penetrates the barrier layer and the channel layer in sequence; the bottom surface of the doped layer is flush with the bottom surface of the channel layer; and the nitride layer is located between the source and the drain. The embodiment of the present application can solve the problem that high-density electron-hole pair non-equilibrium carriers are generated in the device by incident high-energy particles, which affects the electric field distribution of the high-voltage device, and causes the device to be prone to single event burnout (SEB) at a voltage lower than the normal rated voltage.

Description

TECHNICAL FIELD

[0001] The embodiment of the present application relates to the technical field of semiconductor devices, in particular to an anti-single-particle burnout high electron mobility transistor and a preparation method thereof. BACKGROUND

[0002] Gallium nitride (GaN) is a representative of the third generation of semiconductor materials, compared with silicon or gallium arsenide, has a wide band gap, superior anti-radiation, high avalanche breakdown electric field, good thermal conductivity and high electron drift rate under strong field and many excellent characteristics, therefore, the GaN-based power device is widely used in laser, LED, microwave, radio frequency and other fields. High electron mobility transistor (HEMT) is a kind of heterojunction field effect transistor, due to the existence of high mobility two-dimensional electron gas (2DEG) in the heterojunction, so that the HEMT device has high frequency, high power, high temperature resistance, strong anti-radiation ability and other superior performance.

[0003] The depletion mode GaN-based HEMT will cause high switching loss under no external bias, and an additional negative bias is needed to maintain the non-working state (off state) to increase the circuit power consumption, and the current application is greatly limited. On the contrary, the enhancement mode P-type nitride gate HEMT is off under no external bias, and has no off-state power consumption, which is increasingly valued by people.

[0004] Under the space radiation environment, high-energy particles and cosmic rays will have a great impact on the electrical parameters of electronic devices, and even may directly cause permanent failure of the device. For high-voltage devices, single-particle effect is a key factor affecting its space application. P-GaN enhancement mode power device is sensitive to single-particle effect, because the incident high-energy particles generate high-density electron-hole pair non-equilibrium carriers in the device, affect the electric field distribution of high-voltage device, and cause single-particle burnout of the device under lower than normal rated voltage. SUMMARY

[0005] The embodiment of the present application provides an anti-single-particle burnout high electron mobility transistor and a preparation method thereof, which improves the anti-single-particle burnout capability of the enhancement mode electron mobility transistor device.

[0006] To solve the above technical problems, in a first aspect, the embodiments of the present application provide a high electron mobility transistor resistant to single event burnout, comprising: a substrate, a buffer layer, a channel layer and a barrier layer stacked in sequence on the substrate, a source and a drain respectively located on two sides of the barrier layer, a doped layer located between the source and the drain, a nitride layer located on the barrier layer, and a gate located on the nitride layer; the source and the drain are in contact with the barrier layer; the doped layer penetrates the barrier layer and the channel layer in sequence; the bottom surface of the doped layer is flush with the bottom surface of the channel layer; the nitride layer is located between the source and the drain; and the bottom of the gate is in contact with the nitride layer.

[0007] In some example embodiments, the doped layer comprises a P-type doped layer and an N-type doped layer covering the sidewall and the bottom surface of the P-type doped layer.

[0008] In some example embodiments, the doping concentration of the P-type doped layer is 1×10 17 cm -3 ~ 1×10 20 cm -3 ; and the doping concentration of the N-type doped layer is 1×10 17 cm -3 ~ 1×10 20 cm -3 .

[0009] In some example embodiments, the bottom surface of the P-type doped layer is flush with the bottom surface of the barrier layer, and the top surface of the P-type doped layer is flush with the top surface of the barrier layer.

[0010] In some example embodiments, in the direction from the source to the drain, the width of the P-type doped layer is smaller than the width of the N-type doped layer.

[0011] In some example embodiments, the high electron mobility transistor further comprises: a nitride buried layer located below the source, and the bottom of the nitride buried layer extends to the inside of the buffer layer.

[0012] In some example embodiments, the high electron mobility transistor further comprises: a first passivation layer and a second passivation layer, the first passivation layer is located between the source and the nitride layer, and the second passivation layer is located between the nitride layer and the drain.

[0013] In some example embodiments, the high electron mobility transistor further comprises: a gate field plate and a drain field plate located between the gate and the drain; one side of the gate field plate is connected with the gate, and the other side extends into the second passivation layer; one side of the drain field plate is connected with the drain, and the other side extends into the second passivation layer.

[0014] In a second aspect, the embodiments of the present application further provide a preparation method of a high electron mobility transistor resistant to single event burnout, comprising: providing a substrate, forming a buffer layer, a channel layer and a barrier layer in sequence on the substrate; forming a doped layer in the channel layer and the barrier layer; forming an epitaxial layer on a side of the barrier layer away from the channel layer; etching the epitaxial layer to form a nitride layer; forming a source electrode and a drain electrode on the barrier layer; forming a gate electrode on the nitride layer; and leading out electrodes above the gate electrode, the source electrode and the drain electrode.

[0015] In some example embodiments, the forming of the doped layer in the channel layer and the barrier layer comprises: forming an N-type doped layer and a P-type doped layer in the channel layer and the barrier layer, respectively.

[0016] The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0017] The embodiments of the present application are aimed at high-density electron-hole pairs generated by incident high-energy particles in a device, which affects the electric field distribution of the high-voltage device and causes the single event burnout of the device at a voltage lower than the normal rated voltage. The embodiments of the present application provide a high electron mobility transistor resistant to single event burnout and a preparation method thereof. First, the embodiments of the present application increase the P-N junction between the gate electrode and the drain electrode, so that the electric field distribution of the drain electrode is more uniform, the high electric field caused by the electron aggregation at the drain electrode is alleviated, the burnout of the device is prevented, and the single event burnout resistance of the device is improved. Second, the embodiments of the present application add a gate field plate and a drain field plate to the gate electrode and the drain electrode, respectively, so that the peak electric field at the edges of the gate electrode and the drain electrode is alleviated by the field plates, the single event burnout of the device caused by the local electric field concentration is avoided, and the single event burnout resistance of the device is further improved. In addition, the embodiments of the present application add a nitride buried layer below the source electrode, so that the formation of the electron leakage path between the source electrode and the drain electrode is delayed, the avalanche breakdown caused by the interaction of the high-concentration electron-hole pairs in the device is reduced, the single event burnout resistance of the device is improved, and the device has a good application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0018] One or more embodiments are illustrated by way of example in the figures that are part of this document, and which illustrate by way of example the principles of the embodiments. The drawings are not intended to limit the embodiments to the subject matter of the drawings. Unless otherwise indicated, the drawings are not necessarily to scale.

[0019] Figure 1 A structure schematic diagram of a high electron mobility transistor resistant to single event burnout provided by an embodiment of the present application;

[0020] Figure 2 A structure schematic diagram of a high electron mobility transistor resistant to single event burnout provided by another embodiment of the present application;

[0021] Figure 3A structure diagram of a high electron mobility transistor resistant to single event burnout is provided for another embodiment of the present application;

[0022] Figure 4 A flowchart of a preparation method of a high electron mobility transistor resistant to single event burnout is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0023] As can be known from the background art, high-density electron-hole pair non-equilibrium carriers are generated in the device by incident high-energy particles, which affects the electric field distribution of the high-voltage device, resulting in the problem that the device is prone to single event burnout at a voltage lower than the normal rated voltage.

[0024] With the continuous development of space satellites, space exploration and other aerospace technologies, the demand for power systems that are resistant to high temperature, high power, small size and suitable for extreme radiation environments is increasingly evident. As one of the core representatives of wide bandgap semiconductor technology, gallium nitride-based power devices have advantages such as high breakdown voltage, small on-resistance, high temperature resistance and radiation resistance compared to traditional silicon devices, and can meet the application requirements of new generation of spacecraft power systems. In the universe, there are various high-energy particles, and aerospace systems are constantly threatened by high-energy particles in such an environment.

[0025] When high-energy ions act on these integrated circuits and semiconductor devices, a series of effects will be triggered, and single event effect is one of the important effects. Single event effect refers to a radiation effect that causes abnormal changes in the state of a device when a single high-energy particle is incident on the sensitive area of the electronic device. It is a phenomenon that occurs with the trend of designing electronic devices towards smaller feature sizes and higher device densities. The most important failure mode is the single event burnout phenomenon of power devices. Single event burnout has become a key technology that restricts the development of aerospace radiation resistance fields. Mature silicon-based devices do not have strong radiation resistance due to their own material properties, making it difficult to apply them to the field of aerospace radiation resistance. The advantages of gallium nitride power devices are highlighted. Although there has been some research on the single event burnout of the third generation of wide bandgap devices, the threshold voltage of single event burnout of all current material devices is very low and far below the breakdown voltage of the device itself, which has serious reliability problems. It is urgent to develop new transistor structures with enhanced single event burnout characteristics.

[0026] Traditional P-GaN enhanced power devices are sensitive to single event effects. High-density electron-hole pair non-equilibrium carriers are generated in the device by incident high-energy particles, which affects the electric field distribution of the high-voltage device, resulting in the problem that the device is prone to single event burnout at a voltage lower than the normal rated voltage.

[0027] To solve the above technical problems, the embodiment of the present application provides a high electron mobility transistor resistant to single event burnout, comprising: a substrate and a buffer layer, a channel layer and a barrier layer stacked in sequence on the substrate, a source and a drain respectively located on two sides of the barrier layer, a doped layer located between the source and the drain, a nitride layer located on the barrier layer, and a gate located on the nitride layer; the source and the drain are in contact with the barrier layer respectively; the doped layer penetrates the barrier layer and the channel layer in sequence; the bottom surface of the doped layer is flush with the bottom surface of the channel layer; the nitride layer is located between the source and the drain; and the bottom of the gate is in contact with the nitride layer. The embodiment of the present application increases the P-N junction between the gate and the drain, so that the electric field distribution of the drain is more uniform, and the high electric field caused by the electron aggregation at the drain is relieved. Meanwhile, the gate field plate and the drain field plate are added to the gate and the drain respectively, so that the peak electric field at the edges of the gate electrode and the drain electrode is relieved through the field plate, the single event burnout of the device caused by the local electric field concentration is avoided, the single event burnout resistance of the device is improved, and the nitride buried layer is added below the source to delay the formation of the electron leakage path between the source and the drain, so that the avalanche breakdown caused by the interaction of the high-concentration electron hole pairs in the device is reduced, and the single event burnout resistance of the high electron mobility transistor device is further improved.

[0028] The embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are proposed in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0029] Referring to Figure 1 The embodiment of the present application provides a high electron mobility transistor resistant to single event burnout, comprising: a substrate 101 and a buffer layer 102, a channel layer 103 and a barrier layer 104 stacked in sequence on the substrate 101, a source 105 and a drain 106 respectively located on two sides of the barrier layer 104, a doped layer 107 located between the source 105 and the drain 106, a nitride layer located on the barrier layer 104, and a gate 109 located on the nitride layer 108; the source 105 and the drain 106 are in contact with the barrier layer 104 respectively; the doped layer 107 penetrates the barrier layer 104 and the channel layer 103 in sequence; the bottom surface of the doped layer 107 is flush with the bottom surface of the channel layer 103; the nitride layer 108 is located between the source 105 and the drain 106; and the bottom of the gate 109 is in contact with the nitride layer 108.

[0030] In some embodiments, the material of the substrate 101 includes one of sapphire, silicon carbide (SiC), silicon (Si), and gallium nitride. For example, the substrate 101 can adopt a silicon carbide substrate or a sapphire substrate. The thickness of the substrate 101 is 30 nm to 200 nm in the direction from the lower surface of the substrate 101 to the upper surface of the substrate 101. For example, the thickness of the substrate 101 can be 30 nm, 80 nm, 100 nm, 150 nm, or 200 nm. It should be noted that the thicknesses of the film layers in the following embodiments of the present application are all in the thickness direction.

[0031] In some embodiments, the material of the buffer layer 102 includes one or more of gallium nitride, aluminum nitride, and aluminum gallium nitride. The thickness of the buffer layer 102 is 0.5 μm to 5 μm. For example, the thickness of the buffer layer 102 can be 0.5 μm, 1 μm, 2 μm, 2.5 μm, 3.5 μm, or 5 μm. As an example, the material of the buffer layer 102 can adopt AlGaN, the impurity for doping is C or Fe, and the doping concentration is 1 × 1018cm-3to 1 × 1020cm-3. 15 ~ 1 × 1020cm-3. 18 cm -3 .

[0032] In some embodiments, the material of the channel layer 103 includes one of gallium nitride and aluminum gallium nitride. Preferably, the materials of the buffer layer 102 and the channel layer 103 are both gallium nitride. The thickness of the channel layer 103 is 50 nm to 500 nm. For example, the thickness of the channel layer 103 can be 50 nm, 100 nm, 200 nm, 400 nm, or 500 nm.

[0033] In some embodiments, the material of the barrier layer 104 is AlGaN of wurtzite structure. Specifically, the material of the barrier layer 104 is Al0.1Ga0.9N. When the barrier layer 104 is Al0.1Ga0.9N, the component (the value of x) of Al is 0.1 to 0.2. The thickness of the barrier layer 104 is 10 nm to 40 nm. For example, the thickness of the barrier layer 104 can be 10 nm, 15 nm, 20 nm, 25 nm, 35 nm, or 40 nm. x Ga (1-x) N. When the barrier layer 104 is Al x Ga (1-x) N, the component (the value of x) of Al is 0.1 to 0.2. The thickness of the barrier layer 104 is 10 nm to 40 nm. For example, the thickness of the barrier layer 104 can be 10 nm, 15 nm, 20 nm, 25 nm, 35 nm, or 40 nm.

[0034] It should be noted that the source 105 and the drain 106 are respectively located on the left and right sides of the barrier layer 104, and the source 105 and the drain 106 respectively form ohmic contacts with the barrier layer 104. In some embodiments, the source 105 and the drain 106 can adopt a metal combination of Ti / Al / Ni / Au or Ti / Al / Pt / Au to form ohmic contacts with the barrier layer 104, respectively.

[0035] Specifically, the bottom of the gate 109 forms an ohmic contact or a Schottky contact with the nitride layer 108. In some embodiments, the gate 109 is made of a metal that can form an ohmic contact or a Schottky contact with the nitride layer 108.

[0036] In some embodiments, the material of the nitride layer 108 includes p-type gallium nitride (P-GaN) or p-type aluminum nitride (P-AlN). Preferably, the material of the nitride layer 108 is p-type GaN; typically, the material of the nitride layer 108 is Mg-doped p-type GaN. The thickness of the nitride layer 108 along the thickness direction of the substrate 101 is 10 nm to 40 nm.

[0037] like Figure 1 As shown, the nitride layer 108 is located to the right of the source 105, and the spacing between the nitride layer 108 and the source 105 is 1 μm to 5 μm; for example, the spacing between the nitride layer 108 and the source 105 can be 1 μm, 2 μm, 2.5 μm, 3.5 μm, or 5 μm. When the nitride layer 108 is P-type GaN, the doping concentration of P-type ions is 1 × 10⁻⁶. 17 cm -3 ~1×10 20 cm -3 .

[0038] See Figures 1 to 3 In some embodiments, the doped layer 107 includes a P-type doped layer 107a and an N-type doped layer 107b covering the sidewalls and bottom surface of the P-type doped layer 107a.

[0039] In some exemplary embodiments, the bottom surface of the P-type doped layer 107a is flush with the bottom surface of the barrier layer 104, and the top surface of the P-type doped layer 107b is flush with the top surface of the barrier layer 104. In some exemplary embodiments, along the direction from the gate 109 to the nitride layer 108, the height of the P-type doped layer 107a is the same as the height of the barrier layer 104, that is, the height of the P-type doped layer 107a is 10nm to 40nm. The top surface of the N-type doped layer 107b is flush with the top surface of the P-type doped layer 107a, and the bottom surface of the N-type doped layer 107b is flush with the bottom surface of the channel layer 103. Figure 1 As shown, the thickness of the N-type doped layer 107b is greater than the thickness of the P-type doped layer 107a. Here, the thickness of the N-type doped layer 107b is its height. Figure 1 As can be seen, the N-type doped layer 107b covers the sidewalls and bottom wall of the P-type doped layer 107a, forming a PN junction between the gate 109 and the drain 106, making the electric field distribution of the drain 106 more uniform and alleviating the high electric field caused by electron accumulation at the drain 106; in addition, the N-type doped layer 107b prevents the two-dimensional electron gas from being unable to conduct, increases the electron migration path, and thus reduces the accumulation of electrons at the drain.

[0040] As shown in Figure 1 , the P-type doped layer 107a is located in the barrier layer 104; along the direction from the source 105 to the drain 106, the width of the P-type doped layer 107a is 1-2 μm, and the distance between the P-type doped layer 107a and the gate 109 is 3.5-4.5 μm, that is, the P-type doped layer 107a is located at the right side of the gate 109 by 3.5-4.5 μm.

[0041] The N-type doped layer 107b is located below and at both ends of the P-type doped layer 107a, and completely covers the four sides and the bottom of the P-type doped layer 107a. Along the direction from the source 105 to the drain 106, the length of the N-type doped layer 107b is 2-4 μm; along the direction from the gate 109 to the nitride layer 108, the thickness of the N-type doped layer 107b is greater than the thickness of the P-type doped layer 107a, and the thickness of the N-type doped layer 107b is equal to the sum of the thicknesses of the channel layer 103 and the barrier layer 104.

[0042] The high electron mobility transistor provided by the embodiment of the present application can be used in the power conversion circuit of an aerospace system. Since the aerospace system is in the environment containing various high-energy particles in the space, the aerospace system is always threatened by the high-energy particles, and the single particle effect makes the GaN power device easily cause single particle burnout, thereby causing the problem of early breakdown of the device. In view of the technical problem, the doped layer 107 is arranged on the channel layer 103 and the barrier layer 104 between the source 105 and the drain 106 of the device, to form a P-N junction between the gate 108 and the drain 106, form a P-type doped region in the barrier layer 104, and form an N-type doped region in the channel layer 103 and the barrier layer 104; the P-N junction makes the electric field distribution of the drain 106 more uniform, and relieves the high electric field caused by the electron aggregation at the drain 106; the addition of the N-type doped region prevents the two-dimensional electron gas from being conductive, increases the migration path of the electrons, thereby reducing the aggregation of the drain electrons and making them able to withstand higher voltage, thereby improving the working life and reliability of the aerospace power system.

[0043] In some example embodiments, the doping concentration of the P-type doped layer 107a is 1×10 17 cm -3 -1×10 20 cm -3 ; and the doping concentration of the N-type doped layer 107b is 1×10 17 cm -3 -1×10 20 cm -3 .

[0044] In some example embodiments, the width of the P-type doped layer 107a is less than the width of the N-type doped layer 107b in the direction from the source 105 to the drain 106.

[0045] In some example embodiments, the high electron mobility transistor further comprises a nitride buried layer 110 under the source 105, the bottom of the nitride buried layer 110 extending into the buffer layer 102. As a leakage path of electrons is formed between the source 105 and the drain 106 when a single particle is incident, the nitride buried layer 110 is added under the source 105 to inhibit the electron migration between the source 105 and the drain 106, effectively reducing the transient current after heavy ion irradiation, and improving the single event burnout resistance of the device.

[0046] In some embodiments, the nitride buried layer 110 is a P-Type buried layer, and the doping concentration of the P-Type buried layer is 1x1018cm-3~1x1020cm-3, for example, the P-type doping concentration can be 1x1018cm-3, 5x1018cm-3, 6x1018cm-3, 8x1018cm-3, 1x1019cm-3, 5x1019cm-3, 6x1019cm-3, 8x1019cm-3, 1x1020cm-3, or the like. 17 cm -3 ~1x10 20 cm -3 , for example, the P-type doping concentration can be 1x1018cm-3, 5x1018cm-3, 6x1018cm-3, 8x1018cm-3, 1x1019cm-3, 5x1019cm-3, 6x1019cm-3, 8x1019cm-3, 1x1020cm-3, or the like. 17 cm -3 , for example, the P-type doping concentration can be 1x1018cm-3, 5x1018cm-3, 6x1018cm-3, 8x1018cm-3, 1x1019cm-3, 5x1019cm-3, 6x1019cm-3, 8x1019cm-3, 1x1020cm-3, or the like. 17 cm -3 , for example, the P-type doping concentration can be 1x1018cm-3, 5x1018cm-3, 6x1018cm-3, 8x1018cm-3, 1x1019cm-3, 5x1019cm-3, 6x1019cm-3, 8x1019cm-3, 1x1020cm-3, or the like. 17 cm -3 , for example, the P-type doping concentration can be 1x1018cm-3, 5x1018cm-3, 6x1018cm-3, 8x1018cm-3, 1x1019cm-3, 5x1019cm-3, 6x1019cm-3, 8x1019cm-3, 1x1020cm-3, or the like. 17 cm -3 , for example, the P-type doping concentration can be 1x1018cm-3, 5x1018cm-3, 6x1018cm-3, 8x1018cm-3, 1x1019cm-3, 5x1019cm-3, 6x1019cm-3, 8x1019cm-3, 1x1020cm-3, or the like. 18 cm -3 The P-Type buried layer is one of doped P-type GaN, AlN, AlGaN, for example, the P-Type buried layer can adopt a P-GaN structure.

[0047] It should be noted that the width of the nitride buried layer 110 is the same as the width of the source 105 in the direction from the source 105 to the drain 106. As shown in FIG. 1, the nitride buried layer 110 is located directly below the source 105. The two sides of the nitride buried layer 110 are flush with the two sides of the source 105. In the thickness direction of the substrate 101, the thickness of the nitride buried layer 110 can be 0.4μm~0.6μm; for example, the thickness of the nitride buried layer 110 can be 0.4μm, 0.5μm or 0.6μm. Figure 3

[0048] In some example embodiments, the high electron mobility transistor further comprises a first passivation layer 111 and a second passivation layer 112, the first passivation layer 111 being located between the source 105 and the nitride layer 108; the second passivation layer 112 being located between the nitride layer 108 and the drain 106.

[0049] ​It should be noted that the material of the first passivation layer 111 and the material of the second passivation layer 112 can be the same or different. The material of the first passivation layer 111 and the second passivation layer 112 can be a material with high critical breakdown field strength, such as hafnium oxide (Hf02), titanium oxide (Ti02), zirconium oxide (Zr02), yttrium oxide (Y203), lanthanum oxide (La203), tantalum oxide (Ta205), silicon dioxide (Si02), silicon nitride (Si3N4). The material of the first passivation layer 111 and the second passivation layer 112 can also be a conventional passivation material, such as silicon oxide (Si02), aluminum oxide (Al203), silicon nitride (Si3N4).

[0050] It should be noted that the first passivation layer 111 and the second passivation layer 112 can be formed by atomic layer deposition (ALD). The conventional passivation layer formed by ALD has a critical breakdown field strength of about 5 MV / cm. The first passivation layer 111 and the second passivation layer 112 can also be formed by plasma enhanced chemical vapor deposition (PECVD).

[0051] Specifically, since the first passivation layer 111 and the second passivation layer 112 can be made at the same time, it is preferred that the material of the first passivation layer 111 and the second passivation layer 112 is the same and the height is the same. In the direction from the gate 109 to the nitride layer 108, the height of the first passivation layer 111 and the second passivation layer 112 is 90-300 nm.

[0052] In some exemplary embodiments, the high electron mobility transistor described above further comprises: a gate field plate 109a and a drain field plate 106a located between the gate 109 and the drain 106; one side of the gate field plate 109a is connected with the gate 109, and the other side extends into the second passivation layer 112; one side of the drain field plate 106a is connected with the drain 106, and the other side extends into the second passivation layer 112.

[0053] Referring to Figure 2 and Figure 3 , the gate field plate 109a is located on the second passivation layer 112, and the gate field plate 109a is located on the side of the gate 109 close to the drain 106. The gate field plate 109a is connected with the gate 109, and the width of the gate field plate 109a is 1-5 μm. The drain field plate 106a is located on the second passivation layer 112, and the drain field plate 106a is located on the side of the drain 106 close to the gate 109, and the drain field plate 106a is connected with the drain 106.

[0054] In addition, in some example embodiments, the high electron mobility transistor resistant to single event burnout further comprises an insertion layer, which can be located between the channel layer 103 and the barrier layer 104. The insertion layer is used to improve the carrier mobility, and the material of the insertion layer includes but is not limited to AlN, InAlN, and AlGaN.

[0055] Referring to Figure 4 The example embodiments of the present application further provide a preparation method of the high electron mobility transistor resistant to single event burnout, which comprises the following steps:

[0056] In step S1, a substrate is provided, and a buffer layer, a channel layer, and a barrier layer are sequentially stacked on the substrate.

[0057] In step S2, a doped layer is formed in the channel layer and the barrier layer.

[0058] In step S3, an epitaxial layer is formed on a side of the barrier layer away from the channel layer.

[0059] In step S4, the epitaxial layer is etched to form a nitride layer.

[0060] In step S5, a source electrode and a drain electrode are formed on the barrier layer.

[0061] In step S6, a gate electrode is formed on the nitride layer.

[0062] In step S7, electrodes are led out above the gate electrode, the source electrode, and the drain electrode.

[0063] Specifically, in the preparation of the high electron mobility transistor, first, a substrate 101 is provided, and a buffer layer 102, a channel layer 103, and a barrier layer 104 are sequentially stacked on the substrate 101.

[0064] It should be noted that before the formation of the stacked film layers on the substrate 101, the substrate 101 is first pretreated and heat-treated, and a nucleation layer can be deposited on the substrate 101. Specifically, the nucleation layer is deposited by using a Metal Organic Chemical Vapor Deposition (MOCVD) process. Then, the buffer layer 102 and the channel layer 103 are sequentially deposited on the nucleation layer by using the MOCVD process. Then, the barrier layer 104 is deposited on the channel layer 103 by using the MOCVD process. Preferably, the material of the barrier layer 104 is Al x Ga (1-x) N, and the value of x is between 0.1 and 0.2. In the example embodiments of the present application, the thickness of the substrate 101 is between 30 nm and 200 nm; the thickness of the nucleation layer is between 30 nm and 100 nm; the thickness of the buffer layer 102 is between 0.5 μm and 5 μm; the thickness of the channel layer 103 is between 50 nm and 500 nm; and the thickness of the barrier layer 104 is between 10 nm and 40 nm.

[0065] In step S1, the operation steps of the pretreatment and the heat treatment of the substrate 101 are: ultrasonic cleaning of the substrate 101 with acetone, anhydrous ethanol solution and deionized water, and heat treatment of the substrate 101 at 1050°C for 10 minutes in a hydrogen atmosphere. In the process of depositing the nucleation layer, the pressure in the MOCVD process is 10 Torr-100 Torr, the Al source flow rate is 10 sccm-100 sccm, the ammonia flow rate is 3000 sccm-6000 sccm, the hydrogen flow rate is 1000 sccm-2000 sccm, and the temperature is 900°C.

[0066] In the process of depositing the buffer layer 102 and the channel layer 103, the reaction chamber pressure in the MOCVD process is 10 Torr-100 Torr, the Ga source flow rate is 50 μmol / min-100 μmol / min, the ammonia flow rate is 3000 sccm-6000 sccm, the hydrogen flow rate is 1000 sccm-2000 sccm, and the temperature is 900°C.

[0067] In the process of depositing the barrier layer 104, the reaction chamber pressure in the MOCVD process is 10 Torr-100 Torr, the Al source flow rate is 10 μmol / min-30 μmol / min, the Ga source flow rate is 30 μmol / min-90 μmol / min, the ammonia flow rate is 3000 sccm-6000 sccm, the hydrogen flow rate is 1000 sccm-2000 sccm, and the temperature is 900°C.

[0068] Step S2, forming a doped layer 107 in the channel layer 103 and the barrier layer 104.

[0069] In some example embodiments, as shown in FIG. 1, the doped layer 107 is formed in the channel layer 103 and the barrier layer 104, including: forming an N-type doped layer 107b and a P-type doped layer 107a in the channel layer 103 and the barrier layer 104, respectively. Figure 3

[0070] Specifically, the N-type doped layer 107b (N-type doped region) and the P-type doped layer 107a (P-type doped region) are formed by doping N-type ions and P-type ions in the channel layer 103 and the barrier layer 104, respectively. The P-type ions include one of Mg, Zn, C or Fe; and the N-type ions include Si or Ge. Optionally, the doping concentration of the P-type ions can be equal to the doping concentration of the N-type ions.

[0071] ​Preferably, the P-type ions can be Mg ions, and the N-type ions can be Si ions or Ge ions; the N-type doped layer 107b region in the channel layer 103 and the barrier layer 104 is formed by ion implanting Si ions or Ge ions to form an N region, and the P-type doped layer 107a region is formed by ion implanting Mg ions to form a p region. The present application forms a P-N junction between the gate 109 and the drain 106 to make the electric field distribution of the drain 106 more uniform and relieve the high electric field caused by the electron aggregation at the drain 106; the N-type doped region prevents the two-dimensional electron gas from being unable to conduct, and increases the electron migration path, thereby reducing the aggregation of the drain electrons.

[0072] Step S3, forming an epitaxial layer on the side of the barrier layer 104 away from the channel layer 103. Specifically, a MOCVD process is used to deposit an epitaxial layer with a thickness of 60-90 nm. Here, the material of the epitaxial layer is P-type gallium nitride or P-type aluminum nitride.

[0073] In the process of depositing the epitaxial layer, the reaction chamber pressure in the MOCVD process is 10-100 Torr, the Ga source flow rate is 50-100 μmol / min, the ammonia flow rate is 3000-6000 sccm, the hydrogen flow rate is 1000-2000 sccm, and the temperature is 900°C.

[0074] Step S4, etching the epitaxial layer to form a nitride layer 108. Specifically, the epitaxial layer is patterned and etched to expose the surface of the barrier layer 104 except the part covered by the nitride layer 108.

[0075] Step S5, forming a source 105 and a drain 106 on the barrier layer 104. Specifically, a mask is made on the barrier layer 104, and an electron beam evaporation process is used to deposit the source 105 and the drain 106, and annealing is performed at 850°C to form the source 105 and the drain 106. Preferably, the materials of the source 105 and the drain 106 are a combination of Ti / Al / Ni / Au metals, wherein the thickness of the metal Ti is 20-100 nm, the thickness of the metal Al is 100-300 nm, the thickness of the metal Ni is 20-200 nm, and the thickness of the metal Au is 20-200 nm.

[0076] Step S6, forming a gate 109 on the nitride layer 108. Specifically, a mask is made on the nitride layer 108, and an electron beam evaporation process is used to deposit the gate 109. The material of the gate 109 is a combination of Ni / Au metals, wherein the thickness of the metal Ni is 20-100 nm, and the thickness of the metal Au is 50-500 nm.

[0077] Next, a passivation material layer is formed above the barrier layer 104, the source 105, the drain 106 and the gate 109, and then the passivation material layer is etched to form the first passivation layer 111 and the second passivation layer 112.

[0078] Finally, electrodes are led out above the gate 109, the source 105 and the drain 106 to obtain the single-event burnout resistant high electron mobility transistor as shown in FIG. 1C. Figure 1

[0079] In some other embodiments, the method for manufacturing the single-event burnout resistant high electron mobility transistor further comprises: after the source 105 and the drain 106 are formed on the barrier layer 104, a drain field plate 106a is formed on the side of the drain 106 close to the source 105; and after the gate 109 is formed on the nitride layer 108, a gate field plate 109a is formed on the side of the gate 109 close to the drain 106. One side of the drain field plate 106a is connected to the drain 106, and the other side extends into the second passivation layer 112; one side of the gate field plate 109a is connected to the gate 109, and the other side extends into the second passivation layer 112.

[0080] Next, a passivation material layer is formed above the barrier layer 104, the source 105, the drain 106, the drain field plate 106a, the gate 109 and the gate field plate 109a, and then the passivation material layer is etched to form the first passivation layer 111 and the second passivation layer 112.

[0081] Finally, electrodes are led out above the gate 109, the source 105 and the drain 106 to obtain the single-event burnout resistant high electron mobility transistor as shown in FIG. 1C. Figure 2

[0082] In some other embodiments, the method for manufacturing the single-event burnout resistant high electron mobility transistor further comprises: before the source 105 is formed on the barrier layer 104, a buried nitride layer 110 is formed at a position directly below the source 105. Specifically, the barrier layer 104, the channel layer 103 and the buffer layer 102 are etched to form a slot for accommodating the buried nitride layer 110. The bottom of the slot extends into the buffer layer 102, and the vertical distance between the bottom of the slot and the bottom surface of the buffer layer 102 is one third to one half of the thickness of the buffer layer 102. The buried nitride layer 110 is formed in the slot, and the top surface of the buried nitride layer 110 is higher than the bottom surface of the channel layer 103 and lower than the top surface of the channel layer 103. The buried nitride layer 110 can be a P-Type buried layer, and the material of the P-Type buried layer can be one of doped P-type GaN, AlN and AlGaN. The doping concentration of the P-Type buried layer is 1 x 1018cm-1~1 x 1020cm-1. 17 -3 20 -3 ​​​​​The nitride buried layer 110 is added below the source 105 to delay the formation of the electron leakage path between the source 105 and the drain 106, reduce the avalanche breakdown caused by the interaction of high-concentration electron-hole pairs in the device, and further improve the single-event burnout resistance of the device.

[0083] Next, a passivation material layer is formed above the barrier layer 104, the source 105, the drain 106, the drain field plate 106a, the gate 109, and the gate field plate 109a, and then the passivation material layer is etched to form the first passivation layer 111 and the second passivation layer 112. Finally, electrodes are led out above the gate 109, the source 105, and the drain 106 to obtain the single-event burnout-resistant high electron mobility transistor as shown in FIG. 1C. Figure 3

[0084] According to the technical solutions above, the embodiments of the present application are aimed at the high-density electron-hole pairs generated by the incident high-energy particles in the device, the influence of the high-voltage device electric field distribution, and the single-event burnout problem of the device at a lower normal rated voltage. The single-event burnout-resistant high electron mobility transistor and the preparation method thereof are provided. The P-N junction is added between the gate 109 and the drain 106 to make the electric field distribution of the drain 106 more uniform and relieve the high electric field caused by the electron aggregation at the drain 106. The gate field plate 109a and the drain field plate 106a are added to the gate 109 and the drain 106, respectively, to relieve the peak electric field at the edges of the gate 109 and the drain 109 by the field plate, avoid the single-event burnout of the device caused by the local electric field concentration, improve the single-event burnout resistance of the device, improve the single-event burnout resistance of the device, and have a good application prospect.

[0085] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be limited by the scope defined in the claims.​

Claims

1. A single event burnout immune high electron mobility transistor, characterized by, The application relates to a semiconductor device, comprising: a substrate and a buffer layer, a channel layer and a barrier layer stacked in sequence on the substrate; a source and a drain respectively located on two sides of the barrier layer and respectively in contact with the barrier layer; a doped layer located between the source and the drain, the doped layer penetrating through the barrier layer and the channel layer in sequence, and a bottom surface of the doped layer being flush with a bottom surface of the channel layer; a nitride layer located on the barrier layer and between the source and the drain; a gate located on the nitride layer and having a bottom in contact with the nitride layer; the doped layer comprises a P-type doped layer and an N-type doped layer covering a side wall and a bottom surface of the P-type doped layer.

2. The single-event burnout immune high electron mobility transistor of claim 1, wherein, The doping concentration of the P-type doped layer is 1×10⁻⁶. 17 cm -3 ~1×10 20 cm -3 ; The N-type doped layer has a doping concentration of 1 x 10 17 cm -3 ~1 x 10 20 cm -3 .

3. The single-event burnout immune high electron mobility transistor of claim 1, wherein, A bottom surface of the P-type doped layer is flush with a bottom surface of the barrier layer, and a top surface of the P-type doped layer is flush with a top surface of the barrier layer.

4. The single-event burnout immune high electron mobility transistor of claim 1, wherein, In a direction from the source to the drain, a width of the P-type doped layer is smaller than a width of the N-type doped layer.

5. The single event burnout immune high electron mobility transistor of claim 1, wherein, The application further comprises: a nitride buried layer located below the source and having a bottom extending into the buffer layer.

6. The single-event burnout immune high electron mobility transistor of claim 1, wherein, The application further comprises: a first passivation layer located between the source and the nitride layer; a second passivation layer located between the nitride layer and the drain.

7. The single-event burnout immune high electron mobility transistor of claim 6, wherein, The application further comprises a gate field plate and a drain field plate located between the gate and the drain. One side of the gate field plate is connected with the gate, and the other side extends into the second passivation layer. One side of the drain field plate is connected with the drain, and the other side extends into the second passivation layer.

8. A method of manufacturing a single event burnout immune high electron mobility transistor, the method being for manufacturing a single event burnout immune high electron mobility transistor as claimed in any one of claims 1 to 7, characterized in that, The application relates to a semiconductor device, comprising: providing a substrate, and forming a buffer layer, a channel layer and a barrier layer stacked in sequence on the substrate; forming a doped layer in the channel layer and the barrier layer; forming an epitaxial layer on a side of the barrier layer away from the channel layer; etching the epitaxial layer to form a nitride layer; forming a source and a drain on the barrier layer; forming a gate on the nitride layer; leading out electrodes above the gate, the source and the drain.

9. The method for fabricating a high electron mobility transistor resistant to single-particle burn-off according to claim 8, characterized in that, The application relates to a semiconductor device, comprising: forming an N-type doped layer and a P-type doped layer in the channel layer and the barrier layer respectively.

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