Bandpass filter with multiple nulls and high out-of-band rejection based on ipd technology

Abstract

The application discloses a band-pass filter with multiple zero points and high out-of-band suppression based on an IPD technology. Mainly includes main circuit, input and output port; the main circuit includes first parallel capacitor, first series capacitor, first parallel inductor, second parallel capacitor, second parallel inductor, second parallel capacitor, second series capacitor, third parallel capacitor, first series inductor, third series capacitor, fourth parallel capacitor, fourth series inductor, fourth series capacitor. The application adds four zero points to suppress high frequency and low frequency, realizes higher out-of-band suppression, and improves the filtering characteristic of the band-pass filter; and higher out-of-band suppression is realized by adopting an optimized circuit structure.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency / microwave / communication technology, specifically relating to a bandpass filter with high out-of-band rejection and multiple zeros based on IPD technology. Background Technology

[0002] As a core component of the RF front-end, passive RF filters play a crucial role in wireless communication systems. With increasing integration in communication systems, the size requirements for bandpass filters are also rising. Integral Partition Difference (IPD) technology enables filter miniaturization. IPD technology uses semiconductor fabrication processes such as diffusion, photolithography, and etching to fabricate inductors, capacitors, and resistors onto semiconductors, resulting in smaller, thinner, and more integrated circuit templates. A bandpass filter is a passive device that allows selectivity at a specific frequency. For bandpass filters, high out-of-band rejection (OBS) has become a research hotspot for achieving better filtering within a specific frequency band. Traditional bandpass filter designs currently suffer from the following problems: As the frequency increases, parasitic effects also arise, and harmonics will appear in the passband, affecting the passband performance of the filter; planar bandpass filters based on microstrip line structures, although small in size, usually have high insertion loss; bandpass filters based on waveguide structures, although having good performance, are usually large in size and have low integration density, failing to meet the miniaturization requirements of RF front-ends; ceramic bandpass filters based on high dielectric constants, although having good out-of-band suppression and stable temperature coefficients, require sophisticated manufacturing processes, resulting in high costs. Summary of the Invention

[0003] The first objective of this invention is to address the problems of large size, poor selectivity, high insertion loss, and high cost of current bandpass filters in the prior art by providing a miniaturized bandpass filter with high out-of-band rejection based on IPD technology. The filter adopts IPD process design and a novel circuit topology, and has the advantages of low cost, high integration, good performance, and high selectivity, which can meet the needs of the current RF / microwave / communication technology field.

[0004] The technical solution adopted in this invention is as follows:

[0005] A bandpass filter with high out-of-band rejection and multiple zeros based on IPD technology includes: a main circuit and input / output ports;

[0006] The input ports include a first input port pad (4-1), a second input port pad (4-2), and a third input port pad (4-3); the output ports include a first output port pad (4-4), a second output port pad (4-5), and a third output port pad (4-6); the first input port pad (4-1) and the third input port pad (4-3) are input grounding ports, the second input port pad (4-2) is a signal input terminal, the first output port pad (4-4) and the third input port pad (4-6) are output grounding ports, and the second output port pad (4-5) is a signal output terminal.

[0007] The main circuit includes a first parallel capacitor (5), a first series capacitor (6), a first parallel inductor (7), a second parallel capacitor (8), a second parallel inductor (12), a second parallel capacitor (13), a second series capacitor (9), a first series inductor (11), a third series capacitor (14), a fourth parallel capacitor (17), a fourth series inductor (15), and a fourth series capacitor (16). One end of the first series capacitor (6), one end of the first parallel inductor (7), and one end of the first parallel capacitor (5) are connected to the second input port pad (4-2). The other end of the first series capacitor (6) is connected to one end of the second parallel inductor (12) and one end of the second series inductor (9). The other end of the first series inductor (7) is connected to one end of the second parallel capacitor (8). The other end of the second parallel capacitor (8) is grounded, and the other end of the first parallel capacitor (5) is grounded. The second series capacitor (9)... The other end is connected to one end of the first series inductor (11) and one end of the third series capacitor (14). The other end of the third series capacitor (14) and the other end of the first series inductor (11) are connected to one end of the fourth parallel capacitor (17), one end of the fourth series capacitor (16), and one end of the fourth series inductor (15). The other end of the fourth parallel capacitor (17) is grounded. The other end of the fourth series capacitor (16) and the other end of the fourth series inductor (15) are connected to the second output port pad (4-5).

[0008] Preferably, the main circuit further includes a high-frequency suppression module; one end of the high-frequency suppression module is connected to the other end of the second series capacitor (9) and one end of the first series inductor (11), and the other end is grounded;

[0009] More preferably, the high-frequency suppression module includes a third parallel capacitor (10);

[0010] Preferably, the shapes of the second parallel inductor (12), the first series inductor (11), and the first parallel inductor (7) include, but are not limited to, polygons such as circles, ellipses, spirals, rectangles, hexagons, and octagons;

[0011] More preferably, the second parallel inductor (12) and the first series inductor (11) are octagonal inductors; the first parallel inductor (7) is an octagonal gradient inductor, wherein the line width and line spacing of the octagonal gradient inductor gradually narrow from the outside to the inside;

[0012] Preferably, the first parallel capacitor (5), the first series capacitor (6), the second parallel capacitor (8), the second parallel capacitor (13), the second series capacitor (9), the third parallel capacitor (10), the third series capacitor (14), the fourth parallel capacitor (17), and the fourth series capacitor (16) are planar capacitors or surface-mount capacitors.

[0013] Preferably, the dielectric layer is achieved by filling with oxides and nitrides.

[0014] The second objective of this invention is to provide a design method for the aforementioned multi-zero high out-of-band rejection bandpass filter, specifically:

[0015] Step 1: Based on the given design specifications, the out-of-band suppression requirements for low and high frequencies are relatively high. This design uses a high-pass and low-pass cascaded design, and finally adds an infinite zero point to suppress high frequencies.

[0016] Step 2: Construct a high-pass filter

[0017] 2-1 According to the design specifications for low-frequency out-of-band suppression, a first resonant circuit is constructed consisting of a first parallel inductor (7), a second parallel capacitor (8), and a first series capacitor (6). A second resonant circuit is constructed consisting of a second series capacitor (9), a second parallel inductor (12), and a second parallel capacitor (13). These two resonant circuits form a high-pass filter, creating two zeros at low frequencies, thereby achieving the low-frequency specifications.

[0018] The high-pass filter transfer matrix is ​​then:

[0019]

[0020] Where B1 = wC1 / 1 - w 2 L1C1, B2=wC3 / 1-w 2 L2C3, X1 = 1 / wC2, X2 = 1 / wC4, where w is the zero-point frequency of the filter.

[0021] Equivalent circuit of a two-port network, parameter transformation of S-parameters to the ABCD matrix:

[0022]

[0023]

[0024] From formula (1), we get AD - BC = 1;

[0025] Therefore S 12 =S 21 Finding the zero-point frequency position is S. 12 =0 frequency, where Z0 = 50;

[0026] Substituting formula (1) into formula (2) yielded two transmission zeros, resulting in... Therefore, it can be deduced that the movement of the zero point at w1 is related to the first parallel inductor (7) and the first series capacitor (6): when the first parallel inductor (7) and the first series capacitor (6) increase, the zero point at the high frequency will move to the low frequency. The movement of the zero point at w2 is related to the second parallel inductor (12) and the second parallel capacitor (8): when the second parallel inductor (12) and the second parallel capacitor (8) increase, the zero point at the high frequency will move to the low frequency.

[0027] 2-2 By optimizing the high-pass filter, out-of-band suppression of the two zeros at low frequencies is achieved;

[0028] Step 3: Construct a low-pass filter

[0029] 3-1 According to the design specifications for high-frequency out-of-band suppression, a third resonant circuit is constructed, consisting of a third parallel capacitor (10), a first series inductor (11), and a third series capacitor (14). A fourth resonant circuit is constructed, consisting of a fourth series capacitor (16), a fourth series inductor (15), and a fourth parallel capacitor (17). These two resonant circuit structures form a low-pass filter, creating two zeros at high frequencies, thereby achieving the low-frequency specifications.

[0030] The low-pass filter transfer matrix is ​​then:

[0031]

[0032] Where X3 = wL3 / 1 - w 2 L3C7,X4=wL4 / 1-w 2 L4C8, B3 = wC6, B4 = wC9, where w is the added low-frequency zero;

[0033] Substituting formula (4) into formula (2) makes S 12 =0, solving for two transmission zeros, and obtaining Therefore, it can be deduced that the movement of the zero point at w3 is related to the first series inductor (11) and the third series capacitor (14): when the first series inductor (11) and the third series capacitor (14) increase, the zero point at the high frequency will move to the low frequency. The movement of the zero point at w4 is related to the fourth series inductor (15) and the fourth parallel capacitor (17): when the fourth series inductor (15) and the fourth parallel capacitor (17) increase, the zero point at the high frequency will move to the low frequency.

[0034] 3-2 By optimizing the low-pass filter, out-of-band suppression of the two zeros at high frequencies can be achieved;

[0035] Step 4: Cascade the above high-pass filter and low-pass filter to form a bandpass filter with high out-of-band rejection; then connect a first parallel capacitor (5) to generate an infinite zero at high frequencies, which suppresses the high frequencies of the bandpass filter. Finally, integrate the circuit and optimize it. By optimizing the parameters, the circuit can reach the optimal state.

[0036] The beneficial effects of this invention are as follows:

[0037] 1. The design adopts IPD process, and replaces the traditional discrete component structure of capacitors and inductors with octagonal inductors, octagonal gradient inductors and MIM capacitors. This improves the performance of the filter while achieving miniaturization. It also has the advantages of low cost and high integration, making it suitable for mass production.

[0038] 2. This invention adds four zeros to suppress high and low frequencies, achieving higher out-of-band rejection and improving the filtering characteristics of the bandpass filter;

[0039] 3. This invention changes the operating frequency of the filter by altering the number and value of octagonal inductors, gradient octagonal inductors, and MIM capacitors, making it suitable for various frequency bands such as VHF, UHF, 700 & 800MHz, Wifi, and 5G. Attached Figure Description

[0040] Figure 1(a) is the equivalent circuit diagram of the multi-zero bandpass filter of the present invention in the 5G band;

[0041] Figure 1(b) is the equivalent circuit diagram of the multi-zero bandpass filter for the Wi-Fi band of the present invention;

[0042] Figure 2 This is a schematic diagram of the overall structure of the dielectric layer, metal layer, and grounding ring of the present invention;

[0043] Figure 3(a) is a schematic diagram of the circuit topology of the multi-zero bandpass filter in the 5G band of the present invention;

[0044] Figure 3(b) is a schematic diagram of the circuit topology of the multi-zero bandpass filter in the WiFi band of the present invention;

[0045] Figure 4 This is a schematic diagram of the stacked structure of the dielectric layer, metal layer and substrate of the present invention;

[0046] Figure 5(a) shows the S-parameter results of the multi-zero bandpass filter of the present invention in the 5G band;

[0047] Figure 5(b) shows the S-parameter results of the multi-zero bandpass filter for the Wi-Fi band of the present invention. Detailed Implementation

[0048] To more clearly illustrate the problems solved by the present invention, the technical solutions adopted, and the beneficial effects, the specific embodiments of the present invention are described below in conjunction with the figures. The preferred embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. All modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be within the protection scope of the present invention.

[0049] Example 1: Multi-zero bandpass filter for 5G bands

[0050] like Figure 2 As shown, the multi-zero high out-of-band rejection bandpass filter based on IPD technology includes a circuit layer 1, a ground ring 2 surrounding the circuit layer 1, a dielectric layer 3, and a substrate.

[0051] The dielectric layer is located on the upper surface of the substrate and is composed of oxide and silicon nitride (SiN); from bottom to top, it includes a first oxide layer, a first silicon nitride layer, a second oxide layer, a second silicon nitride layer, a third oxide layer, and a third silicon nitride layer.

[0052] The metal layer consists of TM2, TV1, TM1, V1, M1, and CAP; TM1 and TM2 are located in the second silicon nitride layer and the third silicon nitride layer, respectively; M1 and CAP are located in the first silicon nitride layer; TV1 is used to connect TM1 and TM2, one V1 is used to connect TM1 and M1, and the other V1 is used to connect TM1 and CAP;

[0053] The circuit layer 1 includes the main circuit and input / output ports.

[0054] As shown in Figure 3(a), the input ports include a first input port pad 4-1, a second input port pad 4-2, and a third input port pad 4-3; the output ports include a first output port pad 4-4, a second output port pad 4-5, and a third output port pad 4-6; the first input port pad 4-1 and the third input port pad 4-3 are input ground ports, the second input port pad 4-2 is a signal input terminal, the first output port pad 4-4 and the third input port pad 4-6 are output ground ports, and the second output port pad 4-5 is a signal output terminal;

[0055] The main circuit shown in Figure 3(a) includes a first parallel capacitor 5, a first series capacitor 6, a first parallel inductor 7, a second parallel capacitor 8, a second parallel inductor 12, a second parallel capacitor 13, a second series capacitor 9, a third parallel capacitor 10, a first series inductor 11, a third series capacitor 14, a fourth parallel capacitor 17, a fourth series inductor 15, and a fourth series capacitor 16. One end of the first series capacitor 6, one end of the first parallel inductor 7, and one end of the first parallel capacitor 5 are connected to the second input port pad 4-2. The other end of the first series capacitor 6 is connected to one end of the second parallel inductor 12 and one end of the second series inductor 9. The other end of the first series inductor 7 is connected to one end of the second parallel capacitor 8. The other end of the second parallel capacitor 8 is grounded. The other end of the first parallel capacitor 5 is grounded. The other end of the second series capacitor 9 is connected to one end of the third parallel capacitor 10, the first series inductor 11, and the third series capacitor 14. The third parallel capacitor 10 is grounded. The other end of the third series capacitor 14 and the first series inductor 11 is connected to one end of the fourth parallel capacitor 17, the fourth series capacitor 16, and the fourth series inductor 15. The fourth parallel capacitor 17 is grounded. The other end of the fourth series capacitor 16 and the other end of the fourth series inductor 15 are connected to the second output port pad 4-5.

[0056] Figure 1(a) is the equivalent circuit diagram of the high out-of-band rejection bandpass filter of the main circuit shown in Figure 3(a);

[0057] The first parallel capacitor 5 is equivalent to C2, the first series capacitor 6 is equivalent to C1, the second parallel capacitor 8 is equivalent to C3, the second parallel capacitor 13 is equivalent to C4, the second series capacitor 9 is equivalent to C5, the third parallel capacitor 10 is equivalent to C6, the third series capacitor 14 is equivalent to C7, the fourth parallel capacitor 17 is equivalent to C8, the fourth series capacitor 16 is equivalent to C9, the first parallel inductor 7 is equivalent to L1, the second parallel inductor 12 is equivalent to L2, the first series inductor 11 is equivalent to L3, and the fourth series inductor 15 is equivalent to L4.

[0058] As shown in Figure 1(a), the working principle of this circuit is as follows: a resonant circuit structure is formed by capacitor C1, inductor L1, and capacitor C3; a resonant circuit structure is also formed by capacitor C5, inductor L2, and capacitor C4. These two resonant circuit structures form a high-pass filter, which forms two zeros at low frequencies. As shown in Figure 1(a), a resonant circuit structure is formed by capacitor C6, inductor L3, and capacitor C7; a resonant circuit structure is also formed by capacitor C9, inductor L4, and capacitor C8. These two resonant circuit structures form a low-pass filter, which forms two zeros at high frequencies. The high-pass filter and the low-pass filter are cascaded to form a bandpass filter with high out-of-band rejection. Capacitor C2 generates an infinite zero at high frequencies, which suppresses the high frequencies of the bandpass filter.

[0059] As shown in Figure 5(a), the insertion loss of the 5G bandpass filter in this embodiment is relatively small, about 2dB; the return loss in the passband is about -20dB; there are two zeros each at high and low frequencies, which suppresses higher harmonics, and the out-of-band suppression of low and high frequencies is good.

[0060] Example 2: Multi-zero bandpass filter for Wi-Fi band

[0061] like Figure 2 As shown, the multi-zero high out-of-band rejection bandpass filter based on IPD technology includes a circuit layer 1, a ground ring 2 surrounding the circuit layer 1, a dielectric layer 3, and a substrate.

[0062] The dielectric layer is located on the upper surface of the substrate and is composed of oxide and silicon nitride (SiN); from bottom to top, it includes a first oxide layer, a first silicon nitride layer, a second oxide layer, a second silicon nitride layer, a third oxide layer, and a third silicon nitride layer.

[0063] The metal layer consists of TM2, TV1, TM1, V1, M1, and CAP; TM1 and TM2 are located in the second silicon nitride layer and the third silicon nitride layer, respectively; M1 and CAP are located in the first silicon nitride layer; TV1 is used to connect TM1 and TM2, one V1 is used to connect TM1 and M1, and the other V1 is used to connect TM1 and CAP;

[0064] The circuit layer 1 includes the main circuit and input / output ports.

[0065] As shown in Figure 3(b), the input ports include a first input port pad 4-1, a second input port pad 4-2, and a third input port pad 4-3; the output ports include a first output port pad 4-4, a second output port pad 4-5, and a third output port pad 4-6; the first input port pad 4-1 and the third input port pad 4-3 are input ground ports, the second input port pad 4-2 is a signal input terminal, the first output port pad 4-4 and the third input port pad 4-6 are output ground ports, and the second output port pad 4-5 is a signal output terminal;

[0066] The main circuit shown in Figure 3(b) includes a first parallel capacitor 5, a first series capacitor 6, a first parallel inductor 7, a second parallel capacitor 8, a second parallel inductor 12, a second parallel capacitor 13, a second series capacitor 9, a first series inductor 11, a third series capacitor 14, a fourth parallel capacitor 17, a fourth series inductor 15, and a fourth series capacitor 16. One end of the first series capacitor 6, one end of the first parallel inductor 7, and one end of the first parallel capacitor 5 are connected to the second input port pad 4-2. The other end of the first series capacitor 6 is connected to one end of the second parallel inductor 12 and one end of the second series inductor 9. The other end of the first series inductor 7 is connected to one end of the second parallel capacitor 8. The other end of the second parallel capacitor 8 is grounded. The other end of the first parallel capacitor 5 is grounded. The other end of the second series capacitor 9 is connected to one end of the first series inductor 11 and one end of the third series capacitor 14. The other end of the third series capacitor 14 and the first series inductor 11 are connected to one end of the fourth parallel capacitor 17, the fourth series capacitor 16, and the fourth series inductor 15. The fourth parallel capacitor 17 is grounded. The other ends of the fourth series capacitor 16 and the fourth series inductor 15 are connected to the second output port pad 4-5.

[0067] Figure 1(b) is the equivalent circuit diagram of the high out-of-band rejection bandpass filter of the main circuit shown in Figure 3(b);

[0068] The first parallel capacitor 5 is equivalent to C2, the first series capacitor 6 is equivalent to C1, the second parallel capacitor 8 is equivalent to C3, the second parallel capacitor 13 is equivalent to C4, the second series capacitor 9 is equivalent to C5, the third series capacitor 14 is equivalent to C7, the fourth parallel capacitor 17 is equivalent to C8, the fourth series capacitor 16 is equivalent to C8, the first parallel inductor 7 is equivalent to L1, the second parallel inductor 12 is equivalent to L2, the first series inductor 11 is equivalent to L3, and the fourth series inductor 15 is equivalent to L4.

[0069] As shown in Figure 1(b), the working principle of this circuit is as follows: a resonant circuit structure is formed by capacitor C1, inductor L1, and capacitor C3, and a resonant circuit structure is also formed by capacitor C5, inductor L2, and capacitor C4. These two resonant circuit structures form a high-pass filter, which forms two zeros at low frequencies. As shown in Figure (a), a resonant circuit structure is formed by capacitor L3, inductor L3, and capacitor C7, and a resonant circuit structure is also formed by capacitor C9, inductor L4, and capacitor C8. These two resonant circuit structures form a low-pass filter, which forms two zeros at low frequencies. The high-pass filter and the low-pass filter are cascaded to form a bandpass filter with high out-of-band rejection. Capacitor C2 generates an infinite zero at high frequencies, which suppresses the high frequencies of the bandpass filter.

[0070] As shown in Figure 5(b), the insertion loss of the multi-zero bandpass filter in the Wi-Fi band of this embodiment is relatively small, about 1.66dB; the return loss in the passband is about -20dB; there are two zeros each for high and low frequencies, which suppresses higher harmonics, and the out-of-band suppression of low and high frequencies is good.

[0071] The above embodiments are not intended to limit the present invention, and the present invention is not limited to the above embodiments. Any embodiment that meets the requirements of the present invention is within the protection scope of the present invention.

Claims

1. A bandpass filter with high out-of-band rejection and multiple zeros based on IPD technology, comprising: The main circuit includes input and output ports. The input ports include a first input port pad (4-1), a second input port pad (4-2), and a third input port pad (4-3). The output ports include a first output port pad (4-4), a second output port pad (4-5), and a third output port pad (4-6). The first input port pad (4-1) and the third input port pad (4-3) are input grounding ports, the second input port pad (4-2) is a signal input terminal, the first output port pad (4-4) and the third output port pad (4-6) are output grounding ports, and the second output port pad (4-5) is a signal output terminal. Its characteristic is that: The main circuit includes a first parallel capacitor (5), a first series capacitor (6), a first parallel inductor (7), a second parallel capacitor (8), a second parallel inductor (12), a second parallel capacitor (13), a second series capacitor (9), a first series inductor (11), a third series capacitor (14), a fourth parallel capacitor (17), a fourth series inductor (15), and a fourth series capacitor (16). One end of the first series capacitor (6), one end of the first parallel inductor (7), and one end of the first parallel capacitor (5) are connected to the second input port pad (4-2). The other end of the first series capacitor (6) is connected to one end of the second parallel inductor (12) and one end of the second series capacitor (9). The other end of the first series inductor (7) is connected to one end of the second parallel capacitor (8). The other end of the second parallel capacitor (8) is grounded, the other end of the first parallel capacitor (5) is grounded, the other end of the second series capacitor (9) is connected to one end of the first series inductor (11) and one end of the third series capacitor (14), the other end of the third series capacitor (14) and the other end of the first series inductor (11) are connected to one end of the fourth parallel capacitor (17), one end of the fourth series capacitor (16) and one end of the fourth series inductor (15), the other end of the fourth parallel capacitor (17) is grounded, the other end of the fourth series capacitor (16) and the other end of the fourth series inductor (15) are connected to the second output port pad (4-5); the other end of the second parallel inductor (12) is connected to one end of the second parallel capacitor (13), and the other end of the second parallel capacitor (13) is grounded; A resonant circuit structure is formed by the first series capacitor (6), the first parallel inductor (7), and the second parallel capacitor (8). Another resonant circuit structure is formed by the second series capacitor (9), the second parallel inductor (12), and the second parallel capacitor (13). These two resonant circuit structures form a high-pass filter, which forms two zeros at low frequencies. A resonant circuit structure is formed by the first series inductor (11) and the third series capacitor (14). Another resonant circuit structure is formed by the fourth series capacitor (16), the fourth series inductor (15), and the fourth parallel capacitor (17). These two resonant circuit structures form a low-pass filter, which forms two zeros at high frequencies. The above high-pass filter and low-pass filter are cascaded to form a bandpass filter with high out-of-band rejection. The first parallel capacitor (5) generates an infinite zero at high frequencies, which suppresses the high frequencies of the bandpass filter.

2. A bandpass filter with high out-of-band rejection and multiple zeros based on IPD technology according to claim 1, characterized in that... The main circuit also includes a high-frequency suppression module; one end of the high-frequency suppression module is connected to the other end of the second series capacitor (9) and one end of the first series inductor (11), and the other end is grounded.

3. A bandpass filter with high out-of-band rejection and multiple zeros based on IPD technology according to claim 2, characterized in that... The high-frequency suppression module includes a third parallel capacitor (10).

4. A bandpass filter with high out-of-band rejection based on IPD technology according to claim 1, characterized in that... The second parallel inductor (12) and the first series inductor (11) are octagonal inductors.

5. A bandpass filter with high out-of-band rejection based on IPD technology according to claim 1, characterized in that... The first parallel inductor (7) adopts an octagonal gradient inductor.

6. A bandpass filter with high out-of-band rejection and multiple zeros based on IPD technology according to claim 5, characterized in that... The linewidth and line spacing of the octagonal gradient inductor gradually narrow from the outside to the inside.

7. A bandpass filter with high out-of-band rejection based on IPD technology according to claim 1, characterized in that... The shapes of the second parallel inductor (12), the first series inductor (11), and the first parallel inductor (7) include circular, elliptical, spiral, rectangular, hexagonal, or octagonal.

8. A bandpass filter with high out-of-band rejection and multiple zeros based on IPD technology according to claim 1, characterized in that... The first parallel capacitor (5), the first series capacitor (6), the second parallel capacitor (8), the second parallel capacitor (13), the second series capacitor (9), the third parallel capacitor (10), the third series capacitor (14), the fourth parallel capacitor (17), and the fourth series capacitor (16) are either planar capacitors or surface-mount capacitors.

9. The design method of the multi-zero high out-of-band rejection bandpass filter according to any one of claims 1-8, specifically: Step 1: Construct a high-pass filter 1-1 According to the design specifications for low-frequency out-of-band suppression, a first resonant circuit is constructed consisting of a first parallel inductor (7), a second parallel capacitor (8), and a first series capacitor (6). A second resonant circuit is constructed consisting of a second series capacitor (9), a second parallel inductor (12), and a second parallel capacitor (13). These two resonant circuits form a high-pass filter, creating two zeros at low frequencies, thereby achieving the low-frequency specifications. The high-pass filter transfer matrix is ​​then: Equation (1) in , , , w is the zero frequency of the filter; Equivalent circuit of a two-port network, parameter transformation of S-parameters to the ABCD matrix: Equation (2) Equation (3) From formula (1), we get AD - BC = 1; Therefore S 12 = S 21 Finding the zero-point frequency position is S. 12 =0 frequency, where Z0=50; Substituting formula (1) into formula (2) yielded two transmission zeros, resulting in... , Therefore, it can be deduced that the movement of the zero point at w1 is related to the first parallel inductor (7) and the first series capacitor (6): when the first parallel inductor (7) and the first series capacitor (6) increase, the zero point at the high frequency will move to the low frequency. The movement of the zero point at w2 is related to the second parallel inductor (12) and the second parallel capacitor (8): when the second parallel inductor (12) and the second parallel capacitor (8) increase, the zero point at the high frequency will move to the low frequency. 1-2 By optimizing the high-pass filter, out-of-band suppression of the two zeros at low frequencies is achieved; Step 2: Construct a low-pass filter 2-1 According to the design specifications for high-frequency out-of-band suppression, a third resonant circuit is constructed, consisting of a third parallel capacitor (10), a first series inductor (11), and a third series capacitor (14). A fourth resonant circuit is constructed, consisting of a fourth series capacitor (16), a fourth series inductor (15), and a fourth parallel capacitor (17). These two resonant circuit structures form a low-pass filter, creating two zeros at high frequencies, thereby achieving the low-frequency specifications. The low-pass filter transfer matrix is ​​then: Equation (4) in , , , w represents the added low-frequency zero; Substituting formula (4) into formula (2) makes S 12 =0, solving for two transmission zeros yielded the following result. , Therefore, it can be deduced that the movement of the zero point at w3 is related to the first series inductor (11) and the third series capacitor (14): when the first series inductor (11) and the third series capacitor (14) increase, the zero point at the high frequency will move to the low frequency. The movement of the zero point at w4 is related to the fourth series inductor (15) and the fourth parallel capacitor (17): when the fourth series inductor (15) and the fourth parallel capacitor (17) increase, the zero point at the high frequency will move to the low frequency. 2-2 By optimizing the low-pass filter, out-of-band suppression of the two zeros at high frequencies is achieved; Step 3: Cascade the above high-pass filter and low-pass filter to form a bandpass filter with high out-of-band rejection; then connect a first parallel capacitor (5) to generate an infinite zero at high frequencies, which suppresses the high frequencies of the bandpass filter. Finally, integrate the circuit and optimize it. By optimizing the parameters, the circuit can reach the optimal state.

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