A single drive type multi-power switch series circuit topology capable of dynamic voltage equalization

Abstract

The application belongs to the technical field of voltage equalization control of power switches, and particularly relates to a single-drive type multi-power switch series circuit topology capable of dynamic voltage equalization. i , n power switches M i in series, n first Zener diodes Z i1 , and n second Zener diodes Z i2 , a main active clamp dynamic voltage equalization circuit is connected in parallel between the gate G and the drain D of the power switch M i , the main active clamp dynamic voltage equalization circuit comprises a third Zener diode D zi , a current-limiting resistor R gdi , and a power diode D i connected in series; and an RCD buffer circuit is connected in parallel between the drain D and the source S of the power switch M i . The application can effectively realize dynamic voltage equalization of a multi-power semiconductor device series circuit, avoid overvoltage problems that may damage devices in the active clamp voltage equalization scheme, and avoid the use of an excessively large RCD buffer circuit under the condition of excessively high power.

Description

Technical Field

[0001] This invention belongs to the field of voltage equalization control technology for power switches, specifically a single-drive multi-power switch series circuit topology capable of dynamic voltage equalization. Background Technology

[0002] For the application of power switching devices in high-voltage fields, a relatively reliable solution is to connect multiple devices directly in series to achieve higher voltage levels. However, voltage equalization is a pressing issue in multi-power switching device series technology, typically caused by differences in device parameters, external circuit parameters (such as drive signal delay), and operating points (including voltage, load current, and junction temperature). Voltage equalization encompasses two aspects: static voltage equalization and dynamic voltage equalization. Static voltage equalization can generally be achieved by connecting equalizing resistors in series across each device, while dynamic voltage equalization is more complex. Dynamic voltage equalization, addressing different factors affecting dynamic voltage equalization, can be categorized into load-side voltage equalization, gate-to-gate (G) signal voltage equalization, voltage clamping, and control methods.

[0003] Compared to multi-drive series power switching circuits, single-drive circuits have the advantages of simplicity, reliability, and low cost. For example, the topology proposed by Ren Yu... Figure 1 As shown, a capacitor drives the switch of the next-stage device; this topology can be classified as a capacitively coupled structure. Another topology where devices are directly connected in series uses an auxiliary source to drive the higher-stage MOSFET to conduct, such as... Figure 2 As shown. In "A CompactSeries-Connected SiCMOSFETs Module and Its Application in High Voltage Nanosecond Pulse Generator", Lei Pang proposed three different capacitive coupling topologies. Regardless of the single-drive circuit, dynamic voltage equalization is an important problem that needs to be solved.

[0004] In the selection of dynamic voltage equalization schemes, since the improvement of the load-side voltage equalization method cannot overcome the disadvantages such as large size and serious loss, the load-side voltage equalization method can only be used as an auxiliary measure in combination with other schemes. Summary of the Invention

[0005] The present invention aims to solve the technical problems of large size and severe loss in the improvement of existing load-side voltage equalization methods, and provides a single-drive multi-power switch series circuit topology that can dynamically equalize voltage.

[0006] The technical means adopted by this invention to solve its technical problem is: a single-drive multi-power switch series circuit topology capable of dynamic voltage equalization, wherein the single-drive multi-power switch series circuit includes n-1 coupling capacitors C1~C1. n-1n power switches M1~M in series n n first Zener diodes Z 11 ~Z n1 and n second Zener diodes Z 12 ~Z n2 The gate G of power switch M1 is connected to an external drive signal, and the source S of power switch M1 is grounded. i The drain D of (i=1,2,3…,n-1) is connected to the power switch M. i+1 The source S of power switch M1 (i=1,2,3…,n-1) is connected in parallel; coupling capacitor C1 is connected in parallel between the source S of power switch M1 and the gate G of power switch M2, coupling capacitor C2 is connected in parallel between the source S of power switch M2 and the gate G of power switch M3, and so on, coupling capacitor C... n-1 Parallel to power switch M n-1 The source S and power switch M n Between the gates G and Z; the first Zener diode Z 11 Second Zener diode Z 12 After being connected in series, it is connected in parallel between the gate G and source S of the power switch M1, and the first Zener diode Z 21 Second Zener diode Z 22 After being connected in series, they are connected in parallel between the gate G and source S of power switch M2, and so on, with the first Zener diode Z... n1 Second Zener diode Z n2 After being connected in series, it is then connected in parallel to the power switch M. n Between the gate G and the source S, each power switch M1~M n An active clamping dynamic voltage equalization circuit is connected in parallel between the gate G and the drain D. The active clamping dynamic voltage equalization circuit includes a third Zener diode D connected in series. z Current limiting resistor R gd and power diode D; each power switch M1~M n An RCD snubber circuit is connected in parallel between the drain (D) and source (S). The RCD snubber circuit includes a diode D connected in series. d and capacitor C d diode D d A resistor R is connected in parallel across its two ends. d .

[0007] Preferably, it also includes n-1 static voltage equalizing resistors R1~R n-1 Static equalizing resistors R1~R n-1 They are connected in parallel to coupling capacitors C1~C respectively. n-1 The two ends;

[0008] The beneficial effects of this invention are: it can effectively achieve dynamic voltage equalization of multiple power semiconductor devices in series circuits; it can achieve dynamic voltage equalization of series devices without using overly complex control algorithms and strategies; it avoids the overvoltage problem that may damage devices in active clamping voltage equalization schemes; in the case of excessively high power, it is unnecessary to use an excessively large RCD buffer circuit; and it enables the entire single drive circuit to achieve good voltage equalization using only passive devices. Attached Figure Description

[0009] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a capacitively coupled single-drive circuit in the background art of this invention.

[0011] Figure 2 This is a schematic diagram of a single-drive circuit with an auxiliary source in the background art of this invention.

[0012] Figure 3 This is the topology of the series circuit of the single-drive multi-power switch described in this invention.

[0013] Figure 4 for Figure 3 The circuit topology after adding a static voltage equalizing resistor.

[0014] Figure 5 for Figure 4 The circuit topology after adding a hybrid dynamic voltage equalization scheme. Detailed Implementation

[0015] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] In the description of this invention, it should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0017] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0018] One embodiment of the present invention is a single-drive multi-power switch series circuit topology capable of dynamic voltage equalization, wherein the single-drive multi-power switch series circuit includes n-1 coupling capacitors C i (i=1,2,3…n-1), n ​​power switches M connected in series i (i=1,2,3…n), n first Zener diodes Z i1 (i=1,2,3…n) and n second Zener diodes Z i2 (i=1,2,3…n), the gate G of power switch M1 is connected to the external drive signal, the source S of power switch M1 is grounded, and power switch M… i The drain D of (i=1,2,3…,n-1) is connected to the power switch M. i+1 The source S of (i=1,2,3…,n-1) is specifically such that the drain D of power switch M1 is connected to the source S of power switch M2, adjacent power switches are connected in series through their drain D and source S, and so on, power switches M n-1 The drain D is connected to the power switch M. n The source S; coupling capacitor C i Parallel to power switch M i The source S and power switch M i+1 Between the gates G and Z; the first Zener diode Z i1 Second Zener diode Z i2 After being connected in series, it is then connected in parallel to the power switch M. i Between the gate G and the source S, each power switch M i An active clamping dynamic voltage equalization circuit is connected in parallel between the gate G and drain D of each of the (i=1,2,3…n) terminals. The active clamping dynamic voltage equalization circuit includes a third Zener diode D connected in series. zi (i=1,2,3…n), current-limiting resistor R gdi (i=1,2,3…n) and power diode D i (i=1,2,3…n); each power switch M i An RCD snubber circuit is connected in parallel between the drain D and source S of (i=1,2,3…n). The RCD snubber circuit includes diodes D connected in series. di(i=1,2,3…n) and capacitor C di (i=1,2,3…n), each diode D di A resistor R is connected in parallel across the two ends of (i=1,2,3…n). di (i=1,2,3…n).

[0019] Among them, such as Figure 3 As shown, except for the bottom power switch M1, each of the remaining power switches is triggered by a coupling capacitor connected in parallel between the source S of that power switch and the gate G of the next lower power switch. For example, power switch M2 is triggered by a coupling capacitor C1 connected in parallel between the source S of that power switch M2 and the gate G of the next lower power switch M1. The triggering method of the series circuit of single-drive multi-power switches is sequential triggering. After the first-stage power switch M1 is turned on, a trigger signal is sent to the second-stage power switch M2 through the coupling capacitor C1, causing the second-stage power switch M2 to turn on. The third-stage power switch M3 is triggered by the coupling capacitor C2 after the second-stage power switch M2 is turned on, and so on. Higher-level power switches are triggered by the power switch one level below it being turned on through the corresponding coupling capacitor.

[0020] Each power switch is equipped with a first Zener diode and a second Zener diode, wherein the first Zener diode Z i1 (i=1,2,3…n) can clamp the forward drive voltage of the i-th stage power switch to a reasonable range, preventing excessive voltage from damaging the i-th stage power switch and causing the entire series circuit to malfunction; the second Zener diode Z i2 (i=1,2,3…n) is to prevent the power switch from being damaged by excessively low turn-off negative voltage of the i-th stage power switch. Negative voltage turn-off is intended to ensure reliable turn-off of the power switch, but excessively low turn-off negative voltage can also damage the power switch. Therefore, a second Zener diode Z is required. i2 Specifically, as will be understood by those skilled in the art, the first Zener diode Z 11 Second Zener diode Z 12 After being connected in series, it is connected in parallel between the gate G and source S of the power switch M1, and the first Zener diode Z 21 Second Zener diode Z 22 After being connected in series, they are connected in parallel between the gate G and source S of power switch M2, and so on, with the first Zener diode Z... n1 Second Zener diode Z n2 After being connected in series, it is then connected in parallel to the power switch M. n Between the gate G and the source S.

[0021] like Figure 5As shown, the hybrid dynamic voltage equalization scheme consists of an active clamping dynamic voltage equalization circuit and an RCD buffer circuit. The active clamping dynamic voltage equalization circuit is introduced as a dynamic voltage equalization scheme on the drive side, and the RCD buffer circuit is introduced as a dynamic voltage equalization scheme on the load side.

[0022] In the active clamping dynamic voltage equalization circuit, a third Zener diode D is used. zi A current-limiting resistor R gdi and a power diode D i It is connected in series to the corresponding power switch M. i The drain (D) and gate (G) terminals. Third Zener diode D. zi The sum of the avalanche voltages equals the drain-gate clamping voltage. When the drain-source voltage reaches the clamping voltage, the third Zener diode D... zi Breakdown, active clamping dynamic voltage equalization circuit to power switch M i The gate G is injected with current, the magnitude of which can be determined by the current-limiting resistor R. gdi Adjustments are made to suppress further increases in the drain-gate voltage. Power switches M in each stage are adjusted accordingly. i An active clamping dynamic voltage equalization circuit is introduced to achieve voltage equalization; the third Zener diode D... zi It can be constructed using multiple Zener diodes connected in series. The active clamping dynamic voltage equalization circuit has excellent static voltage equalization performance, but its dynamic voltage equalization performance is limited. Specifically, when using only the active clamping dynamic voltage equalization scheme after introducing a static voltage equalization resistor, although the static voltage equalization effect is good, there is still a significant overvoltage phenomenon across the power switch during turn-on and turn-off, which could potentially damage the power switch. This makes it difficult to use the active clamping dynamic voltage equalization circuit as a standalone dynamic voltage equalization scheme; therefore, an RCD snubber circuit is also introduced. Specifically, an active clamping dynamic voltage equalization circuit is connected in parallel between the gate G and drain D of the power switch M1. The active clamping dynamic voltage equalization circuit includes a third Zener diode D connected in series. z1 Current limiting resistor R gd1 Both the power diode D1 and the power switch M2 have an active clamping dynamic voltage equalization circuit connected in parallel between their gate G and drain D. This active clamping dynamic voltage equalization circuit includes a third Zener diode D connected in series. z2 Current limiting resistor R gd2 And power diode D2; and so on, power switch M n An active clamping dynamic voltage equalization circuit is connected in parallel between the gate G and the drain D. The active clamping dynamic voltage equalization circuit includes a third Zener diode D connected in series. zn Current limiting resistor R gdn and power diode D n .

[0023] The RCD snubber circuit achieves excellent dynamic voltage equalization. It employs two dynamic voltage equalization schemes: combining an active clamping dynamic voltage equalization circuit with the RCD snubber circuit as a novel hybrid voltage equalization solution. This not only provides better voltage equalization than simply adding a static voltage equalization resistor, but also outperforms using an active clamping circuit alone. Specifically, an RCD snubber circuit is connected in parallel between the drain (D) and source (S) of the power switch M1. The RCD snubber circuit includes a diode D connected in series. d1 and capacitor C d1 diode D d1 A resistor R is connected in parallel across its two ends. d1 An RCD snubber circuit is connected in parallel between the drain (D) and source (S) of power switch M2. The RCD snubber circuit includes a diode D connected in series. d2 and capacitor C d2 diode D d2 A resistor R is connected in parallel across its two ends. d2 Similarly, power switch M n An RCD snubber circuit is connected in parallel between the drain (D) and source (S). The RCD snubber circuit includes a diode D connected in series. dn and capacitor C dn diode D dn A resistor R is connected in parallel across its two ends. dn .

[0024] Furthermore, as a specific implementation of this embodiment, it also includes n-1 static voltage equalization resistors R. i (i=1,2,3…n-1), static equalizing resistor R i Connected in parallel to coupling capacitor C i The two ends.

[0025] In this approach, a static voltage equalization resistor R is added to the hybrid dynamic voltage equalization scheme. i Add static voltage equalization resistor R i ,like Figure 4 As shown, this serves two purposes: static voltage equalization and ensuring reliable gate G turn-off of the corresponding power switch.

[0026] Among them, power switch M i It can be any normally closed power switching device, including MOSFETs and IGBTs. If the voltage rating of the series-connected SiC MOSFETs is relatively high, the actively clamped third Zener diode D... zi This can be achieved by connecting multiple Zener diodes in series. Specifically, the capacitor C... di The value of R is not large. di A larger value can be selected to achieve low loss.

[0027] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A single-drive multi-power switch series circuit topology capable of dynamic voltage equalization, wherein the series circuit of the single-drive multi-power switch includes n-1 coupling capacitors C i (i=1,2,3…n-1), n ​​power switches M connected in series i (i=1,2,3…n), n first Zener diodes Z i1 (i=1,2,3…n) and n second Zener diodes Z i2 (i=1,2,3…n), the gate G of power switch M1 is connected to the external drive signal, the source S of power switch M1 is grounded, and power switch M… i The drain D of (i=1,2,3…,n-1) is connected to the power switch M. i+1 The source S (i=1,2,3…,n-1); the coupling capacitor C i Parallel to power switch M i The source S and power switch M i+1 Between the gates G and Z; the first Zener diode Z i1 Second Zener diode Z i2 After being connected in series, it is then connected in parallel to the power switch M. i Between the gate G and the source S, characterized in that, Each power switch M i An active clamping dynamic voltage equalization circuit is connected in parallel between the gate G and the drain D. The active clamping dynamic voltage equalization circuit includes a third Zener diode D connected in series. zi (i=1,2,3…n), current-limiting resistor R gdi (i=1,2,3…n) and power diode D i (i=1,2,3…n); each power switch M i An RCD snubber circuit is connected in parallel between the drain (D) and source (S). The RCD snubber circuit includes a diode D connected in series. di (i=1,2,3…n) and capacitor C di (i=1,2,3…n), each diode D di Resistors R are connected in parallel at both ends. di (i=1,2,3…n).

2. The single-drive multi-power switch series circuit topology capable of dynamic voltage equalization according to claim 1, characterized in that, It also includes n-1 static voltage equalization resistors R i (i=1,2,3…n-1), static equalizing resistor R i Connected in parallel to coupling capacitor C i The two ends.

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