Switching strategy and control logic for a differential capacitance analog-to-digital conversion array

Abstract

The application discloses a switch strategy and logic control implementation of a differential capacitance type analog-digital conversion array, wherein high 3-bit binary weight capacitors are split into 7 equal weight capacitors under the premise of ensuring total weight, the switch strategy enables the capacitance type analog-digital conversion array to realize thermometer code control of the high 3-bit weight capacitors under the framework based on the common-mode voltage, thus, the influence of unit capacitor mismatch in the binary weight capacitor array can be reduced while compatible with lower plate sampling and minimizing the capacitor array area and dynamic energy consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more specifically, to a switching strategy and control logic for a differential capacitor analog-to-digital converter array. Background Technology

[0002] The successive approximation register (SAR) is one of the earliest architectures for implementing analog-to-digital converters (ADCs). It is primarily used in the design of medium-precision, medium-speed ADCs, offering advantages such as low power consumption, compact structure, low conversion delay, and benefiting from advancements in CMOS technology. The charge-redistribution-based capacitive analog-to-digital converter (CDAC) array is its core module, integrating sample-and-hold and analog-to-digital conversion functions. It features zero static power consumption and is a key module for achieving high linearity performance in ADCs. Under the control of the successive approximation register, the output voltage of the CDAC array converges to a preset value (or 0 for a differential structure). The final state of the successive approximation register is the quantization result of the ADC. Generally, under the control of the successive approximation register, the amplitude of the CDAC array output voltage changes according to a binary weighting pattern; this is known as a binary-weighted CDAC array. The lower plate switching strategy of this invention is specifically designed for binary-weighted CDAC arrays.

[0003] From a sampling perspective, CDAC arrays can be divided into two structures: bottom-plate sampling and top-plate sampling. Bottom-plate sampling offers advantages such as low distortion and near-insensitivity to charge injection in the sampling switch channel, making it easier to achieve higher dynamic linearity. However, it requires an additional clock cycle to transfer the sampled input voltage to the top plate through charge redistribution. While top-plate sampling is more affected by charge injection in the sampling switch channel, it allows direct comparison of the input signal after sampling, meaning the comparison can be performed before setting the register, thus saving half the capacitor area. For differential structures, if the bottom plate is set to the common-mode voltage after sampling, the capacitor area can also be halved, while the average dynamic power consumption of the capacitor array is minimized.

[0004] However, the actual weight of each weight capacitor constituting the CDAC array is affected by random errors, and the higher the weight, the greater the impact of random errors. The difference between the output voltages corresponding to the final state of the register (i.e., the output of the SAR ADC) equaling the two adjacent codewords 011…111 and 100…000 usually reaches its maximum value. Therefore, the maximum value of the SAR ADC differential nonlinearity (DNL) occurs here.

[0005] To mitigate the impact of random capacitor errors, three methods can be adopted: (1) Use an additional calibration capacitor array to calibrate the capacitance of each weight capacitor in sequence. This requires a front-end operation and an additional register to store the calibration code. It can only work normally after calibration is completed. In practice, only the high 3 bits of the weight are usually calibrated to obtain a better balance; (2) Split the high-bit binary weight capacitor into smaller equivalent capacitors controlled by thermometer codes (for example, split the high 3 bits of binary weight capacitor into 7 equivalent capacitors). In this way, the capacitance change corresponding to adjacent binary codes is greatly reduced, and thus its impact from random errors is also greatly reduced; (3) Use dynamic element matching, random jitter and other techniques to average out the random deviation of the weight capacitor. This type of method based on digital algorithms weakens the advantages of real-time conversion of SAR architecture and has limited application scenarios.

[0006] Traditional CDAC arrays often employ the second method for lower plate switching, where the high 3 bits of the register state (binary code) are used in conjunction with the strategy of switching the lower plate of the seven equally weighted capacitors. Figure 1 As shown ('1' indicates connection to the reference voltage, '0' indicates connection to ground). Figure 2 The control logic circuit for a binary code-thermometer code decoder is presented. All gate delays are two-stage gates, allowing for low delays in the switching control logic. However, this strategy requires setting the bit first and then comparing it to determine whether to retain the set value, thus doubling the required unit capacitor. This not only means doubling the capacitor area but also that the reference voltage buffer needs to consume more power to achieve sufficient drive capability.

[0007] Both the monotonic switching strategy based on upper plate sampling and the switching strategy based on common mode voltage can compare first and then set, thus achieving a reduction of half the required unit capacitor. However, the circuit implementation of suppressing random errors using method (2) is relatively complex. Generally, the first or third method is used, both of which have the disadvantage of poor real-time performance.

[0008] This invention proposes a novel switching strategy for the lower plate of a differential capacitor-type CDAC array, based on a common-mode voltage-based switching strategy. This strategy allows the lower plate to sample, thus exhibiting excellent sampling linearity. Furthermore, the lower plate is set to the common-mode voltage after sampling, requiring only half the unit capacitance of the conventional approach. Crucially, it significantly reduces the maximum capacitance change, similar to a binary-thermometric decoder, thereby substantially improving the ADC's DNL without the need for additional calibration. Summary of the Invention

[0009] To address the aforementioned technical problems, this invention proposes a switching strategy and control logic for a differential capacitor analog-to-digital converter array.

[0010] The first aspect of the present invention provides a switching strategy for a differential capacitor analog-to-digital converter array, which is used to reduce the impact of unit capacitance mismatch in a binary weighted capacitor array while being compatible with plate sampling and minimizing capacitor area and dynamic energy consumption.

[0011] The high 3 bits of binary weighted capacitors are split into 7 equal-weighted capacitors while keeping the total weight unchanged. The lower plates of the 7 equal-weighted capacitors are denoted as T7-T1 respectively.

[0012] The logic control signals for implementing this switching strategy include: sampling signal ENb, shift register Q, and successive approximation register D. The logic control circuits of the lower plates of the capacitor-type analog-to-digital converter array on both sides of the differential are the same. The positive terminal is controlled by the in-phase state of the successive approximation register D, and the negative terminal is controlled by the out-of-phase state of the successive approximation register D.

[0013] The lower plate switching strategy after splitting the high 3-bit weighted capacitor into 7 equally weighted capacitors is as follows: Figure 3 As shown, the switching strategy of the present invention specifically includes the following steps:

[0014] When sampling (ENb=0), the lower plate of all weighted capacitors is connected to the sampling signal Vin, and the upper plate is connected to the common-mode voltage VCM.

[0015] The shift register Q[i] (i = 11-0) is reset to 0;

[0016] After sampling ends (ENb is pulled high), the lower plate of all weighted capacitors is connected to the common-mode voltage VCM, and the sampled differential voltage is transferred to the upper plate of the capacitor. The highest bit D[n-1] of the successive approximation register is obtained through the comparator.

[0017] Driven by the edge transition after the comparator is established, the highest bit Q[n-1] of the shift register is pulled high;

[0018] If D[n-1]=0, then the lower plates of T7, T6, T5, and T4 should be grounded (GND);

[0019] If D[n-1]=1, then the lower plates of T4, T3, T2, and T1 should be connected to the reference voltage (VREF).

[0020] The above steps cause the differential voltage of the upper plate to increase or decrease by VREF. After the voltage is established, the next comparison is performed. After the comparison is completed, Q[n-2] is pulled high. At the same time, based on the result of D[n-1:n-2], as follows... Figure 3 The potential of the lower plate connection of T7-T1 is determined as shown.

[0021] The above steps cause the differential voltage of the upper plate to increase or decrease by VREF / 2. After the voltage is established, the next comparison is performed. After the comparison is completed, Q[n-3] is pulled high. At the same time, based on the result of D[n-1:n-3], as follows... Figure 3 The potential of the lower plate connection of T7-T1 is determined as shown.

[0022] At this point, the lower plate of T7-T1 should either be connected to ground (GND) or to the reference voltage (VREF);

[0023] Next, following the traditional switching strategy, the lower plate of the corresponding weighted capacitor is switched to the reference voltage (VREF) or ground (GND) according to the value of D[j] (j=n-4:1).

[0024] Finally, based on the result of D[1], the potential of the lower plate of the least significant weighted capacitor (i.e., unit capacitor) is determined. Then, after the establishment is completed, a final comparison is performed to obtain D[0]. At this point, the conversion ends.

[0025] The second aspect of this invention provides a logic control circuit for implementing the above-described switching strategy. The high 3-bit weighted capacitor is split into 7 equally weighted capacitors, and a single-pole four-throw switch connected to its lower plate Ti (i = 1-7) is used as follows: Figure 4 As shown, when G[i] (i = 1-7) is high, switch N1 is turned on; otherwise, it is turned off. When VC[i] (i = 1-7) is high, switch N2 is turned on; otherwise, it is turned off. When VR[i] (i = 1~7) is low, switch N1 is turned on; otherwise, it is turned off.

[0026] The present invention discloses a second technical solution: a control logic circuit for the lower plate of a differential capacitor analog-to-digital converter array, including multiple MOS transistors connected to the lower plates of each weight capacitor, the multiple MOS transistors being connected in parallel, and the multiple MOS transistors including NMOS transistor N1, NMOS transistor N2 and PMOS transistor P1;

[0027] The drains of NMOS transistors N1 and N2 and PMOS transistor P1 are connected together on the lower plate.

[0028] The gate of the NMOS transistor N1 is connected to the control logic G[i], and the source of the NMOS transistor N1 is grounded to GND;

[0029] The gate of the NMOS transistor N2 is connected to the control logic VC[i], and the source of the NMOS transistor N2 is connected to the common-mode voltage VCM;

[0030] The gate of the PMOS transistor P1.

[0031] In a preferred embodiment of the present invention, there are multiple lower electrode plates, denoted as T. i.

[0032] In a preferred embodiment of the present invention, there are 7 lower electrode plates, which are respectively designated as T1, T2, T3, T4, T5, T6, and T7.

[0033] In a preferred embodiment of the present invention, the relationship between the high 3 bits of the successive approximation register and the state of the lower plate connection potential (0 / VREF) of the 7 highest weighted capacitors is a binary code-thermometer code relationship.

[0034] The present invention discloses another technical solution: a control logic for the switching of the lower plate of the seven equally weighted capacitors corresponding to the high 3 weighted capacitors of a differential capacitor type analog-to-digital converter array. The control logic includes control logic G[i], control logic VC[i] and control logic VR[i] (i = 7~1). After sampling, the control logic G[i], control logic VC[i] and control logic VR[i] control the switching of the lower plate of the weighted capacitor in a mutually exclusive manner.

[0035] The technical solution of the present invention has the following advantages compared with the prior art:

[0036] (1) A new lower plate switching strategy is adopted. Compared with the traditional scheme using thermometer code, it can achieve the same goal of reducing the unit capacitance error rate requirement, but the required capacitance area is only half. This invention guarantees the minimum capacitance area and can be switched in real time without additional front-end calibration.

[0037] (2) The switching strategy in this application is used to reduce the impact of unit capacitance mismatch in binary weighted capacitor array while being compatible with lower plate sampling and minimizing capacitor area and dynamic energy consumption. Attached Figure Description

[0038] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, some of the drawings in the following description are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0039] Figure 1 It is the logical truth table of the binary code-thermometer code decoder;

[0040] Figure 2 It is the control logic circuit of a binary code-thermometer code decoder;

[0041] Figure 3 This is the control logic diagram of the lower plate switch of the high 7 bits of the equally weighted capacitor in the switching strategy of this invention embodiment;

[0042] Figure 4 This is a circuit diagram of a single-pole four-throw switch connected to the lower plate of a weighted capacitor in an embodiment of the present invention. Detailed Implementation

[0043] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0044] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0045] Example 1

[0046] See Figure 1-4 As shown, the present invention proposes a control logic circuit for the lower plate of a differential capacitor type analog-to-digital converter array, including multiple MOS transistors connected to the lower plate of each weight capacitor, the multiple MOS transistors being connected in parallel, and the multiple MOS transistors including NMOS transistor N1, NMOS transistor N2 and PMOS transistor P1;

[0047] The drains of NMOS transistors N1 and N2 and PMOS transistor P1 are connected together on the lower plate.

[0048] The gate connection control logic G[i] of NMOS transistor N1, and the source of NMOS transistor N1 is grounded to GND;

[0049] The gate connection control logic VC[i] of NMOS transistor N2, and the source connection common-mode voltage VCM of NMOS transistor N2;

[0050] The gate connection control logic VR[i] of PMOS transistor P1, and the source connection reference voltage VREF of PMOS transistor P1.

[0051] Furthermore, there are multiple lower electrode plates, denoted as T. i There are 7 lower electrode plates, which are respectively designated as T1, T2, T3, T4, T5, T6, and T7.

[0052] Another technical solution proposed in this invention is: a lower plate switching strategy for an analog-to-digital converter array, which is used to reduce the impact of unit capacitance mismatch in the binary weighted capacitor array while being compatible with lower plate sampling and minimizing capacitor area and dynamic energy consumption. The high 3 bits of the binary weighted capacitor are split into 7 equal weighted capacitors controlled by thermometer code, and the lower plates of the 7 equal weighted capacitors are denoted as T7-T1 respectively.

[0053] The input signals of the logic control circuit that implements this switching strategy come from the sampling signal ENb, the shift register Q, and the successive approximation register D. The logic control circuits of the lower plates of the capacitor-type analog-to-digital converter array on both sides of the differential are the same. The positive terminal is controlled by the in-phase state of the successive approximation register, and the negative terminal is controlled by the out-of-phase state of the successive approximation register.

[0054] During phase sampling, the upper plate of the capacitive analog-to-digital converter array is connected to the common-mode voltage VCM, and the lower plate is connected to the input voltage Vin. When sampling ends, the upper plate switch is turned off, and the lower plate switch is turned off shortly thereafter. Since the upper plate has no charge discharge channel, the charge collected in the capacitor array is preserved.

[0055] The switching strategy of the differential capacitor analog-to-digital converter array in this application includes the following steps:

[0056] During sampling, G[i] (i = 1-7) and VC[i] (i = 1-7) are at low level, VR[i] (i = 1-7) is at high level, and the lower plate of all weight capacitors is connected to the input voltage to sample Vin;

[0057] After sampling ends (ENb is pulled high), G[i] (i = 1-7) remains low, VC[i] (i = 1-7) becomes high, and VR[i] (i = 1-7) remains high. At this time, the lower plate of all weighted capacitors is connected to the common-mode voltage VCM, and the sampled differential voltage is transferred to the upper plate of the capacitor. The highest bit D[n-1] of the successive approximation register is obtained through the comparator.

[0058] Driven by the edge transition after the comparator is established, the highest bit Q[n-1] of the shift register is pulled high;

[0059] If D[n-1] = 0, then G[i] (i = 4-7) is connected to a high level and VC[i] (i = 4-7) is connected to a low level, so that the lower plates of T7, T6, T5 and T4 are grounded (GND);

[0060] If D[n-1] = 1, then VR[i] (i = 1-4) is switched to low level, VC[i] (i = 1-4) is switched to low level, so that the lower plate of T4, T3, T2 and T1 is switched to the reference voltage (VREF);

[0061] The above steps cause the differential voltage of the upper plate to increase or decrease by VREF. After the voltage is established, the next comparison is performed. After the comparison is completed, Q[n-2] is pulled high. At the same time, based on the result of D[n-1:n-2], as follows... Figure 3 , Figure 4As shown, the potential of the lower plate of T7-T1 is determined by changing the potential of G[i], VC[i], and VR[i] to control the conduction of the switching circuit.

[0062] The above steps cause the differential voltage of the upper plate to increase or decrease by VREF. After the voltage is established, the next comparison is performed. After the comparison is completed, Q[n-3] is pulled high. At the same time, based on the result of D[n-1:n-3], as follows... Figure 3 , Figure 4 As shown, the potential of the lower plate of T7-T1 is determined by changing the potential of G[i], VC[i], and VR[i] to control the conduction of the switching circuit.

[0063] At this point, all VC[i] (i = 1-7) go low, and the lower plates of T7-T1 are either connected to ground (GND) or to the reference voltage (VREF).

[0064] Next, following the traditional switching strategy, the lower plate of the corresponding weighted capacitor is switched to the reference voltage or grounded according to the value of D[j] (j=n-4:1);

[0065] Finally, based on the result of D[1], the potential of the lower plate of the least significant weighted capacitor (i.e., unit capacitor) is determined. Then, after the establishment is completed, a final comparison is performed to obtain D[0]. At this point, the conversion ends.

[0066] Specifically, taking a 12-bit implementation as an example, the high 3 bits are controlled using a temperature-controlled code, and the weighted capacitors from low to high are C0 and C1 respectively. u 2C u 4C u 8C u 16C u 32C u 64C u 128C u And 7 256C u Under the control of shift register Q[11:0], the first 8 weighted capacitors from low to high are controlled by bits 1-8 (i.e., D[1] to D[8]) of the successive approximation register, and the nominal weights of the 7 higher bits are 256C. u Weighted capacitors (such as) Figure 2 The three bits D[11:9] of the successive approximation register (marked as T7-T1) are controlled by the high three bits D[11:9] of the successive approximation register.

[0067] During sampling (ENb=0), the lower plate of all weighted capacitors is connected to the sampling signal Vin while the upper plate is connected to the common-mode voltage VCM. At the same time, the shift register Q[i] (i=11,10,…,1,0) is reset to 0. After sampling ends (ENb is pulled high), Q[11:1] = 11'b0, so the lower plate of all weighted capacitors is connected to VCM, and the sampled differential voltage is transferred to the upper plate of the capacitor. The highest bit D

[11] of the successive approximation register is obtained through the comparator. At the same time, under the edge change drive after the comparator is established, the highest bit of the shift register is pulled high (i.e., Q11 = 1). If D

[11] = 0, then the lower plates of T7, T6, T5, and T4 are grounded (GND); if D

[11] = 1, then the lower plates of T4, T3, T2, and T1 are connected to the reference voltage (VREF). Under this switching strategy, the differential voltage transferred to the upper plate is either reduced by VREF / 2 or increased by VREF / 2. After the establishment is completed, the next comparison is performed. After the comparison is completed, Q

[10] is pulled high, and the process continues according to the established parameters. Figure 3 The switching strategy shown changes the potential of the lower plate of T7-T1. Until Q[11:9]=3'b111 (the third comparison is completed), the lower plate of T7~T1 is either connected to ground (GND) or to the reference voltage (VREF). The subsequent weighted capacitors are all connected to the reference voltage (VREF) or ground (GND) according to the traditional strategy based on whether D[j] (j=8,7,…,2,1) is 1 or 0. Finally, the least significant weighted capacitor (C) is determined according to the result of D[1]. u The voltage of the lower plate is calculated, and then a final comparison is performed after the conversion is completed to obtain D[0]. The entire conversion is then complete.

[0068] When the conversion of the three highest bits is completed (Q

[11] -Q[9] are all pulled high), the relationship between the state of the lower plate connection potential (0 / VREF) of the three highest bits of the successive approximation register and the seven highest weight capacitors (T7-T1) is the relationship between binary code and thermometer code, that is, only one weight capacitor is different between adjacent bits of D[11:9].

[0069] A control logic for switching the lower plates of seven equally weighted capacitors corresponding to the high 3 weighted capacitors of a differential capacitor-type analog-to-digital converter array. The control logic includes control logic G[i], control logic VC[i], and control logic VR[i] (i = 7~1). After sampling, control logic G[i], control logic VC[i], and control logic VR[i] control the switching of the lower plates of the weighted capacitors in a mutually exclusive manner.

[0070] Specifically, the switching circuit of the lower plate of the seven weighted capacitors in the highest bit is as follows: Figure 4As shown, the lower plate Ti (i = 1-7) of each weighted capacitor is connected to ground (GND) through the first NMOS transistor N1 controlled by G[i], connected to the common-mode voltage (VCM) through the second NMOS transistor N2 controlled by VC[i], and connected to the reference voltage (VREF) through the first PMOS transistor P1 controlled by VR[i]. According to... Figure 3 The control logic for obtaining G[i], VC[i], and VR[i] is as follows:

[0071]

[0072]

[0073] VE[7]=Q 11 ·Q 10 ·Q9·D 11 ·D 10 ·D9·ENb

[0074]

[0075]

[0076] VR[6]=Q 11 ·Q 10 ·D 11 ·D 10 ·ENb

[0077]

[0078]

[0079] VR[5]=Q 11 ·Q 10 ·D 11 ·(D 10 +Q9·D9)·ENb

[0080]

[0081]

[0082]

[0083]

[0084]

[0085]

[0086]

[0087]

[0088]

[0089]

[0090]

[0091]

[0092] Based on the above logic equations, the logic circuits controlling G[i], VC[i], and VR[i] can be obtained.

[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to the above embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0095] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A switching method for a differential capacitor analog-to-digital converter array, characterized in that, The high 3 bits of binary weighted capacitors are split into 7 equal-weighted capacitors while keeping the total weight unchanged. The lower plates of the 7 equal-weighted capacitors are denoted as T7-T1 respectively. The logic control signals for implementing this switching method include: sampling signal ENb, shift register Q, successive approximation register D. The logic control circuits of the lower plates of the capacitive analog-to-digital converter array on both sides of the differential are the same. The positive terminal is controlled by the in-phase state of the successive approximation register D, and the negative terminal is controlled by the out-of-phase state of the successive approximation register D. Includes the following steps: During sampling, ENb=0, and the lower plate of all weighted capacitors is connected to the sampling signal Vin; The upper plate is connected to the common-mode voltage VCM; The shift register Q[n-1:0] is reset to all zeros, where n is the number of binary bits in the capacitive analog-to-digital converter array; After sampling, ENb=1, the lower plate of all weighted capacitors is connected to VCM, the sampled differential voltage is transferred to the upper plate of the capacitor, and the highest bit D[n-1] of the successive approximation register is obtained through the comparator; Driven by the edge change after the comparator is established, the highest bit of the shift register is pulled high Q[n-1]=1; If D[n-1]=0, then the lower plates of T7, T6, T5, and T4 should be grounded to GND; If D[n-1]=1, then the lower plates of T4, T3, T2, and T1 should be connected to the reference voltage VREF. The above switching method causes the differential voltage of the upper plate to increase or decrease by VREF / 2. After the voltage is established, the next comparison is performed. After the comparison is completed, Q[n-2] is pulled high. If D[n-1:n-2]=00, the lower plates of T3 and T2 should be grounded to GND; If D[n-1:n-2]=01, the lower plates of T2 and T1 should be connected to the reference voltage VREF. If D[n-1:n-2]=10, the lower plates of T7 and T6 should be grounded to GND; If D[n-1:n-2]=11, the lower plates of T6 and T5 should be connected to the reference voltage VREF. The above switching method causes the differential voltage of the upper plate to increase or decrease by VREF / 4. After the voltage is established, the next comparison is performed. After the comparison is completed, Q[n-3] is pulled high. If D[n-1:n-3]=000, the lower plate of T1 should be grounded to GND; If D[n-1:n-3]=001, the lower plate of T1 should be connected to the reference voltage VREF. If D[n-1:n-3]=010, the lower plate of T3 should be grounded to GND; If D[n-1:n-3]=011, the lower plate of T3 should be connected to the reference voltage VREF. If D[n-1:n-3]=100, the lower plate of T5 should be grounded to GND; If D[n-1:n-3]=101, the lower plate of T5 should be connected to the reference voltage VREF. If D[n-1:n-3]=110, the lower plate of T7 should be grounded to GND; If D[n-1:n-3]=111, the lower plate of T7 should be connected to the reference voltage VREF. At this point, the voltages connected to the lower plates of the top 7 equal-weighted capacitors are all determined. The above switching method causes the differential voltage of the upper plate to be increased or decreased by VREF / 4. After the establishment is completed, the next comparison is performed. After the comparison is completed, D[n-4] is obtained and Q[n-4] is pulled high. Next, based on D[n-4], the lower plate of the lower weight capacitor is reconnected to the reference voltage VREF or ground GND, and so on until the least significant bit D[0] of the successive approximation register is obtained.

2. A control method for switching the lower plates of the seven equally weighted capacitors corresponding to the high 3 weighted capacitors of the differential capacitor-type analog-to-digital converter array as described in claim 1, the control method comprising control logic G[i], control logic VC[i] and control logic VR[i], wherein the value of i ranges from 1 to 7; after sampling, the control logic G[i], control logic VC[i] and control logic VR[i] control the switching of the lower plates connected to the weighted capacitors in a mutually exclusive manner.

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