Low-dropout regulator based on charge pump

Abstract

In some aspects, the voltage regulator includes a transfer transistor and an amplifier, the transfer transistor being coupled between the input and output of the voltage regulator, the amplifier having a first input coupled to a reference voltage, a second input coupled to the output of the voltage regulator via a feedback path, and an output. The voltage regulator also includes a boost converter coupled between the output of the amplifier and the gate of the transfer transistor. In some aspects, the boost converter includes a first capacitor and a second capacitor for dual charge pumping. In some aspects, the control circuitry of the boost converter is coupled to a voltage source independent of the output voltage of the amplifier.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Indian Patent Application No. 202041031744, filed with the Indian Patent Office on 24 July 2020, the entire specification of which is incorporated herein by reference as if fully set forth below and used for all applicable purposes. Technical Field

[0003] The aspects of this disclosure generally relate to voltage regulators, and more specifically, to low dropout (LDO) regulators. Background Technology

[0004] Voltage regulators are used in various systems to provide regulated voltage to the power supply circuits within the system. A commonly used voltage regulator is the low-dropout (LDO) regulator. LDO regulators can be used to provide a clean, regulated voltage to power circuits from noisy input supply voltages. LDO regulators typically include a transfer element coupled in the feedback loop and an error amplifier to maintain a nearly constant output voltage based on a stable reference voltage. Summary of the Invention

[0005] The following is a simplified summary of one or more embodiments to provide a basic understanding of such embodiments. This summary is not an exhaustive overview of all contemplated embodiments and is neither intended to identify key or necessary elements of all embodiments nor to outline the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that follows.

[0006] The first aspect relates to a voltage regulator. The voltage regulator includes a transfer transistor coupled between an input and an output of the voltage regulator. The amplifier has a first input coupled to a reference voltage, a second input coupled to the output of the voltage regulator via a feedback path, and an output. The voltage regulator also includes a boost converter having an input coupled to the output of the amplifier and an output coupled to the gate of the transfer transistor. The boost converter includes a first capacitor, a second capacitor, a first switch coupled between the input of the boost converter and a first terminal of the first capacitor, a second switch coupled between the input of the boost converter and a first terminal of the second capacitor, a third switch coupled between the first terminal of the first capacitor and the output of the boost converter, and a fourth switch coupled between the first terminal of the second capacitor and the output of the boost converter.

[0007] The second aspect relates to a chip. The chip includes a power rail, circuitry, and a voltage regulator having an input coupled to the power rail and an output coupled to the circuitry. The voltage regulator includes a transfer transistor coupled between the input and output of the voltage regulator, the transfer transistor having a first input coupled to a reference voltage, a second input coupled to the output of the voltage regulator via a feedback path, and an output. The voltage regulator also includes a boost converter having an input coupled to the output of the amplifier and an output coupled to the gate of the transfer transistor. The boost converter includes a first capacitor, a second capacitor, a first switch coupled between the input of the boost converter and a terminal of the first capacitor, a second switch coupled between the input of the boost converter and a terminal of the second capacitor, a third switch coupled between a terminal of the first capacitor and the output of the boost converter, and a fourth switch coupled between a terminal of the second capacitor and the output of the boost converter.

[0008] A third aspect relates to a method of operating a voltage regulator. The voltage regulator includes a transfer transistor and an amplifier, the transfer transistor being coupled between an input and an output of the voltage regulator, the amplifier having a first input coupled to a reference voltage, a second input coupled to the output of the voltage regulator via a feedback path, and an output. The method includes, during a first time period, transferring charge between the output of the amplifier and a first terminal of a first capacitor, boosting the voltage of a second capacitor, and transferring charge between the first terminal of the second capacitor and an output capacitor, wherein the output capacitor is coupled to the gate of the transfer transistor. The method further includes, during a second time period, transferring charge between the output of the amplifier and the first terminal of the second capacitor, boosting the voltage of the first capacitor, and transferring charge between the first terminal of the first capacitor and the output capacitor. Attached Figure Description

[0009] Figure 1 An example of a low-dropout (LDO) regulator is shown.

[0010] Figure 2 An example of an LDO regulator including a voltage divider in the feedback path is shown.

[0011] Figure 3 An example of an LDO regulator including a booster is shown according to certain aspects of this disclosure.

[0012] Figure 4 An exemplary embodiment of a booster according to certain aspects of this disclosure is shown.

[0013] Figure 5 The illustrations depict certain aspects of this disclosure. Figure 4 Timing diagram of exemplary signals in a boost converter.

[0014] Figure 6 Another exemplary embodiment of a booster according to certain aspects of this disclosure is shown.

[0015] Figure 7 The illustrations depict certain aspects of this disclosure. Figure 6 Timing diagram of exemplary signals in a boost converter.

[0016] Figure 8 An exemplary embodiment of a control circuit according to certain aspects of this disclosure is shown.

[0017] Figure 9 This is a timing diagram illustrating exemplary control signals generated by a control circuit according to certain aspects of this disclosure.

[0018] Figure 10 An example of a latch-up state in a booster according to certain aspects of this disclosure is shown.

[0019] Figure 11 An example of a circuit configured to prevent latch-up in a booster is shown, according to certain aspects of this disclosure.

[0020] Figure 12 Another example of a circuit configured to prevent latch-up in a booster, according to certain aspects of this disclosure, is shown.

[0021] Figure 13 An example of a boost converter according to certain aspects of this disclosure is shown, comprising a start-up diode-connected transistor and an RC circuit.

[0022] Figure 14 An example of a chip including a voltage regulator is shown according to certain aspects of this disclosure.

[0023] Figure 15 This is a flowchart illustrating a method of operating a voltage regulator according to certain aspects of this disclosure. Detailed Implementation

[0024] The detailed description given below with reference to the accompanying drawings is intended as a description of various configurations, and not as representing the only configuration in which the concepts described herein can be practiced. For the purpose of providing a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in the form of block diagrams to avoid obscuring these concepts.

[0025] Figure 1An example of a low-dropout (LDO) regulator 100 according to certain aspects of this disclosure is shown. The LDO regulator 100 can be used to provide a clean, regulated voltage to a noise-sensitive circuit (not shown) to power the circuit from a noisy input supply voltage. The noisy input supply voltage can come from a switching regulator used to convert the battery voltage to the input supply voltage, or it can come from another voltage source.

[0026] LDO regulator 100 includes a transfer n-type field-effect transistor (NFET) 115 and an error amplifier 125. The transfer NFET 115 has a drain coupled to the input 105 of LDO regulator 100, a gate coupled to the output of error amplifier 125, and a source coupled to the output 130 of LDO regulator 100. The input 105 of LDO regulator 100 is coupled to a voltage power rail to receive the power supply voltage VDD. Figure 1 In the middle, resistor R L This represents the load of the circuit (not shown) coupled to the output 130 of the LDO regulator 100.

[0027] Error amplifier 125 controls the resistance of transfer NFET 115 between input 105 and output 130 of LDO regulator 100 by adjusting the gate voltage of transfer NFET 115. More specifically, error amplifier 125 increases the resistance of transfer NFET 115 by decreasing the gate voltage and decreases the resistance of transfer NFET 115 by increasing the gate voltage.

[0028] In this example, a reference voltage (denoted as "Vref") is input to a first input 122 (e.g., a positive input) of error amplifier 125. A second input 124 (e.g., a negative input) of error amplifier 125 is coupled to output 130 via feedback path 150. In this example, the regulated voltage Vreg at output 130 is fed back to the second input 124 of error amplifier 125 as a feedback voltage (denoted as "Vfb") via feedback path 150. During operation, error amplifier 125 drives the gate of transfer NFET 115 in a direction that reduces the difference (i.e., error) between the reference voltage Vref and the feedback voltage Vfb. Since the feedback voltage Vfb is approximately equal to the regulated voltage Vreg in this example, error amplifier 125 drives the gate of transfer NFET 115 in a direction that makes the regulated voltage Vreg approximately equal to the reference voltage Vref.

[0029] exist Figure 1 In the example shown, the regulated voltage Vreg is directly fed to the error amplifier 125. However, it should be understood that this disclosure is not limited to this example. For example, Figure 2Another example of an LDO regulator 100 is shown, in which the regulated voltage Vref is fed back to an error amplifier 125 via a voltage divider 215. The voltage divider 215 includes two series resistors R1 and R2 coupled to the output 130 of the LDO regulator 100. The voltage at node 220 between resistors R1 and R2 is fed back to the amplifier 125. In this example, the feedback voltage Vfb is related to the regulated voltage Vreg as follows:

[0030]

[0031] In equation (1), R1 and R2 are the resistance values ​​of resistors R1 and R2, respectively. Therefore, in this example, the feedback voltage Vfb is proportional to the regulated voltage Vreg, where the ratio is set by the ratio of the resistances of resistors R1 and R2.

[0032] Error amplifier 125 drives the gate of transfer NFET 115 in the direction of reducing the difference (i.e., error) between the feedback voltage Vfb and the reference voltage Vref. This feedback results in an regulated voltage Vreg approximately equal to:

[0033]

[0034] As shown in equation (2), in this example, the regulated voltage can be set to the desired voltage by correspondingly setting the ratio of the resistances of resistors R1 and R2. Therefore, it should be understood in this disclosure that the feedback voltage Vfb can be equal to or proportional to the regulated voltage Vreg.

[0035] exist Figure 1 and Figure 2 In the example, the transfer element of the LDO regulator 100 is implemented using a transfer NFET 115. The transfer NFET 115 can be fabricated using planar technology, FinFET technology, and / or another manufacturing process. Implementing the transfer element using a transfer NFET 115 has several advantages over implementing it using a p-type field-effect transistor (PFET). One advantage is that the relatively low impedance of the transfer NFET 115 at the output 130 of the LDO regulator 100 helps prevent the formation of low-frequency poles at the output 130. This eliminates the need for a large compensation capacitor at the output 130. Furthermore, this makes the loop stability essentially independent of the load. Additionally, NFET-based LDO regulators may have better power supply rejection ratio (PSRR), lower output ripple, and higher stability.

[0036] However, a problem with using the transfer NFET 115 as the transfer element in the LDO regulator 100 is that the gate voltage of the transfer NFET 115 needs to be at least higher than the threshold voltage of the transfer NFET 115 than the regulated voltage Vreg in order for the transfer NFET 115 to turn on. When the error amplifier 125 is powered by VDD, the maximum voltage that the error amplifier 125 can output to the gate of the transfer NFET 115 can be approximately VDD. In these cases, the maximum regulated voltage Vreg at the output 130 of the LDO regulator 100 is limited to approximately VDD minus the threshold voltage of the transfer NFET 115, which reduces the regulated voltage range of the LDO regulator 100.

[0037] One way to solve the above problem is to boost the voltage at the output of the error amplifier 125 and apply the boosted voltage to the gate of the transmission NFET 115. In this regard, Figure 3 An exemplary LDO regulator 100 is shown, comprising a boost converter 330 coupled between the output of an error amplifier 125 and the gate of a transmission NFET 115. The boost converter 330 has an input 332 coupled to the output of the error amplifier 125 and an output 334 coupled to the gate of the transmission NFET 115. The boost converter 330 is configured to receive the output voltage of the amplifier 125 at its input 332 (labeled “Vin”), boost (i.e., increase) the output voltage of the amplifier 125 to generate a boosted voltage, and output the boosted voltage (labeled “Vout”) at its output 334. For example, the boost converter 330 can double the voltage at the output of the error amplifier 125. In this example, the boost converter 330 may be referred to as a voltage doubler. The boosted voltage at the gate of the transfer NFET 115 may exceed the supply voltage VDD, thereby allowing the LDO regulator 100 to set the regulated voltage Vreg closer to VDD and reduce the voltage difference across the transfer NFET 115.

[0038] exist Figure 3 In the example shown, the regulated voltage Vreg is fed directly to the error amplifier 125 via feedback path 150. However, it should be understood that this disclosure is not limited to this example. For example, a voltage divider (e.g., voltage divider 215) may be placed in the feedback path 150 from the output 130 of the LDO regulator 100 to the second input 124 of the error amplifier 125, in which case the feedback voltage Vfb is proportional to the regulated voltage Vreg, as discussed above.

[0039] Figure 4An exemplary embodiment of a boost converter 330 according to certain aspects of this disclosure is shown. In this example, the boost converter 330 includes a first switch 415, a second switch 420, a third switch 425, a first capacitor C1, a second capacitor C2, an output capacitor Cs, and a control circuit 450.

[0040] A first switch 415 is coupled between the input 332 of the boost converter 330 and the first terminal 432 of the first capacitor C1, and a second switch 420 is coupled between the input 332 of the boost converter 330 and the first terminal 442 of the second capacitor C2. A control circuit 450 is coupled to the second terminal 434 of the first capacitor C1 and the second terminal 444 of the second capacitor C2. As discussed further below, the control circuit 450 applies a control signal phi1 to the second terminal 434 of the first capacitor C1 to selectively boost the voltage at the first terminal 432 of the first capacitor C1, and applies a control signal phi2 to the second terminal 444 of the second capacitor C2 to selectively boost the voltage at the first terminal 442 of the second capacitor C2. The control signals phi1 and phi2 can also be referred to as boosting voltages.

[0041] exist Figure 4 In the example, control circuitry 450 is coupled to control input 417 of the first switch 415 and control input 422 of the second switch 420. As discussed further below, control circuitry 450 inputs control signal bst1 to control input 417 of the first switch 415 to selectively open and close the first switch 415, and inputs control signal bst2 to control input 422 of the second switch 420 to selectively open and close the second switch 420. As used herein, a switch's "control input" is an input that controls whether the switch is closed or open based on a signal (e.g., voltage) input to the control input.

[0042] exist Figure 4 In the example, the first switch 415 is implemented using an NFET having a drain coupled to the input 332 of the boost converter 330 and a source coupled to the first terminal 432 of the first capacitor C1, wherein the control input 417 of the first switch 415 is located at the gate of the NFET. The second switch 420 is implemented using an NFET having a drain coupled to the input 332 of the boost converter 330 and a source coupled to the first terminal 442 of the second capacitor C2, wherein the control input 422 of the second switch 420 is located at the gate of the NFET. It should be understood that this disclosure is not limited to this example, and each of the first switch 415 and the second switch 420 can be implemented using other types of transistors, transmission gates, etc.

[0043] The third switch 425 is coupled between the first terminal 442 of the second capacitor C2 and the output 334 of the boost converter 330. The control input 427 of the third switch 425 is coupled to the first terminal 432 of the first capacitor C1. Therefore, in this example, the third switch 425 is controlled by the voltage at the first terminal 432 of the first capacitor C1. The output capacitor Cs is coupled between the output 334 of the boost converter 330 and ground.

[0044] exist Figure 4 In the example, the third switch 425 is implemented using a PFET having a drain coupled to the output 334 of the boost converter 330 and a source coupled to the first terminal 442 of the second capacitor C2, wherein the control input 427 of the third switch 425 is located at the gate of the PFET. As discussed further below, the voltage at the first terminal 432 of the first capacitor C1 controls whether the third switch 425 is open or closed. It should be understood that the invention is not limited to this example, and the third switch 425 can be implemented using other types of transistors, transmission gates, etc.

[0045] Control circuit 450 receives a clock signal (denoted as "Clk") and generates control signals bst1, bst2, phi1, and phi2 based on the clock signal Clk. The clock signal Clk can come from an oscillator, a phase-locked loop (PLL), and / or another clock source. In some respects, the frequency of the clock signal Clk can vary over a wide frequency range (e.g., between 20MHz and 100MHz).

[0046] Now, based on certain aspects, Figure 5 describe Figure 4 The exemplary operation of the booster 330 is shown in the figure. Figure 5 This is a timing diagram illustrating an example of control signals bst1, bst2, phi1, and phi2 generated by control circuit 450. In this example, control signals bst1, bst2, phi1, and phi2 are periodic signals with the same frequency. The frequency of the control signals can be equal to the frequency of the clock signal Clk. Each of control signals phi1 and phi2 oscillates between the input voltage Vin of boost converter 330 and approximately zero volts. Each of control signals bst2 and bst1 oscillates between Vin and Vin+VDD.

[0047] During time period Tl, the voltage of control signal bstl is Vin. As a result, the first switch 415 is turned off (i.e., disconnected), which isolates the first capacitor C1 from the input 332 of the boost converter 330.

[0048] During time period T2 (which is within time period T1), the voltage of control signal phi1 is Vin. As a result, control signal phi1 boosts the voltage at the first terminal 432 of the first capacitor C1 to Vin. Assuming the first capacitor C1 was previously charged to Vin, the boosted voltage at the first terminal 432 of the first capacitor C1 is approximately equal to 2Vin (i.e., twice Vin). Because the control input 427 (e.g., the gate) of the third switch 425 is coupled to the first terminal 432 of the first capacitor C1 (e.g., ... Figure 4 As shown in the diagram, in this example, a voltage of 2Vin is applied to the control input 427 of the third switch 425, which causes the third switch 425 to turn off (i.e., open). Therefore, during time T2, the second capacitor C2 is isolated from the output capacitor Cs.

[0049] During time period T3 (which falls within time period T2), the voltage of control signal phi2 is approximately zero volts. As a result, the voltage at the first terminal 442 of the second capacitor C2 is not boosted.

[0050] During time period T4 (which falls within time period T3), the voltage of control signal bst2 is Vin + Vdd, which turns on (i.e. closes) the second switch 420. This allows charge to flow through the second switch 420 between the output of error amplifier 125 and the first terminal 442 of the second capacitor C2.

[0051] During time period T5, the voltage of control signal bst2 is Vin. As a result, the second switch 420 is turned off (i.e., disconnected), and the second capacitor C2 is isolated from the input 332 of the boost converter 330.

[0052] During time period T6 (which falls within time period T5), the voltage of control signal phi2 is Vin. As a result, control signal phi2 boosts the voltage at the first terminal 442 of the second capacitor C2 to Vin. Since the second capacitor C2 was previously charged to Vin, the boosted voltage at the first terminal 442 of the second capacitor C2 is approximately equal to 2Vin (i.e., twice Vin).

[0053] During time period T7 (which falls within time period T6), the voltage of control signal phi1 is approximately zero volts. As a result, the voltage at the first terminal 432 of the first capacitor C1 is not boosted, but is approximately equal to Vin. Since the control input 427 (e.g., the gate) of the third switch 425 is coupled to the first terminal 432 of the first capacitor C1, in this example, the voltage of Vin is applied to the control input 427 of the third switch 425, which turns on (i.e., closes) the third switch 425. As a result, the second capacitor C2 is coupled to the output capacitor Cs through the second switch 420, thereby allowing charge to flow between the second capacitor C2 and the output capacitor Cs. During the charge transfer, the voltage at the first terminal 442 of the second capacitor C2 is boosted by control signal phi2.

[0054] During time period T8 (which falls within time period T7), the voltage of the control signal bstl is Vin + VDD, which turns on the first switch 415. This allows charge to flow through the first switch 415 between the output of the error amplifier 125 and the first terminal 432 of the first capacitor C1.

[0055] In this example, during each cycle (i.e., period) of the clock signal Clk, charge is transferred between the second capacitor C2 and the output capacitor Cs, while the voltage of the second capacitor C2 is boosted. This allows the voltage at the output 334 of the boost converter 330 to be boosted to approximately 2Vin (i.e., doubling the input voltage of the boost converter 330).

[0056] It should be understood that charge transfer between the second capacitor C2 and the output capacitor Cs can be in either direction. For example, if amplifier 125 increases Vin (e.g., in response to an increase in the current load), then charge can be transferred from the second capacitor C2 to the output capacitor Cs to increase the boost voltage. On the other hand, if amplifier 125 decreases Vin (e.g., in response to a decrease in the current load), then charge can be transferred from the output capacitor Cs to the second capacitor C2 to decrease the boosted voltage, thereby reflecting the decrease in Vin. Therefore, it should be understood in this disclosure that, unless otherwise stated, charge transfer can be in either direction.

[0057] In this example, charge is transferred once per clock signal Clk cycle between the second capacitor C2 and the output capacitor Cs. The output capacitor Cs is used to store charge at the output 334 of the boost converter 330 to help maintain the boosted voltage at the output 334 between charge transfers. In some respects, the output capacitor Cs can be omitted. In these respects, the gate capacitor of the transfer NFET 115 can be used as the output capacitor to store charge from the second capacitor C2.

[0058] exist Figure 4 In the example, LDO regulator 100 includes an NFET 460 coupled between the output 130 of LDO regulator 100 and ground, wherein the gate of NFET 460 is biased by a bias voltage (denoted as "nbias"). In this example, the bias voltage turns on NFET 460, causing NFET 460 to draw a small current from output 130. This small current can be approximately equal to the minimum current required for LDO regulator 100 to maintain voltage regulation. This allows LDO regulator 100 to operate without drawing current from a load (i.e., when LDO regulator 100 is not supplying current to a load). Figure 4 (Not shown) Sufficient current is sourced to sustain voltage regulation during adjustment. It should be understood that in some implementations, the NFET 460 can be omitted. Note that the circuitry coupled to the output 130 of the LDO regulator 100 is not shown in [the diagram / document]. Figure 4 It is clearly shown in the text.

[0059] exist Figure 4 In the example, charge is transferred once per clock signal Clk cycle between the second capacitor C2 and the output capacitor Cs. The voltage of the first capacitor C1 is used to control the third switch 425, which is turned on when the voltage of the first capacitor C1 is not boosted and turned off when the voltage of the first capacitor C1 is boosted.

[0060] In some respects, the boost converter 330 can employ a dual charge-pumping architecture, wherein charge is transferred to or from the output capacitor Cs twice per cycle (i.e., period) of the clock signal Clk. This allows the same amount of charge to be transferred to / from the output capacitor Cs twice per clock cycle using a smaller capacitor, which reduces the area of ​​the LDO regulator 100. Furthermore, transferring charge to / from the output capacitor Cs twice per clock cycle improves the settling time of the LDO regulator 100. The terms “transferred to… / transferred from…” indicate that the charge transfer can be in either direction (e.g., depending on whether the amplifier 125 responds to a change in the current load Vin by increasing or decreasing it).

[0061] in this regard, Figure 6An example of a boost converter 330 employing a dual charge pumping architecture according to certain aspects of this disclosure is shown. In this example, the boost converter 330 includes the first switch 415, the second switch 420, the first capacitor C1, the second capacitor C2, the output capacitor Cs, and the control circuitry 450 discussed above. Furthermore, the boost converter 330 includes a third switch 610 and a fourth switch 615. As discussed further below, the third switch 610 and the fourth switch 615 are used to alternately transfer charge between the first capacitor C1 and the output capacitor Cs, and to alternately transfer charge between the second capacitor C2 and the output capacitor Cs for dual charge pumping.

[0062] A first switch 415 is coupled between the input 332 of the boost converter 330 and the first terminal 432 of the first capacitor C1, and a second switch 420 is coupled between the input 332 of the boost converter 330 and the first terminal 442 of the second capacitor C2. The second terminal 434 of the first capacitor C1 is coupled to the control circuit 450, and the second terminal 444 of the second capacitor C2 is coupled to the control circuit 450. As discussed above, the control circuit 450 applies a control signal phi1 to terminal 434 of the first capacitor C1 and a control signal phi2 to terminal 444 of the second capacitor C2. Figure 6 In the example, each of the first and second switches 415 and 420 is implemented using an NFET. However, it should be understood that each of the switches 415 and 420 can be implemented using another type of transistor, transmission gate, etc. As discussed above, the control circuit 450 inputs a control signal bst1 to the control input 417 of the first switch 415 and a control signal bst2 to the control input 422 of the second switch 420.

[0063] The third switch 610 is coupled between the first terminal 432 of the first capacitor C1 and the output 334 of the boost converter 330, wherein the control input 612 of the third switch is coupled to the first terminal 442 of the second capacitor C2. Therefore, in this example, the third switch 610 is controlled by the voltage at the first terminal 442 of the second capacitor C2. Figure 6 This is controlled by being marked as "phi2_bst". Note that in... Figure 6 For ease of explanation, the connection between the control input 612 of the third switch 610 and the first terminal 442 of the second capacitor C2 is not explicitly shown. Figure 6 In the example shown, the third switch 610 is implemented using a PFET, wherein the control input 612 of the third switch 610 is located at the gate of the PFET. However, it should be understood that the third switch 610 is not limited to this example.

[0064] The fourth switch 615 is coupled between the first terminal 442 of the second capacitor C2 and the output 334 of the boost converter 330, wherein the control input 617 of the fourth switch 615 is coupled to the first terminal 432 of the first capacitor C1. Therefore, in this example, the fourth switch 615 is controlled by the voltage at the first terminal 432 of the first capacitor C1. Figure 6 This is controlled by being marked as "phi1_bst". Note that in... Figure 6 For ease of explanation, the connection between the control input 617 of the fourth switch 615 and the first terminal 432 of the first capacitor C1 is not explicitly shown. Figure 6 In the example shown, the fourth switch 615 is implemented using a PFET, wherein the control input 617 of the fourth switch 615 is located at the gate of the PFET. However, it should be understood that the fourth switch 615 is not limited to this example.

[0065] As discussed above, the control circuit 450 receives a clock signal (denoted as "Clk") and generates control signals bst1, bst2, phi1, and phi2 based on the clock signal Clk.

[0066] Now, based on certain aspects, Figure 7 To describe an exemplary operation of the boost converter 330. Figure 7 This is a timing diagram illustrating an example of control signals bst1, bst2, phi1, and phi2 generated by control circuit 450. In this example, control signals bst1, bst2, phi1, and phi2 are periodic signals with the same frequency (e.g., the frequency of a clock signal Clk). The control signals phi1 and phi2 oscillate between the input voltage Vin of boost converter 330 and approximately zero volts. Each control signal bst2 and bst1 oscillates between Vin and Vin+VDD. Figure 7 In the example, each of the first switch 415 and the second switch 420 is implemented using an NFET, and each of the third switch 610 and the fourth switch 615 is implemented using a PFET.

[0067] Figure 7 An example is also shown of the voltage phi1_bst at the first terminal 432 of the first capacitor C1 and the voltage phi2_bst at the first terminal 424 of the second capacitor C2. Figure 7 In the example, each voltage in phi1_bst and phi2_bst oscillates between approximately Vin and 2Vin.

[0068] exist Figure 7In the example, it is assumed that the charge transfer in each of the first and second capacitors C1 and C2 is relatively small during a single clock cycle (i.e., a time period). This assumption may be valid under steady-state conditions where there are no sudden large changes in the current load. Based on this assumption, the small changes in the voltages of the first and second capacitors C1 and C2 due to the small charge transfer within a single clock cycle are ignored to simplify the process. Figure 7 The discussion.

[0069] During time period T1, charge is transferred between the second capacitor C2 and the output capacitor Cs. More specifically, during time period T1, the control circuit 450 applies a voltage boost voltage of approximately Vin to the second terminal 444 of the second capacitor C2 by setting the control signal phi2 to approximately Vin, thereby boosting the voltage at the first terminal 442 of the second capacitor C2. Furthermore, during time period T1, the control circuit 450 turns off (i.e., disconnects) the second switch 420 by setting the control signal bst2 to approximately Vin, and the fourth switch 615 is turned on (i.e., closed) by the voltage phi1_bst. This allows charge to flow between the second capacitor C2 and the output capacitor Cs through the fourth switch 615, while the voltage of the second capacitor C2 is boosted.

[0070] Furthermore, during time period Tl, the third switch 610 is turned off by voltage phi2_bst, and the control circuit 450 turns on (i.e. closes) the first switch 415 by setting the control signal bstl to approximately Vin + Vdd, thereby allowing charge to flow between the output of the error amplifier 125 and the first capacitor C1. During this time period, the voltage of the first capacitor C1 is not boosted.

[0071] Therefore, during time period T1, charge is transferred between the second capacitor C2 and the output capacitor Cs.

[0072] During time period T2, charge is transferred between the first capacitor C1 and the output capacitor Cs. More specifically, during time period T2, the control circuit 450 applies a voltage boost voltage of approximately Vin to the second terminal 434 of the first capacitor C1 by setting the control signal phi1 to approximately Vin, thereby boosting the voltage at the first terminal 432 of the first capacitor C1. Furthermore, during time period T2, the control circuit turns off (i.e., disconnects) the first switch 415 by setting the control signal bst1 to approximately Vin, and the third switch 610 is turned on (i.e., closed) by the voltage phi2_bst. This allows charge to flow between the first capacitor C1 and the output capacitor Cs through the third switch 610, while the voltage of the first capacitor C1 is boosted.

[0073] Furthermore, during time period T2, the fourth switch 615 is turned off by voltage phi1_bst, and the control circuit 450 turns on (i.e. closes) the second switch 420 by setting the control signal bst2 to approximately Vin + VDD, thereby allowing charge to flow between the output of the error amplifier 125 and the second capacitor C2. During this time period, the voltage of the second capacitor C2 is not boosted.

[0074] Therefore, during time period T2, charge is transferred between the first capacitor C1 and the output capacitor Cs.

[0075] In this example, during one clock cycle (i.e., time period), charge is transferred to / from the output capacitor Cs twice. During the first part of the clock cycle (e.g., time period T1), charge is transferred between the second capacitor C2 and the output capacitor Cs, and during the second part of the clock cycle (e.g., time period T2), charge is transferred between the first capacitor C1 and the output capacitor Cs.

[0076] The two charge transfers per clock cycle improve the settling time of the LDO regulator 100 and allow the use of smaller capacitors to transfer the same amount of charge to / from the output capacitor Cs per clock cycle. For example, the size of the first capacitor C1 and the second capacitor C2 can be reduced by about half, while still transferring approximately the same amount of charge to / from the output capacitor Cs per clock cycle.

[0077] exist Figure 6 In the example, the third switch 610 is implemented using a PFET, wherein the source of the PFET is coupled to the output capacitor Cs and the drain of the PFET is coupled to the first capacitor C1. In this example, when turned on by the voltage phi2_bst, the third switch 610 can transfer charge from the first capacitor C1 to the output capacitor Cs when the drain voltage is higher than the source voltage, and transfer charge from the output capacitor Cs to the first capacitor C1 when the source voltage is higher than the drain voltage.

[0078] In addition, Figure 6 In the example, the fourth switch 615 is implemented using a PFET, wherein the source of the PFET is coupled to the output capacitor Cs and the drain of the PFET is coupled to the second capacitor C2. In this example, when turned on by the voltage phi1_bst, the fourth switch 615 can transfer charge from the second capacitor C2 to the output capacitor Cs when the drain voltage is higher than the source voltage, and transfer charge from the output capacitor Cs to the second capacitor C2 when the source voltage is higher than the drain voltage.

[0079] Although the voltages of capacitors C1 and C2 are boosted by a boost voltage Vin in the example above, it should be understood that this disclosure is not limited to this example, and the boost voltage may have other voltages besides Vin.

[0080] Figure 8 An exemplary embodiment of a control circuit 450 according to certain aspects of this disclosure is shown. As discussed above, the control circuit 450 generates control signals bst1 and bst2 for controlling the first and second switches 415 and 420, respectively. Figure 8 In the example shown, control circuitry 450 includes a first NFET 810, a second NFET 815, a third capacitor C3, a fourth capacitor C4, and a boost circuit 835. The drains of the first and second NFETs 810 and 815 are coupled to the input 332 of boost converter 330. The first and second NFETs 810 and 815 are cross-coupled, with the gate of the first NFET 810 coupled to the source of the second NFET 815, and the gate of the second NFET 815 coupled to the source of the first NFET 810. The first terminal 822 of the third capacitor C3 is coupled to the source of the first NFET 810, and the first terminal 832 of the fourth capacitor C4 is coupled to the source of the second NFET 815.

[0081] The boost circuit 835 is configured to alternately boost the voltage of the third capacitor C3 and the fourth capacitor C4 by alternately applying a boost voltage to the second terminal 824 of the third capacitor C3 and the second terminal 834 of the fourth capacitor C4. The boost voltage can be VDD or another voltage.

[0082] In this example, the boost circuit 835 includes a signal generator 840. The signal generator 840 has an input 842 configured to receive a clock signal Clk, a first output 844 coupled to a second terminal 824 of a third capacitor C3, and a second output 846 coupled to a second terminal 834 of a fourth capacitor C4. The signal generator 840 is configured to generate control signals phi1b and phi2b, outputting signal phi1b to the second terminal 824 of the third capacitor C3 via the first output 844, and outputting signal phi2b to the second terminal 834 of the fourth capacitor C4 via the second output 846. Figure 9 An exemplary timing diagram of signals phi1b and phi2b is shown, in which each of signals phi1b and phi2b oscillates between VDD and approximately zero volts.

[0083] The control signal bst1 is taken from the first terminal 822 of the third capacitor C3. Therefore, in this example, the voltage of the control signal bst1 is equal to the voltage at the first terminal 822 of the third capacitor C3. The control signal bst2 is taken from the first terminal 832 of the fourth capacitor C4. Therefore, in this example, the voltage of the control signal bst2 is equal to the voltage at the first terminal 832 of the fourth capacitor C4.

[0084] During operation, the voltages of signals phi1b and phi2b alternately swing to VDD. When the voltage of signal phi1b is VDD and the voltage of signal phi2b is low (e.g., approximately zero volts), the first NFET 810 is turned off and the second NFET 815 is turned on. The voltage at the first terminal 822 of the third capacitor C3 (and therefore the voltage of the control signal bst1) is boosted to a voltage approximately equal to the sum of Vin and VDD (i.e., Vin + VDD). As a result, the first switch 415 is turned on. The boosted voltage at the first terminal 822 of the third capacitor C3 (which is also coupled to the gate of the second NFET 815) turns on the second NFET 815. As a result, charge flows through the second NFET 815 between the fourth capacitor C4 and the output of the error amplifier 125. During this time, the voltage at the first terminal 832 of the fourth capacitor C4 is not boosted because signal phi2b is low. Therefore, the voltage of the control signal bst2 does not exceed Vin, which turns off the second switch 420.

[0085] When the voltage of signal philb is low (e.g., approximately zero volts) and the voltage of signal phi2b is VDD, the first NFET 810 is turned on and the second NFET 815 is turned off. The voltage at the first terminal 832 of the fourth capacitor C4 (and therefore the voltage of control signal bst2) is boosted to approximately equal to Vin + VDD, which turns on the second switch 420. The boosted voltage at the first terminal 832 of the fourth capacitor C4 (which is also coupled to the gate of the first NFET 810) also turns on the first NFET 810. As a result, charge flows through the first NFET 810 between the third capacitor C3 and the output of the error amplifier 125. During this time, the voltage at the first terminal 822 of the third capacitor C3 (the voltage of control signal bst1) does not exceed Vin, which turns off the first switch 415.

[0086] exist Figure 8In the example, the boost circuit 835 further includes a first inverter 850 coupled between a first output 844 of the signal generator 840 and a second terminal 434 of the first capacitor C1, and a second inverter 855 coupled between a second output 846 of the signal generator 840 and a second terminal 444 of the second capacitor C2. In this example, the first inverter 850 is configured to generate signal phi1 by inverting signal phi1b from the signal generator 840, and the second inverter 855 is configured to generate signal phi2 by inverting signal phi2b from the signal generator 840. In some respects, each of the inverters 850 and 855 is powered by a voltage input to the boost converter 330, such that the voltage of each of the signals phi1 and phi2 swings between Vin and approximately zero volts.

[0087] Boost converter 330 can enter a latched state under certain conditions. For example, boost converter 330 can enter a latched state when the current load at output 130 suddenly drops. This may happen, for example, when the circuit coupled to output 130 is turned off. A sudden drop in the current load may cause a sudden large increase in the regulated voltage Vreg, which in turn causes a sudden large increase in the feedback voltage Vfb input to error amplifier 125. In response to the sudden large increase in the feedback voltage Vfb, the output voltage of error amplifier 125 may suddenly drop to approximately zero volts. An example of this is... Figure 10 The diagram illustrates how the input voltage Vin from error amplifier 125 to boost converter 330 drops abruptly from approximately 0.7V to approximately zeroV due to a sudden drop in the current load. While the voltage prior to the drop is approximately 0.7V in this example, it should be understood that the voltage prior to the drop can vary depending on the load conditions of the LDO regulator 100 before the drop. Note that error amplifier 125 is not... Figure 10 As shown in the image.

[0088] In this scenario, a sudden drop in Vin to approximately zero volts could cause boost converter 330 to enter a latched state, as follows. With the first NFET 810 turned on during the voltage drop, the third capacitor C3 is rapidly discharged to approximately zero volts, causing the gate voltage of the second NFET 815 and the voltage of the control signal bst1 to drop to approximately zero volts. As a result, the second NFET 815 and the first switch 415 are turned off. Because the second NFET 815 is turned off, the voltage at the first terminal 832 of the fourth capacitor C4 remains high (e.g., approximately 1.6V). As a result, the first NFET 810 and the second switch 420 are turned on. Additionally, the third switch 610 is turned on and the fourth switch 615 is turned off. Figure 10In this system, the off switch is indicated by "OFF" next to it, while the on switch is indicated by "ON" next to it.

[0089] In this example, there is no discharge current path from the output capacitor Cs to the output of the error amplifier 125. This is because the first switch 415 is turned off, which blocks the discharge current path through the third switch 610 and the first switch 415, and the fourth switch 615 is turned off, which blocks the discharge current path through the fourth switch 615 and the second switch 420. Because there is no discharge current path from the output capacitor Cs to the output of the error amplifier 125, the voltage at the output capacitor Cs can remain high, causing the boost converter 330 to remain in a latched state.

[0090] Latching can lead to overvoltage violations in boost converter 330. An overvoltage violation occurs when the voltage between the two terminals of a transistor exceeds a voltage limit. In one example, the voltage limit could be approximately 1.3V. In this example, a gate voltage of approximately 1.6V at the gate of the first NFET 810 causes an overvoltage violation at the first NFET 810 because the voltage between the gate and drain of the first NFET 810 exceeds the voltage limit, and the voltage between the gate and source of the first NFET 810 also exceeds the voltage limit. Transistors in the switch may also experience overvoltage violations. Overvoltage violations may persist until boost converter 330 recovers from the latching state.

[0091] To address the latch-up problem, aspects of this disclosure couple the control circuitry 450 to a voltage source (e.g., a fixed voltage source) instead of the input 332 of the boost converter 330. In this respect, Figure 11 An example of a voltage source 1110 coupled to control circuitry 450 is shown, and more specifically, coupled to the drains of NFETs 810 and 815. Voltage source 1110 provides a voltage Vp to control circuitry 450, which is independent of the input voltage Vin provided by the output of error amplifier 125. Therefore, when the input voltage Vin suddenly drops to approximately zero volts (e.g., due to a sudden drop in current load), the voltage Vp from voltage source 1110 will not drop, which helps prevent boost converter 330 from entering a latched state. Voltage Vp can be set to a voltage level that allows control circuitry 450 to alternately turn on the first switch 415 and the second switch 420 while avoiding overvoltage violations.

[0092] Figure 11An exemplary embodiment of voltage source 1110 is shown, wherein voltage source 1110 includes voltage divider 1120 and enable transistor 1140. Enable transistor 1140 is coupled between a power rail having a supply voltage VCC and voltage divider 1120, and voltage divider 1120 is coupled between enable transistor 1140 and ground. Supply voltage VCC may be different from supply voltage VDD coupled to input 105 of LDO regulator 100. In some aspects, supply voltage VCC may be lower than supply voltage VDD.

[0093] In this example, enable transistor 1140 is configured to selectively enable or disable voltage source 1110 based on an enable signal En input to its gate. When enable transistor 1140 is turned on by enable signal En, it couples voltage divider 1120 to the supply voltage VCC, and voltage source 1110 is enabled. When enable transistor 1140 is turned off by enable signal En, voltage source 1110 is disabled. Figure 11 In the example shown, the enable transistor 1140 is implemented using an NFET. However, it should be understood that the enable transistor 1140 can be implemented using another type of transistor.

[0094] In this example, voltage divider 1120 includes a first resistor 1132 and a second resistor 1134 connected in series between enable transistor 1140 and ground. A voltage Vp is generated at node 1130 between the first resistor 1132 and the second resistor 1134. Figure 11 In the example, node 1130 is coupled to the drain of NFETs 810 and 815. In this example, the voltage Vp is given by:

[0095]

[0096] In equation (3), R1 and R2 are the resistances of the first resistor 1132 and the second resistor 1134, respectively. Therefore, in this example, the voltage Vp can be set to the desired voltage by appropriately setting the ratio of the resistances of resistors 1132 and 1134.

[0097] Figure 12Another exemplary embodiment of a voltage divider 1120 according to certain aspects is shown. In this example, the voltage divider 1120 includes a first diode-connected transistor 1210, a second diode-connected transistor 1215, and a third diode-connected transistor 1220, series-coupled between an enable transistor 1140 and ground. In a steady state, the current flowing to NFETs 810 and 815 is approximately zero. Because the diode-connected transistors 1210, 1215, and 1220 are series-coupled, approximately the same current flows through them in a steady state. Since the current flowing through the diode-connected transistors 1210, 1215, and 1220 is approximately the same, they maintain the same gate-to-source voltage, which distributes the voltage VCC evenly across them. Because the voltage VCC is evenly distributed among the diode-connected transistors 1210, 1215, and 1220, the voltage between the first diode-connected transistor 1210 and the second diode-connected transistor 1215 is approximately 2 / 3 VCC, and the voltage between the second diode-connected transistor 1215 and the third diode-connected transistor 1220 is approximately 1 / 3 VCC. In this example, the size of the enable transistor 1140 can be determined such that the voltage drop across the enable transistor 1140 is minimized.

[0098] exist Figure 12 In the example, a voltage Vp is generated at node 1230 between transistor 1210 (connected to the first diode) and transistor 1215 (connected to the second diode). Therefore, in this example, voltage Vp is approximately equal to 2 / 3 VCC. Alternatively, voltage Vp can be taken from node 1235 between transistor 1215 (connected to the second diode) and transistor 1220 (connected to the third diode), in which case voltage Vp is 1 / 3 VCC.

[0099] exist Figure 12 In the example shown, each of the diode-connected transistors 1210, 1215, and 1220 is implemented using an NFET. However, it should be understood that this disclosure is not limited to this example, and each of the diode-connected transistors 1210, 1215, and 1220 could be implemented using another type of transistor.

[0100] Figure 13An example is shown where the boost converter 330 also includes a diode-connected transistor 1310 coupled between the input 332 and the output 334 of the boost converter 330. When the boost converter 330 is initially turned on, the diode-connected transistor 1310 provides faster startup of the boost converter 330 by charging the output capacitor Cs. More specifically, when the boost converter 330 is initially turned on, the diode-connected transistor 1310 is forward biased and provides a charging path between the output of the error amplifier 125 and the output capacitor Cs (assuming Vin is initially greater than Vout). The charging path allows the output of the error amplifier 125 to quickly charge the output capacitor Cs through the diode-connected transistor 1310.

[0101] During normal operation, the diode-connected transistor 1310 is reverse-biased. This is because, during normal operation, the boosted voltage at the output 334 of the boost converter 330 is greater than the output voltage of the error amplifier 125. As a result, the diode-connected transistor 1310 does not conduct charge during normal operation. Therefore, the diode-connected transistor 1310 is initially forward-biased to provide a charging path from the output of the error amplifier 125 to the output capacitor Cs, allowing for faster startup and reverse biasing during normal operation. Figure 13 In the example, the diode-connected transistor 1310 is implemented using a PFET, which has a source coupled to the output of the error amplifier 125, and a gate and drain connected together at the output 334 of the boost converter 330.

[0102] exist Figure 13 In the example, boost converter 330 also includes an RC circuit 1320 coupled to the output 334 of boost converter 330. RC circuit 1320 may include resistor 1330 and capacitor Cdo. RC circuit 1320 can form a low-pass RC filter to filter out high-frequency ripple from the output 334 of boost converter 330. RC circuit 1320 can also be used to adjust the pole at the gate of the transmission NFET 115 for gate compensation. For example, the pole at the gate of the transmission NFET 115 can be adjusted by adjusting the capacitance of capacitor Cdo and / or the resistance of resistor 1330. Figure 13 In the example, the output capacitor Cs is coupled to the output 334 of the boost converter 330 via the RC circuit 1320.

[0103] Figure 14 An example of a chip 1410 including an LDO regulator 100 according to certain aspects of this disclosure is shown. The LDO regulator 100 can be used... Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 11 , Figure 12 and Figure 13 Implemented by any of the exemplary embodiments shown. Chip 1410 includes power rail 1435, power pad 1430, reference circuitry 1440, and circuitry 1450.

[0104] In this example, power pad 1430 is coupled to an external power supply 1420 (i.e., an off-chip power supply). Power supply 1420 may include a battery, a power management integrated circuit (PMIC), and / or another power source. For an example where power supply 1420 includes a PMIC, the PMIC may include a switching regulator (not shown) configured to convert the voltage from the battery to the supply voltage VDD. Power pad 1430 may be coupled to power supply 1420 via a metal line 1433 (e.g., on a printed circuit board).

[0105] Power rail 1435 is coupled to power pad 1430. In some aspects, power rail 1435 is configured to receive power supply voltage VDD from power supply 1420 via power pad 1430. Power rail 1435 may include one or more metal layers on chip 1410. Power rail 1435 may also include one or more vias and / or one or more other metal interconnect structures to couple one or more metal layers.

[0106] In this example, input 105 of LDO regulator 100 is coupled to power rail 1435 and output 130 of LDO regulator 100 is coupled to circuit 1450. LDO regulator 100 receives a power supply voltage VDD at input 105 and generates a regulated voltage Vreg from the power supply voltage VDD at output 130, as discussed above. The regulated voltage Vreg is provided to circuit 1450 to power the circuit. Circuit 1450 may include a modem, logic circuitry (e.g., combinational logic and / or sequential logic), processor, memory, and / or another type of circuitry.

[0107] Reference circuit 1440 is coupled to error amplifier 125 in LDO regulator 100. Figure 14 The first input 122 (not shown in the diagram) is the reference circuit 1440. The reference circuit 1440 is configured to generate a reference voltage Vref and output the reference voltage Vref to the first input 122 of the error amplifier 125. As discussed above, the LDO regulator 100 regulates the voltage at output 130 based on the reference voltage and the feedback voltage Vfb. The reference circuit 1440 can be implemented using a voltage divider, a bandgap reference circuit, etc. In the example where the reference circuit 1440 is implemented using a voltage divider (not shown), the voltage divider may include one or more variable resistors, wherein the resistance of the one or more variable resistors can be programmed to program the reference voltage Vref.

[0108] Figure 15This is a flowchart illustrating a method 1500 for operating a voltage regulator according to certain aspects of this disclosure. The voltage regulator (e.g., LDO regulator 100) includes a transfer transistor (e.g., a transfer NFET 115) and an amplifier (e.g., amplifier 125) coupled between an input (e.g., input 105) and an output (e.g., output 130) of the voltage regulator. The amplifier (e.g., amplifier 125) has a first input (e.g., first input 122) coupled to a reference voltage, a second input (e.g., second input 124) coupled to the output of the voltage regulator via a feedback path (e.g., feedback path 150), and an output.

[0109] At block 1510, during the first time period, charge is transferred between the amplifier output and the first terminal of the first capacitor. The first capacitor may correspond to the first capacitor C1, and the first time period may correspond to... Figure 7 The first time period is T1. In some respects, the first time period can be the first part of a clock cycle. In one example, the charge transfer between the amplifier output and the first terminal of the first capacitor can be performed by the first switch 415 and the control circuit 450.

[0110] At block 1520, during the first time period, the voltage of the second capacitor is boosted. For example, the voltage of the second capacitor (e.g., second capacitor C2) can be boosted by control circuit 450.

[0111] At block 1530, during the first time period, charge is transferred between the first terminal of the second capacitor and the output capacitor, wherein the output capacitor is coupled to the gate of the transmission transistor. For example, charge can be transferred between the first terminal of the second capacitor and the output capacitor (e.g., output capacitor Cs) via a fourth switch 615.

[0112] At block 1540, during the second time period, charge is transferred between the amplifier output and the first terminal of the second capacitor. The second time period can correspond to... Figure 7 The second time period is T2. In some respects, the second time period can be the second part of the clock cycle discussed above. The charge transfer between the amplifier output and the first terminal of the second capacitor can be performed by the second switch 420 and the control circuit 450.

[0113] At block 1550, during the second time period, the voltage of the first capacitor is boosted. For example, the voltage of the first capacitor can be boosted by control circuit 450.

[0114] At block 1560, during the second time period, charge is transferred between the first terminal of the first capacitor and the output capacitor. For example, charge can be transferred between the first terminal of the first capacitor and the output capacitor via a third switch 610.

[0115] In some aspects, transferring charge between the amplifier output and a first terminal of a first capacitor may include closing a first switch (e.g., first switch 415), and transferring charge between the amplifier output and a first terminal of a second capacitor may include closing a second switch (e.g., second switch 420). In these aspects, method 1500 may include opening the second switch during a first time period and opening the first switch during a second time period.

[0116] In some aspects, boosting the voltage of the first capacitor may include applying a boost voltage to a second terminal of the first capacitor, and boosting the voltage of the second capacitor may include applying a boost voltage to a second terminal of the second capacitor. The boost voltage may be Vin or another voltage.

[0117] In some aspects, transferring charge between a first terminal of the first capacitor and the output capacitor includes closing a first switch (e.g., a third switch 610), and transferring charge between a first terminal of the second capacitor and the output capacitor may include closing a second switch (e.g., a fourth switch 615). In these aspects, method 1500 may include opening the first switch during a first time period and opening the second switch during a second time period. In some aspects, closing the first switch includes routing the voltage of the second capacitor to a control input (e.g., control input 612) of the first switch (third switch 610), and closing the second switch includes routing the voltage of the first capacitor to a control input (e.g., control input 617) of the second switch (e.g., fourth switch 615).

[0118] Examples of various implementation methods are described in the following numbered clauses:

[0119] 1. A voltage regulator, comprising:

[0120] The transmission transistor is coupled between the input and output of the voltage regulator;

[0121] An amplifier having a first input coupled to a reference voltage, a second input coupled via a feedback path to the output of a voltage regulator, and an output; and

[0122] A boost converter having an input coupled to the output of an amplifier and an output coupled to the gate of a transmission transistor, wherein the boost converter includes:

[0123] First capacitor;

[0124] Second capacitor;

[0125] A first switch coupled between the input of the boost converter and the first terminal of the first capacitor;

[0126] A second switch coupled between the input of the boost converter and the first terminal of the second capacitor;

[0127] A third switch coupled between the first terminal of the first capacitor and the output of the boost converter; and

[0128] A fourth switch is coupled between the first terminal of the second capacitor and the output of the boost converter.

[0129] 2. The voltage regulator according to Clause 1, wherein the third switch has a control input coupled to a first terminal of the second capacitor.

[0130] 3. The voltage regulator according to Clause 2, wherein the fourth switch has a control input coupled to a first terminal of the first capacitor.

[0131] 4. The voltage regulator according to Clause 3, wherein:

[0132] The third switch includes a first transistor, wherein the control input of the third switch is located at the gate of the first transistor; and

[0133] The fourth switch includes the second transistor, wherein the control input of the fourth switch is located at the gate of the second transistor.

[0134] 5. The voltage regulator according to Clause 4, wherein the first transistor includes a first p-type field-effect transistor (PFET) and the second transistor includes a second PFET.

[0135] 6. The voltage regulator according to any one of clauses 1 to 5 further includes an output capacitor coupled between the output of the voltage regulator and ground.

[0136] 7. The voltage regulator according to any one of clauses 1 to 6 further comprises:

[0137] A voltage source, wherein the voltage source includes a voltage divider coupled between a power supply voltage rail and ground.

[0138] 8. The voltage regulator according to Clause 7, wherein the voltage divider comprises a plurality of diode-connected transistors coupled in series.

[0139] 9. The voltage regulator according to any one of clauses 1 to 3 further includes a voltage source, wherein the voltage source includes a voltage divider coupled between a power supply voltage rail and ground;

[0140] Control circuit, wherein the control circuit includes:

[0141] Third capacitor;

[0142] Fourth capacitor;

[0143] The first transistor coupled between the voltage source and the first terminal of the third capacitor; and

[0144] A second transistor coupled between a voltage source and a first terminal of a fourth capacitor, wherein the gate of the second transistor is coupled to the source of the first transistor, and the source of the second transistor is coupled to the gate of the first transistor.

[0145] The first terminal of the third capacitor is coupled to the control input of the first switch, and the first terminal of the fourth capacitor is coupled to the control input of the second switch.

[0146] 10. The voltage regulator according to Clause 9, wherein the control circuitry further includes a boost circuit configured to alternately apply a boost voltage to the second terminal of the third capacitor and the second terminal of the fourth capacitor.

[0147] 11. The voltage regulator according to any one of clauses 4 to 8 further includes

[0148] A voltage source, wherein the voltage source includes a voltage divider coupled between a power supply voltage rail and ground;

[0149] Control circuit, wherein the control circuit includes:

[0150] Third capacitor;

[0151] Fourth capacitor;

[0152] A third transistor coupled between a voltage source and the first terminal of a third capacitor; and

[0153] A fourth transistor is coupled between a voltage source and a first terminal of a fourth capacitor, wherein the gate of the fourth transistor is coupled to the source of a third transistor, and the source of the fourth transistor is coupled to the gate of the third transistor.

[0154] The first terminal of the third capacitor is coupled to the control input of the first switch, and the first terminal of the fourth capacitor is coupled to the control input of the second switch.

[0155] 12. The voltage regulator according to Clause 11, wherein the control circuit further includes a boost circuit configured to alternately apply a boost voltage to the second terminal of the third capacitor and the second terminal of the fourth capacitor.

[0156] 13. The voltage regulator according to any one of clauses 1 to 8 further includes a control circuit coupled to the first switch and the second switch, wherein the control circuit is configured to:

[0157] During the first time period, the first switch is turned on and the second switch is turned off; and

[0158] During the second time period, the first switch is turned off and the second switch is turned on.

[0159] 14. The voltage regulator according to Clause 13, wherein the control circuit is coupled to a second terminal of a first capacitor and a second terminal of a second capacitor, and the control circuit is configured to:

[0160] During the first time period, a boost voltage is applied to the second terminal of the second capacitor; and

[0161] During the second time period, a boost voltage is applied to the second terminal of the first capacitor.

[0162] 15. The voltage regulator according to clause 13 or 14 further includes a voltage source coupled to the control circuit, the voltage source including a voltage divider coupled between the power supply voltage rail and ground.

[0163] 16. The voltage regulator according to Clause 15, wherein the voltage divider comprises a plurality of diode-connected transistors coupled in series.

[0164] 17. A chip, comprising:

[0165] Power rail;

[0166] Circuits; and

[0167] A voltage regulator having an input coupled to a power rail and an output coupled to a circuit, wherein the voltage regulator includes:

[0168] A transfer transistor coupled between the input and output of a voltage regulator;

[0169] An amplifier having a first input coupled to a reference voltage, a second input coupled via a feedback path to the output of a voltage regulator, and an output; and

[0170] A boost converter having an input coupled to the output of an amplifier and an output coupled to the gate of a transmission transistor, wherein the boost converter includes:

[0171] First capacitor;

[0172] Second capacitor;

[0173] A first switch coupled between the input of the boost converter and the terminals of the first capacitor;

[0174] A second switch coupled between the input of the boost converter and the terminals of the second capacitor;

[0175] A third switch coupled between the terminals of the first capacitor and the output of the boost converter; and

[0176] A fourth switch is coupled between the terminals of the second capacitor and the output of the boost converter.

[0177] 18. The chip as described in Clause 17, wherein the circuitry includes at least one of a modem, logic circuitry, a processor, or memory.

[0178] 19. The chip as described in Clause 17 or 18 also includes pads coupled to power rails.

[0179] 20. The chip according to any one of clauses 17 to 19 further includes a reference circuit coupled to a first input of the amplifier, wherein the reference circuit is configured to generate a reference voltage.

[0180] 21. The chip according to any one of clauses 17 to 20, wherein the third switch has a control input coupled to a first terminal of the second capacitor.

[0181] 22. The chip according to Clause 21, wherein the fourth switch has a control input coupled to a first terminal of the first capacitor.

[0182] 23. The chip according to any one of clauses 17 to 22 further includes control circuitry coupled to the first switch and the second switch, wherein the control circuitry is configured to:

[0183] During the first time period, the first switch is turned on and the second switch is turned off; and

[0184] During the second time period, the first switch is turned off and the second switch is turned on.

[0185] 24. The chip according to Clause 23, wherein the control circuit is coupled to a second terminal of a first capacitor and a second terminal of a second capacitor, and the control circuit is configured to:

[0186] During the first time period, a boost voltage is applied to the second terminal of the second capacitor; and

[0187] During the second time period, a boost voltage is applied to the second terminal of the first capacitor.

[0188] 25. The chip according to clause 23 or 24 further includes a voltage source coupled to the control circuit, the voltage source including a voltage divider coupled between the power supply voltage rail and ground.

[0189] 26. The chip according to Clause 25, wherein the voltage divider comprises a plurality of diode-connected transistors coupled in series.

[0190] 27. A method for operating a voltage regulator, wherein the voltage regulator includes a transfer transistor and an amplifier, the transfer transistor being coupled between an input of the voltage regulator and an output of the voltage regulator, the amplifier being coupled to a first input of a reference voltage, a second input coupled via a feedback path to the output of the voltage regulator, and an output, the method comprising:

[0191] During the first time period, charge is transferred between the amplifier output and the first terminal of the first capacitor;

[0192] During the first time period, the voltage of the second capacitor is boosted;

[0193] During the first time period, charge is transferred between the first terminal of the second capacitor and the output capacitor, wherein the output capacitor is coupled to the gate of the transmission transistor;

[0194] During the second time period, charge is transferred between the amplifier output and the first terminal of the second capacitor;

[0195] During the second time period, the voltage of the first capacitor is boosted; and

[0196] During the second time period, charge is transferred between the first terminal of the first capacitor and the output capacitor.

[0197] 28. The method described according to Clause 27, wherein:

[0198] The voltage regulator includes: a first switch coupled between the output of the amplifier and a first terminal of a first capacitor, and a second switch coupled between the output of the amplifier and a first terminal of a second capacitor;

[0199] Transferring charge between the amplifier output and the first terminal of the first capacitor includes closing the first switch; and

[0200] Transferring charge between the amplifier's output and the first terminal of the second capacitor involves closing the second switch.

[0201] 29. The method described under Clause 28 further includes:

[0202] During the first time period, disconnect the second switch; and

[0203] During the second time period, the first switch is disconnected.

[0204] 30. The method according to any one of clauses 27 to 29, wherein:

[0205] Boosting the voltage of the first capacitor includes applying a boosted voltage to the second terminal of the first capacitor; and

[0206] Boosting the voltage of the second capacitor involves applying a boost voltage to the second terminal of the second capacitor.

[0207] 31. The method according to Clause 27, wherein:

[0208] The voltage regulator includes: a first switch coupled between a first terminal of a first capacitor and an output capacitor, and a second switch coupled between a first terminal of a second transistor and the output capacitor;

[0209] Transferring charge between the first terminal of the first capacitor and the output capacitor includes closing the first switch; and

[0210] Transferring charge between the first terminal of the second capacitor and the output capacitor involves closing the second switch.

[0211] 32. The method according to Clause 31, wherein:

[0212] Closing the first switch includes routing the voltage of the second capacitor to the control input of the first switch; and

[0213] Closing the second switch involves routing the voltage of the first capacitor to the control input of the second switch.

[0214] 33. The method according to any one of clauses 28 to 30, wherein:

[0215] The voltage regulator includes: a third switch coupled between a first terminal of a first capacitor and an output capacitor, and a fourth switch coupled between a first terminal of a second transistor and an output capacitor;

[0216] Transferring charge between the first terminal of the first capacitor and the output capacitor includes closing the third switch; and

[0217] Transferring charge between the first terminal of the second capacitor and the output capacitor involves closing the fourth switch.

[0218] 34. The method described according to Clause 33, wherein:

[0219] Closing the third switch includes routing the voltage of the second capacitor to the control input of the third switch; and

[0220] Closing the fourth switch involves routing the voltage of the first capacitor to the control input of the fourth switch.

[0221] Any reference to elements in this document using names such as "first," "second," etc., generally does not restrict the number or order of those elements. Rather, these names are used in this document as a convenient way to distinguish two or more elements or instances of elements. Therefore, references to the first and second elements do not imply that only two elements can be used, or that the first element must precede the second element.

[0222] In this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. As used herein, the terms "about" and "approximately" relating to specified values ​​or properties are intended to mean within 10% of the specified value or property (i.e., between 90% and 110% of the specified value or property).

[0223] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A voltage regulator, comprising: A transmission transistor is coupled between the input and the output of the voltage regulator; An amplifier having a first input coupled to a reference voltage, a second input coupled to the output of the voltage regulator via a feedback path, and an output; as well as A boost converter having an input coupled to the output of the amplifier and an output coupled to the gate of the transmission transistor, wherein the boost converter includes: First capacitor; Second capacitor; A first switch is coupled between the input of the boost converter and the first terminal of the first capacitor; A second switch is coupled between the input of the boost converter and the first terminal of the second capacitor; A third switch is coupled between the first terminal of the first capacitor and the output of the boost converter; and A fourth switch is coupled between the first terminal of the second capacitor and the output of the boost converter; A voltage source, wherein the voltage source includes a voltage divider coupled between a power supply voltage rail and ground; Control circuit, wherein the control circuit includes: Third capacitor; Fourth capacitor; A first transistor is coupled between the voltage source and a first terminal of the third capacitor; and A second transistor is coupled between the voltage source and the first terminal of the fourth capacitor, wherein the gate of the second transistor is coupled to the source of the first transistor, and the source of the second transistor is coupled to the gate of the first transistor. The first terminal of the third capacitor is coupled to the control input of the first switch, and the first terminal of the fourth capacitor is coupled to the control input of the second switch.

2. The voltage regulator of claim 1, wherein the third switch has a control input coupled to a first terminal of the second capacitor.

3. The voltage regulator of claim 2, wherein the fourth switch has a control input coupled to a first terminal of the first capacitor.

4. The voltage regulator according to claim 3, wherein: The third switch includes a first transistor, wherein the control input of the third switch is located at the gate of the first transistor; and The fourth switch includes a second transistor, wherein the control input of the fourth switch is located at the gate of the second transistor.

5. The voltage regulator of claim 4, wherein the first transistor comprises a first p-type field-effect transistor (PFET), and the second transistor comprises a second PFET.

6. The voltage regulator according to claim 1 further includes an output capacitor coupled between the output of the boost converter and ground.

7. The voltage regulator of claim 1, wherein the voltage divider comprises a plurality of diode-connected transistors coupled in series.

8. The voltage regulator of claim 1, wherein the control circuit further comprises a boost circuit configured to alternately apply a boost voltage to the second terminal of the third capacitor and the second terminal of the fourth capacitor.

9. The voltage regulator of claim 1, wherein the control circuit is configured to: During the first time period, the first switch is turned on and the second switch is turned off; and During the second time period, the first switch is turned off and the second switch is turned on.

10. The voltage regulator of claim 9, wherein the control circuit is coupled to a second terminal of the first capacitor and a second terminal of the second capacitor, and the control circuit is configured to: During the first time period, a boost voltage is applied to the second terminal of the second capacitor; and During the second time period, the boost voltage is applied to the second terminal of the first capacitor.

11. The voltage regulator of claim 10, wherein the third switch has a control input coupled to a first terminal of the second capacitor.

12. The voltage regulator of claim 11, wherein the fourth switch has a control input coupled to a first terminal of the first capacitor.

13. The voltage regulator of claim 9, wherein the voltage divider comprises a plurality of diode-connected transistors coupled in series.

14. A chip, comprising: Power rail; Circuit; as well as The voltage regulator as described in any one of claims 1-13 has an input coupled to the power rail and an output coupled to the circuit.

15. The chip of claim 14, wherein the circuitry comprises at least one of a modem, logic circuitry, a processor, or a memory.

16. The chip of claim 14, further comprising pads coupled to the power rail.

17. The chip of claim 14, further comprising a reference circuit coupled to a first input of the amplifier, wherein the reference circuit is configured to generate the reference voltage.

18. A method of operating a voltage regulator, wherein the voltage regulator includes a transfer transistor and an amplifier, the transfer transistor being coupled between an input of the voltage regulator and an output of the voltage regulator, the amplifier having a first input coupled to a reference voltage, a second input coupled to the output of the voltage regulator via a feedback path, and an output, the method comprising: During the first time period, a first switch is used to transfer charge between the output of the amplifier and the first terminal of the first capacitor; During the first time period, the voltage of the second capacitor is boosted; During the first time period, charge is transferred between the first terminal of the second capacitor and the output capacitor, wherein the output capacitor is coupled to the gate of the transmission transistor; During the second time period, a second switch is used to transfer charge between the output of the amplifier and the first terminal of the second capacitor; During the second time period, the voltage of the first capacitor is boosted; as well as During the second time period, charge is transferred between the first terminal of the first capacitor and the output capacitor. The voltage regulator mentioned above includes: A voltage source, wherein the voltage source includes a voltage divider coupled between a power supply voltage rail and ground; Control circuit, wherein the control circuit includes: Third capacitor; Fourth capacitor; A first transistor is coupled between the voltage source and a first terminal of the third capacitor; and A second transistor is coupled between the voltage source and the first terminal of the fourth capacitor, wherein the gate of the second transistor is coupled to the source of the first transistor, and the source of the second transistor is coupled to the gate of the first transistor. The first terminal of the third capacitor is coupled to the control input of the first switch, and the first terminal of the fourth capacitor is coupled to the control input of the second switch.

19. The method of claim 18, wherein: The voltage regulator includes: a first switch coupled between the output of the amplifier and a first terminal of the first capacitor, and a second switch coupled between the output of the amplifier and a first terminal of the second capacitor; Transferring charge between the amplifier's output and the first terminal of the first capacitor includes closing the first switch; and Transferring charge between the output of the amplifier and the first terminal of the second capacitor includes closing the second switch.

20. The method of claim 19, further comprising: During the first time period, the second switch is disconnected; as well as During the second time period, the first switch is disconnected.

21. The method according to claim 18, wherein: Boosting the voltage of the first capacitor includes applying a boosted voltage to the second terminal of the first capacitor; and Boosting the voltage of the second capacitor involves applying a boost voltage to the second terminal of the second capacitor.

22. The method of claim 18, wherein: The voltage regulator includes: a third switch coupled between a first terminal of the first capacitor and the output capacitor, and a fourth switch coupled between a first terminal of the second transistor and the output capacitor; Transferring charge between the first terminal of the first capacitor and the output capacitor includes closing the third switch; and Transferring charge between the first terminal of the second capacitor and the output capacitor includes closing the fourth switch.

23. The method according to claim 22, wherein: Closing the third switch includes routing the voltage of the second capacitor to a control input for the third switch; and Closing the fourth switch includes routing the voltage of the first capacitor to the control input of the fourth switch.

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