6-phase digitally-assisted harmonic rejection transceiver using rf interpolation

Abstract

Architectures are presented for transmitters and receivers that use a harmonic rejection mixer that uses a 6-phase clock signal, while also using a differential in-phase / quadrature input signal (for the transmitter) or output signal (for the receiver). This results in crosstalk between the in-phase and quadrature components, where a digital correction circuit forms a linear combination of the baseband I / Q signals to generate the I / Q for the mixer in order to obtain the desired baseband signal. By using a differential I / Q signal, only two DACs / ADCs are needed, saving circuitry area and power consumption, while providing strong 2nd, 3rd, and 4th clock harmonic rejection. The clock signal can be composed of two sets of 3-phase signals, each signal having a 33% duty cycle.

Description

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 032,606, filed May 30, 2020, entitled “6-PHASE DIGITALLY ASSISTED TX / RX HARMONIC USING RF INTERPOLATION” by Al-Qaq et al., the entire contents of which are incorporated by reference. TECHNICAL FIELD

[0002] The present disclosure relates generally to an architecture for reducing unwanted harmonic content in a transceiver. BACKGROUND

[0003] In wireless terminals such as cellular telephones, there are often unwanted local oscillator clock generation harmonics (harmonics) that can interfere with signal processing. On the transmitter side, these harmonics can be mixed back through non-linearities to near the carrier frequency of the desired signal and create near channel distortion and can impact other wireless terminals using the same or near the same carrier frequency. On the receiver side, blocker signals near the desired signal clock harmonic frequencies can fall on top of the desired signal frequency through the down conversion process when mixed back to baseband frequency to reduce the signal to noise ratio and distortion rate of the received signal. It is desirable to reduce the impact of these clock harmonics as much as possible. SUMMARY

[0004] According to one aspect of the disclosure, a transmitter includes an in-phase / quadrature (IQ) signal source, a frequency synthesizer, and a harmonic rejection mixer. The (IQ) signal source is configured to receive a first IQ signal and generate a second IQ signal from the first IQ signal, the second IQ signal being in a differential format having an in-phase component, a quadrature component, an inverse of the in-phase component, and an inverse of the quadrature component, wherein one or both of the in-phase component and the quadrature component of the second IQ signal is a linear combination of the in-phase component and the quadrature component of the first IQ signal. The frequency synthesizer is configured to generate a 6-phase clock signal including a first set of three non-overlapping clock signals having a combined duty cycle of 100% and a second set of three non-overlapping clock signals having a combined duty cycle of 100%. The harmonic rejection mixer includes a first mixing section having a first set of mixers each configured to receive a corresponding clock signal of the first set of clock signals, a first mixer of the first set of mixers being further configured to receive the in-phase component of the second IQ signal, and a second mixer of the first set of mixers being further configured to receive the inverse of the quadrature component of the second IQ signal, and a second set of mixers each configured to receive a corresponding clock signal of the second set of clock signals, a first mixer of the second set of mixers being further configured to receive the quadrature component of the second IQ signal, and a second mixer of the second set of mixers being further configured to receive the inverse of the in-phase component of the second IQ signal. The harmonic rejection mixer is configured to form a first intermediate signal by combining an output of each of the first set of mixers, form a second intermediate signal by combining an output of each of the second set of mixers, and combine the first intermediate signal and the second intermediate signal to form a first output signal with respect to the harmonic rejection mixer.

[0005] Optionally, in the foregoing aspect, a third mixer of the first set of mixers is further configured to have an input connected to ground; and a third mixer of the second set of mixers is further configured to have an input connected to ground.

[0006] Optionally, in the foregoing aspect, a third mixer of the first set of mixers is further configured to have an input connected to ground; and a third mixer of the second set of mixers is further configured to have an input connected to ground.

[0007] Optionally, in the foregoing aspect, the first mixing section further comprises: a third set of mixers each configured to receive a corresponding clock signal of the first set of clock signals and one of components of the second IQ signal; and a fourth set of mixers each configured to receive a corresponding clock signal of the second set of clock signals and one of components of the second IQ signal. The harmonic rejection mixer is further configured to: form a third intermediate signal by combining outputs of each of the third set of mixers; form a fourth intermediate signal by combining outputs of each of the fourth set of mixers; and further combine the third intermediate signal and the fourth intermediate signal with the first intermediate signal and the second intermediate signal to form the first output signal with respect to the harmonic rejection mixer.

[0008] Optionally, in any of the foregoing aspects, the transmitter further comprises a first variable gain amplifier and a second variable gain amplifier. The first variable gain amplifier is configured to: receive the first intermediate signal; and amplify the first intermediate signal prior to combining the first intermediate signal and the second intermediate signal to form the first output signal with respect to the harmonic rejection mixer. The second variable gain amplifier is configured to: receive the second intermediate signal; and amplify the second intermediate signal prior to combining the first intermediate signal and the second intermediate signal to form the first output signal with respect to the harmonic rejection mixer.

[0009] Optionally, in any of the foregoing aspects, the harmonic rejection mixer further comprises a second mixing section comprising: a third set of mixers each configured to receive a corresponding clock signal of the first set of clock signals, a first mixer of the first set of mixers further configured to receive an inverse of an in-phase component of the second IQ signal, and a second mixer of the first set of mixers further configured to receive a quadrature component of the second IQ signal; and a fourth set of mixers each configured to receive a corresponding clock signal of the second set of clock signals, a first mixer of the second set of mixers further configured to receive an inverse of the quadrature component of the second IQ signal, and a second mixer of the second set of mixers further configured to receive the in-phase component of the second IQ signal. The harmonic rejection mixer is configured to: form a third intermediate signal by combining outputs of each of the third set of mixers; form a fourth intermediate signal by combining outputs of each of the fourth set of mixers; and combine the third intermediate signal and the fourth intermediate signal to form the second output signal with respect to the harmonic rejection mixer.

[0010] Optionally, in the foregoing aspect, the transmitter further includes an inductive coupler comprising: a first coil configured to receive a first output signal with respect to the harmonic suppression mixer at a first terminal and a second output signal with respect to the harmonic suppression mixer at a second terminal; and a second coil inductively coupled to the first coil, the second coil having a first terminal configured to provide a single-ended output by the transmitter and a second terminal connected to ground.

[0011] Optionally, in the foregoing aspects, the transmitter also includes a power amplifier configured to receive and amplify the single-ended output.

[0012] Optionally, in the foregoing aspects, the transmitter also includes an antenna configured to receive and transmit single-ended output.

[0013] Optionally, in any of the foregoing aspects, the frequency synthesizer is configured to generate a 6-phase clock signal by generating a first set of clock signals from a voltage-controlled oscillator and by introducing a phase shift into the first set of clock signals to generate a second set of clock signals based on the first set of clock signals.

[0014] Optionally, in any of the foregoing aspects, the IQ signal source includes: a digital correction circuit configured to receive a first IQ signal in digital format and generate a second IQ signal in digital format based on the first IQ signal; a first digital-to-analog converter configured to receive the in-phase component of the second IQ signal in digital format and generate the in-phase component of the second IQ signal in differential analog format based on the in-phase component of the second IQ signal; and a second digital-to-analog converter configured to receive the quadrature component of the second IQ signal in digital format and generate the quadrature component of the second IQ signal in differential analog format based on the quadrature component of the second IQ signal.

[0015] According to another aspect of this disclosure, a method for transmitting a signal is provided, the method comprising: receiving a first in-phase / quadrature (IQ) signal; and generating a second IQ signal based on the first IQ signal, the second IQ signal being in a differential format having an in-phase component, a quadrature component, an out-of-phase in-phase component, and an out-of-phase quadrature component, wherein one or both of the in-phase and quadrature components of the second IQ signal are linear combinations of the in-phase and quadrature components of the first IQ signal. The method further comprises: receiving a six-phase clock signal, the six-phase clock signal comprising a first set of three non-overlapping clock signals having a combined duty cycle of 100% and a second set of three non-overlapping clock signals having a combined duty cycle of 100%; and generating a first output signal based on the second IQ signal and the six-phase clock signal. The first output signal is generated by the following operations: receiving a corresponding clock signal from a first set of clock signals at each mixer in the first set of mixers; receiving the in-phase component of the second IQ signal at the first mixer in the first set of mixers; receiving the out-of-phase component of the quadrature component of the second IQ signal at the second mixer in the first set of mixers; combining the outputs of each mixer in the first set of mixers to form a first intermediate signal; receiving a corresponding clock signal from a second set of clock signals at each mixer in the second set of mixers; receiving the out-of-phase component of the in-phase component of the second IQ signal at the first mixer in the second set of mixers; receiving the quadrature component of the second IQ signal at the second mixer in the second set of mixers; combining the outputs of each mixer in the second set of mixers to form a second intermediate signal; and generating the first output signal by combining the first intermediate signal and the second intermediate signal.

[0016] Optionally, in the foregoing aspects, the first output signal is also generated based on the second IQ signal and the 6-phase clock signal by connecting the input of the third mixer in the first set of mixers to ground; and connecting the input of the third mixer in the second set of mixers to ground.

[0017] Optionally, in the first aspect of the method of transmitting the signal described above, the first output signal is further generated based on the second IQ signal and the 6-phase clock signal by: receiving, at the third mixer in the first set of mixers, the components of the second IQ signal other than the in-phase components and the out-of-phase quadrature components; and receiving, at the third mixer in the second set of mixers, the components of the second IQ signal other than the out-of-phase quadrature components and the out-of-phase components.

[0018] Optionally, in the foregoing aspects, the first output signal is further generated based on the second IQ signal and the 6-phase clock signal by: receiving one of the corresponding clock signal and the second IQ signal components from the first set of clock signals at each mixer in the third set of mixers; combining the outputs of each mixer in the third set of mixers to form a third intermediate signal; receiving one of the corresponding clock signal and the second IQ signal components from the second set of clock signals at each mixer in the fourth set of mixers; and combining the outputs of each mixer in the fourth set of mixers to form a fourth intermediate signal, wherein the first output signal is generated by further combining the third and fourth intermediate signals with the first and second intermediate signals.

[0019] Optionally, in any of the foregoing aspects of the method of transmitting a signal, the method further includes: amplifying the first intermediate signal and the second intermediate signal separately before combining the first intermediate signal with the second intermediate signal to generate the first output signal.

[0020] Optionally, in any of the foregoing aspects of the method of transmitting the signal, the method further includes: generating a second output signal based on the second IQ signal and the 6-phase clock signal by: receiving a corresponding clock signal from the first group of clock signals at each mixer in the third group of mixers; receiving an inverted portion of the in-phase component of the second IQ signal at the first mixer in the third group of mixers; receiving a quadrature component of the second IQ signal at the second mixer in the third group of mixers; combining the outputs of each mixer in the third group of mixers to form a third intermediate signal; receiving a corresponding clock signal from the second group of clock signals at each mixer in the fourth group of mixers; receiving an in-phase component of the second IQ signal at the first mixer in the fourth group of mixers; receiving an inverted portion of the quadrature component of the second IQ signal at the second mixer in the fourth group of mixers; combining the outputs of each mixer in the fourth group of mixers to form a fourth intermediate signal; and generating the second output signal by combining the third intermediate signal with the fourth intermediate signal.

[0021] Optionally, in the foregoing aspects, the method further includes: applying a first output signal and a second output signal to a first terminal and a second terminal of a first coil of an inductive coupler, respectively; receiving and amplifying the output from a second coil of the inductive coupler, the second coil being inductively coupled to the first coil; and transmitting the amplified output.

[0022] Optionally, in any of the foregoing aspects of the method of transmitting signals, the method further includes: generating a 6-phase clock signal by generating a first set of clock signals from a voltage-controlled oscillator; and generating a second set of clock signals based on the first set of clock signals by introducing a phase shift into the first set of clock signals.

[0023] Optionally, in any of the foregoing aspects of the method of transmitting a signal, the method further includes: receiving a first IQ signal in digital format; generating a second IQ signal in digital format based on the first IQ signal in digital format; generating an in-phase component of the second IQ signal in differential analog format based on the in-phase component of the second IQ signal in digital format; and generating a quadrature component of the second IQ signal in differential analog format based on the quadrature component of the second IQ signal in digital format.

[0024] According to another aspect of this disclosure, a receiver includes: a frequency synthesizer configured to generate a six-phase clock signal comprising a first set of three non-overlapping clock signals having a combined duty cycle of 100% and a second set of three non-overlapping clock signals having a combined duty cycle of 100%; a harmonic suppression mixer; and a correction circuit. The harmonic suppression mixer includes a first mixer section comprising: a first set of mixers, each mixer configured to receive and mix a clock signal from a first set of clock signals and an input signal to generate an in-phase component of a differential in-phase / quadrature (IQ) signal in the first mixer of the first set of mixers, and to generate an out-of-phase quadrature component of the differential IQ signal in a second mixer of the first set of mixers; and a second set of mixers, each mixer configured to receive and mix a clock signal from a second set of clock signals and an input signal to generate an out-of-phase component of the differential IQ signal in the first mixer of the second set of mixers, and to generate an out-of-phase component of the differential IQ signal in the second mixer of the second set of mixers. The correction circuit is configured to receive components of the differential IQ signal and generate a baseband IQ signal based on the components of the differential IQ signal, wherein one or both of the in-phase and quadrature components of the baseband IQ signal are linear combinations of the components of the differential IQ signal.

[0025] Optionally, in the foregoing aspects, the third mixer in the first group of mixers is further configured to have an output terminal connected to ground; and the third mixer in the second group of mixers is further configured to have an output terminal connected to ground.

[0026] Optionally, in the first aspect above for the receiver, the third mixer in the first set of mixers is further configured to generate a differential IQ signal other than the out-of-phase components of the in-phase and quadrature components; and the third mixer in the second set of mixers is further configured to generate a differential IQ signal other than the out-of-phase components of the quadrature and in-phase components.

[0027] Optionally, in any of the foregoing aspects of the receiver, the receiver further includes: one or more low-noise amplifiers configured to: receive and amplify the input signal; and supply the amplified input signal to a harmonic suppression mixer.

[0028] Optionally, in the foregoing aspects, one or more low-noise amplifiers are configured to provide amplified input signals as differential outputs, and the first mixer receives the positive-side output of the low-noise amplifier. The harmonic suppression mixer further includes a second mixer comprising: a first group of three mixers, each mixer configured to receive and mix one clock signal from the first group of clock signals with the negative-side output of the low-noise amplifier to generate an out-of-phase component of the in-phase differential IQ signal in the first mixer of the first group of mixers, and to generate a quadrature component of the differential IQ signal in the second mixer of the first group of mixers; and a second group of mixers, each mixer configured to receive and mix one clock signal from the second group of clock signals with the negative-side output of the low-noise amplifier to generate an out-of-phase component of the quadrature component of the differential IQ signal in the first mixer of the second group of mixers, and to generate an in-phase component of the differential IQ signal in the second mixer of the second group of mixers.

[0029] Alternatively, in either of the aforementioned two aspects of the receiver, the receiver further includes an antenna configured to receive the input signal and supply it to one or more low-noise amplifiers.

[0030] Alternatively, in any of the foregoing aspects for the receiver, the frequency synthesizer is configured to generate a 6-phase clock signal by generating a first set of clock signals from a voltage-controlled oscillator and by introducing a phase shift into the first set of clock signals to generate a second set of clock signals based on the first set of clock signals.

[0031] Optionally, in any of the foregoing aspects for the receiver, the correction circuit includes: a first analog-to-digital converter configured to receive the in-phase component of a differential IQ signal in analog format and generate an in-phase component of an input IQ signal in digital format based on the in-phase component of the differential IQ signal; a second analog-to-digital converter configured to receive the quadrature component of the differential IQ signal in analog format and generate a quadrature component of the input IQ signal in digital format based on the quadrature component of the differential IQ signal; and a digital correction circuit configured to receive the input IQ signal in digital format and generate a baseband IQ signal based on the input IQ signal.

[0032] According to another aspect of this disclosure, a method for receiving a signal is provided, the method comprising: receiving an input signal; receiving a six-phase clock signal, the six-phase clock signal comprising a first group of three non-overlapping clock signals having a combined duty cycle of 100% and a second group of three non-overlapping clock signals having a combined duty cycle of 100%; and generating a baseband IQ signal based on the input signal. Generating the baseband IQ signal includes: receiving a corresponding clock signal and an input signal from a first set of clock signals at each mixer in the first set of mixers; generating an in-phase component of a differential in-phase / quadrature (IQ) signal in the first mixer in the first set of mixers; generating an out-of-phase quadrature component of the differential IQ signal in the second mixer in the first set of mixers; receiving a corresponding clock signal from a second set of clock signals and the input signal at each mixer in the second set of mixers; generating a quadrature component of the differential IQ signal in the first mixer in the second set of mixers; generating a quadrature component of the differential IQ signal in the second mixer in the second set of mixers; and generating the baseband IQ signal based on the components of the differential IQ signal, wherein one or both of the in-phase and quadrature components of the baseband IQ signal are a linear combination of the components of the differential IQ signal.

[0033] Optionally, in the foregoing aspects, the baseband IQ signal is also generated by: setting the output of the third mixer in the first set of mixers to ground; and setting the output of the third mixer in the second set of mixers to ground.

[0034] Optionally, in the first aspect of the method for receiving signals described above, the baseband IQ signal is further generated by: generating components of the differential IQ signal other than the in-phase component and the out-of-phase quadrature component in a third mixer in a first set of mixers; and generating components of the differential IQ signal other than the out-of-phase quadrature component and the out-of-phase component in a third mixer in a second set of mixers.

[0035] Optionally, in the foregoing aspects, the baseband IQ signal is further generated by: receiving a corresponding clock signal and an input signal from the first set of clock signals at each mixer in the third set of mixers; generating a component of the differential IQ signal in each mixer in the third set; receiving a corresponding clock signal and an input signal from the second set of clock signals at each mixer in the fourth set of mixers; and generating a component of the differential IQ signal in each mixer in the fourth set of mixers.

[0036] Optionally, in any of the foregoing aspects of the method of receiving a signal, the method further includes: amplifying the input signal in one or more low-noise amplifiers; and supplying the amplified input signal from one or more low-noise amplifiers to a first set of mixers and a second set of mixers.

[0037] Optionally, in the foregoing aspects, one or more low-noise amplifiers are configured to provide the amplified input signal, which is a differential output, as the positive-side output of the low-noise amplifier to the first and second mixers. The baseband IQ signal is also generated according to the input signal by: receiving a corresponding clock signal from the first set of clock signals and the negative-side output of the low-noise amplifier at each mixer in the third mixer; generating an inverted version of the in-phase component of the differential IQ signal in the first mixer in the third mixer; generating a quadrature component of the differential IQ signal in the second mixer in the third mixer; receiving a corresponding clock signal from the second set of clock signals and the input signal at each mixer in the fourth mixer; generating a quadrature component of the differential IQ signal in the first mixer in the fourth mixer; and generating an inverted version of the quadrature component of the differential IQ signal in the second mixer in the fourth mixer.

[0038] Alternatively, in either of the foregoing aspects, the method of receiving a signal further includes: receiving an input signal from an antenna and supplying the input signal to one or more low-noise amplifiers.

[0039] Optionally, in any of the foregoing aspects of the method of receiving signals, receiving the 6-phase clock signal includes: generating a first set of clock signals from a voltage-controlled oscillator; and generating a second set of clock signals based on the first set of clock signals by introducing a phase shift into the first set of clock signals.

[0040] Optionally, in any of the foregoing aspects of the method of receiving the signal, generating the baseband IQ signal based on the components of the differential IQ signal includes: receiving the in-phase component of the differential IQ signal in analog format, and generating the in-phase component of the input IQ signal in digital format based on the in-phase component of the differential IQ signal; receiving the quadrature component of the differential IQ signal in analog format, and generating the quadrature component of the input IQ signal in digital format based on the quadrature component of the differential IQ signal; and receiving the input IQ signal in digital format and generating the baseband IQ signal based on the input IQ signal.

[0041] This summary is provided to present a series of concepts in a simplified form, which will be further described in the detailed description below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that address any or all the shortcomings pointed out in the background art. Attached Figure Description

[0042] Various aspects of this disclosure are shown by way of example and are not limited to the accompanying drawings, in which similar reference numerals indicate elements.

[0043] Figure 1A wireless network used for transmitting data is shown.

[0044] Figure 2 It is possible in, for example Figure 1 A block diagram of the wireless communication system used in the network.

[0045] Figure 3 This is a block diagram of a first embodiment of a 6-phase digitally assisted harmonic suppression transmitter that uses RF interpolation to improve harmonic suppression.

[0046] Figure 4 It shows Figure 3 The 6-phase frequency synthesizer block is used as an implementation of a dual 3-phase frequency synthesizer.

[0047] Figure 5 It shows from Figure 4 Timing diagram of each clock and its duty cycle of the frequency synthesizer block.

[0048] Figure 6 It shows the use of Figure 3 The simulation results show the performance of the power amplifier in the proposed implementation.

[0049] Figure 7 It is shown that it is used for, for example Figure 3 A flowchart of the first embodiment of the operation of the transceiver in the implementation method.

[0050] Figure 8 This is a block diagram of a first embodiment of a 6-phase digitally assisted harmonic suppression receiver that uses RF interpolation to improve harmonic suppression.

[0051] Figure 9 It is shown that it is used for, for example Figure 8 A flowchart illustrating the implementation of the receiver's operation in the proposed implementation.

[0052] Figure 10 An alternative implementation of the receiver using RF interpolation and overlapping 6-phase clocks is presented.

[0053] Figure 11 It shows the use of Figure 10 The simulation results show the performance at the output of the power amplifier in the proposed implementation.

[0054] Figure 12 Is with Figure 10 An alternative implementation of the receiver using digital compensation to correspond to the transmitter implementation.

[0055] Figure 13 and Figure 14 Another set of alternative implementations of the transmitter and receiver is presented. Detailed Implementation

[0056] This disclosure will now be described with reference to the accompanying drawings. This disclosure generally relates to techniques for reducing unwanted harmonic content from transmitters and receivers. An implementation of a 6-phase digitally assisted harmonic suppression transmitter and receiver using RF interpolation is presented. The transmitter and receiver include a harmonic suppression mixer that uses a 6-phase clock signal, along with differential in-phase / quadrature (I / Q) input signals for the transmitter path and an output signal for the receiver path. This causes crosstalk between the in-phase and quadrature components. To obtain the desired baseband signal and remove crosstalk, a digital correction circuit forms a linear combination of the baseband I / Q signals to generate differential I / Q signals for the mixer. By using differential I / Q signals, only two DAC / ADCs are required, saving circuit area and power consumption, while providing strong second, third, and fourth clock harmonic suppression. The clock signal can consist of two sets of 3-phase signals, each with a 33% duty cycle.

[0057] It should be understood that the present embodiments of this disclosure can be implemented in many different forms, and the scope of the claims should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art. In fact, this disclosure is intended to cover alternatives, modifications, and equivalents of these embodiments included within the scope and spirit of this disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present embodiments of this disclosure, numerous specific details are set forth in order to provide a thorough understanding. However, it will be apparent to those skilled in the art that embodiments of this disclosure can be practiced without such specific details.

[0058] Figure 1 A wireless network for transmitting data is shown. Communication system 10 includes, for example, user equipment 11A to 11C, radio access networks (RANs) 12A to 12B, a core network 13, a public switched telephone network (PSTN) 14, the Internet 15, and other networks 16. Additional or alternative networks include private and public packet networks—including corporate intranets. Although a specific number of these components or elements are shown in the figure, any number of these components or elements may be included in system 10.

[0059] In one implementation, the wireless network may be a fifth-generation (5G) network including at least one 5G base station that communicates with the communication device using orthogonal frequency-division multiplexing (OFDM) and / or non-OFDM and a transmission time interval (TTI) of less than 1 millisecond (ms) (e.g., 100 microseconds or 200 microseconds). Generally, the reference to a base station can refer to either an eNB or a 5G base station (gNB). Furthermore, the network may also include a network server for processing information received from the communication device via at least one eNB or gNB base station.

[0060] System 10 enables multiple wireless users to send and receive data and other content. System 10 can implement one or more channel access methods, such as, but not limited to, code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA).

[0061] User equipment (UE) 11A to 11C are configured to operate and / or communicate in system 10. For example, UE 11A to 11C are configured to transmit and / or receive wireless or wired signals. Each UE 11A to 11C represents any suitable end-user device and may include (or be referred to as) a device such as: user equipment / device, wireless transceiver unit (UE), mobile station, fixed or mobile subscriber unit, cellular phone, personal digital assistant (PDA), smartphone, laptop computer, computer, touchpad, wireless sensor, wearable device, or consumer electronics device.

[0062] In the depicted implementation, RANs 12A to 12B each include one or more base stations 17A, 17B (collectively referred to as base stations 17). Each of the base stations 17 is configured to wirelessly interface with one or more UEs 11A, 11B, 11C to enable access to the core network 13, PSTN 14, Internet 15, and / or other networks 16. For example, a base station (BS) 17 may include one or more of the following well-known devices: such as a base transceiver station (BTS), a Node-B (NodeB), an evolved NodeB (eNB), a next-generation (5G) NodeB (gNB), a home NodeB, a home eNodeB, a site controller, an access point (AP), or a wireless router, or a server, router, switch, or other processing entity with wired or wireless networks.

[0063] In one implementation, base station 17A forms part of RAN 12A, which may include other base stations, elements, and / or devices. Similarly, base station 17B forms part of RAN 12B, which may include other base stations, elements, and / or devices. Each of the base stations 17 operates to transmit and / or receive radio signals within a specific geographic area or region—sometimes referred to as a “cell.” In some implementations, multiple-input multiple-output (MIMO) technology with multiple transceivers for each cell may be employed.

[0064] Base station 17 communicates with one or more user equipment 11A to 11C via one or more air interfaces (not shown) using wireless communication links. The air interfaces can utilize any suitable wireless access technology.

[0065] It is conceivable that system 10 may use multi-channel access capabilities, including, for example, schemes in which base station 17 and user equipment 11A to 11C are configured to implement Long Term Evolution (LTE), LTE Advanced (LTE-A), and / or LTE Multimedia Broadcast Multicast Service (MBMS). In other embodiments, base station 17 and user equipment 11A to 11C are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and radio protocols may be utilized.

[0066] RANs 12A to 12B communicate with core network 13 to provide voice, data, application, Voice over Internet Protocol (VoIP), or other services to user equipment 11A to 11C. It should be understood that RANs 12A to 12B and / or core network 13 can communicate directly or indirectly with one or more other RANs (not shown). Core network 13 can also serve as a gateway access for other networks (e.g., PSTN 14, Internet 15, and other networks 16). Furthermore, some or all of user equipment 11A to 11C may include functionality for communicating with different wireless networks via different wireless links using different wireless technologies and / or protocols.

[0067] RANs 12A to 12B may also include millimeter and / or microwave access points (APs). An AP may be part of base station 17 or may be located remotely from base station 17. An AP may include, but is not limited to, a connection point (millimeter wave, or mmW, CP) or a base station 17 capable of mmW communication (e.g., an mmW base station). An mmW AP may transmit and receive signals in a frequency range, for example, from 24 GHz to 100 GHz, but is not required to operate across that entire range. As used herein, the term "base station" is used to refer to a base station and / or a wireless access point.

[0068] although Figure 1 An example of a communication system is shown, but it is possible to... Figure 1Various modifications can be made. For example, the communication system 10 may include any number of user equipment, base stations, networks, or other components in any suitable configuration. It should also be understood that the term "user equipment" can refer to any type of wireless device that communicates with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are target devices, device-to-device (D2D) user equipment, machine-type user equipment or user equipment capable of machine-to-machine (M2M) communication, laptop computers, PDAs, iPads, tablet computers, mobile terminals, smartphones, laptop embedded equipped (LEE), laptop mounted equipment (LME), and USB dongles.

[0069] Figure 2 This is a block diagram of a wireless communication system 100, such as a mobile phone or user equipment 11A to 11C or a base station 17, showing some of the elements discussed with respect to the following figures. To transmit an output signal from the circuitry of processor 111, transmitter (Tx) RF / analog unit 101, according to the configuration of Tx digital baseband block 107, upconverts the output signal from the baseband or intermediate frequency (IF) range to the radio frequency (RF) range, and also amplifies and filters the transmitted signal before supplying it to antenna 105. Transmitter (Tx) RF / analog unit 101 can also be configured to perform other processes to prepare the transmitted signal. The output signal generated by Tx digital baseband block 107 is in phase / quadrature (I / Q) format as an in-phase signal I. Tx and the quadrature signal Q Tx Provided to Tx RF / Analog Unit 101. Although Tx Digital Baseband Block 107 is... Figure 2 The components are shown as separate blocks from the Tx RF / analog section 101, but according to the implementation, these components may be combined differently as circuit elements and implemented in hardware, firmware, software or a combination thereof.

[0070] The signal is received by antenna 105 and supplied to receiver (Rx) RF / analog unit 102. Before transmitting the signal to other components on the device represented by processor 111, Rx unit 102 performs any necessary or desired signal processing, such as down-conversion from the radio frequency (RF) range to the intermediate frequency (IF) range and filtering. Figure 2In this embodiment, the output of the Rx RF / analog unit 102 is in I / Q format, while the Rx digital baseband unit 117 converts the output of the Rx RF / analog unit 102 into a receive signal supplied to the processor. Although in Figure 2 The Rx digital baseband section 117 is shown as a separate block from the Rx RF / analog section 102, but according to embodiments, these components can be combined differently as circuit elements and implemented in hardware, firmware, software, or a combination thereof. Furthermore, although Figure 2 The Tx RF / analog section 101 and the Rx RF / analog section 102 are represented as separate elements; however, depending on the implementation, the transmitter path and receiver path may share many elements or be implemented as a combined transceiver. In the following text, "transceiver" can generally be used to refer to a combined transmitter / receiver, separate transceiver and receiver sections, or an implementation where one or more components (e.g., a local oscillator) are shared between the transmitter and receiver.

[0071] In transceivers such as mobile phones, there are often undesirable clock harmonics generated from the local oscillator. On the transmitter side, these clock harmonics can be non-linearly mixed back to frequencies close to the desired signal, producing near-channel distortion (e.g., CIM2, CIM3, CIM5, where CIMx is the x-th order counter intermodulation) and also affecting other nearby wireless terminals using the nearby carrier frequency. On the receiver side, during current switching, blocking signals near the clock harmonic frequencies of the desired signal may fall on top of the desired signal frequency when mixed back to the baseband frequency, degrading the received signal. Therefore, it is desirable to minimize the effects of these undesirable clock harmonics as much as possible.

[0072] Typically, some of these unwanted harmonics can be removed through multiphase (N-phase) mixer design, with appropriate selection of N, where a higher value of N removes more harmonics. For example, in a typical analog IF interpolation method, the transmitter or receiver can use two analog-to-digital converters (ADCs) and two digital-to-analog converters (DACs) with two IF circuitry pairs. This method relies on an IF resistor interpolation network between the IF and RF stages for 4-phase to N-phase conversion in the transmitter path (or N-phase to 4-phase for the receiver). This resistor interpolation network typically introduces increased noise and power consumption due to mixer switching loads. Typical digital interpolation uses N / 2 DAC / ADC and N / 2 IF pairs (e.g., for a 6-phase transmitter harmonic suppression system, three DAC and IF pairs would be required). This results in increased IF area requirements and power consumption. Digital interpolation offers good performance, but this performance is excessive and, in many cases, comes at the cost of increased IF area / power. The following implementation addresses the increased IF area / power in digital interpolation by requiring only two DAC / ADC / IF pairs, and uses the concept of RF interpolation to mitigate the increased power and noise caused by analog IF interpolation.

[0073] The following describes an implementation of a transmitter and receiver, along with a Harmonic Rejection Mixer (HRM) mixer architecture that uses mixer switches to perform RF interpolation and then applies digital compensation to correct any generated in-phase / quadrature (I / Q) crosstalk. This approach can be used with equally weighted or unweighted, and piecewise or unpiecewise variable gain amplifiers (in the transmitter path) and low-noise amplifiers (in the receiver path). The following discussion is primarily presented in the context of a 6-phase (or dual 3-phase) transmitter and receiver implementation. Six phases offer the opportunity to use 1.5x local oscillator (LO) clock generation for the Ultra-High Band (UHB), as opposed to the 2x LO clock generation of a 4-phase system. This provides power savings when dealing with LO generation in the sub-8 GHz 5G UHB band.

[0074] Figure 3 This is a block diagram of a first embodiment of a 6-phase digitally assisted harmonic suppression transmitter that uses RF interpolation to improve harmonic suppression. Considering a higher level... Figure 3 IQ Source 107—it can Figure 2The Tx digital baseband block 107 internally generates—provides the signal to be transmitted. The signal from the IQ source 107 is in I / Q format and, as described below, is converted into differential I / Q in the signal source 241. The differential I / Q components provide the source signal to the harmonic suppression block HRM 200. A frequency synthesizer block 230 with a phase-locked loop 233 having a voltage-controlled oscillator (VCO) 231 that powers a 6-phase signal generator 235 provides the clock signal to the HRM 200. The output of the HRM 200 is supplied to the antenna 105 through a set of variable gain amplifiers VGA 221-i and VGA 223-i, an inductive coupler 251, a power amplifier PA 253, and a filter 255.

[0075] Figure 4 It shows Figure 3 The 6-phase frequency synthesizer block is presented as one implementation of a dual 3-phase frequency synthesizer. The different implementations presented below will primarily rely on the use of... Figure 5 The diagram shows a 6-phase 33% duty cycle overlapping clock signal. However, it should be noted that the technique described herein is also applicable to other duty cycle overlapping or non-overlapping clock arrangements.

[0076] In use Figure 4 In the frequency synthesizer 230 block of the embodiment, VCO 231 may be part of phase-locked loop (PLL) 233. The VCO can operate at a frequency fVCO = 1.5 * fLO, where fLO is the local oscillator or carrier frequency. The VCO output is fed to a first 3-phase clock generation block 435 to generate clk0, clk120, and clk240. The VCO output is also fed to a 90-degree phase shift block 437 and then to a second 3-phase generation block 439. Since the 3-phase generation block 439 is essentially a division by 1.5 operation, the initial 90-degree phase shift becomes 60 degrees at the final carrier frequency, meaning that clk60, clk180, and clk300 will be generated in block 439. For all six clocks (clk0, clk120, clk240, clk60, clk180, and clk300), in this embodiment, each clock has a duty cycle of 33.33%, such that the three clock signals from each of the generating blocks 435 and 439 are non-overlapping and add together to 100%, but the clocks forming different blocks overlap.

[0077] Figure 5 This is a timing diagram showing each clock from the frequency synthesizer block 230 and its duty cycle in one embodiment. (See diagram for example.) Figure 5As shown, clk0, clk120, and clk240 form the first set of non-overlapping signals for the three-phase clock signals, and clk60, clk180, and clk300 form the second set of non-overlapping signals for the three-phase clock signals. By combining all six clocks, they become overlapping clocks.

[0078] Return to Figure 3 In the IQ signal path, the IQ data from IQ source 107 has IQ components. bb and Q bb The baseband I / Q signal is supplied to the digital correction block 243, as described in more detail below, which adjusts the I / Q signal according to the baseband I / Q signal. bb and Q bb A linear combination of the pairs forms a differential I / Q signal with I and Q components. Digital-to-analog converters DAC_I 245-1 and DAC_Q 245-2 then convert the digital (I, Q) pairs into analog signals, which are then filtered by low-pass filters LPF_I 247-1 and LPF_Q 247-2 to remove unwanted distortion and noise. Typically, the DACs and LPFs are relatively unaffected by other noise sources within the transceiver. This means that in addition to the I (0-degree phase) and Q (90-degree phase) signals, complementary signals Ib (180-degree phase) and Qb (270-degree phase) are created and provided to the HRM 200. Components 107, 243, 245-1, 245-2, 247-1, and 247-2 together form the differential I / Q signal source 241. Note that although a 6-phase clock signal is used, only two DACs are used to provide the input signal.

[0079] The two p-side intermediate outputs of the HRM 200 each go to the corresponding one of VGA 221-1 or VGA 221-2. The inputs of each of these VGAs are combined outputs from a set of three mixers, each receiving one of a set of clock signals with phase (0°, 120°, 240°) or phase (60°, 180°, 300°): VGA221-1's inputs are combined outputs from mixer 201 receiving input signals I and clk0, mixer 202 having a ground input and receiving clk120, and mixer 203 receiving input signals Qb and clk240, these outputs being combined to produce a first p-side intermediate output; and VGA 221-2's inputs are combined outputs from mixer 204 receiving input signals Q and clk60, mixer 205 having an input connected to ground and receiving clk300, and mixer 206 receiving input signals Ib and clk180, these outputs being combined to produce a second p-side intermediate output. Because mixers 202 and 205 have their inputs connected to ground, they act as dummy mixers in this embodiment. As mentioned above, each clock signal in each group has a 1 / 3 or 33% duty cycle and is non-overlapping, but the sum of each group together is 100%. In summary, as Figure 5 As shown in the implementation method, the two sets of three clock signals that make up the 6-phase signal overlap.

[0080] A similar arrangement is used for the n-side intermediate outputs of the HRM 200, each n-side intermediate output going to one of the corresponding VGA 223-1 or VGA 223-2. The input of each of these VGAs is a combined output from a set of three mixers, each mixer receiving one clock signal from the same set of clock signals on the n-side, and except for the pseudo-mixer, now receiving the inverted version of the corresponding input: the input of VGA 223-1 is a combined output from mixer 211 receiving Ib and clk0, pseudo-mixer 212 receiving clk120, and mixer 213 receiving Q and clk240, to produce the first n-side intermediate output; and the input of VGA 221-2 is a combined output from mixer 214 receiving Qb and clk60, pseudo-mixer 215 receiving clk300, and mixer 216 receiving I and clk180, to produce the second n-side intermediate output. As mentioned above, each of these clock signals has a duty cycle of 1 / 3 or 33% and is non-overlapping, but each group together adds up to 100%.

[0081] The RF intermediate output from the p-side mixer is amplified and combined by VGAs 221-1 and 221-2 to provide the p-side output signal from the HRM 200, and similarly, the RF intermediate output from the n-side mixer is amplified and combined by VGAs 223-1 and 223-2 to provide the n-side output signal from the HRM 200. To convert the RF output from the VGAs to a single-ended output, an inductive coupler 251 can be used, wherein the combined p-side output and the combined n-side output are connected across a first coil and a second coil of the inductive coupler 251, one side of which is grounded and the other side provides a single-ended signal at the output. A power amplifier PA 253 amplifies the single-ended output and filters the PA output through an RF filter 255 to remove unwanted distortion. Finally, the filtered RF output is fed to antenna 105 for transmission.

[0082] Typically, the mixer within the HRM 200 is a passive mixer used in cellular applications, meaning that overlapping clocks can introduce crosstalk between different paths. To avoid this, such as Figure 3 As shown, segmented VGA 221-1, 221-2, 223-1, and 223-2 can be used to make each individual path have a non-overlapping clock.

[0083] Figure 3 The implementation method uses information about Figure 5 The discussion focuses on the transmitter RF interpolation of the overlapping 6-phase 33% duty cycle clocks. Pseudo-mixers 202, 205, 212, and 215 are used to ensure proper cyclic switching across all clock phases. In other words, the added clock cycles for each segmented VGA (221-1, 221-2, 223-1, and 223-2) should add up to 100% of the full cycle. Using pseudo-mixers allows the total number of mixers to be reduced to 12 (compared to the implementation discussed later), but may affect the output transmitter noise falling within the nearby receive band. This makes this configuration more suitable for time-division multiplexing (TDD) UHB bands, where receive band noise is not a concern. Although Figure 3 The implementation shows equally weighted VGAs (i.e., VGAs with the same gain), but the method can also be applied to cases where segmented VGAs are designed to have unequal gains.

[0084] Regarding digital correction block 243, I and Q are the differential analog I / Q waveforms at the outputs of I and Q DACs LPF_I 247-1 and LPF_Q 247-2, respectively. Assuming the unity-gain passive mixer and VGA are used for illustrative purposes only (and without loss of generality), it can be shown that the RF output complex envelope (Vout) of this embodiment is given by the following equation:

[0085] Vout=I+1 / 2*Q+j*sqrt(3) / 2*Q.

[0086] From the above equations, it is clear that a portion of the Q signal (highlighted in bold) leaks into the (in-phase) I path. Furthermore, note that the expected I and Q terms are not scaled equally. This I / Q crosstalk can be digitally compensated within the Tx digital front end (DFE) before the DAC input by the digital correction block 243.

[0087] The digital compensation applied in this case is shown in digital correction block 243 and is a linear combination:

[0088] I = I bb *sqrt(3) / 2-Q bb / 2; and

[0089] Q = Q bb .

[0090] In the above, I bb and Q bb These are the "ideal" transmitter digital baseband I / Q signal components from source 107, and they are the intended I / Q signals to be transmitted. Using this correction factor, Vout = sqrt(3) / 2(I bb +j*Q bb Besides the normalization factor, it is I bb +j*Q bb The desired output of the baseband I / Q signal.

[0091] Figure 3 The transmitter can provide 2nd, 3rd, and 4th clock harmonic suppression. A 6-phase implementation using a 33% duty cycle suppresses the 2nd and 4th harmonics because each of the three-phase (0, 60, and 120) LO clocks has its corresponding equally weighted differential pair (180, 240, and 300) LO clocks. This ensures 2nd and 4th harmonic cancellation. Furthermore, since a 33% duty cycle LO clock naturally does not contain 3rd harmonic content, the 3rd harmonic content is suppressed. Figure 6Simulations demonstrate the performance of this RF interpolation HRM architecture at the PA 253 output. With proper impairment management, performance comparable to a standard 6-phase HRM can be achieved. Figure 3 In the transmitter chain of the implementation, PA 253 is shown as a single-ended design, which means that it has strong even-order nonlinearity, resulting in some second harmonics introduced by the power amplifier being converted to CIM2.

[0092] Figure 6 It shows the use of Figure 3 The simulation results show the performance at the output of the power amplifier in this implementation method. More specifically, Figure 6 The graph, plotted in decibels (dB), shows the output of the 6-phase power amplifier as a function of frequency, normalized to achieve the desired transmitter (Tx) signal at 0 dB. Figure 6 In the curve graph, for the purpose of rapid simulation, the desired signal frequency (approximately 1.2288 x 10⁻⁶) is... 8 (Hz) was chosen as a frequency lower than the actual RF target frequency. In addition to the expected Tx signal, at slightly lower frequencies, the peak value was reduced by about -60dB due to LO leakage, and by more than -80dB due to image distortion.

[0093] Regarding harmonics, and intermodulation of a second-order counter, Figure 6 The peak value on the positive CIM2p side decreased by -90 dB. No other significant spikes were observed. Therefore, Figure 6 Simulation results show that the output performance of the PA253 power amplifier in the 6-phase digitally assisted harmonic suppression transceiver using RF interpolation is comparable to that of a standard 6-phase HRM. The system's spectrum demonstrates that all CIM distortion levels are sufficiently low for cellular applications.

[0094] Figure 7 It shows how to use such Figure 3 A flowchart of the first embodiment of the transceiver operation in the implementation is provided. At 701, an initial baseband I / Q signal (Ibb, Qbb) is received from IQ source 107. At 703, an input signal for HRM200 is generated from signal source 241. Digital correction block 243 adjusts the input signal based on the source baseband I / Q signal (Ibb, Qbb). bb Q bb A linear combination of these signals forms the I / Q signal pair (I, Q) provided to the HRM200. Figure 3 In this implementation, the differential signal pairs I, Ib and Q, Qb are generated by DACs 245-1, 245-2 and LPFs 247-1, 247-2 from the I / Q signals from the correction block 243.

[0095] At position 705, frequency synthesizer 230 generates the LO clock signal, and HRM 200 receives the LO clock signal. The LO clock signal includes the information described above. Figure 5 The 6-phase clock signal shown, in which, regarding Figure 4 In the illustrated embodiment, these 6-phase clock signals can be three components of the first 3-phase clock signal generator 435 and three components of the second 3-phase clock signal generator 439. Figure 4 In the implementation, the first three-phase clock signal is all the clock signals Clk0, Clk120, and Clk240 with a 1 / 3 duty cycle from generator block 435, and the second three-phase clock signal is offset by 60 degrees relative to the first three-phase signal and is all the clock signals Clk60, Clk180, and Clk300 with a 1 / 3 duty cycle from generator block 439. Although Figure 7 The flowchart presents its elements in a specific order, but it should be understood that these can all be executed simultaneously (i.e., 701, 703, and subsequent elements are performed concurrently during the operation) to achieve [the desired result]. Figure 3 The circuit generates an output signal while transmitting.

[0096] At position 707, the clock signal of the first group of clock signals is mixed with the input I component and Qb component of the input signal. For example, in Figure 3 In this implementation, in the first set of mixers on the p-side of the HRM 200, the clock signal components (0, 240) are mixed with components (I, Qb) in mixers 201 and 203, respectively, wherein the clock signal component clk120 is used by the pseudo mixer 202. In the alternative implementation presented below, mixer 202 may also receive the I / Q signal components instead of grounding its signal input. At 709, the outputs of mixers 201, 202, and 203 are combined to form a first intermediate signal for the p-side, which is then amplified in the VGA 221-1.

[0097] Executions 711 and 713 are performed simultaneously with 707 and 709. At 711, the second set of clock signals is mixed with the Ib and Q components of the input signal. For example, in Figure 3 In the implementation, in the second set of mixers on the p-side of the HRM 200, clock signals (clk60, clk180) are mixed with (Q, Ib) signals in mixers 204 and 206, respectively. Mixer 205 is a pseudo-mixer that receives the clk300 clock signal and has a ground signal input. In the alternative implementation presented below, mixer 205 can also receive components of the differential I / Q input signals. At 713, the outputs of mixers 204, 205, and 206 are combined to form a second intermediate signal for the p-side, which is then amplified in the VGA 221-2.Figure 3 In the two-sided implementation shown, two n-sided intermediate outputs are generated as described above to supplement the p-sided processes 707 to 713.

[0098] At position 715, the first intermediate signal and the second intermediate signal are combined to generate the signal at position 715. Figure 3 The two-sided implementation describes the output signal on the p-side of the HRM 200. After amplifying the intermediate signal, the outputs of VGA 221-1 and 221-2 are combined to provide the output signal on the p-side of the HRM 200. Figure 3 In the two-sided implementation, the middle output on the n-side will be similarly combined to provide an output signal on the n-side of the HRM 200.

[0099] Then, the output signal is sent in 717. Similar to... Figure 3 In the two-sided implementation, the p-side output and n-side output are converted to a single-sided output at the coil of the inductive coupler 251. Then, the single-sided output is amplified in the power amplifier PA 253, filtered at the filter 255, and then transmitted from the antenna 105.

[0100] The implementation of receiver configuration can be similar to Figure 3 The transmitter configuration is reversed; that is, the variable gain amplifier is replaced by a low-noise amplifier and the DAC is replaced by an ADC. Similar to the transmitter case, I / Q crosstalk also occurs when RF interpolation is applied to the receiver, and digital compensation can be used to extract the desired baseband I / Q signals. Figure 8 As shown in the implementation, the corresponding digital baseband compensation can be completed within the receiver's digital front end and applied to the ADCI / Q output.

[0101] Figure 8 This is a block diagram of an implementation of a 6-phase receiver system that suppresses blocking at or near the 2nd, 3rd, and 4th clock harmonics. Roughly speaking, except for signal path reversal, Figure 8 The overall structure of the receiver implementation is similar to Figure 3 The transmitter implementation is described above. In the receiver implementation presented herein, a segmented low noise amplifier (LNA) is used to avoid overlapping crosstalk.

[0102] More specifically, the frequency synthesizer 830 can have the same characteristics as... Figure 3 The frequency synthesizer 230 has the same or similar structure, wherein the VCO 831, PLL 833 and 6-phase generator block 835 can operate as described above with respect to the corresponding elements 231, 233 and 235.

[0103] The HRM 700 no longer receives differential I / Q input signals; instead, it generates differential I / Q outputs. Figure 8 Again, this is a two-sided implementation. The complementary output signal pairs (I, Ib) and (Q, Qb) act as differential inputs to a set of low-pass filters and analog-to-digital converters. More specifically, the (I, Ib) pair is a differential input to LPF_I 847-1, and its output goes to ADC_I 845-1 to give the (single-ended) in-phase component of that output. Similarly, the (Q, Qb) pair is a differential input to LPF_Q 847-2, and its output goes to ADC_Q 845-2 to give the (single-ended) quadrature component of the 3-phase output. Then, similar to the above process for the reverse process in correction block 243, digital correction block 843 uses a linear combination of the input I / Q signal components (I, Q) to extract the baseband I / Q signal components (Ibb, Qbb).

[0104] The input to HRM 800 comes from segmented LNAs 821-1 and 821-2 on the p-side and LNAs 823-1 and 823-2 on the n-side, each LNA being connected to receive signals from antenna 105 via RF filter 855. An alternative implementation may use a pair of LNAs with differential outputs, each LNA having a p-side output leading to a p-side mixer in the corresponding group of HRM 800 and an n-side output leading to an n-side mixer in the corresponding group of HRM 800.

[0105] Within the HRM 800, the p-side output from LNA 821-1 goes to the first set of p-side mixers 801, 802, and 803 to be mixed with clk0, clk120, and clk240 respectively, generating output component I in 801 and output component Qb in 803, where 802 is a pseudo-mixer with a grounded output. On the n-side, the output from LNA 823-1 goes to the first set of n-side mixer pairs 811, 812, and 813 to be mixed with clk0, clk120, and clk240 respectively, generating output component Ib, a grounded pseudo-output, and Q.

[0106] Similarly, the p-side output from LNA 821-2 goes to a set of p-side mixers 804, 805, and 806, which are mixed with clk60, clk300, and clk180, respectively, to generate output components Q, a ground pseudo-output, and Ib. On the n-side, the output from LNA 823-2 goes to a set of n-side mixers 814, 815, and 816, which are mixed with clk60, clk300, and clk180, respectively, to generate output components Qb, a ground pseudo-output, and I.

[0107] Figure 9 It is shown that it is used for, for example Figure 8 A flowchart illustrating the operation of the receiver in the implementation scheme. At point 901, an input signal is received. (See reference...) Figure 8 In this implementation, the input signal is received by antenna 105 and then sent to segmented LNAs 821-1, 821-2, 823-1, and 823-2, with the output supplied to the p-side and n-side of HRM 800. At 903, frequency synthesizer 830 generates an LO clock signal, and HRM 800 receives the LO clock signal. Figure 8 The LO clock signal in the implementation may include two sets of six-phase clock signals clk0, clk120 and clk240 and clk60, clk180 and clk300, all of which have a 1 / 3 (33%) duty cycle.

[0108] At position 905, for each component of the first set of clock signals (clk0, clk120, and clk240), the p-side input signal from LNA821-1 is mixed with the clock signal to generate I from the output of mixer 801 and Qb from the output of mixer 803. (The rest of the text appears to be a continuation of the previous sentence and can be left as is.) Figure 3 As in the transmitter implementation, mixer 802, which receives clk120, is a pseudo-mixer and its output is grounded. At 907, for each component of the second set of clock signals (clk60, clk180, and clk300), the p-side input signal from LNA 821-2 is mixed with the clock signal to generate Q from the output of mixer 804 and Ib from mixer 806. Figure 3 As in the transmitter implementation, the mixer 805 that receives clk300 is a pseudo mixer and its output is grounded.

[0109] The outputs from 905 and 907 together provide the I / Q components. The differential outputs can then be routed to LPF 847-1 and 847-2, and subsequently to ADC 845-1 and 845-2, to generate a (single-sided) digital I / Q signal with components (I, Q). To remove in-phase / quadrature crosstalk and generate the desired baseband I / Q signal, at 909, digital correction block 843 forms a linear combination of the I / Q from HRM 800 to provide the I component. bb and Q bb The baseband I / Q signal.

[0110] For example Figure 8In the two-sided implementation, the n-side outputs of LNAs 823-1 and 823-2 are respectively sent to a first set of n-side mixers (811, 812, 813) to be mixed with a first set of clock signals, and to a second set of n-side mixers (814, 815, 816) to be mixed with a second set of clock signals. These respectively generate another copy of the I / Q output signal, which can be used similarly when generating the IQ output.

[0111] Compared to previous methods that required more IF circuit area or more power-consuming and noisy analog IF interpolation networks, regarding Figure 3 to Figure 9 The described implementation can reduce the IF area and eliminate the need for IF interpolation. Figure 3 and Figure 8 Such a particular implementation also allows for a relatively small number of mixers, although this may come at the cost of some trade-off with transmitter noise falling in the receive band, but receive band noise is less of a concern in applications such as time-division multiplexing (TDD) UHB bands.

[0112] Figure 10 An alternative implementation of a transmitter using RF interpolation and overlapping 6-phase 33% duty cycle clocks is presented. (See reference...) Figure 3 As described in the implementation, this arrangement provides good 2nd harmonic suppression, 3rd harmonic suppression, and 4th harmonic suppression. Figure 10 The transmitter implementation uses 24 mixers with equal weighted VGA and no spurious mixers, which provides improved noise performance and is suitable for both low-band and high-band applications because there is no receiver band noise problem.

[0113] Figure 10 Differential I / Q in a signal source, frequency synthesizer block, power amplifier, filter, or antenna is not shown, but these can be implemented as... Figure 3 The differential I / Q signals are received from signal source 241, frequency synthesizer block 230, PA 253, filter 255, and antenna 105. The HRM 1000 again receives (corrected) differential I / Q input signal components I, Ib and Q, Qb, as well as a 6-phase clock signal including the first group clk0, clk120, clk240 and the second group clk60, clk180, clk300.

[0114] On the p-side, the HRM 1000 includes, except for two pseudo-mixers grounded instead of its inputs, similar to... Figure 3The implementation uses six p-side mixers connected in a first group of mixers 1001, 1002, 1003 and a second group of mixers 1004, 1005, 1006. Mixer 1002 now mixes clk120 with Q, and mixer 1006 now mixes clk300 with Qb. The outputs of 1001, 1002, and 1003 are combined to form a first p-side intermediate output, which is then amplified in VGA 1021-1 and supplied to the p-side of the first coil of inductive coupler 1051. Similarly, the outputs of 1004, 1005, and 1006 are combined to form a second p-side intermediate output, which is then amplified in VGA 1021-2 and supplied to the p-side of the first coil of inductive coupler 1051.

[0115] Now, relative to Figure 3 In this implementation, the p-side of the HRM also includes two additional sets of three mixers. Sets 1007, 1008, and 1009 receive the same clock signal as sets 1001, 1002, and 1003, but mix these clock signals with different components of the differential I / Q inputs. Specifically, 1007 mixes clk0 with Q, 1008 mixes clk120 with Ib, and 1009 mixes clk240 with Ib. The outputs of 1007, 1008, and 1009 are then combined to form a third p-side intermediate output, which is amplified in VGA 1021-3 and supplied to the p-side of the first coil of inductive coupler 1051.

[0116] The fourth group of p-side mixers 1010, 1011, and 1012, along with groups 1004, 1005, and 1006, receive the same clock signal, but mix these clock signals with different components of the differential I / Q inputs. Specifically, 1010 mixes clk60 with I, 1011 mixes clk180 with Qb, and 1012 mixes clk300 with I. The outputs of 1010, 1011, and 1012 are then combined to form a fourth p-side intermediate output, which is amplified in VGA 1021-4 and supplied to the p-side of the first coil of inductive coupler 1051.

[0117] The HRM 1000 is an n-side mirror image of the p-side, where mixers 1051 to 1062 receive the same clock signal as mixers 1001 to 1012, but each of the I / Q signal inputs is inverted, such that each I / Q signal input is inverted relative to the corresponding p-side mixer (I→Ib, Q→Qb, Ib→I, and Qb→Q). The outputs of the four n-side mixers are then combined to form four intermediate n-side outputs, which are amplified in VGAs 1023-1, 1023-2, 1023-3, and 1023-4, and then sequentially combined and supplied to the n-side of the first coil of inductive coupler 1051.

[0118] for Figure 10 The transmitter in the embodiment of the present invention has a complex RF output envelope given by the following formula:

[0119] Vout=2*I+Q+j*sqrt(3)*Q,

[0120] The resulting crosstalk terms are again highlighted in bold. Furthermore, note that the expected I and Q terms are not scaled equally. Despite the increase in the overall factor of 2, this is otherwise... Figure 3 The combinations of terms in the transmitter of the implementation are the same. Therefore, the digital compensation applied to the correction block can be shown again as:

[0121] I = I bb *sqrt(3) / 2-Q bb / 2; and

[0122] Q = Q bb .

[0123] In the above text, I bb and Q bb These are still the “ideal” transmitter baseband I / Q signal components from Source 107, which are the expected I / Q signals intended to be transmitted.

[0124] Figure 11 It shows the use of Figure 10 The simulation results of the performance at the output of the power amplifier in the implementation method, and with Figure 6 It is presented similarly. More specifically, Figure 11 The graph, plotted in decibels (dB), represents the frequency as a function of [the frequency]. Figure 10 The output of the 6-phase power amplifier in this implementation is normalized to make the desired transmitter (Tx) signal at 0dB. Figure 11 In the curve graph, for the purpose of rapid simulation, the desired signal frequency (approximately 1.2288 x 10⁻⁶) is... 8(Hz) was chosen as a frequency lower than the actual RF target frequency. In addition to the expected Tx signal, at slightly lower frequencies, the peak value was reduced by about -60dB due to LO leakage, and by more than -80dB due to image distortion.

[0125] Regarding harmonics, and intermodulation of a second-order counter, Figure 11 The peak value on the positive CIM2p side decreased by approximately -90 dB. Among other significant peaks, the largest was CIM5, which decreased by -80 dB. Therefore, Figure 11 Simulation results show that the output performance of the power amplifier PA 1053 of the 6-phase digitally assisted harmonic suppression transceiver using RF interpolation is comparable to that of a standard 6-phase HRM. The system's spectrum shows that all CIM distortion levels are sufficiently low for cellular applications.

[0126] Figure 12 Is with Figure 8 An alternative implementation of the receiver using digital compensation to correspond to the transmitter implementation. Figure 12 This excludes components or frequency synthesizers used to convert differential I / Q signals into baseband (one-sided) components Ibb and Qbb, but these can be addressed as described above. Figure 8 The frequency synthesizer 830 and LPF 847-1, 847-2, ADC 845-1, 845-2 and digital correction block 843 are described as follows. Figure 8 Like in the middle, Figure 12 The system includes an antenna 105 connected to a filter 1255, which in turn supplies the signal from the antenna 105 to a set of low-noise amplifiers.

[0127] For example, regarding Figure 10The HRM 1200 is arranged like the HRM 1000 transmitter, with 12 mixers on each of the p and n sides, but now the input comes from one of the LNAs and the output of each mixer is one of the components of the differential I / Q signal. More specifically, on the n-side, LNA 1221-1 supplies mixers 1201, 1202, and 1203 with clock signals clk0, clk120, and clk240 to generate I, Q, and Qb, respectively; LNA 1221-2 supplies mixers 1204, 1205, and 1206 with clock signals clk60, clk180, and clk300 to generate Q, Ib, and Qb, respectively; LNA 1221-3 supplies mixers 1207, 1208, and 1209 with clock signals clk0, clk120, and clk240 to generate Q, Ib, and Ib, respectively; and LNA 1221-4 supplies mixers 1210, 1211, and 1212 with clock signals clk60, clk180, and clk300 to generate I, Qb, and I, respectively.

[0128] The n-side HRM 1200 mirrors the p-side, but the components of the differential I / Q signals are replaced by their inversion. More specifically, LNA1223-1 supplies mixers 1251, 1252, and 1253 with clock signals clk0, clk120, and clk240 to generate Ib, Qb, and Q respectively; LNA 1223-2 supplies mixers 1254, 1255, and 1256 with clock signals clk60, clk180, and clk300 to generate Qb, I, and Q respectively; LNA 1223-3 supplies mixers 1257, 1258, and 1259 with clock signals clk0, clk120, and clk240 to generate Qb, I, and I respectively; and LNA 1223-4 supplies mixers 1260, 1261, and 1262 with clock signals clk60, clk180, and clk300 to generate Ib, Q, and Ib respectively.

[0129] and Figure 3 and Figure 8 Compared to the implementation method, Figure 10 The implementation can exhibit improved transmitter noise in the receive band and is better suited for frequency division multiplexing in both low-band and high-band cellular applications. This noise reduction improvement comes at the cost of an increased number of mixer switches, but in many implementations this is not a significant increase in area.

[0130] Figure 13 and Figure 14 Another set of alternative implementations for the transmitter and receiver is presented. Structurally, Figure 13 and Figure 14 Similar toFigure 10 and Figure 12 However, it features different allocations of I / Q components to the mixer. The p-side of the HRM 1300 includes four groups of three mixers (1301, 1302, 1303), (1304, 1305, 1306), (1307, 1308, 1309), and (1310, 1311, 1312), whose receivers and... Figure 10 The corresponding mixer in the implementation uses the same clock signal group, but now receives inputs (1, Q, Qb), (Q, Ib, Qb), (1, Q, Ib), and (1, Ib, Qb). Relative to... Figure 10 , from Figure 3 The non-pseudo-mixer receives the same inputs, but the inputs supplied to the other mixers are rearranged. Therefore, the HRM 1300 will operate similarly to the HRM 1000, but will use different linear combinations of the baseband I / Q signals to generate differential I / Q signals. For example... Figure 13 As shown, four sets of three mixers combine their outputs to form four p-side intermediate output signals, which are amplified, combined, and then supplied to the p-side of the first coil of the inductive coupler 1351 in VGA 1321-1, 1321-2, 1321-3, and 1321-4.

[0131] On the n-side of the HRM 1300, four sets of three mixers (1351, 1352, 1353), (1354, 1355, 1356), (1357, 1358, 1359), and (1360, 1361, 1362) receive and... Figure 10 The corresponding mixer in the implementation uses the same clock signal group, but now receives inputs (Ib, Qb, Q), (Qb, I, Q), (Ib, Qb, I), and (Ib, I, Q). Relative to... Figure 10 , from Figure 3 The non-pseudo-mixer receives the same input, but the inputs supplied to other mixers are rearranged again. Therefore, the HRM1300 will operate similarly to the HRM 1000, but will use different linear combinations of the baseband I / Q signals to generate differential I / Q signals. For example... Figure 13 As shown, four sets of three mixers combine their outputs to form four n-side intermediate output signals, which are amplified, combined, and then supplied to the n-side of the first coil of the inductive coupler 1351 in VGA 1323-1, 1323-2, 1323-3, and 1323-4.

[0132] Figure 13 The configuration features higher output power and lower digital image compensation. This will be discussed in more detail below. Figure 13The complex output envelope of the implementation method is given by the following formula:

[0133] Vout=2.5*I-1 / 2*Q+j*sqrt(3) / 2*I+j*3*sqrt(3) / 2*Q

[0134] The resulting crosstalk term is again highlighted in bold. The corresponding correction factor is discussed and determined below, where the above expression corresponds to Equation 5 below. Relative to Figure 10 , Figure 13 The implementation method can provide higher output and lower digital image correction.

[0135] Figure 14 receiver and Figure 12 The receivers are arranged similarly, but with different output assignments. More specifically, antenna 105 is connected to filter 1455 to supply the received signal to LNAs 1421-1, 1421-2, 1421-3, and 1421-4 on the p-side and LNAs 1423-1, 1423-2, 1423-3, and 1423-4 on the n-side. Mixer groups (1401, 1402, 1403), (1404, 1405, 1406), (1407, 1408, 1409), and (1410, 1411, 1412) are arranged as follows: Figure 12 The corresponding mixers on the p-side are now assigned outputs as (I, Q, Qb), (Q, Ib, Qb), (I, Q, Ib), and (I, Ib, Qb), respectively. On the n-side, mixer groups (1451, 1452, 1453), (1454, 1455, 1456), (1457, 1458, 1459), and (1460, 1461, 1462) are arranged as follows: Figure 12 The corresponding mixers on the n-side are now assigned as (Ib, Qb, Q), (Qb, I, Q), (Ib, Qb, I), and (Ib, I, Q), respectively.

[0136] Regarding the determination of the baseband I / Q signal—which is used to generate the target… Figure 14 and Figure 13 The harmonic suppression mixer in the embodiment uses a linear combination of the differential I / Q signals as a correction factor, where I(t) is the baseband in-phase time-domain signal and Q(t) is the baseband quadrature time-domain signal. For notation simplification, ignoring time arguments, this gives the complex envelope:

[0137] XL = I + jQ,

[0138] And the corresponding image (XL) * Simply put, it's conjugate:

[0139] XL ＊=I-jQ.

[0140] To eliminate crosstalk between in-phase and quadrature components, the desired complex envelope RF output signal after RF interpolation should take the following form:

[0141] Vout_expected = A*XL(t) = A*[I(t) + jQ(t)], (Equation 1)

[0142] Where A is the complex scaling factor, which does not affect the quality of the transmitted (or received) signal.

[0143] However, 6-phase RF interpolation typically causes I / Q crosstalk, which produces unwanted image signal components (XL). * Therefore, the RF output signal obtained after 6-phase RF interpolation can be expressed as:

[0144] Vout=A*XL+B*XL*, (Formula 2)

[0145] In Equation 2, the second term on the right-hand side represents the unwanted image signal that needs to be digitally corrected (or eliminated). Traditionally, the correction of the image in the second term of Equation 2 is accomplished by injecting a digital image elimination term scaled by -B / A. In other words, digital correction (to the input of the I / Q Tx DAC) can generally be expressed as:

[0146] I+jQ=XL bb -B / A*(XL* bb )=Ibb+j*Q bb -B / A*(I bb -jQ bb (Equation 3)

[0147] Among them, I bb and Q bb These are the original digital in-phase baseband signal and the quadrature baseband signal, respectively. Therefore, in order to determine the correction for any 6-phase RF interpolation implementation, it is only necessary to determine terms A and B in Equation 2 above, which are generated by the RF interpolation action.

[0148] exist Figure 13 and Figure 14 In the implementation method, when considering Figure 13 The transmitter (where it can be used for) Figure 14(Similar reasoning applies to the receiver), and considering only the single-ended positive connection of the I and Q outputs at the transmitter's low-pass filter output (corresponding to the outputs of LPF_I 247-1 and LPF-Q 247-2), the "I" baseband filter output is connected twice to the 0-degree phase LO clock (clk0 or P0) (mixers 1301, 1307), and once to the 60-degree phase LO clock (clk60 or P60) (mixer 1310). Similarly, the Q baseband filter output is connected once to the 60-degree phase LO clock (mixer 1304) and twice to the 120-degree phase LO clock (mixers 1302, 1308). Therefore, after up-conversion at the transmitter and combination with the equally weighted transmitter VGA, the complex envelope RF output signal can be expressed as:

[0149] Vout=I*(2*P0+P60)+Q*(P60+2*P120), (Equation 4)

[0150] in:

[0151] P0 = exp(j*0) = 1;

[0152] P60 = exp(j * PI / 3) = 0.5 + j * sqrt(3) / 2; and

[0153] P120=exp(j*2*Pl / 3)=-0.5+j*sqrt(3) / 2

[0154] Substituting P0, P60, and P120 into Equation 4 above, we get:

[0155] Vout=2.5*I-1 / 2*Q+j*sqrt(3) / 2*I+j*3*sqrt(3) / 2*Q. (Formula 5)

[0156] The bolded entries show the resulting I / Q crosstalk terms. Note also that the expected I and Q terms are not scaled equally.

[0157] Please note the following:

[0158] I = 1 / 2 * (XL + XL *); and (Equation 6.1)

[0159] Q=-j*1 / 2*(XL-XL*). (Formula 6.2)

[0160] Substituting equations 6.1 and 6.2 into equation 5 and rearranging the terms, it can be seen that for Figure 13 Implementation method:

[0161] Vout = (2.5490 + j0.6830) * XL + (-0.0490 + j0.1830) * XL *. (Equation 7)

[0162] Now, note that equation 7 has the form of equation 2 above, where:

[0163] A = (2.5490 + j0.6830); and

[0164] B = (-0.0490 + j0.1830).

[0165] Substituting the values ​​of A and B into Equation 3 above, we can... Figure 13 The digital correction in the implementation method takes the following form:

[0166] I = I bb –0.07081*Q bb ;as well as

[0167] Q = Q bb –0.07081*I bb .

[0168] For all the implementations presented here, the 6-phase implementation using a 33% duty cycle suppresses both the 2nd and 4th harmonics because each of the three-phase (0, 60, and 120) LO clocks has its corresponding equally weighted differential pair (180, 240, and 300) LO clocks. This ensures both 2nd and 4th harmonic cancellation. Furthermore, since a 33% duty cycle LO clock naturally does not contain a 3rd harmonic, the 3rd harmonic content is suppressed.

[0169] The techniques described herein can be implemented using hardware, firmware, software, or a combination thereof. The software or firmware used can be stored on one or more processor-readable storage devices for... Figure 3 to Figure 14The processor-readable storage device may be programmed with one or more blocks to perform the functions described herein. The processor-readable storage device may include computer-readable media, such as volatile and non-volatile media, removable and non-removable media. By way of example, and not limitation, the computer-readable medium may include computer-readable storage media and communication media. The computer-readable storage medium may be implemented in any method or technique for storing information such as computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disc storage devices, magnetic tape cassettes, magnetic tape, disk storage devices or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by the aforementioned components. One or more computer-readable media do not include propagated, modulated, or transient signals.

[0170] Communication media typically embody computer-readable instructions, data structures, program modules, or other data as propagated, modulated, or transient data signals via carrier waves or other transmission mechanisms, and include any information transmission medium. The term "modulated data signal" refers to a signal having one or more characteristics that are set or altered in a manner that encodes information in the signal. By way of example and not limitation, communication media include wired media such as wired networks or wired connections and wireless media such as RF and other wireless media. Any combination of the above is also included within the scope of computer-readable media.

[0171] In alternative implementations, some or all of the software or firmware may be replaced by dedicated hardware logic components. For example, but not limited to, exemplary types of hardware logic components that may be used include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), dedicated computers, etc. In one implementation, software (stored on a storage device) implementing one or more implementations is used to program one or more processors. One or more processors may communicate with one or more computer-readable media / storage devices, peripheral devices, and / or communication interfaces.

[0172] It should be understood that this subject matter can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the subject matter thorough and complete, and to fully convey the contents of this disclosure to those skilled in the art. In fact, this subject matter is intended to cover alternatives, modifications, and equivalents to these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, numerous specific details are set forth in the detailed description of this subject matter to provide a thorough understanding of it. However, it will be apparent to those skilled in the art that this subject matter can be practiced without these specific details.

[0173] Aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to create a machine, such that the instructions, which execute via a processor of a computer or other programmable instruction execution apparatus, create a mechanism for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0174] The description of this disclosure is provided for purposes of illustration and description, but is not intended to be exhaustive or limited to the form of the disclosure. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of this disclosure. The aspects of the disclosure herein were chosen and described in order to best explain the principles and practical applications of this disclosure and to enable others skilled in the art to understand this disclosure, and to adapt various modifications to the particular purpose contemplated.

[0175] For the purposes of this document, each process associated with the disclosed technology may be performed sequentially and by one or more computing devices. Each step in the process may be performed by the same or different computing devices used in other steps, and each step need not necessarily be performed by a single computing device.

[0176] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

Claims

1. A transmitter, the transmitter comprising: An in-phase / quadrature (IQ) signal source is configured to receive a first IQ signal and generate a second IQ signal based on the first IQ signal. The second IQ signal is in a differential format having an in-phase component, a quadrature component, an out-of-phase component of the in-phase component, and an out-of-phase component of the quadrature component, wherein one or both of the in-phase component and the quadrature component of the second IQ signal are a linear combination of the in-phase component and the quadrature component of the first IQ signal. A frequency synthesizer configured to generate a 6-phase clock signal, the 6-phase clock signal comprising a first set of three non-overlapping clock signals with a combined duty cycle of 100% and a second set of three non-overlapping clock signals with a combined duty cycle of 100%; and Harmonic suppression mixer, comprising: The first mixer section includes: A first set of mixers is configured to receive a corresponding clock signal from a first set of clock signals. A first mixer in the first set of mixers is further configured to receive the in-phase component of the second IQ signal, and a second mixer in the first set of mixers is further configured to receive the out-of-phase component of the quadrature component of the second IQ signal. The second set of mixers is configured to receive the corresponding clock signal from the second set of clock signals. The first mixer in the second set of mixers is further configured to receive the quadrature component of the second IQ signal, and the second mixer in the second set of mixers is further configured to receive the inverted component of the in-phase component of the second IQ signal. The harmonic suppression mixer is configured as follows: The first intermediate signal in the first mixer section is formed by combining the outputs of each mixer in the first group of mixers in the first mixer section. The second intermediate signal in the first mixer is formed by combining the outputs of each mixer in the second group of mixers in the first mixer section. The first intermediate signal and the second intermediate signal in the first mixer section are combined to form a first output signal for the harmonic suppression mixer; and The harmonic suppression mixer also includes: The second mixer section includes: A first group of mixers, each mixer configured to receive a corresponding clock signal from the first group of clock signals, wherein a first mixer in the first group of mixers is further configured to receive the inverted phase of the in-phase component of the second IQ signal, and a second mixer in the first group of mixers is further configured to receive the quadrature component of the second IQ signal; and The second group of mixers, each mixer configured to receive a corresponding clock signal from the second group of clock signals, further includes a first mixer configured to receive the inverted quadrature component of the second IQ signal, and a second mixer configured to receive the in-phase component of the second IQ signal. The harmonic suppression mixer is configured as follows: The first intermediate signal of the second mixer is formed by combining the outputs of each mixer in the first group of mixers in the second mixer section; The second intermediate signal of the second mixer is formed by combining the outputs of each mixer in the second group of mixers in the second mixer section; and The first intermediate signal and the second intermediate signal in the second mixing section are combined to form a second output signal for the harmonic suppression mixer.

2. The transmitter according to claim 1, wherein: The third mixer in the first group of mixers is further configured to have an input terminal connected to ground; and The third mixer in the second group of mixers is also configured to have an input that is connected to ground.

3. The transmitter according to claim 1, wherein: The third mixer in the first group of mixers is further configured to receive components of the second IQ signal other than the out-of-phase components of the in-phase and quadrature components; and The third mixer in the second set of mixers is also configured to receive components in the second IQ signal other than the quadrature component and the out-of-phase component.

4. The transmitter according to claim 3, wherein, The first mixer section further includes: A third set of mixers, each mixer configured to receive one of the corresponding clock signal of the first set of clock signals and one component of the second IQ signal; and The fourth group of mixers, each mixer is configured to receive one of the corresponding clock signal from the second group of clock signals and one component of the second IQ signal. The harmonic suppression mixer is further configured to: The third intermediate signal is formed by combining the outputs of each mixer in the third set of mixers; The fourth intermediate signal is formed by combining the outputs of each mixer in the fourth group of mixers; and The third and fourth intermediate signals are further combined with the first and second intermediate signals to form a first output signal for the harmonic suppression mixer.

5. The transmitter according to claim 1, further comprising: The first variable gain amplifier is configured to: Receive the first intermediate signal; as well as The first intermediate signal is amplified before combining the first intermediate signal with the second intermediate signal to form a first output signal with respect to the harmonic suppression mixer; as well as The second variable gain amplifier is configured as follows: Receive the second intermediate signal; and The second intermediate signal is amplified before combining the first intermediate signal with the second intermediate signal to form a first output signal for the harmonic suppression mixer.

6. The transmitter according to claim 1, further comprising: An inductive coupler, comprising: A first coil is configured to receive a first output signal from the harmonic suppression mixer at a first terminal and a second output signal from the harmonic suppression mixer at a second terminal; and A second coil, which is inductively coupled to the first coil, has a first terminal configured to provide a single-ended output to the transmitter and a second terminal connected to ground.

7. The transmitter according to claim 6, further comprising: A power amplifier configured to receive and amplify the single-ended output.

8. The transmitter according to claim 7, further comprising: An antenna configured to receive and transmit the single-ended output.

9. The transmitter according to any one of claims 1 to 8, wherein, The frequency synthesizer is configured to generate a 6-phase clock signal by generating the first set of clock signals from a voltage-controlled oscillator and by introducing a phase shift into the first set of clock signals to generate a second set of clock signals based on the first set of clock signals.

10. The transmitter according to any one of claims 1 to 8, wherein, The IQ signal source includes: A digital correction circuit is configured to receive the first IQ signal in digital format and generate a second IQ signal in digital format based on the first IQ signal. A first digital-to-analog converter is configured to receive the in-phase component of the second IQ signal in digital format, and to generate an in-phase component of the second IQ signal in differential analog format based on the in-phase component of the second IQ signal; and A second digital-to-analog converter is configured to receive the quadrature components of the second IQ signal in digital format, and to generate quadrature components of the second IQ signal in differential analog format based on the quadrature components of the second IQ signal.

11. A method for transmitting a signal, comprising: Receive the first in-phase / quadrature (IQ) signal; A second IQ signal is generated based on the first IQ signal. The second IQ signal is in a differential format having an in-phase component, a quadrature component, an out-of-phase component of the in-phase component, and an out-of-phase component of the quadrature component. One or both of the in-phase component and the quadrature component of the second IQ signal are linear combinations of the in-phase component and the quadrature component of the first IQ signal. Receives a 6-phase clock signal, wherein the 6-phase clock signal includes a first group of three non-overlapping clock signals with a combined duty cycle of 100% and a second group of three non-overlapping clock signals with a combined duty cycle of 100%; and The first output signal is generated based on the second IQ signal and the 6-phase clock signal through the following operations: At each mixer in the first group of mixers, the corresponding clock signal from the first group of clock signals is received. The in-phase component of the second IQ signal is received at the first mixer in the first group of mixers. The inverted quadrature component of the second IQ signal is received at the second mixer in the first set of mixers. The outputs of each mixer in the first group are combined to form a first intermediate signal. At each mixer in the second set of mixers, the corresponding clock signal from the second set of clock signals is received. The inverted phase of the in-phase component of the second IQ signal is received at the first mixer in the second set of mixers. The quadrature component of the second IQ signal is received at the second mixer in the second group of mixers. The outputs of each mixer in the second group are combined to form a second intermediate signal, and The first output signal is generated by combining the first intermediate signal and the second intermediate signal; and The second output signal is generated based on the second IQ signal and the 6-phase clock signal through the following operations: At each mixer in the third set of mixers, the corresponding clock signal from the first set of clock signals is received; The in-phase component of the second IQ signal is received at the first mixer in the third set of mixers; The quadrature component of the second IQ signal is received at the second mixer in the third set of mixers. The outputs of each mixer in the third group of mixers are combined to form a third intermediate signal; At each mixer in the fourth group of mixers, the corresponding clock signal from the second group of clock signals is received; The in-phase component of the second IQ signal is received at the first mixer in the fourth set of mixers; The inverted quadrature component of the second IQ signal is received at the second mixer in the fourth set of mixers; The outputs of each mixer in the fourth group of mixers are combined to form a fourth intermediate signal; and The second output signal is generated by combining the third intermediate signal with the fourth intermediate signal.

12. The method according to claim 11, wherein, The first output signal is also generated based on the second IQ signal and the 6-phase clock signal through the following operations: Connect the input of the third mixer in the first group of mixers to ground; and Connect the input of the third mixer in the second set of mixers to ground.

13. The method according to claim 11, wherein, The first output signal is also generated based on the second IQ signal and the 6-phase clock signal through the following operations: The third mixer in the first set of mixers receives the components of the second IQ signal other than the out-of-phase components of the in-phase and quadrature components. as well as The third mixer in the second set of mixers receives the components of the second IQ signal other than the quadrature component and the out-of-phase component.

14. The method according to claim 13, wherein, The first output signal is also generated based on the second IQ signal and the 6-phase clock signal through the following operations: At each of the third set of mixers, one of the corresponding clock signals from the first set of clock signals and one of the components of the second IQ signal is received; The outputs of each mixer in the third group of mixers are combined to form a third intermediate signal; At each of the fourth set of mixers, one of the corresponding clock signals from the second set of clock signals and one of the components of the second IQ signal is received; as well as The outputs of each mixer in the fourth group are combined to form a fourth intermediate signal. The first output signal is generated by further combining the third intermediate signal and the fourth intermediate signal with the first intermediate signal and the second intermediate signal.

15. The method of claim 11, further comprising: Before combining the first intermediate signal and the second intermediate signal to generate the first output signal, the first intermediate signal and the second intermediate signal are amplified separately.

16. The method of claim 11, further comprising: The first output signal and the second output signal are respectively applied to the first terminal and the second terminal of the first coil of the inductive coupler; The output from the second coil of the inductive coupler is received and amplified, the second coil being inductively coupled to the first coil; as well as Send the amplified output.

17. The method according to any one of claims 11 to 16, further comprising: The 6-phase clock signal is generated through the following operations: The first set of clock signals is generated from the voltage-controlled oscillator; as well as The second set of clock signals is generated by introducing a phase shift into the first set of clock signals.

18. The method according to any one of claims 11 to 16, wherein, Generating the second IQ signal based on the first IQ signal includes: Receive the first IQ signal in digital format; The second IQ signal is generated in digital format based on the first IQ signal in digital format; The in-phase component of the second IQ signal in differential analog format is generated based on the in-phase component of the second IQ signal in digital format; and The quadrature components of the second IQ signal in differential analog format are generated based on the quadrature components of the second IQ signal in digital format.

19. A receiver, comprising: A frequency synthesizer is configured to generate a 6-phase clock signal, the 6-phase clock signal comprising a first set of three non-overlapping clock signals with a combined duty cycle of 100% and a second set of three non-overlapping clock signals with a combined duty cycle of 100%. Harmonic suppression mixer, comprising: The first mixer section includes: A first group of mixers, each mixer configured to receive and mix one clock signal from a first group of clock signals with an input signal to generate an in-phase component of a differential in-phase / quadrature (IQ) signal in a first mixer within the first group of mixers, and to generate an out-of-phase quadrature component of the differential IQ signal in a second mixer within the first group of mixers; and The second set of mixers, each mixer being configured to receive and mix one of the clock signals from the second set of clock signals with the input signal, to generate the quadrature component of the differential IQ signal in the first mixer of the second set of mixers, and to generate the inverted component of the in-phase component of the differential IQ signal in the second mixer of the second set of mixers. The second mixer section includes: A first set of mixers, each mixer configured to receive and mix one clock signal from the first set of clock signals with the negative-side outputs of one or more low-noise amplifiers, to generate an inverted component of the in-phase differential IQ signal in a first mixer in the first set of mixers, and to generate a quadrature component of the differential IQ signal in a second mixer in the first set of mixers; and A second set of mixers, each mixer configured to receive and mix one clock signal from the second set of clock signals with the negative-side outputs of the one or more low-noise amplifiers, to generate an inverted quadrature component of the differential IQ signal in a first mixer in the second set of mixers, and to generate an in-phase component of the differential IQ signal in a second mixer in the second set of mixers; and A correction circuit is configured to receive components of the differential IQ signal and generate a baseband IQ signal based on the components of the differential IQ signal, wherein one or both of the in-phase and quadrature components of the baseband IQ signal are linear combinations of the components of the differential IQ signal.

20. The receiver according to claim 19, wherein: The third mixer in the first group of mixers is further configured to have an output that is connected to ground; and The third mixer in the second group of mixers is also configured to have an output that is connected to ground.

21. The receiver according to claim 19, wherein: The third mixer in the first set of mixers is also configured to generate the differential IQ signal, excluding the out-of-phase components of the in-phase component and the quadrature component; as well as The third mixer in the second set of mixers is also configured to generate the differential IQ signal, excluding the quadrature component and the out-of-phase component of the in-phase component.

22. The receiver according to claim 21, wherein, The first mixer section further includes: A third set of mixers, each configured to receive and mix one clock signal from the first set of clock signals with the input signal to generate components of the differential IQ signal; and The fourth set of mixers, each configured to receive and mix one of the clock signals from the second set of clock signals with the input signal to generate components of the differential IQ signal.

23. The receiver of claim 19, further comprising: The one or more low-noise amplifiers are configured to: Receive and amplify the input signal; as well as The amplified input signal is supplied to the harmonic suppression mixer.

24. The receiver according to claim 23, wherein, The one or more low-noise amplifiers are configured to provide an amplified input signal as a differential output, and the first mixer receives the positive side output of the low-noise amplifier.

25. The receiver of claim 23, further comprising: An antenna configured to receive the input signal and supply the input signal to one or more low-noise amplifiers.

26. The receiver according to any one of claims 19 to 25, wherein, The frequency synthesizer is configured to generate a 6-phase clock signal by generating the first set of clock signals from a voltage-controlled oscillator and by introducing a phase shift into the first set of clock signals to generate a second set of clock signals based on the first set of clock signals.

27. The receiver according to any one of claims 19 to 25, wherein, The correction circuit includes: A first analog-to-digital converter is configured to receive the in-phase component of the differential IQ signal in analog format and generate the in-phase component of the input IQ signal in digital format based on the in-phase component of the differential IQ signal. A second analog-to-digital converter is configured to receive the quadrature components of the differential IQ signal in analog format, and to generate quadrature components of the input IQ signal in digital format based on the quadrature components of the differential IQ signal; and A digital correction circuit is configured to receive the input IQ signal in digital format and generate the baseband IQ signal based on the input IQ signal.

28. A method for receiving a signal, comprising: Receive input signals; The system receives a 6-phase clock signal, which includes a first group of three non-overlapping clock signals with a combined duty cycle of 100% and a second group of three non-overlapping clock signals with a combined duty cycle of 100%. as well as The baseband IQ signal is generated based on the input signal through the following operations: At each mixer in the first group of mixers, the corresponding clock signal from the first group of clock signals and the input signal are received. The in-phase component of the differential in-phase / quadrature (IQ) signal is generated in the first mixer of the first group of mixers. The inverted quadrature components of the differential IQ signal are generated in the second mixer of the first set of mixers. At each mixer in the second set of mixers, the corresponding clock signal from the second set of clock signals and the input signal are received. The quadrature components of the differential IQ signal are generated in the first mixer of the second set of mixers. The quadrature components of the differential IQ signal are generated in the second mixer of the second set of mixers, and A baseband IQ signal is generated based on the components of the differential IQ signal, wherein one or both of the in-phase and quadrature components of the baseband IQ signal are linear combinations of the components of the differential IQ signal; and The baseband IQ signal is also generated based on the input signal through the following operations: At each of the third set of mixers, a corresponding clock signal from the first set of clock signals and the negative-side output of one or more low-noise amplifiers are received. The inverted phase of the in-phase component of the differential IQ signal is generated in the first mixer of the third set of mixers; The quadrature components of the differential IQ signal are generated in the second mixer of the third set of mixers; At each mixer in the fourth group of mixers, the corresponding clock signal from the second group of clock signals and the input signal are received; The quadrature components of the differential IQ signal are generated in the first mixer of the fourth set of mixers; and The inverted quadrature components of the differential IQ signal are generated in the second mixer of the fourth mixer group.

29. The method according to claim 28, wherein, The baseband IQ signal is also generated through the following operations: Set the output of the third mixer in the first group of mixers to ground; and Set the output of the third mixer in the second group of mixers to ground.

30. The method according to claim 28, wherein, The baseband IQ signal is also generated through the following operations: The differential IQ signal is generated in the third mixer of the first set of mixers, excluding the in-phase component and the out-of-phase component of the quadrature component. as well as The differential IQ signal, excluding the quadrature component and the out-of-phase component, is generated in the third mixer of the second set of mixers.

31. The method according to claim 30, wherein, The baseband IQ signal is also generated through the following operations: At each mixer in the third set of mixers, the corresponding clock signal from the first set of clock signals and the input signal are received; The components of the differential IQ signal are generated in each mixer in the third group; At each mixer in the fourth group of mixers, the corresponding clock signal from the second group of clock signals and the input signal are received; as well as The components of the differential IQ signal are generated in each mixer in the fourth group.

32. The method of claim 28, further comprising: The input signal is amplified in one or more low-noise amplifiers; as well as The amplified input signal from the one or more low-noise amplifiers is supplied to the first set of mixers and the second set of mixers.

33. The method according to claim 32, wherein, The one or more low-noise amplifiers are configured to provide the amplified input signal, which is a differential output, as the positive side output of the low-noise amplifier to the first set of mixers and the second set of mixers.

34. The method of claim 32, further comprising: The input signal is received from the antenna and supplied to one or more low-noise amplifiers.

35. The method according to any one of claims 28 to 34, wherein, Receiving the 6-phase clock signal includes: The first set of clock signals is generated from the voltage-controlled oscillator; and The second set of clock signals is generated by introducing a phase shift into the first set of clock signals.

36. The method according to any one of claims 28 to 34, wherein, Generating the baseband IQ signal based on the components of the differential IQ signal includes: Receive the in-phase component of the differential IQ signal in analog format, and generate the in-phase component of the input IQ signal in digital format based on the in-phase component of the differential IQ signal. Receives the quadrature components of the differential IQ signal in analog format, and generates quadrature components of the input IQ signal in digital format based on the quadrature components of the differential IQ signal; and The input IQ signal is received in digital format, and the baseband IQ signal is generated based on the input IQ signal.

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