Adaptive data sampling method and adaptive data sampling device

Abstract

The application provides an adaptive data sampling method and an adaptive data sampling device. The method comprises the following steps: a first device sends a preset data sequence to a second device, and the second device returns a response data sequence to the first device; the first device generates an original sampling clock signal by using a first delay chain, generates at least one first predicted sampling clock signal, a reference sampling clock signal and at least one second predicted sampling clock signal by using a second delay chain, samples the response data sequence by using the reference sampling clock signal, the first predicted sampling clock signal and the second predicted sampling clock signal, and adjusts the reference sampling clock signal according to the sampling results of the response data sequence by using the reference sampling clock signal, the first predicted sampling clock signal and the second predicted sampling clock signal. The application also provides an adaptive data sampling device for realizing the above method. The application can adaptively adjust the sampling points.

Description

Technical Field

[0001] This invention relates to the technical field of data sampling, specifically to an adaptive data sampling method and an adaptive data sampling device. Background Technology

[0002] In a computer system, the processor, memory, and storage devices are the three indispensable components. The processor performs calculations and control functions, memory temporarily stores data required for program execution, and storage devices store programs or other data that needs to be preserved permanently. Currently, flash memory, such as SD / eMMC, is a commonly used storage device. In practical applications, the processor and memory typically constitute the host system, while the flash memory serves as a peripheral device. The host system accesses the flash memory through its internal controller.

[0003] When the host system needs to read data from flash memory, it needs to be able to correctly sample the data sent from flash memory so that the correct data can be stored in memory for the processor to use. Therefore, data exchange between two hardware devices is very common in computer systems. For example... Figure 1 As shown, the first device 11 can be a host system, and the second device 12 can be a flash memory. Data sent from the second device 12 to the first device 11 requires correct sampling by the first device 11 for accurate data transmission. However, in practical applications, correct data sampling by the first device 11 often presents challenges. For example, if there is a delay between the first device 11 and the second device 12, the first device 11 may fail to sample data correctly due to changes in the delay. Typically, the delay between the first device 11 and the second device 12 varies with different devices, PCB layouts, and operating conditions (such as temperature and voltage). Changes in delay may render previously usable sampling points unusable when the first device 11 samples data, causing data sampling errors and ultimately leading to data transmission failure.

[0004] To address the issue of incorrect data sampling caused by delay variations between two devices, the primary approach is a delay chain-based tuning method. The steps are as follows: First, the first device (11), acting as the host system, sends a command to the second device to read a preset data sequence. Second, the second device sends a response data sequence to the first device. Third, the first device verifies the received response data sequence. If the verification passes, the current sampling point is confirmed as usable; otherwise, it is confirmed as unusable. Fourth, the first device modifies the sampling point using an internal delay chain. This involves changing the delay value of the delay chain to alter the phase of the sampling clock signal without changing its frequency. After traversing all sampling points, the first device obtains a usable sampling interval. Fifth, the first device uses the midpoint of the sampling interval as the sampling point for normal data reception.

[0005] The preset data sequence used in the above method can be a tuning data block supported by the memory itself of the second device 12. The limitation of this case is that not all devices or all operating modes of a specific device support tuning data blocks. For example, eMMC only supports tuning data blocks in HS200 mode. The preset data sequence can also be a data sequence pre-sent to the flash memory by the host system. In this case, the above limitation does not exist.

[0006] However, existing tuning methods based on delay chains cannot adapt to changes in operating conditions. After the sampling point tuning is completed and the system is in operation, changes in operating conditions (such as temperature) can cause phase shifts in the data. These shifts may cause reliable sampling points determined during initial tuning to become unreliable, or even previously confirmed usable sampling points to become unusable. Furthermore, the higher the system's operating frequency, the more pronounced these problems become.

[0007] Furthermore, existing tuning methods based on delay chains require numerous steps, most of which are implemented using software programs, resulting in long tuning times for sampling points and impacting data transmission. Summary of the Invention

[0008] The first objective of this invention is to provide an adaptive data sampling method that can avoid the unavailability of sampling points due to environmental changes.

[0009] A second objective of the present invention is to provide an adaptive data sampling apparatus for implementing the above-described adaptive data sampling method.

[0010] To achieve the first objective of this invention, the adaptive data sampling method provided by this invention includes a first device sending a preset data sequence to a second device, and the second device returning a response data sequence to the first device; wherein, the first device uses a first delay chain to generate an original sampling clock signal, and uses a second delay chain to generate at least one first predictive sampling clock signal, a reference sampling clock signal, and at least one second predictive sampling clock signal based on the original sampling clock signal; the first device uses the reference sampling clock signal, the first predictive sampling clock signal, and the second predictive sampling clock signal to sample the response data sequence; and the reference sampling clock signal is adjusted according to the sampling result of the reference sampling clock signal, the first predictive sampling clock signal, and the second predictive sampling clock signal.

[0011] As can be seen from the above scheme, by setting two different delay chains, the first delay chain is used to adjust the phase of the original sampling clock signal, and the second delay chain is used to adjust the phase of each predictive sampling clock signal. Since the response data sequence is sampled by the reference sampling clock signal, the first predictive sampling clock signal, and the second predictive sampling clock signal, it is determined whether the above three clock signals can correctly sample the response data sequence, and thus the reference sampling clock signal is adjusted.

[0012] As can be seen, the first and second predictive sampling clock signals at the outermost edge actually constitute the upper and lower thresholds of the available sampling points. Since the reference sampling clock signal and multiple predictive sampling clock signals sample the response data sequence simultaneously during the data sampling process, data sampling can be achieved quickly, and the tuning speed of the sampling points is fast.

[0013] Furthermore, since the present invention uses multiple clock signals with phase differences to sample data, the first predictive sampling clock signal and the second predictive sampling clock signal can serve as early warning clock signals for deviations from the reference sampling clock signal. By using the early warning clock signals to predict changes in the sampling points, the reference sampling clock signal can be adjusted in advance before the predicted sampling points may deviate, thereby adapting to changes in various working conditions. When changes in working conditions cause clock signal or data phase drift, automatic and real-time adjustment of the sampling points can be achieved.

[0014] In a preferred embodiment, the interval between two adjacent first predictive sampling clock signals is the delay value of the second delay chain; and the interval between the first predictive sampling clock signal closest to the reference sampling clock signal and the reference sampling clock signal is the delay value of the second delay chain, with the reference sampling clock signal lagging behind the first predictive sampling clock signal.

[0015] Furthermore, the interval between two adjacent second predictive sampling clock signals is the delay value of the second delay chain; and the interval between the second predictive sampling clock signal closest to the reference sampling clock signal and the reference sampling clock signal is the delay value of the second delay chain, with the second predictive sampling clock signal lagging behind the reference sampling clock signal.

[0016] Therefore, the first predictive sampling clock signal and the second predictive sampling clock signal form warning clock signals on both sides of the reference sampling clock signal. Furthermore, by adjusting the delay value of the second delay chain, the phase of the two predictive sampling clock signals can be flexibly adjusted, making the adjustment of the reference sampling clock signal more flexible.

[0017] A further approach involves adjusting the reference sampling clock signal based on the sampling results of the response data sequence using the reference sampling clock signal, the first predictive sampling clock signal, and the second predictive sampling clock signal. This includes: if the first predictive sampling clock signal fails to correctly sample the response data sequence, increasing the delay value of the first delay chain; and if the second predictive sampling clock signal fails to correctly sample the response data sequence, decreasing the delay value of the first delay chain.

[0018] Therefore, by judging whether the two predictive sampling clock signals can correctly sample the response data sequence, the delay value of the first delay chain can be dynamically adjusted, thereby quickly adjusting the phase of the reference sampling clock signal and adaptively adjusting the sampling point.

[0019] A further proposed solution is that the delay value of the second delay chain is a preset value of the period of the reference sampling clock signal, which is less than 1 / 2; and, in the case of single-edge sampling, the time between the first output and the last output of the second delay chain does not exceed one period of the reference sampling clock signal, and in the case of double-edge sampling, the time between the first output and the last output of the second delay chain does not exceed half a period of the reference sampling clock signal.

[0020] Therefore, when the frequency of the reference sampling clock signal changes, the delay value of the second delay chain also changes. Thus, the present invention can adaptively and dynamically adjust the phase of the two predictive sampling clock signals according to the frequency change of the reference sampling clock signal, making the adjustment of the reference sampling clock signal more accurate.

[0021] A further approach is to set the preset value before the first device sends the preset data sequence to the second device.

[0022] It is evident that by setting preset values ​​in advance, avoiding dynamic setting of preset values ​​through software during the sampling point adjustment process, the amount of software program execution during the sampling point adjustment process can be reduced. Adjusting the phase of the two predictive sampling clock signals through hardware can improve the adjustment speed of the sampling points.

[0023] A further approach involves sampling the response data sequence using a reference sampling clock signal, a first predictive sampling clock signal, and a second predictive sampling clock signal. This includes: sampling the response data sequence using the reference sampling clock signal, the first predictive sampling clock signal, and the second predictive sampling clock signal to obtain three target sampled data; sampling the data using the reference sampling clock signal to obtain a verification status signal; sampling the three target sampled data and the verification status signal using the reference sampling clock signal to obtain three synchronous clock signals and a synchronous verification signal; and determining whether the sampled values ​​of the three synchronous clock signals within the interval of the synchronous verification signal are correct.

[0024] As can be seen, the above steps can easily determine whether the reference sampling clock signal, the first predictive sampling clock signal, and the second predictive sampling clock signal can correctly sample the response data sequence. Moreover, all the above steps are implemented in hardware, which can improve the speed of sampling point adjustment and make the sampling point adjustment more flexible.

[0025] A further approach involves sampling the three target sample data and the verification status signal using a reference sampling clock signal, including sampling the three target sample data and the verification status signal using the falling edge of the reference sampling clock signal.

[0026] A further approach is to obtain the verification status signal by sampling the reference sampling clock signal, which includes: after the reference sampling clock signal samples the start bit of the verification signal, outputting the verification status signal at the first falling edge.

[0027] This allows for the rapid output of a verification status signal, facilitating the accurate identification of whether the three synchronous clock signals have correctly obtained sampled values.

[0028] To achieve the second objective mentioned above, the adaptive data sampling device provided by the present invention includes a first device and a second device. The first device sends a preset data sequence to the second device, and the second device returns a response data sequence to the first device. The first device is equipped with a first delay chain and a second delay chain. The first device uses the first delay chain to generate an original sampling clock signal, and uses the second delay chain to generate at least one first predictive sampling clock signal, a reference sampling clock signal, and at least one second predictive sampling clock signal based on the original sampling clock signal. The first device uses the reference sampling clock signal, the first predictive sampling clock signal, and the second predictive sampling clock signal to sample the response data sequence, and adjusts the reference sampling clock signal based on the sampling result of the reference sampling clock signal, the first predictive sampling clock signal, and the second predictive sampling clock signal. Attached Figure Description

[0029] Figure 1This is a structural block diagram of the first and second devices.

[0030] Figure 2 This is a schematic diagram of the system structure of an embodiment of the adaptive data sampling device of the present invention.

[0031] Figure 3 This is a schematic diagram of the verification status of a successful response data sequence verification in an embodiment of the adaptive data sampling method of the present invention.

[0032] Figure 4 This is a schematic diagram of the verification status when the response data sequence verification fails in an embodiment of the adaptive data sampling method of the present invention.

[0033] Figure 5 This is a flowchart of an embodiment of the adaptive data sampling method of the present invention.

[0034] Figure 6 This is a waveform diagram of each signal sampled from a preset data sequence using an embodiment of the adaptive data sampling method of the present invention.

[0035] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0036] The adaptive data sampling method of the present invention is used to adjust the data sampling points between two devices in a computer system, and can automatically adjust the sampling points according to the delay changes between the two devices transmitting and receiving data.

[0037] The adaptive data sampling device of the present invention includes a first device and a second device. The first device can send a preset data sequence to the second device. After receiving the preset data sequence, the second device sends a response data sequence to the first device. The first device calculates the available sampling points by sampling the response data sequence.

[0038] See Figure 2 The first device contains a first delay chain 21 and a second delay chain 22. The first delay chain 21 is used for tuning the sampling point (adjusting an available sampling point when the system first starts working) and adjusting the sampling clock delay during operation. The second delay chain 22 is used to adjust the reference sampling clock signal and two predictive sampling clock signals based on the original sampling clock signal. Figure 2As can be seen, after the clock signal passes through the first delay chain 21, a usable original sampled clock signal is formed through the adjustment of the first delay chain 21. The second delay chain can receive the delay value output by the first delay chain. Each time the clock signal passes through the second delay chain, a delay of one stage is generated in the clock signal; this delay is the delay value of the second delay chain. Therefore, after the original sampled clock signal passes through the second delay chain, the second delay chain can delay the original sampled clock signal multiple times, thereby forming multiple clock signals with the same frequency and phases successively differing by a preset phase. These clock signals include a first predictive sampled clock signal, a reference sampled clock signal, and a second predictive sampled clock signal with successively lagging phases.

[0039] Of course, in this embodiment, there is only one first predictive sampling clock signal and one second predictive sampling clock signal. In actual applications, there can be two or more first predictive sampling clock signals and second predictive sampling clock signals. Furthermore, the interval between two adjacent first predictive sampling clock signals is the delay value of the second delay chain; and the interval between the first predictive sampling clock signal closest to the reference sampling clock signal and the reference sampling clock signal is the delay value of the second delay chain, with the reference sampling clock signal lagging behind the first predictive sampling clock signal.

[0040] The interval between two adjacent second predictive sampling clock signals is the delay value of the second delay chain. The interval between the second predictive sampling clock signal closest to the reference sampling clock signal and the reference sampling clock signal is the delay value of the second delay chain, and the second predictive sampling clock signal lags behind the reference sampling clock signal.

[0041] The reference sampling clock signal and the two predictive sampling clock signals are used to sample the response data sequence. That is, the input data is sampled by the reference sampling clock signal and the two predictive sampling clock signals. The sampled data is judged to determine whether the three sampling clock signals have correctly sampled the response data sequence, and the delay value of the first delay chain is adjusted accordingly.

[0042] In this embodiment, the first device can be an SD / eMMC storage host system, and the second device can be a storage device. The SD / eMMC protocol specification stipulates that after the storage device receives data from the host system, it performs a CRC check on the received data and returns the check result (CRCStatus) to the host system via the data0 line to indicate whether the data reception was successful. If the check is successful, the returned check result is "010"; if the check fails, the returned check result is "101". Figure 3 and Figure 4As shown, S in data0 represents the start bit, which has a data value of 0, i.e., a low-level signal; E in data0 represents the end bit, which has a data value of 1, i.e., a high-level signal.

[0043] Typically, data transfer operations on the host system, such as read and write operations, occur frequently, and the intervals between read and write operations are not long. Therefore, the host can usually automatically adjust the sampling point using the verification result returned by the flash memory during a normal write transfer operation, in which case the verification result value is "010". Of course, a normal write transfer may also result in the flash memory receiving data incorrectly for some reason, thus returning a verification result value of "101". In this case, it indicates that some kind of error has occurred in the data transfer between the host system and the flash memory. This error will be responded to and handled by the host system, and the automatic adjustment mechanism for the sampling point can choose to ignore such adjustment.

[0044] Of course, there may be situations where the host system does not issue any write operations for an extended period. In this case, the host system will not receive verification results during this time and will be unable to adjust the sampling point. To address this, a timer is added within the host system. If the lack of write operations exceeds a certain time, the host system is triggered to initiate an "additional write operation." The write data in this operation is a pre-defined erroneous data sequence. Because it is an erroneous data sequence, the flash memory will inevitably fail the verification, so the returned verification result is "101". The host system's controller can then use this fixed data sequence "101" to automatically adjust the sampling point.

[0045] The timing of the "additional write transfers" mentioned above can be flexibly controlled by the host system. A reasonable interval value can be debugged according to the specific application scenario, or it can be prioritized to be sent during idle time when there is no need for data interaction between the host system and the flash memory. The "additional write transfers" mentioned above are a certain error data sequence set by the host system. Using the error data sequence can ensure that the device returns a verification result of "101", and on the other hand, erroneous data will not be written to the flash memory.

[0046] Whether it's a "010" data sequence for normal write transmission or a "101" data sequence for additional write transmission, the sampling method used in this embodiment follows the same processing logic. The following example uses a "101" data sequence. Figure 5 The workflow of this embodiment will be described.

[0047] First, execute step S11 to determine if this is the first operation, i.e., whether the first device and the second device are transmitting data for the first time. If it is the first operation, it means that the first device and the second device have not undergone sampling point adjustment and have not obtained a usable original sampling clock signal. In this case, step S12 needs to be executed to obtain a usable original sampling clock signal using the first delay chain tuning. If this is not the first operation, then a usable sampling clock signal was already obtained during the previous operation, and step S13 can be executed directly without obtaining a reference sampling clock signal.

[0048] In step S12, before the host system begins operation, it first uses a tuning method to select a reliable sampling point using its internal first delay chain to determine the phase of the original sampling clock signal. Thus, when the host system begins operation, it first uses the previously selected sampling point for sampling. During subsequent operation, the host system automatically adjusts the sampling point each time it receives a verification result.

[0049] Then, step S13 is executed, where data transmission occurs between the host system and the flash memory. For example, the host system sends a preset data sequence to the flash memory, and after receiving the preset data sequence, the flash memory returns a response data sequence to the host system. In this embodiment, the host system continuously monitors the sampling points during data transmission and can dynamically adjust the sampling points. To this end, step S14 is executed to determine whether the data transmission has ended. If the data transmission has ended, the adaptive data sampling program ends. If the data transmission has not ended, step S15 is executed to determine whether a response data sequence sent by the flash memory has been received. If no response data sequence has been received, the process returns to step S13 to continue data transmission. If a response data sequence has been received, step S16 is executed.

[0050] In step S16, the host system generates a first predictive sampling clock signal, a reference sampling clock signal, and a second predictive sampling clock signal based on the original sampling clock signal and by applying a second delay chain. See also... Figure 6 data0 is the response data sequence returned by the flash memory, which includes the verification result. Figure 6 The verification result is a data sequence of "101". The part between numbers 3 and 4 is the start bit of the verification result, which is a low-level signal. The part between numbers 4 and 5 is the first bit of the verification result, which is a binary number "1". The part between numbers 5 and 6 is the second bit of the verification result, which is a binary number "0". The part between numbers 6 and 7 is the third bit of the verification result, which is a binary number "1". The part between numbers 7 and 8 is the end bit of the verification result, which is a high-level signal.

[0051] The first predicted sampling clock signal generated based on the second delay chain is clk1, the generated reference sampling clock signal is clk2, and the generated second predicted sampling clock signal is clk3. In this embodiment, the delay value of the second delay chain is a preset value of the period of the reference sampling clock signal clk2, and the preset value is less than 1 / 2, for example, the preset value is 1 / 4 or 1 / 8, etc. The preset value can be preset, for example, by software program. The preset value can be set according to the actual use scenario, and is not limited to 1 / 4 or 1 / 8, but can also be set to other preset values. Furthermore, this preset value is set before the host system sends the preset data sequence to the flash memory.

[0052] Furthermore, in the case of single-edge sampling, the time between the first output and the last output of the second delay chain does not exceed one cycle of the reference sampling clock signal, and in the case of double-edge sampling, the time between the first output and the last output of the second delay chain does not exceed half a cycle of the reference sampling clock signal.

[0053] from Figure 6 As can be seen, the first predictive sampling clock signal clk1, the reference sampling clock signal clk2, and the second predictive sampling clock signal clk3 have the same frequency. The phase of the first predictive sampling clock signal clk1 leads the phase of the reference sampling clock signal clk2, while the phase of the second predictive sampling clock signal clk3 lags behind the phase of the reference sampling clock signal clk2. Thus, the first predictive sampling clock signal clk1 and the second predictive sampling clock signal clk3 are actually warning clock signals formed on both sides of the reference sampling clock signal clk2.

[0054] It is understandable that if both the first predictive sampling clock signal clk1 and the second predictive sampling clock signal clk3 can correctly sample the data sequence of the verification results, then the reference sampling clock signal can be considered a suitable sampling point, and there is no need to adjust the phase of the reference sampling clock signal clk2. If the first predictive sampling clock signal clk1 or the second predictive sampling clock signal clk3 fails to correctly sample the verification data, it indicates that the phase of the reference sampling clock signal clk2 is inappropriate, and the phase of the reference sampling clock signal clk2 needs to be adjusted, that is, the delay value of the first delay chain needs to be adjusted.

[0055] Therefore, after executing step S16, step S17 needs to be executed to sample the response data sequence using the first predictive sampling clock signal clk1, the reference sampling clock signal clk2, and the second predictive sampling clock signal clk3. Specifically, the first predictive sampling clock signal clk1, the reference sampling clock signal clk2, and the second predictive sampling clock signal clk3 are used to sample data0 respectively, obtaining three target sampled data, namely, the target sampled data data0_clk1, data0_clk2, and data0_clk3. Furthermore, after the reference sampling clock signal clk2 samples the start bit of the verification result, it outputs the verification status signal crc_status on the first falling edge to indicate the valid range of the verification result.

[0056] Then, the target sampled data data0_clk1, data0_clk2, and data0_clk3 are sampled using the falling edge of the reference sampling clock signal clk2 to obtain three synchronized clock signals data0_clk1_sync, data0_clk2_sync, and data0_clk3_sync. Furthermore, the verification status signal crc_status is sampled using the falling edge of the reference sampling clock signal clk2 to obtain the synchronization verification signal crc_status_sync. Finally, it is determined whether the sampled values ​​of the three synchronization clock signals data0_clk1_sync, data0_clk2_sync, and data0_clk3_sync within the interval of the synchronization verification signal crc_status_sync are correct.

[0057] Therefore, after executing step S17, step S18 needs to be executed to determine whether the sampling point has deviated, that is, to determine whether the sampling values ​​of the three synchronous clock signals data0_clk1_sync, data0_clk2_sync, and data0_clk3_sync within the interval of the synchronous verification signal crc_status_sync are correct. If there is no deviation, it is not necessary to adjust the phase of the reference sampling clock signal clk2, that is, it is not necessary to adjust the delay value of the first delay chain, and return to execute step S13.

[0058] If any of the sampled values ​​of the three synchronization clock signals data0_clk1_sync, data0_clk2_sync, and data0_clk3_sync within the interval of the synchronization verification signal crc_status_sync are incorrect, it indicates that the sampling point has deviated, and step S19 needs to be executed to adjust the delay value of the first delay chain, which is actually adjusting the phase of the reference sampling clock signal clk2.

[0059] like Figure 6 As shown, the sampled values ​​of the three synchronization clock signals data0_clk1_sync, data0_clk2_sync, and data0_clk3_sync within the interval of the synchronization verification signal crc_status_sync are 010, 101, and 101, respectively. Since the correct sampled value should be 101, therefore... Figure 6 The results show that the first predicted sampling clock signal clk1 did not correctly sample the verification result, indicating that the predicted sampling point was too early. Therefore, the delay value of the first delay chain needs to be increased. If the second predicted sampling clock signal clk3 did not correctly sample the verification result, indicating that the predicted sampling point was too late, the delay value of the first delay chain should be decreased.

[0060] Finally, the transmitted data is sampled using the phase-adjusted reference sampling clock signal clk2, and then the process returns to step S13.

[0061] Because this embodiment generates two predictive sampling clock signals through a second delay chain, these two predictive sampling clock signals can serve as early warning clock signals for deviations from the reference sampling clock signal. By predicting changes in the sampling point using these early warning clock signals, the reference sampling clock signal can be adjusted in advance when a deviation occurs, thus adapting to changes in various operating conditions. In this way, when changes in operating conditions cause clock signal or data phase drift, automatic and real-time adjustment of the sampling point can be achieved.

[0062] Furthermore, since the sampling of the synchronization clock signal and the synchronization check signal is implemented through hardware circuitry, and the acquisition of the sampled values ​​corresponding to the three synchronization clock signals data0_clk1_sync, data0_clk2_sync, and data0_clk3_sync within the interval of the synchronization check signal crc_status_sync is also implemented through hardware circuitry, and the increase or decrease of the delay value of the first delay chain can also be implemented through hardware circuitry, the phase adjustment process of the reference sampling clock signal clk2 is basically implemented through hardware circuitry. Compared with the method of adjusting the sampling points through sampling software programs, this embodiment can quickly achieve the adjustment of the sampling points.

[0063] Finally, it should be emphasized that the present invention is not limited to the above-described embodiments. For example, changes in the delay value of the second delay chain or changes in the sampling method of the synchronization clock signal should also be included within the scope of protection of the claims of the present invention.

Claims

1. An adaptive data sampling method, comprising: The first device sends a preset data sequence to the second device, and the second device returns a response data sequence to the first device; Its features are: The first device uses a first delay chain to generate an original sampling clock signal, and uses a second delay chain to generate at least one first predicted sampling clock signal, a reference sampling clock signal, and at least one second predicted sampling clock signal based on the original sampling clock signal. The device uses the reference sampling clock signal, the first predicted sampling clock signal, and the second predicted sampling clock signal to sample the response data sequence, and adjusts the reference sampling clock signal according to the sampling result of the reference sampling clock signal, the first predicted sampling clock signal, and the second predicted sampling clock signal. The sampling of the response data sequence using the reference sampling clock signal, the first prediction sampling clock signal, and the second prediction sampling clock signal includes: The response data sequence is sampled using the reference sampling clock signal, the first predictive sampling clock signal, and the second predictive sampling clock signal to obtain three target sampled data. A verification status signal is obtained by sampling using the reference sampling clock signal. The three target sampled data and the verification status signal are sampled using the reference sampling clock signal to obtain three synchronization clock signals and a synchronization verification signal. It is then determined whether the sampled values ​​of the three synchronization clock signals within the interval of the synchronization verification signal are correct. The delay value of the second delay chain is a preset value of the period of the reference sampling clock signal, and the preset value is less than 1 / 2; During single-edge sampling, the time interval between the first and last outputs of the second delay chain does not exceed one cycle of the reference sampling clock signal; during double-edge sampling, the time interval between the first and last outputs of the second delay chain does not exceed half a cycle of the reference sampling clock signal.

2. The adaptive data sampling method according to claim 1, characterized in that: The interval between two adjacent first predictive sampling clock signals is the delay value of the second delay chain; and the interval between the first predictive sampling clock signal closest to the reference sampling clock signal and the reference sampling clock signal is the delay value of the second delay chain, wherein the reference sampling clock signal lags behind the first predictive sampling clock signal.

3. The adaptive data sampling method according to claim 2, characterized in that: The interval between two adjacent second predictive sampling clock signals is the delay value of the second delay chain; and the interval between the second predictive sampling clock signal closest to the reference sampling clock signal and the reference sampling clock signal is the delay value of the second delay chain, wherein the second predictive sampling clock signal lags behind the reference sampling clock signal.

4. The adaptive data sampling method according to claim 3, characterized in that: Adjusting the reference sampling clock signal based on the result of sampling the response data sequence using the reference sampling clock signal, the first predictive sampling clock signal, and the second predictive sampling clock signal includes: If the first predictive sampling clock signal fails to correctly sample the response data sequence, the delay value of the first delay chain is increased; If the second predictive sampling clock signal fails to correctly sample the response data sequence, the delay value of the first delay chain is reduced.

5. The adaptive data sampling method according to claim 1, characterized in that: The preset value is set before the first device sends the preset data sequence to the second device.

6. The adaptive data sampling method according to claim 1, characterized in that: Sampling the three target sampled data and the verification status signal using the reference sampling clock signal includes: The falling edge of the reference sampling clock signal is used to sample the three target sampling data and the verification status signal.

7. The adaptive data sampling method according to claim 5, characterized in that: The verification status signal is obtained by sampling the reference sampling clock signal, including: After the reference sampling clock signal samples the start bit of the verification signal, the verification status signal is output at the first falling edge.

8. An adaptive data sampling device, comprising a first device and a second device, wherein the first device sends a preset data sequence to the second device, and the second device returns a response data sequence to the first device; Its features are: The first device is equipped with a first delay chain and a second delay chain. The first device uses the first delay chain to generate an original sampling clock signal and uses the second delay chain to generate at least one first predictive sampling clock signal, a reference sampling clock signal, and at least one second predictive sampling clock signal based on the original sampling clock signal. The first device uses the reference sampling clock signal, the first predictive sampling clock signal, and the second predictive sampling clock signal to sample the response data sequence. The reference sampling clock signal is adjusted according to the result of sampling the response data sequence using the reference sampling clock signal, the first predictive sampling clock signal, and the second predictive sampling clock signal. The sampling of the response data sequence using the reference sampling clock signal, the first prediction sampling clock signal, and the second prediction sampling clock signal includes: The response data sequence is sampled using the reference sampling clock signal, the first predictive sampling clock signal, and the second predictive sampling clock signal to obtain three target sampled data. A verification status signal is obtained by sampling using the reference sampling clock signal. The three target sampled data and the verification status signal are sampled using the reference sampling clock signal to obtain three synchronization clock signals and a synchronization verification signal. It is then determined whether the sampled values ​​of the three synchronization clock signals within the interval of the synchronization verification signal are correct. The delay value of the second delay chain is a preset value of the period of the reference sampling clock signal, and the preset value is less than 1 / 2; During single-edge sampling, the time interval between the first and last outputs of the second delay chain does not exceed one cycle of the reference sampling clock signal; during double-edge sampling, the time interval between the first and last outputs of the second delay chain does not exceed half a cycle of the reference sampling clock signal.

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