Data transmission apparatus, method and system

Abstract

A data transmission device, method and system. The device comprises: a control unit configured to obtain characteristic parameters of to-be-transmitted data from a memory at a processing system end, the to-be-transmitted data being fixed-point data and not zero-padded; a transmission unit configured to read the to-be-transmitted data from the memory at the processing system end according to a bandwidth of a transmission interface based on the first characteristic parameters obtained by the control unit, and to generate each individual to-be-transmitted data by shifting the read data; a data processing unit configured to process the to-be-transmitted data generated by the transmission unit based on second characteristic parameters obtained by the control unit; and a data rearrangement unit configured to zero-pad and align the to-be-transmitted data processed by the data processing unit based on third characteristic parameters obtained by the control unit, to obtain input data of an AI accelerator and to write the input data into a memory at an acceleration engine end. The above scheme can improve data transmission efficiency.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology, and specifically to a data transmission device, method, and system. Background Technology

[0002] Artificial Intelligence (AI) accelerators are a type of specialized hardware accelerator or computer system designed to accelerate the application of artificial intelligence, especially artificial neural networks, machine vision, and machine learning.

[0003] In practical applications, preprocessed data is typically stored in the processing system's memory. The direct memory access module can read data from the processing system's memory and store it in the acceleration engine's memory. The acceleration engine's memory is connected to the AI ​​accelerator and provides input data to it.

[0004] However, the existing process of providing input data for AI accelerators involves some waste of resources, resulting in long data transmission times and low data transmission efficiency. Summary of the Invention

[0005] The problem this invention aims to solve is: how to improve data transmission efficiency in the process of providing input data for AI accelerators?

[0006] To address the above problems, embodiments of the present invention provide a data transmission device, the device comprising:

[0007] A control unit is connected to a processing system-side memory; the processing system-side memory has a transmission interface and stores data to be transmitted; the control unit is used to obtain characteristic parameters of the data to be transmitted from the processing system-side memory, the data to be transmitted being fixed-point data and not padded with zeros; the characteristic parameters include: a first characteristic parameter, a second characteristic parameter, and a third characteristic parameter;

[0008] The transmission unit is connected to the processing system-side memory and the control unit. Based on the first characteristic parameter obtained by the control unit, it reads the data to be transmitted from the processing system-side memory according to the bandwidth of the transmission interface, and shifts the read data to generate each individual data to be transmitted.

[0009] A data processing unit, connected to the transmission unit and the control unit, processes the data to be transmitted generated by the transmission unit based on the second feature parameter obtained by the control unit.

[0010] The data rearrangement unit, connected to the data processing unit and the control unit, performs zero-padding alignment on the data to be transmitted after being processed by the data processing unit based on the third feature parameter obtained by the control unit, thereby obtaining the input data of the AI ​​accelerator and writing it into the memory of the acceleration engine.

[0011] This invention also provides a data transmission system, which includes the data transmission device described above.

[0012] This invention also provides a data transmission method, the method comprising:

[0013] The characteristic parameters of the data to be transmitted are obtained from the memory of the processing system. The data to be transmitted is fixed-point data and is not padded with zeros. The characteristic parameters include: a first characteristic parameter, a second characteristic parameter, and a third characteristic parameter.

[0014] Based on the first feature parameter, the data to be transmitted is read from the memory of the processing system according to the bandwidth of the transmission interface; and the read data is shifted to generate each individual data to be transmitted.

[0015] Based on the second feature parameter, the spliced ​​and shifted data to be transmitted is processed;

[0016] Based on the third feature parameter, the data to be transmitted for data processing is zero-padded and aligned to obtain the input data of the AI ​​accelerator and written to the memory of the acceleration engine.

[0017] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0018] By applying the solution of this invention, since the data to be transmitted stored in the processing system's memory is not padded with zeros, the data read by the transmission unit from the processing system's memory does not contain zero-padded bits. This allows for full utilization of the transmission interface bandwidth of the processing system's memory, thereby improving reading efficiency. The data read from the processing system's memory sequentially passes through the transmission unit, data processing unit, and data rearrangement unit to obtain the input data for the AI ​​accelerator and is written to the acceleration engine's memory. Throughout the data transmission process, the transmission interface bandwidth of the processing system's memory is fully utilized, further improving data transmission efficiency. Furthermore, the data transmission device of this invention has one end connected to the processing system's memory and the other end connected to the acceleration engine's memory. The control unit can simultaneously control the transmission unit, data processing unit, and data rearrangement unit. This is a hardware implementation scheme. Using the data transmission device of this invention to perform data preprocessing such as zero padding, compared to using software for data preprocessing on the processing system side, saves more time and further improves data transmission efficiency.

[0019] Furthermore, the data rearrangement unit can rearrange the data to be transmitted after being processed by the data processing unit, or it can choose not to rearrange the data to be transmitted after being processed by the data processing unit. This allows the data transmission device to adjust the input data written to the acceleration engine's memory according to actual needs, so as to better meet actual requirements.

[0020] Furthermore, when determining whether to rearrange the data to be transmitted after processing by the data processing unit, the data rearrangement unit can rearrange the data to be transmitted based on the bit width supported by the AI ​​accelerator. This allows the input data written to the acceleration engine's memory to be compatible with the AI ​​accelerator's computing resources, reducing the waste of computing resources. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a data transmission process;

[0022] Figure 2 This is a schematic diagram of the structure of a data transmission device according to an embodiment of the present invention;

[0023] Figure 3 This is a flowchart of a data transmission method according to an embodiment of the present invention. Detailed Implementation

[0024] Figure 1 This is a schematic diagram of the existing process for providing input data to AI accelerators. (Refer to...) Figure 1 The data to be transmitted is preprocessed and stored in the processing system-side memory 11. The direct storage access module 12 reads data from the processing system-side memory 11 and stores the read data in the acceleration engine-side memory 13, thus completing the conversion from the processing system spatial data layout format to the acceleration engine spatial data layout format. The AI ​​accelerator 14 can read input data from the acceleration engine-side memory 13.

[0025] The preprocessing includes zero-padding and quantization. Since the number of data channels supported by the AI ​​accelerator 14 and the number of channels in the data to be transmitted may not match—for example, the AI ​​accelerator 14 supports 32 channels of data, but the data to be transmitted may be 3 channels—zero-padding is necessary to convert the 3-channel data to 32-channel data. Quantization is used to convert the data to be transmitted from floating-point data to fixed-point data.

[0026] Fixed-point and floating-point data refer to whether the decimal point in a given number is fixed or floating in a computer's memory. Fixed-point data has a fixed decimal point, while floating-point data has a floating decimal point. Generally, fixed-point formats can represent a limited range of values ​​but require simpler processing hardware. Floating-point formats can represent a wide range of values ​​but require more complex processing hardware. To accommodate the AI ​​Accelerator 14, the data to be transmitted needs to be converted from floating-point to fixed-point data.

[0027] During the aforementioned data transmission process, the processing system-side memory 11 has a high-performance interface. The bandwidth supported by this high-performance interface is typically much larger than the actual bandwidth of the preprocessed data. Therefore, bandwidth is wasted when reading data through the high-performance interface. For example, if the actual bandwidth of the preprocessed data is 24 bits, while the high-performance interface supports a bandwidth of 64 bits, and the data written to the acceleration engine-side memory 13 should be 512 bits, then when reading data through the high-performance interface, 64 bits of data are read from the processing system-side memory 11 each time. Of these, 24 bits of the first 64 bits read are valid data, and the remaining bits are padded with zeros (i.e., all remaining bits are 0). The remaining reads also use padded zeros. Therefore, bandwidth is wasted, leading to long data transmission times and low data transmission efficiency.

[0028] To address this problem, the present invention provides a data transmission device in which the data to be transmitted stored in the processing system-side memory is not padded with zeros. Therefore, when the transmission unit reads data from the processing system-side memory, the data read does not contain zero-padded bits. The transmission interface bandwidth of the processing system-side memory can be fully utilized, thereby improving reading efficiency and thus improving data transmission efficiency.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Reference Figure 2 This invention provides a data transmission device 20, which may include: a control unit 210, a transmission unit 220, a data processing unit 230, and a data rearrangement unit 240. Wherein:

[0031] The control unit 210 is connected to the processing system-side memory 10; the processing system-side memory 10 stores a plurality of data to be transmitted; the control unit 210 is used to obtain characteristic parameters of the data to be transmitted from the processing system-side memory 10, wherein the data to be transmitted is fixed-point data and is not padded with zeros; the characteristic parameters include: a first characteristic parameter, a second characteristic parameter, and a third characteristic parameter;

[0032] The transmission unit 220 is connected to the processing system-side memory 10 and the control unit 210. Based on the first feature parameter obtained by the control unit 210, it reads the data to be transmitted from the processing system-side memory 10 according to the bandwidth of the transmission interface, and shifts the read data to generate each individual data to be transmitted.

[0033] The data processing unit 230 is connected to the transmission unit 220 and the control unit 210, and processes the data to be transmitted generated by the transmission unit 220 based on the second feature parameter obtained by the control unit 210.

[0034] The data rearrangement unit 240 is connected to the data processing unit 230 and the control unit 210. Based on the third feature parameter obtained by the control unit 210, it performs zero-padding alignment on the data to be transmitted after processing by the data processing unit 230 to obtain the input data of the AI ​​accelerator 40 and writes it into the acceleration engine end memory 30.

[0035] The data transmission device of the present invention has one end connected to the processing system's memory 10 and the other end connected to the acceleration engine's memory 30. The control unit 210 can simultaneously control the transmission unit 220, the data processing unit 230, and the data rearrangement unit 240; this is a hardware implementation scheme. Using the data transmission device of the present invention to perform data preprocessing such as zero padding, compared to using software for data preprocessing on the processing system side, can save more time and further improve data transmission efficiency.

[0036] In a specific implementation, the processing system-side memory 10 refers to the memory within the processing system, used to store the data to be transmitted. The processing system can be a processing system that runs neural network algorithms. The data to be transmitted stored in the processing system-side memory 10 is converted into input data for the AI ​​accelerator via the data transmission device 20 and stored in the acceleration engine-side memory 30. The acceleration engine-side memory 30 refers to the memory connected to the AI ​​accelerator 40 and storing the input data of the AI ​​accelerator 40. The acceleration engine-side memory 30 can be a field-programmable gate array (FPGA) memory or a dedicated acceleration circuit memory, etc.

[0037] In specific implementation, the data to be transmitted stored in the processing system's memory 10 is fixed-point data and is not padded with zeros. That is to say, before the data to be transmitted is stored in the processing system's memory 10, it has been converted from floating-point data to fixed-point data, but no zero-padding operation is performed, and the actual bit width of the data to be transmitted is still maintained.

[0038] Taking image data as an example, each pixel in the image corresponds to a piece of data to be transmitted. The processing system's memory 10 can store multiple pixels, that is, it can store multiple pieces of data to be transmitted.

[0039] In a specific implementation, the processing system-side memory 10 and the transmission unit 220 have a high-performance transmission interface, the transmission bandwidth of which is typically greater than the bit width of the data to be transmitted. When the transmission unit 220 reads data from the processing system-side memory 10, it can read the data according to the bandwidth of the transmission interface.

[0040] It should be noted that, in the embodiments of the present invention, the data to be transmitted may be only one or multiple, and the specific number is not limited. Each data to be transmitted is processed by the data transmission device to form input data for an AI accelerator.

[0041] In a specific implementation, the transmission unit 220 concatenates the data read from two or more times and then generates each individual data to be transmitted by shifting; or, the transmission unit 220 directly shifts the read data to generate each individual data to be transmitted.

[0042] For example, if the bandwidth of the transmission interface is 64 bits and the bit width of the data to be transmitted is 24 bits, then the transmission unit 220 can read 64 bits of data from the processing system's memory 10 each time. Assuming there are 8 data items to be transmitted, and each data item is 3-channel RGB data, since each channel has a bit width of 8 bits, each data item will have a total of 24 bits. In this case, the 64 bits of data read by the transmission unit 220 at one time can include two complete data items to be transmitted, and can also include the R channel data and G channel data of the third data item, totaling 16 bits. The 8 data items to be transmitted total 192 bits. Reading 64 bits at a time requires 3 reads to completely read all 8 data items. At this point, the data from the 3 reads can be concatenated and then used to represent each individual data item to be transmitted.

[0043] Assuming each piece of data to be transmitted is 2-channel data, that is, each piece of data to be transmitted is 16 bits, and the bandwidth of the transmission interface is 64 bits, each time the data is read, there are a total of 4 pieces of data to be transmitted. At this time, the transmission unit 220 can directly shift the data read once to generate each individual piece of data to be transmitted without concatenation.

[0044] In specific implementation, the control unit 210 can obtain characteristic parameters of the data to be transmitted in a variety of ways, without any specific limitation. For example, an external general interface can be set up for staff to input the characteristic parameters.

[0045] In one embodiment of the present invention, a first register may be provided in the control unit 210. The first register may be used to store the feature parameters written to the processing system-side memory. In other words, the processing system-side memory 10 may write the feature parameters into the first memory. The control unit may control the transmission unit 220, the data processing unit 230, and the data rearrangement unit 240 based on the feature parameters.

[0046] In a specific implementation, the feature parameters may include a first feature parameter, a second feature parameter, and a third feature parameter. The first feature parameter is used to control the transmission unit 220, the second feature parameter is used to control the data processing unit 230, and the third feature parameter is used to control the data rearrangement unit 240.

[0047] In a specific implementation, taking image data as an example, the first feature parameter can be the number of channels in the data to be transmitted and the size parameters of the image. For example, the width and height parameters of the image. Based on the first feature parameter, the transmission unit 220 can determine the bit width of each piece of data to be transmitted, as well as the number of pieces of data to be transmitted. Based on the number of channels in the data to be transmitted, the number of bits corresponding to each channel can be determined. Thus, based on the first feature parameter, operations such as splicing and shifting can be performed.

[0048] For example, based on the first feature parameter, it can be determined that there are a total of 8 data points to be transmitted, corresponding to 8 pixels in the image. Each data point to be transmitted is 3-channel RGB data. Thus, the transmission unit 220 can read data three times through the high-performance interface (64-bit width) to obtain the 8 data points to be transmitted. These 8 data points to be transmitted are stored in the transmission unit 220 by concatenation. Then, each data point to be transmitted (24 bits) is generated by shifting, that is, the data corresponding to one pixel is generated.

[0049] In one embodiment of the present invention, the first feature parameter is configurable. Specifically, the first feature parameter written to the first register can be changed by controlling the processing system-side memory 10, thereby allowing for flexible adjustment of the splicing and shifting operation of the transmission unit 220.

[0050] In practice, the transmission unit 220 performs splicing and shifting operations based on the first characteristic parameter. When the first characteristic parameter changes, the specific scheme for splicing and shifting performed by the transmission unit 220 will also change accordingly. For example, the number of channels for the data to be transmitted may not be limited to 3; the splicing and shifting methods will differ depending on the requirements for the number of input data channels.

[0051] In a specific implementation, the second feature parameter may include: mean, scaling factor, etc. The data processing unit 230 processes the data to be transmitted generated by the transmission unit 220 based on the second feature parameter. This processing of the data to be transmitted may include performing the relevant calculations required for quantization, or changing the data range of the data to be transmitted. Specifically, data processing can be performed according to the needs of the AI ​​accelerator in running related algorithms, to facilitate the operation of these algorithms.

[0052] The data processing unit 230 typically includes multipliers and adders, which perform at least one of multiplication and addition operations on the data output by the transmission unit 220 to quantize the data to be transmitted. Each piece of data to be transmitted produces a processing result after passing through the data processing unit 230. When the data processing unit 230 changes the data range, for example, the data to be transmitted can be calculated as follows: subtract the mean value from the number to be transmitted output by the transmission unit 220, and then multiply by a scaling factor. This allows the data processing unit 230 to change the data range of the data to be transmitted.

[0053] In a specific implementation, the third feature parameter may include information such as the number of data channels supported by the AI ​​accelerator 40. Based on the third feature parameter, the data rearrangement unit 240 can directly zero-padded and aligned each processing result output by the data processing unit 230 to obtain the input data of the AI ​​accelerator 40 and write it into the acceleration engine-side memory 30.

[0054] For example, the acceleration engine-side memory 30 should store data in 512-bit units. If the processing result output by the data processing unit 230 has a bit width of 10 bits, the data rearrangement unit 240 can directly pad the 10 bits with zeros to align it to 512 bits before storing it in the acceleration engine-side memory 30.

[0055] In one embodiment of the present invention, the third feature parameter includes a first flag bit. The first flag bit is used to indicate whether the data to be transmitted after being processed by the data processing unit is rearranged.

[0056] Accordingly, the data rearrangement unit 240 can determine whether to rearrange the data to be transmitted after being processed by the data processing unit 230 based on the first flag bit, and process the data to be transmitted after being processed by the data processing unit 230 based on the determination result to obtain the input data of the AI ​​accelerator 40 and write it to the acceleration engine end memory 30.

[0057] Specifically, when the first flag indicates that the data to be transmitted after being processed by the data processing unit 230 is not rearranged, the data rearrangement unit 240 performs zero-padding alignment on the data to be transmitted after being processed by the data processing unit 230 to obtain the input data of the AI ​​accelerator 40 and writes it to the acceleration engine end memory 30.

[0058] When the first flag indicates that the data to be transmitted after being processed by the data processing unit 230 is rearranged, the data to be transmitted is rearranged based on the bit width supported by the AI ​​accelerator 40. After the data is rearranged, the data to be transmitted after being processed by the data processing unit 230 is zero-padded for alignment.

[0059] For example, the value of the first flag can be set to 0 to indicate that the data to be transmitted after processing by the data processing unit 230 is not rearranged, and the value of the first flag can be set to 1 to indicate that the data to be transmitted after processing by the data processing unit 230 is rearranged. When the value of the first flag is 0, the data rearrangement unit 240 does not rearrange the data, but directly pads the data to be transmitted after processing by the data processing unit 230 with zeros for alignment.

[0060] When the value of the first flag bit is 1, the data rearrangement unit 240 rearranges the data to be transmitted after processing by the data processing unit 230, then pads it with zeros for alignment and stores it in the acceleration engine-side memory 30. When the value of the first flag bit is 0, the data rearrangement unit 240 directly pads the data to be transmitted after processing by the data processing unit 230 with zeros for alignment and then stores it in the acceleration engine-side memory 30.

[0061] In practical implementation, when rearranging the data to be transmitted after processing by the data processing unit 230, the rearrangement can be based on the bit width supported by the AI ​​accelerator 40. For RGB image data, the bit width supported by the AI ​​accelerator 40 is the number of channels supported by the AI ​​accelerator 40. The bit width supported by the AI ​​accelerator 40 refers to the bit width required when the input data of the AI ​​accelerator 40 is used for relevant calculations within the AI ​​accelerator 40.

[0062] For example, if the computation within the AI ​​accelerator 40 is a convolutional computation requiring 27 channels, and the data to be transmitted after processing by the data processing unit 230 is 3*3 3-channel data, then this 3*3 3-channel data can be used as the convolution kernel. Each convolutional computation will concatenate image data with a length of 3, a width of 3, and 3 channels to form 27-channel data. This matches the number of channels supported by the convolutional computation within the AI ​​accelerator 40. The data ultimately stored in the acceleration engine's memory 30 is the 27-channel data padded with zeros. When the AI ​​accelerator 40 reads data from the acceleration engine's memory 30, it can obtain the 27-channel data in a single read, eliminating the need for multiple reads.

[0063] Based on the bit width supported by AI Accelerator 40, the data is rearranged and then zero-aligned to better match the relevant calculations within AI Accelerator 40, thereby reducing the waste of computing resources within AI Accelerator 40.

[0064] In another embodiment of the present invention, the data rearrangement unit 240 can perform data filling operation on the rearranged data according to preset filling parameters.

[0065] In a specific implementation, taking image data as an example, the fill parameters may include the number of fill pixels and the fill value. The fill parameters are configurable, thus allowing the edges of the image to be filled by configuring them. This makes the final input data size of the AI ​​accelerator 40 configurable, enabling the input data of the AI ​​accelerator 40 to be applicable to more application scenarios and meet the needs of more functions.

[0066] In one embodiment of the present invention, a second register may also be provided in the control unit 210, which may be used to store a second flag bit. The second flag bit is used to indicate whether the data transmission device 20 is started. When the second flag bit indicates that the data transmission device 20 is started, the transmission unit 220, the data processing unit 230, and the data rearrangement unit 240 begin to perform corresponding operations.

[0067] In a specific implementation, the processing system can control the processing system-side memory 10, causing the processing system-side memory 10 to write the value of the second flag bit to the second register. Before starting, the transmission unit 220, the data processing unit 230, and the data rearrangement unit 240 first read the value of the second flag bit in the second register, and determine whether to start executing the corresponding operation based on the value of the second flag bit.

[0068] For example, when the value of the second flag is 0, it indicates that the transmission unit 220, the data processing unit 230, and the data rearrangement unit 240 do not perform the corresponding operation. When the value of the second flag is 1, it indicates that the transmission unit 220, the data processing unit 230, and the data rearrangement unit 240 begin to perform the corresponding operation.

[0069] In one embodiment of the present invention, the control unit 210 may further include a third register. The third register is used to store the current status information of the transmission unit 220, the data processing unit 230, and the data rearrangement unit 240.

[0070] In specific implementations, the current status information may include the read status of the transmission unit 220 or the write status of the data rearrangement unit 240. For example, whether the transmission unit 220 and the data rearrangement unit 240 have started executing operations, or whether the corresponding operations have been completed, etc.

[0071] In one embodiment, the processing system-side memory 10 can read the current status information of the transmission unit 220, the data processing unit 230, and the data rearrangement unit 240 from the third register, and adjust the first feature parameter, the second feature parameter, and the third feature parameter based on the read current status information.

[0072] By reading the current status information of each unit, the characteristic parameters required for each unit to perform the corresponding operation can be adjusted in a timely manner, thereby enabling more accurate input of the required input data.

[0073] In some embodiments, after the processing system-side memory 10 can read the current status information of the transmission unit 220, the data processing unit 230 and the data rearrangement unit 240 from the third register, it can also verify the current status of the transmission unit 220, the data processing unit 230 and the data rearrangement unit 240 to determine whether the characteristic parameters of the above functional units are correct.

[0074] As can be seen from the above, the data transmission device 20 in this embodiment of the invention, by splicing and shifting the data to be transmitted without padding with zeros, can fully utilize the high-performance interface bandwidth of the processing system-side memory 10, thereby improving data transmission efficiency. Furthermore, the data rearrangement unit 240 can optionally rearrange the data before padding with zeros to match the computing resources of the AI ​​accelerator, reducing the waste of computing resources.

[0075] This invention also provides a data transmission system, referring to... Figure 2 The system may include:

[0076] Processing system-side memory 10;

[0077] The data transmission device 20;

[0078] And acceleration engine-side memory 30.

[0079] The data transmission device 20 is used to read data to be transmitted from the processing system-side memory 10 and write it to the acceleration engine-side memory 30; the data to be transmitted is fixed-point data and is not padded with zeros.

[0080] In a specific implementation, the acceleration engine-side memory 30 can provide input data for the AI ​​accelerator 40.

[0081] Furthermore, in some embodiments, the number of input data channels can be adjusted by the data rearrangement unit of the data transmission device 20, thereby better matching the computing resources of the AI ​​accelerator 40.

[0082] In some embodiments, the input data may be obtained by filling the data processing unit 230 with pixels, wherein the number and value of the pixels filled are configurable, thereby supporting specific data processing and facilitating the completion of corresponding calculations.

[0083] To enable those skilled in the art to better understand and implement the present invention, the methods corresponding to the above-described apparatus are described in detail below.

[0084] Reference Figure 3 This invention also provides a data transmission method, which includes the following steps:

[0085] Step 31: Obtain feature parameters of the data to be transmitted from the memory of the processing system. The data to be transmitted is fixed-point data and is not padded with zeros. The feature parameters include: a first feature parameter, a second feature parameter, and a third feature parameter.

[0086] In practice, the data to be transmitted may be a single piece or multiple pieces. Each piece of data is processed by the data transmission device to form the input data for an AI accelerator.

[0087] In a specific implementation, the third feature parameter is a feature parameter used to control the data rearrangement unit 240.

[0088] Step 32: Based on the first feature parameter, read the data to be transmitted from the memory of the processing system, concatenate the data read more than once, and generate each individual data to be transmitted by shifting.

[0089] In practice, the first feature parameter is used to control the splicing shift. The first feature parameter is configurable. By changing the first feature parameter, the splicing shift operation can be flexibly adjusted.

[0090] Step 33: Based on the second feature parameter, process the spliced ​​and shifted data to be transmitted.

[0091] The second characteristic parameter is used to control the data processing process. By processing the spliced ​​and shifted data to be transmitted, the relevant calculations required for quantizing the data to be transmitted can be completed.

[0092] Step 34: Based on the third feature parameter, zero-padding is performed on the data to be transmitted after data processing to obtain the input data of the AI ​​accelerator and write it into the memory of the acceleration engine.

[0093] In one embodiment, zero-padding can be performed only on the data to be transmitted for data processing to obtain the input data for the AI ​​accelerator.

[0094] In another embodiment, the data to be transmitted for data processing can be rearranged first, and then zero-padding can be used for alignment to obtain the input data for the AI ​​accelerator.

[0095] Among these features, the data to be transmitted can be rearranged according to the bit width supported by the AI ​​accelerator, which can better match the relevant calculations within the AI ​​accelerator and thus reduce the waste of computing resources within the AI ​​accelerator.

[0096] The data transmission method in this embodiment of the invention can be used to accelerate data transmission in neural networks. Specifically, the AI ​​accelerator can run neural network algorithms, such as Convolutional Neural Network (CNN) algorithms. By concatenating and transmitting data without padding with zeros, the interface bandwidth can be maximized, improving data transmission efficiency. Simultaneously completing data processing and rearrangement before writing the data to the acceleration engine's memory better matches the AI ​​accelerator's computing resources, maximizing resource utilization.

[0097] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A data transmission device, characterized in that, include: A control unit is connected to a processing system-side memory; the processing system-side memory has a transmission interface and stores several data items to be transmitted; the control unit is used to obtain characteristic parameters of the data items to be transmitted from the processing system-side memory, wherein the data items to be transmitted are fixed-point data and are not padded with zeros. The feature parameters include: a first feature parameter, a second feature parameter, and a third feature parameter; The transmission unit is connected to the processing system-side memory and the control unit. Based on the first characteristic parameter obtained by the control unit, it reads the data to be transmitted from the processing system-side memory according to the bandwidth of the transmission interface, and shifts the read data to generate each individual data to be transmitted. A data processing unit, connected to the transmission unit and the control unit, processes the data to be transmitted generated by the transmission unit based on the second feature parameters obtained by the control unit and according to the needs of the AI ​​accelerator to run relevant algorithms. The data rearrangement unit, connected to the data processing unit and the control unit, performs zero-padding and alignment directly on the data to be transmitted after processing by the data processing unit, or rearranges the data first and then performs zero-padding and alignment, based on the third feature parameter obtained by the control unit, to obtain the input data of the AI ​​accelerator and write it into the acceleration engine's memory.

2. The data transmission device as described in claim 1, characterized in that, The third feature parameter includes: a first flag bit; the first flag bit is used to indicate whether the data to be transmitted after being processed by the data processing unit is rearranged. When the first flag indicates that the data to be transmitted after being processed by the data processing unit is not to be rearranged, the data rearrangement unit performs zero-padding alignment on the data to be transmitted after being processed by the data processing unit to obtain the input data of the AI ​​accelerator and writes it to the acceleration engine end memory.

3. The data transmission device as described in claim 2, characterized in that, The data rearrangement unit, when the first flag indicates that the data to be transmitted after being processed by the data processing unit is to be rearranged, performs data rearrangement on the data to be transmitted based on the bit width supported by the AI ​​accelerator. After data rearrangement, the data to be transmitted after being processed by the data processing unit is zero-padded for alignment.

4. The data transmission device as described in claim 3, characterized in that, The data rearrangement unit performs data filling operations on the rearranged data according to preset filling parameters.

5. The data transmission device as described in claim 1, characterized in that, The control unit includes a first register for storing the feature parameters written to the memory of the processing system.

6. The data transmission apparatus as described in claim 5, characterized in that, The control unit further includes: a second register for storing a second flag bit; the second flag bit is used to indicate whether the data transmission device is started to operate; when the second flag bit indicates that the data transmission device is started to operate, the transmission unit, the data processing unit and the data rearrangement unit begin to perform corresponding operations.

7. The data transmission apparatus as described in claim 5 or 6, characterized in that, The control unit further includes a third register for storing the current status information of the transmission unit, the data processing unit, and the data rearrangement unit.

8. The data transmission apparatus as described in claim 7, characterized in that, The processing system's memory reads the current status information of the transmission unit, the data processing unit, and the data rearrangement unit from the third register, and adjusts the first feature parameter, the second feature parameter, and the third feature parameter based on the read current status information.

9. The data transmission apparatus as claimed in claim 1, characterized in that, The first feature parameter is configurable.

10. The data transmission apparatus as claimed in claim 1, characterized in that, The transmission unit concatenates the data read from two or more times and then generates each individual data to be transmitted by shifting; or, the transmission unit directly shifts the read data to generate each individual data to be transmitted.

11. A data transmission system, characterized in that, include: Processing system-side memory; The data transmission apparatus according to any one of claims 1 to 10; And an acceleration engine-side memory; wherein, the data transmission device is used to read data to be transmitted from the processing system-side memory and write it into the acceleration engine-side memory; The data to be transmitted is fixed-point data and is not padded with zeros.

12. A data transmission method, characterized in that, include: Retrieve characteristic parameters of the data to be transmitted from the memory of the processing system, wherein the data to be transmitted is fixed-point data and is not padded with zeros; The feature parameters include: a first feature parameter, a second feature parameter, and a third feature parameter; Based on the first feature parameter, according to the bandwidth of the transmission interface, the data to be transmitted is read from the memory of the processing system, and the read data is shifted to generate each individual data to be transmitted. Based on the second feature parameter, the spliced ​​and shifted data to be transmitted is processed according to the needs of the AI ​​accelerator to run relevant algorithms. Based on the third feature parameter, the data to be transmitted after data processing is either directly zeroed and aligned or rearranged first and then zeroed and aligned, to obtain the input data of the AI ​​accelerator and write it to the memory of the acceleration engine.

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