Polishing methods for semiconductor structures

Abstract

This disclosure provides a method for polishing a semiconductor structure, comprising: providing a semiconductor substrate having a functional film layer thereon; providing a polishing pad and spraying a first polishing slurry onto the polishing pad; placing the semiconductor substrate on the polishing pad and polishing the functional film layer; removing the semiconductor substrate from the polishing pad and spraying a first cleaning solution onto the polishing pad to clean it; spraying a second polishing slurry onto the cleaned polishing pad; and placing the semiconductor substrate on the polishing pad again and polishing the functional film layer; wherein the first polishing slurry is different from the second polishing slurry. This polishing method performs two polishing operations on the semiconductor substrate without requiring replacement of the polishing pad, saving costs, simplifying operation, and achieving more precise polishing results.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for polishing semiconductor structures. Background Technology

[0002] Chemical mechanical polishing (CMP) is a commonly used process in semiconductor fabrication. It is used to grind the roughness of semiconductor films to improve their surface smoothness. With advancements in semiconductor technology, the dimensions of semiconductor components are becoming increasingly miniaturized, requiring higher precision in component manufacturing. Therefore, CMP is no longer simply about improving the uniformity of semiconductor films; it aims to further precisely alter the unevenness or step height within the semiconductor film.

[0003] In the prior art, different polishing slurries are often used to polish semiconductor structures in order to achieve the above-mentioned expectations. However, after each change of polishing slurry, the semiconductor needs to be polished on different polishing pads, which increases the consumption and cost of polishing pads and makes the operation complicated.

[0004] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a method for polishing semiconductor structures, which polishes the semiconductor substrate twice without changing the polishing pad in between, saving costs, simplifying the operation, and achieving more precise polishing results.

[0006] A method for polishing a semiconductor structure is provided, comprising: providing a semiconductor substrate having a functional film layer thereon; providing a polishing pad and spraying a first polishing slurry onto the polishing pad; placing the semiconductor substrate on the polishing pad and polishing the functional film layer; removing the semiconductor substrate from the polishing pad and spraying a first cleaning solution onto the polishing pad to clean it; spraying a second polishing slurry onto the cleaned polishing pad; placing the semiconductor substrate on the polishing pad and polishing the functional film layer again; wherein the first polishing slurry is different from the second polishing slurry.

[0007] According to an exemplary embodiment of this disclosure, the functional film layer includes: a first film layer, the first film layer including a plurality of film layer patterns; and a second film layer formed on the first film layer and filling the spaces between the film layer patterns.

[0008] According to an exemplary embodiment of this disclosure, placing the semiconductor substrate on the polishing pad and polishing the functional film layer includes: polishing the second film layer with the first polishing slurry so that the surface of the second film layer is flush with the surface of the first film layer; placing the semiconductor substrate on the polishing pad and polishing the functional film layer again includes: polishing the first film layer with the second polishing slurry so that the surface of the first film layer is lower than the surface of the second film layer.

[0009] According to an exemplary embodiment of this disclosure, placing the semiconductor substrate on the polishing pad and polishing the functional film layer includes: polishing the second film layer with the first polishing slurry to remove the second film layer of a first preset thickness; placing the semiconductor substrate on the polishing pad and polishing the functional film layer again includes: continuing to polish the second film layer after removing the first preset thickness with the second polishing slurry, so that the surface of the second film layer is lower than the surface of the first film layer.

[0010] According to an exemplary embodiment of this disclosure, the functional film layer is a single film layer, and the step of placing the semiconductor substrate on the polishing pad and polishing the functional film layer includes: polishing the functional film layer with the first polishing slurry to remove the functional film layer of a second preset thickness; the step of placing the semiconductor substrate on the polishing pad and polishing the functional film layer again includes: continuing to polish the functional film layer of the second preset thickness using the second polishing slurry.

[0011] According to an exemplary embodiment of this disclosure, the first cleaning solution is deionized water and / or a surfactant.

[0012] According to an exemplary embodiment of this disclosure, the surfactant is one or more of cationic surfactants, nonionic surfactants, and anionic surfactants.

[0013] According to an exemplary embodiment of this disclosure, the pH value of the first polishing slurry is greater than the pH value of the second polishing slurry.

[0014] According to an exemplary embodiment of this disclosure, the abrasive particles in the first abrasive slurry are of a different type than those in the second abrasive slurry.

[0015] According to an exemplary embodiment of this disclosure, the pH value of the first polishing slurry is A1, the pH value of the second polishing slurry is A2, the pH value of the first cleaning slurry is B1, and the average value of A1 and A2 is A. v = (A1+A2) / 2, if A1>A2, then A v -3(A1-A v ) / 4≤B1≤A v+3(A1-A v ) / 4; If A2>A1, then A v -3(A2-A v ) / 4≤B1≤A v +3(A2-A v ) / 4; where A1, A2, A v Both B1 and B2 are positive numbers.

[0016] According to an exemplary embodiment of this disclosure, B1 = Av.

[0017] According to an exemplary embodiment of this disclosure, the flow rate of the first cleaning fluid is at least 500 ml / min, and the cleaning time of the first cleaning fluid is greater than or equal to 3 seconds.

[0018] According to an exemplary embodiment of this disclosure, the flow rates of the first grinding fluid and the second grinding fluid are respectively 50-500 ml / min.

[0019] According to an exemplary embodiment of this disclosure, the functional film layer is at least one of shallow trench isolation, oxide layer, tungsten metal layer, copper metal layer, polycrystalline silicon layer, silicon nitride layer, and the back side of a semiconductor substrate.

[0020] According to an exemplary embodiment of this disclosure, the method further includes: removing the re-polished functional film layer from the polishing pad, spraying a second cleaning solution onto the polishing pad to clean it; spraying a third polishing solution onto the cleaned polishing pad; placing the semiconductor substrate on the polishing pad and continuing to polish the functional film layer; if the functional layer still needs to be polished after polishing, repeating the above method until the functional film layer is polished.

[0021] According to an exemplary embodiment of this disclosure, the pH value of the Nth grinding slurry is A. N The pH value of the (N+1)th grinding slurry is A. N+1 The pH value of the Nth cleaning solution is B. N A N and A N+1 The average value Av' = (A N +A N+1 If A) / 2, N >A N+1 Then Av'-3(A N -Av') / 4≤B N ≤Av'+3(A N -Av') / 4; if A N+1 >A N Then Av'-3(A N+1 -Av') / 4≤B N ≤Av'+3(A N+1-Av') / 4; where N is a positive integer and N≥2; A N A N+1 Av', B N All are positive numbers.

[0022] According to an exemplary embodiment of this disclosure, the method further includes: after the semiconductor substrate has been polished, removing the semiconductor substrate from the polishing pad; and spraying the polishing pad with a post-polishing cleaning solution to clean the polishing pad.

[0023] As can be seen from the above technical solution, this disclosure possesses at least one of the following advantages and positive effects:

[0024] In the polishing method of this embodiment, after the semiconductor substrate is polished by the first polishing slurry, the semiconductor substrate is removed from the polishing pad and the polishing pad is cleaned with a cleaning slurry. A second polishing slurry can be sprayed on the polishing pad to continue polishing the semiconductor substrate. There is no need to replace the polishing pad, which saves costs, simplifies the operation, and makes the polishing effect more accurate. Attached Figure Description

[0025] The above and other features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0026] Figure 1 This is a flowchart of a semiconductor structure polishing method according to an exemplary embodiment of the present disclosure;

[0027] Figure 2 This is a schematic diagram of the spraying of a first polishing slurry to polish a semiconductor structure in an exemplary embodiment of this disclosure;

[0028] Figure 3 This is a schematic diagram of spraying a first cleaning liquid in an exemplary embodiment of this disclosure;

[0029] Figure 4 This is a schematic diagram of the spraying of a second polishing slurry to polish a semiconductor structure in an exemplary embodiment of this disclosure;

[0030] Figure 5 This is a schematic diagram of the semiconductor structure to be ground in an exemplary embodiment of this disclosure;

[0031] Figure 6 for Figure 5 The structure of the semiconductor structure after being polished by the first polishing slurry;

[0032] Figure 7 for Figure 6 The structure of the semiconductor structure after being polished by the second polishing slurry;

[0033] Figure 8This is a schematic diagram of the semiconductor structure to be ground in another exemplary embodiment of this disclosure;

[0034] Figure 9 for Figure 8 The structure of the semiconductor structure after being polished by the first polishing slurry;

[0035] Figure 10 for Figure 8 The structure of the semiconductor structure after being polished by the second polishing slurry;

[0036] Figure 11 This is a schematic diagram of the semiconductor structure to be ground in another exemplary embodiment of this disclosure;

[0037] Figure 12 for Figure 11 The structure of the semiconductor structure after being polished by the first polishing slurry;

[0038] Figure 13 for Figure 12 The structure of the semiconductor structure after being polished by the second polishing slurry.

[0039] Explanation of reference numerals in the attached figures:

[0040] 1. Semiconductor substrate; 11, 11', 11”, functional film layer; 111, 111', first film layer; 112, 112', second film layer; 2. Polishing pad; 3. Polishing disc; 4. First polishing slurry nozzle; 5. Second polishing slurry nozzle; 6. First cleaning slurry nozzle. Detailed Implementation

[0041] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0042] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form part of the present disclosure and illustrate, by way of example, different exemplary structures that can implement various aspects of the present disclosure. It should be understood that other specific embodiments of components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. Moreover, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and not as numerical limitations on the object.

[0043] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily need to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0044] Furthermore, in the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. "Above" and "below" are technical terms indicating location, which are used merely for clarity and are not intended to be limiting.

[0045] like Figures 1 to 13 As shown, this disclosure provides a method for polishing a semiconductor structure. Wherein, Figure 1 This is a flowchart of a semiconductor structure polishing method according to an embodiment of the present disclosure. Figures 2 to 4 This is a schematic diagram of each stage in the grinding method according to an embodiment of the present disclosure. Figures 5 to 13 These are schematic diagrams illustrating the semiconductor structure at different polishing stages in different embodiments. For example... Figure 1 As shown, the semiconductor structure polishing method of this disclosure includes:

[0046] Step S200: Provide a semiconductor substrate 1, on which functional film layers 11, 11', 11' are provided.

[0047] Step S400: Provide a polishing pad 2 and spray a first polishing liquid onto the polishing pad 2.

[0048] Step S600: Place the semiconductor substrate 1 on the polishing pad 2 and polish the functional film layers 11, 11', 11" .

[0049] Step S800: Remove the semiconductor substrate 1 from the polishing pad 2 and spray the polishing pad 2 with a first cleaning solution to clean the polishing pad 2.

[0050] Step S1000: Spray the second polishing liquid onto the cleaned polishing pad 2.

[0051] Step S1200: Place the semiconductor substrate 1 on the polishing pad 2 and polish the functional film layers 11, 11', and 11" again. The first polishing slurry is different from the second polishing slurry.

[0052] In the polishing method of this embodiment, after the semiconductor substrate 1 is polished by the first polishing liquid, the semiconductor substrate 1 is removed from the polishing pad 2, and the polishing pad 2 is cleaned with a cleaning liquid. The second polishing liquid can be sprayed on the polishing pad 2 to continue polishing the semiconductor substrate 1. There is no need to replace the polishing pad 2, which saves costs, makes the operation simpler, and makes the polishing effect more accurate.

[0053] The grinding method for semiconductor structures according to embodiments of this disclosure will now be described in detail.

[0054] Step S200: Provide a semiconductor substrate 1, on which functional film layers 11, 11', 11' are provided.

[0055] Semiconductor substrate 1 may include a semiconductor substrate on which shallow trench isolation is formed, and active regions are disposed between the shallow trench isolations. Word line structures and bit line structures are also disposed in the semiconductor substrate at different heights, and both word line structures and bit line structures are connected to the active regions. The word line structure may include a high-dielectric-constant dielectric layer, a polysilicon layer, a work function layer, and a word line metal layer, etc.

[0056] The semiconductor substrate in this embodiment can be made of silicon, silicon carbide, silicon nitride, silicon-on-insulator, silicon-on-insulator stacked, silicon-on-insulator stacked, silicon-on-germanium, or germanium on-insulator, etc. The semiconductor substrate can also be implanted with certain dopant particles to change its electrical parameters according to design requirements.

[0057] like Figure 5 , Figure 8 and Figure 11 As shown, schematic diagrams of the semiconductor substrate 1 to be polished are illustrated in different embodiments. The functional films 11, 11', and 11" of the semiconductor substrate 1 can be at least one of shallow trench isolation, oxide layer, tungsten metal layer, copper metal layer, polysilicon layer, and silicon nitride layer, or they can be the back side of the semiconductor substrate. It can also be understood that the functional films 11, 11', and 11" are the films of the semiconductor substrate 1 that need to be planarized by polishing.

[0058] refer to Figure 5and Figure 8 As shown, the functional film layers 11, 11', 11" may include two film layers, namely, a first film layer 111, 111' and a second film layer 112, 112'. The first film layers 111, 111' include multiple film layer patterns, and the second film layers 112, 112' are formed on the first film layers 111, 111' and fill the spaces between the film layer patterns. Figure 5 As shown, the first film layers 111 and 111' are silicon oxide, and the second film layers 112 and 112' are metal layers, such as tungsten or copper. Figure 6 As shown, the first film layers 111 and 111' are silicon, and the second film layers 112 and 112' are silicon oxide, as in the shallow trench isolation described above. Of course, the first film layers 111 and 111' or the second film layers 112 and 112' can also be dielectric layers, such as silicon nitride; no special limitation is made here. Figure 11 As shown, the functional membrane layers 11, 11', and 11" can also be single membrane layers.

[0059] Step S400: Provide a polishing pad 2 and spray a first polishing liquid onto the polishing pad 2.

[0060] In the embodiments of this disclosure, a chemical mechanical polishing (CMP) process is used to polish the semiconductor substrate 1. CMP is a process that combines a chemical reaction process with a mechanical polishing process. During CMP, a rotatable polishing disc 3 is provided, and a polishing pad 2 is placed on the polishing disc 3. The semiconductor substrate 1 is placed on the polishing pad 2 with its functional film layers 11, 11', and 11" to be polished facing the polishing pad 2. A polishing head (not shown in the figure) is provided above the semiconductor substrate 1, and a certain pressure is applied to the side of the semiconductor substrate 1 facing away from the polishing pad 2, so that the functional film layers 11, 11', and 11" of the semiconductor substrate 1 are in close contact with the polishing pad 2. The grinding disc 3 rotates, causing the grinding pad 2 to rotate. Simultaneously, the grinding head drives the semiconductor substrate 1 to rotate in the same direction as the grinding pad 2, resulting in mechanical friction between the functional films 11, 11', and 11" of the semiconductor substrate 1 and the surface of the grinding pad 2. During the grinding process, a certain degree of the functional films 11, 11', and 11" are removed through a series of complex mechanical and chemical actions, thereby achieving the planarization of the functional films 11, 11', and 11" of the semiconductor substrate 1.

[0061] like Figure 2 As shown, after providing the polishing pad 2, the first polishing liquid is evenly sprayed onto the polishing pad 2 through the first polishing liquid nozzle 4, and the semiconductor substrate 1 is placed on the polishing pad 2, and polishing is performed using the first polishing particles in the first polishing liquid.

[0062] Step S600: Place the semiconductor substrate 1 on the polishing pad 2 and polish the functional film layers 11, 11', 11" .

[0063] Step S800: Remove the semiconductor substrate 1 from the polishing pad 2 and spray the polishing pad 2 with a first cleaning solution to clean the polishing pad 2.

[0064] like Figure 3 As shown, after the first polishing with the first polishing slurry, the semiconductor substrate 1 is lifted to detach it from the polishing pad 2. The first cleaning slurry is sprayed onto the polishing pad 2 using the first cleaning slurry nozzle 6 to rinse the polishing pad 2, remove the first polishing slurry, and clean the polishing pad 2.

[0065] The first cleaning solution may be deionized water and / or a surfactant. In some embodiments, the surfactant may be one or more of cationic surfactants, nonionic surfactants, and anionic surfactants, as long as it can clean the abrasive pad 2, and no special limitation is made here.

[0066] Step S1000: Spray the second polishing liquid onto the cleaned polishing pad 2.

[0067] like Figure 4 As shown, the second polishing slurry is evenly sprayed onto the cleaned polishing pad 2 using the second polishing slurry nozzle 5 to perform a second polishing on the functional layer of the semiconductor substrate 1.

[0068] Step S1200: Place the semiconductor substrate 1 on the polishing pad 2 and polish the functional film layers 11, 11', and 11" again.

[0069] In this embodiment of the present disclosure, the functional film layers 11, 11', and 11" of the semiconductor substrate 1 are first polished using a first polishing slurry, which can remove a predetermined thickness of the functional film layers 11, 11', and 11". The functional film layers 11, 11', and 11" of the semiconductor substrate 1 are then polished a second time using a second polishing slurry, which can refine the functional film layers 11, 11', and 11" and improve the polishing accuracy. For example, during the second polishing, the uneven structure or step height in the functional film layers 11, 11', and 11" can be precisely changed.

[0070] To achieve the above objectives, in this embodiment, the first polishing slurry is different from the second polishing slurry. Specifically, the types of abrasive particles in the first and second polishing slurries can be different. For example, the abrasive particles in the first polishing slurry can be silicon dioxide, while the abrasive particles in the second polishing slurry can be cerium dioxide; alternatively, the pH values ​​of the first and second polishing slurries can be different. In some embodiments, the pH value of the first polishing slurry is greater than the pH value of the second polishing slurry. For example, the pH value of the first polishing slurry can be 7.5–9, falling within the alkaline range, specifically 7.8, 8, 8.2, 8.5, or 8.8, without particular limitation. The pH value of the second polishing slurry can be 5–6.5, falling within the acidic range, specifically 5.5, 5.8, 6, 6.2, or 6.4, without particular limitation. That is, the abrasive particles in the first and second polishing slurries can be the same, but their pH values ​​will not be the same.

[0071] In one embodiment, the first polishing slurry may be a silica polishing slurry with a pH of 8.5, and the second polishing slurry may be a cerium dioxide polishing slurry with a pH of 5.5. In another embodiment, the first polishing slurry may be a silica polishing slurry with a pH of 8, and the second polishing slurry may also be a silica polishing slurry with a pH of 6. In yet another embodiment, the first polishing slurry may be a cerium dioxide polishing slurry with a pH of 7.8, and the second polishing slurry may also be a cerium dioxide polishing slurry with a pH of 5.8.

[0072] The size (which can be understood as the diameter) of the abrasive particles in the first and second abrasive slurries can be 20–500 nm. Specifically, it can be 100, 200, 300, or 400 nm, without any particular limitation. However, depending on the abrasive requirements, the size of the second abrasive particles can be smaller than that of the first abrasive particles. In this way, the second abrasive process can achieve more precise abrasive grinding of the functional film layers 11, 11', and 11”, thereby improving the abrasive precision.

[0073] In some embodiments, the pH range of the first cleaning solution is: the average of the pH values ​​of the first polishing solution and the second polishing solution, plus or minus three-quarters of the maximum of the pH values ​​of the first and second polishing solutions. For ease of understanding, let the pH value of the first polishing solution be A1, the pH value of the second polishing solution be A2, and the pH value of the first cleaning solution be B1. The average of A1 and A2 is A... v = (A1+A2) / 2, if A1>A2, then A v -3(A1-A v ) / 4≤B1≤A v +3(A1-A v ) / 4; If A2>A1, then A v -3(A2-A v) / 4≤B1≤A v +3(A2-A v ) / 4. Among them, A1, A2, A v Both B1 and B1 are positive numbers. This ensures that the pH value of the first cleaning solution is between the pH values ​​of the first and second grinding solutions, allowing the first cleaning solution to not only clean but also act as a transition between the two grinding solutions, thus ensuring the stability of the second grinding solution.

[0074] In one embodiment, if A1 is 8 and A2 is 6, then A v If the value is 7, then the pH value B1 of the first cleaning solution is 7-3(8-7) / 4≤B1≤7+3(8-7) / 4, that is, 6.25≤B1≤7.75. Within this range, B1 can be 6.5, 7.0, 7.2 or 7.5, which is not limited here.

[0075] In one embodiment, the pH value B1 of the first cleaning solution is the average of the pH values ​​of the first polishing solution and the second polishing solution, i.e., B1 = Av, as in the above embodiment, B1 is 7.0.

[0076] In one embodiment, the flow rate of the first cleaning fluid is at least 500 ml / min, such as 600 ml / min, 800 ml / min, 1000 ml / min, 1200 ml / min, or 1400 ml / min, and the cleaning time of the first cleaning fluid is greater than or equal to 3 seconds, such as 4 seconds, 6 seconds, or 8 seconds, or even longer. The flow rate and cleaning time of the first cleaning fluid can be set according to actual conditions, and no special limitation is made here.

[0077] In one embodiment, the flow rates of the first and second polishing fluids are 50 to 500 ml / min, respectively. Specifically, they can be 80 ml / min, 100 ml / min, 200 ml / min, 300 ml / min or 400 ml / min, without any special limitation.

[0078] The polishing methods for different semiconductor substrates are described in detail below.

[0079] like Figure 5 As shown, the functional film layer 11 of the semiconductor substrate 1 includes two films. The first film layer 111 is a dielectric layer, such as silicon oxide, and the second film layer 112 is a metal layer, such as W or Cu. The second film layer 112 is located on the first film layer 111 and fills the spaces between the film patterns of the first film layer 111. Additionally, a TiN layer is filled between the patterns of the second film layer 112 and the first film layer 111. This can be understood as the metal layer and the TiN layer forming a word line metal layer in the semiconductor structure, allowing both layers to be polished together. In this embodiment, it is desirable to polish the first film layer 111 to a depth lower than the second film layer 112. Figure 6 As shown, the second film layer 112 is polished using a first polishing slurry until its surface is flush with the surface of the first film layer 111. Afterwards, the semiconductor substrate 1 is lifted off the polishing pad 2 and cleaned with a first cleaning solution, as shown... Figure 7 As shown, the first film layer 111 is polished using a second polishing slurry, making the surface of the first film layer 111 lower than the surface of the second film layer 112. The second polishing is more refined than the first polishing. In this embodiment, the pH value and flow rate of the first polishing slurry, the second polishing slurry, and the first cleaning slurry are the same as described in the above embodiments.

[0080] like Figure 8 As shown, the functional film layer 11' of the semiconductor substrate 1 comprises two films. The first film layer 111' can be silicon; the figure shows silicon nitride formed on the silicon. In this embodiment, silicon and silicon nitride can be considered as the first film layer 111'. The second film layer 112 can be a dielectric layer, such as silicon oxide. The second film layer 112 is located on the first film layer 111' and fills the spaces between the film patterns of the first film layer 111'. In this embodiment, it is desirable to grind the second film layer 112 to a depth lower than the first film layer 111'. Figure 9 As shown, the second film layer 112 is polished using a first polishing slurry to remove the second film layer 112 of a first preset thickness. This first preset thickness can be, for example, 10-100 nm, such as 20 nm, 40 nm, 60 nm, or 80 nm, and can be set according to actual needs; no special limitation is made here. Afterwards, the semiconductor substrate 1 is lifted off the polishing pad 2 and cleaned with a first cleaning solution, as shown... Figure 10 As shown, the second polishing slurry is used to further polish the second film layer 112, which has already lost its first preset thickness, until the surface of the second film layer 112 is lower than the surface of the first film layer 111'. The second polishing is more refined than the first polishing. In this embodiment, the pH value and flow rate of the first polishing slurry, the second polishing slurry, and the first cleaning slurry are the same as described in the above embodiments.

[0081] In the above embodiments, the semiconductor substrate 1, which has two functional film layers 11 and 11', is polished. In another embodiment, the functional film layer 11" can also be a single-layer film. Figure 11 As shown, the functional film layer 11” of the semiconductor substrate 1 comprises a monolayer film. In this embodiment, it is desirable to grind the monolayer film to a certain thickness and planarize it. The monolayer film can be a polycrystalline silicon film layer, a dielectric layer, a metal layer, or a semiconductor substrate, and no particular limitation is made here. Figure 12As shown, the functional film layer 11” is polished using a first polishing slurry to remove the functional film layer 11” of a second preset thickness. This second preset thickness can be 1–100 nm, for example, 20 nm, 40 nm, 60 nm, or 80 nm, and can be set according to actual needs; no special limitation is made here. Afterwards, the semiconductor substrate 1 is lifted off the polishing pad 2 and cleaned with a first cleaning solution, as shown... Figure 13 As shown, the functional film layer 11” with the second preset thickness is further polished using a second polishing slurry. The second polishing is more refined than the first polishing. The pH value, flow rate, and abrasive particles of the first polishing slurry, second polishing slurry, and first cleaning slurry will differ depending on the material of the functional film layer 11”. For example, if the functional film layer 11” is polycrystalline silicon, then acidic silica can be selected as the first abrasive particle, the pH value of the first polishing slurry is 5-6, and the polishing rate is ≥50nm / min, so that the removal amount reaches the second preset thickness. The second abrasive particle can still be silica, and the pH value of the second polishing slurry can be adjusted to 2-3, the polishing rate is ≤5nm / min, and the polishing amount is 1-10nm, in order to finely polish the functional film layer 11”, remove its surface defects, and achieve planarization.

[0082] For some functional film layers 11, 11', 11', even two polishing operations may not achieve the desired effect. In some embodiments of this disclosure, after the second polishing is completed, a third, fourth, or more polishing operations can be performed without replacing the polishing pad 2. Between each polishing operation, the semiconductor substrate 1 is removed from the polishing pad 2 and rinsed with a cleaning solution.

[0083] In one embodiment, the polishing method may further include: spraying a third polishing liquid onto the cleaned polishing pad 2; placing the semiconductor substrate 1 on the polishing pad 2 and continuing to polish the functional film layers 11, 11', and 11"; if further polishing is required after polishing the functional layers, the above method is repeated until the functional film layers 11, 11', and 11" are polished.

[0084] Specifically, let the pH value of the Nth grinding fluid be A. N The pH value of the (N+1)th grinding slurry is A. N+1 The pH value of the Nth cleaning solution is B. N A N and A N+1 The average value Av' = (A N +A N+1 If A) / 2, N >A N+1 Then Av'-3(A N -Av') / 4≤B N ≤Av'+3(A N -Av') / 4; if AN+1 >A N Then Av'-3(A N+1 -Av') / 4≤B N ≤Av'+3(A N+1 -Av') / 4. Where N is a positive integer and N≥2; A N A N+1 Av', B N All are positive numbers. The pH values ​​of the Nth polishing fluid, the (N+1)th polishing fluid, and the Nth cleaning fluid can be set with reference to the pH values ​​of the first polishing fluid, the second polishing fluid, and the first cleaning fluid. Other parameters, such as the flow rate of the Nth polishing fluid, the (N+1)th polishing fluid, and the Nth cleaning fluid, can also be set with reference to the first polishing fluid, the second polishing fluid, and the first cleaning fluid, or adjusted according to the actual situation. These will not be elaborated here.

[0085] In some embodiments, the polishing method of this disclosure may further include: after polishing the semiconductor substrate 1, removing the semiconductor substrate 1 from the polishing pad 2; and spraying a post-polishing cleaning solution onto the polishing pad 2 to clean it. The post-polishing cleaning solution is used to clean the polishing pad 2 after polishing. When two polishing operations are performed, since the second polishing solution is generally acidic, the pH value of the post-polishing cleaning solution can be between the pH value of the second polishing solution and 7 (inclusive). After multiple polishing operations (e.g., N+1 polishing operations), the pH value of the post-polishing cleaning solution can be between the pH value of the N+1th polishing solution and 7 (inclusive).

[0086] In summary, in the polishing method of this embodiment, after the semiconductor substrate 1 is polished by the first polishing liquid, the semiconductor substrate 1 is removed from the polishing pad 2, and the polishing pad 2 is cleaned with a cleaning liquid. The second polishing liquid can be sprayed on the polishing pad 2 to continue polishing the semiconductor substrate 1. When polishing the semiconductor structure multiple times, there is no need to replace the polishing pad 2, which saves costs, simplifies the operation, and makes the polishing effect more accurate.

[0087] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to utilize this disclosure.

Claims

1. A method for polishing a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, wherein a functional film layer is present on the semiconductor substrate; A polishing pad is provided, and a first polishing fluid is sprayed onto the polishing pad; The semiconductor substrate is placed on the polishing pad, and the functional film layer is polished. The semiconductor substrate is detached from the polishing pad, and a first cleaning solution is sprayed onto the polishing pad to clean it. Spray a second polishing fluid onto the cleaned polishing pad; The semiconductor substrate is placed on the polishing pad, and the functional film layer is polished again. The first polishing slurry differs from the second polishing slurry. The first cleaning solution is a surfactant. The pH value of the first polishing slurry is A1, the pH value of the second polishing slurry is A2, and the pH value of the first cleaning solution is B1. The average value of A1 and A2 is A. v = (A1+A2) / 2, if A1>A2, then A v -3(A1-A v ) / 4≤B1≤A v +3(A1-A v ) / 4; If A2>A1, then A v -3(A2-A v ) / 4≤B1≤A v +3(A2-A v ) / 4; where A1, A2, A v Both B1 and B2 are positive numbers.

2. The method according to claim 1, characterized in that, The functional membrane layer includes: A first film layer, the first film layer comprising a plurality of film layer patterns; The second film layer is formed on the first film layer and fills the spaces between the film layer patterns.

3. The method according to claim 2, characterized in that, The step of placing the semiconductor substrate on the polishing pad and polishing the functional film layer includes: polishing the second film layer with the first polishing slurry so that the surface of the second film layer is flush with the surface of the first film layer; The step of placing the semiconductor substrate on the polishing pad and polishing the functional film layer again includes: polishing the first film layer with the second polishing slurry so that the surface of the first film layer is lower than the surface of the second film layer.

4. The method according to claim 2, characterized in that, The step of placing the semiconductor substrate on the polishing pad and polishing the functional film layer includes: polishing the second film layer with the first polishing slurry to remove the second film layer of a first preset thickness; The step of placing the semiconductor substrate on the polishing pad and polishing the functional film layer again includes: using the second polishing slurry to continue polishing the second film layer after removing the first preset thickness, so that the surface of the second film layer is lower than the surface of the first film layer.

5. The method according to claim 1, characterized in that, The functional film layer is a single film layer. Placing the semiconductor substrate on the polishing pad and polishing the functional film layer includes: polishing the functional film layer with the first polishing slurry to remove the functional film layer of a second preset thickness. The step of placing the semiconductor substrate on the polishing pad and polishing the functional film layer again includes: using the second polishing slurry to continue polishing the functional film layer after removing the second preset thickness.

6. The method according to claim 1, characterized in that, The surfactant is one or more of cationic surfactants, nonionic surfactants, and anionic surfactants.

7. The method according to claim 1, characterized in that, The types of abrasive particles in the first abrasive slurry are different from those in the second abrasive slurry.

8. The method according to claim 1, characterized in that, B1=Av.

9. The method according to claim 1, characterized in that, The flow rate of the first cleaning fluid is at least 500 ml / min, and the cleaning time of the first cleaning fluid is greater than or equal to 3 seconds.

10. The method according to claim 1, characterized in that, The flow rates of the first and second grinding fluids are 50~500 ml / min, respectively.

11. The method according to claim 1, characterized in that, The functional film layer is at least one of the following: shallow trench isolation, oxide layer, tungsten metal layer, copper metal layer, polycrystalline silicon layer, silicon nitride layer, and the back side of a semiconductor substrate.

12. The method according to claim 1, characterized in that, Also includes: The functional film layer, which has been ground again, is detached from the grinding pad, and a second cleaning solution is sprayed onto the grinding pad to clean it. Spray a third polishing fluid onto the cleaned polishing pad; The semiconductor substrate is placed on the polishing pad, and the functional film layer is polished further. If the functional film layer still needs to be ground after grinding, repeat the above method until the functional film layer is ground.

13. The method according to claim 12, characterized in that, The pH value of the Nth grinding slurry is A. N The pH value of the (N+1)th grinding slurry is A. N+1 The pH value of the Nth cleaning solution is B. N A N and A N+1 The average value Av' = (A N +A N+1 If A) / 2, N >A N+1 Then Av'-3(A N -Av') / 4≤B N ≤Av'+3(A N -Av') / 4; if A N+1 >A N Then Av'-3(A N+1 -Av') / 4≤B N ≤Av'+3(A N+1 -Av') / 4; Where N is a positive integer, and N≥2; A N A N+1 Av', B N All are positive numbers.

14. The method according to any one of claims 1 to 13, characterized in that, Also includes: After the semiconductor substrate has been polished, the semiconductor substrate is removed from the polishing pad. Spray the abrasive pad with a post-abrasion cleaning solution to clean the abrasive pad.

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