A server power timing test apparatus and method

Abstract

The application provides a server power timing test device and method, which comprises a power controller on a central processing unit, a programmable logic chip and a load simulator; the power controller is used for outputting a first PG signal to the input end of the programmable logic chip through the output end after receiving a voltage input; the programmable logic chip is used for performing logic operation on the first PG signal output by the power controller and outputting a second PG signal to the load simulator; and the load simulator is used for outputting a power supply enable signal to the power controller after receiving the second PG signal and delaying for a preset time. The first PG signal is a normal power signal output by the power controller; and the second PG signal is a signal representing whether the power supply of the central processing unit is normal. Based on the device, a server power timing test method is further provided. The application improves the efficiency and test accuracy of a server power SDLE test tool.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of server power supply testing, and particularly relates to a server power supply timing test device and method. BACKGROUND

[0002] With the development of science and technology and the continuous progress of information technology, servers have played a significant role in various industries. Based on different CPUs, the types of servers are also diversified. AMD, as a representative of the rapid development of CPUs in recent years, is widely used in various industries based on its CPU. The development of servers cannot be separated from the support of power supply. There are various power supply schemes, and the test cases are different for different power supply schemes. Especially for CPU core power testing, due to the large voltage regulation range and large load current, AMD has introduced the SDLE tool for testing. SDLE, StarDust Load Emulator, can more conveniently and accurately test the CPU core power. The power supply test of SDLE is completed by using the SVI3 communication protocol. The normal server boot sequence is not suitable for power supply testing. For core power testing through the SDLE device, it is necessary to set the CPLD timing according to the requirements of the device and the characteristics of VR. Therefore, the timing suitable for the test device and the power supply scheme is more suitable for the actual test of the DC power supply, which can effectively improve the test efficiency and reduce the problem solving time.

[0003] In the current power supply test, the CPLD timing mostly uses the full push power version or the normal boot version. The full push power version directly pushes all the power without timing, so it cannot judge the stability of the power supply with timing. For the timing of the normal boot version, there is a lack of signals required for SDLE power supply testing. Figure 1The prior art SDLE signal absence and VR controller non-delay schematic diagram is given. For the server of AMD platform, the SDLE device of AMD can help the power supply test to solve the problem of too large pull current. However, during the SDLE test, several signals are needed as the determination of the normal power supply of the mainboard. After the confirmation, the device can be normally used. The SDLE device needs three signals as the signals for starting the device test: the PowerOK signal, the SVID0 signal and the SVID1 signal. The SVID0 and SVID1 signals are determined according to the SVID communication condition. The PowerOK signal is obtained according to whether the power of the mainboard is normally pushed. It is worth noting that the current server is in the dual-CPU mode, and CPU0 is the main CPU. When the power of all loops on the mainboard is normally pushed, the lattice chip outputs a CPU0 PowerOK signal, so that the SDLE can normally test after receiving the signal. For CPU1, there is no PowerOK signal to output, so the problem that the SDLE device cannot start the test of the core power of the CPU1 side occurs. For the VR of TI (Texas Instruments), the address of the VR controller needs to be identified during the test process, and a 10ms delay is needed. However, the current timing does not add this delay, which leads to the failure to identify the address of the VR controller. Therefore, the prior art disclosed technical solution lacks the signals needed for the SDLE power supply test for the normal start-up version timing. SUMMARY

[0004] In order to solve the above technical problems, the present application provides a server power supply timing test device and method, which improves the efficiency and test accuracy of the server power supply SDLE test tool of the AMD platform.

[0005] In order to achieve the above purpose, the present application adopts the following technical scheme:

[0006] A server power supply timing test device, comprising a power supply controller, a programmable logic chip and a load simulator located on a central processing unit.

[0007] The power supply controller is used for receiving a voltage input, and the output end is connected to the input end of the programmable logic chip through a first PG signal. The programmable logic chip is used for performing logic operation on the first PG signal output by all power supply controllers, and outputting a second PG signal to the load simulator. The load simulator is used for delaying a preset time after receiving the second PG signal, and outputting a power supply enable signal to the power supply controller. The first PG signal is a power supply normal signal output by the power supply controller. The second PG signal is a signal representing whether the power supply of the central processing unit is normal.

[0008] Further, each central processor includes one or more power controllers; and the power controller on each central processor is connected to the same programmable logic chip.

[0009] Further, the power end of the power controller is connected to a 3.3V voltage.

[0010] Further, the programmable logic chip is used to perform logical AND operation on the first PG signals output by all the power controllers, and when all the first PG signals are normal, the second PG signal is output to be normal.

[0011] Further, the preset time is 10ms.

[0012] Further, if each central processor includes multiple power controllers, the load simulator receives the second PG signal, delays the preset time to output the power supply enable signal to the current power controller, and then delays the preset time to output the power supply enable signal to the next power controller.

[0013] Further, the number of central processors is one or more.

[0014] The application further provides a server power timing test method, which is realized based on a server power timing test device and includes the following steps.

[0015] The power controller outputs a first PG signal to the programmable logic chip after receiving the voltage input; the first PG signal is a normal power signal output by the power controller.

[0016] The programmable logic chip performs logical operation on the first PG signals output by all the power controllers, and then outputs a second PG signal to the load simulator.

[0017] The load simulator delays the preset time to output a power supply enable signal to the power controller after receiving the second PG signal; the second PG signal is a signal representing whether the power supply of the central processor is normal.

[0018] Further, the method further includes that the load simulator receives the second PG signal, delays the preset time to output the power supply enable signal to the current power controller, and then delays the preset time to output the power supply enable signal to the next power controller.

[0019] Further, the logical operation is logical AND operation, and when all the first PG signals are normal, the second PG signal is output to be normal.

[0020] The effects provided in the summary are only the effects of the embodiments, and are not all the effects of the application. One of the above technical solutions has the following advantages or beneficial effects:

[0021] The application provides a server power supply timing test device and method, which comprises a power supply controller on a central processing unit, a programmable logic chip and a load simulator; the power supply controller is used for outputting a first PG signal to the input end of the programmable logic chip through the output end after receiving a voltage input; the programmable logic chip is used for performing logic operation on the first PG signal output by the power supply controller and outputting a second PG signal to the load simulator; and the load simulator is used for outputting a power supply enable signal to the power supply controller after receiving the second PG signal, with a preset time delay. The first PG signal is a normal power supply signal output by the power supply controller, and the second PG signal is a signal representing whether the power supply of the central processing unit is normal. Based on the server power supply timing test device, a server power supply timing test method is also provided. The application completes address identification of a TI power supply controller through 10ms time delay after a 3.3V standby voltage is given, and facilitates subsequent setting of test parameters. The second PG signal of CPU0 after normal power supply of the mainboard is used for synchronously pushing up the second PG signal of CPU1, so that the requirement of the load simulator test equipment is met.

[0022] The application improves the efficiency and test accuracy of a server power supply SDLE test tool of an AMD platform. BRIEF DESCRIPTION OF DRAWINGS

[0023] As Figure 1 It is a schematic diagram of SDLE signal loss and VR controller without time delay in the prior art;

[0024] As Figure 2 It is a schematic diagram of SDLE complete signal in embodiment 1 of the application;

[0025] As Figure 3 It is a schematic diagram of VR controller address setting under 10ms time delay in embodiment 1 of the application;

[0026] As Figure 4 It is a schematic diagram of TI CPU core power supply scheme address of an AMD server under 10ms time delay in embodiment 1 of the application;

[0027] As Figure 5 It is a schematic diagram of TI power supply scheme POWEROK signal output of an AMD server in embodiment 1 of the application;

[0028] As Figure 6 It is a flowchart of a server power supply timing test method in embodiment 2 of the application. DETAILED DESCRIPTION

[0029] The present disclosure will be described in further detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are merely exemplary and are not limiting to the present disclosure. In addition, it should also be understood that for the convenience and clarity of the description, only parts of the relevant are shown in the drawings.

[0030] It should be noted that the embodiments and features of the present disclosure can be combined if there is no conflict. The technical solutions of the present disclosure will be described in detail below with reference to the drawings and in combination with the embodiments.

[0031] Unless otherwise specified, the exemplary embodiments / examples shown will be understood as providing exemplary features of various details that can implement the technical concepts of the present disclosure in practice. Therefore, unless otherwise specified, the features of various embodiments / examples can be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of the present disclosure.

[0032] In the drawings, cross-hatching and / or shading are generally used to indicate that a portion of one feature can be located structurally close to another, even though not directly so in the drawing. As such, unless stated otherwise, the presence of cross-hatching or shading is not a requirement for structural closeness. In the drawings, the size and relative sizes of parts can be exaggerated for clarity. This disclosure makes no representation or warranty as to the accuracy of the dimensions of parts relative to each other. The exemplary embodiments can be practiced with the parts in substantially any scale appropriate for the technologies being described.

[0033] When a component is referred to as being "on" or "over" another component, "connected to" or "coupled to" another component, it can be directly on, directly connected to, or directly coupled to the other component, or intervening components can be present. However, when a component is referred to as being "directly on", "directly connected to", or "directly coupled to" another component, there are no intervening components present. For this reason, the term "connected" can refer to physical or electrical connection, with or without intervening components.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including," "includes," "having," "has," "with," or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising." It is also to be noted that the term "substantially" and other similar terms are used herein to refer to the inherent inaccuracy in measured, calculated, and / or provided values and / or dimensions that are inherent to the measurement, calculation, and / or provision of values and / or dimensions.

[0035] Embodiment 1

[0036] Embodiment 1 of the present application provides a server power timing test device, which is necessary for the specific VR controller timing and signal of the AMD matching SDLE test equipment. In this way, the problem of chaotic troubleshooting direction in the early stage and the problem of power test efficiency can be maximally solved, so as to achieve faster and better completion of power test.

[0037] The server power timing test device provided by Embodiment 1 of the present application comprises a power controller, a programmable logic chip and a load simulator located on a central processing unit.

[0038] The power controller is used for receiving a voltage input, and the output end is connected to the input end of the programmable logic chip through a first PG signal; the programmable logic chip is used for performing logic operation on the first PG signal output by all power controllers, and outputting a second PG signal to the load simulator; the load simulator is used for receiving the second PG signal, delaying for a preset time, and outputting a power supply enable signal to the power controller; the first PG signal is a normal power signal output by the power controller; and the second PG signal is a signal representing whether the power supply of the central processing unit is normal.

[0039] As Figure 2 The complete signal diagram of the SDLE in Embodiment 1 of the present application is shown in the figure; for the server of the AMD platform, the SDLE equipment provided by AMD can help solve the problem of excessive load current in power test. However, during the SDLE test, several signals are needed as the determination of the normal power of the mainboard. After confirmation, the equipment can be normally used.

[0040] The SDLE device needs three signals as the signals for starting the device test: a PowerOK signal, an SVID0 signal, and an SVID1 signal. The SVID0 and SVID1 signals are determined according to the SVID communication condition. The PowerOK signal is determined according to whether the power on the mainboard is normally pushed. It is worth noting that the current server is in a dual-CPU mode, and CPU0 is the main CPU. When the power on all circuits on the mainboard is normally pushed, the lattice chip outputs a CPU0 PowerOK signal, so that the SDLE can normally test when receiving the signal. When the power on all circuits on the mainboard is normally pushed, a CPU1 PowerOK signal is output.

[0041] As Figure 3 The figure is a schematic diagram for setting the address of the VR controller in the 10ms delay of embodiment 1 of the application. In the power supply test, it is very important to identify the address of the VR controller. The correct VR controller address can ensure the parameter setting of the VR controller. For the VR controller of TI, the VCC of the controller is controlled by 3V3STBY electricity, that is, when the 3.3V STBY electricity on the mainboard normally works, the VR controller has a starting voltage. In the process from when the VR controller gets the starting voltage to when the VR controller receives the enable signal, a 10ms delay is needed to ensure that the VR controller sets its unique address.

[0042] Lattice: Lattice Semiconductor Corporation provides the widest range of field programmable gate arrays (FPGA), programmable logic devices (PLD) and related software in the industry, including field programmable system chips (FPSC), complex programmable logic devices (CPLD), programmable mixed-signal products and programmable digital interconnection devices.

[0043] STBY: standby state

[0044] VR: Voltage Regulator, power supply controller.

[0045] In embodiment 1 of the application, each central processor includes one or more power supply controllers; and the power supply controller on each central processor is connected to the same programmable logic chip.

[0046] The power supply end of the power supply controller is connected to a 3.3V voltage.

[0047] The programmable logic chip is used for logical AND operation on the first PG signals output by all power supply controllers, and outputs a second PG signal normally when all first PG signals are normal.

[0048] The preset time is 10ms.

[0049] If each central processor includes multiple power controllers, the load simulator receives the second PG signal, delays for a preset time, and then outputs the power supply enable signal to the current power controller after a preset time delay.

[0050] The number of central processors is one or more.

[0051] As Figure 4 The address diagram of the TI CPU core power supply scheme of the AMD server under the 10ms delay in the embodiment 1 of the application is shown, and Texas Instruments TI is taken as an example for description, and the three VR controllers under each central processor control the CPU core power. When the mainboard is normally powered on, the voltage of the 3.3V STBY normally works, at this time, the VR controller has the input voltage of the VCC, and the VR controller has the ability of setting the address. At this time, the delay is 10ms, and the next loop voltage is enabled according to the time sequence, so that there is a time difference between the VCC voltage and the enable signal received by the VR controller, which is enough for the VR controller to set the address. TI, namely TEXAS INSTRUMENTS.

[0052] As Figure 5 The output diagram of the POWEROK signal of the TI power supply scheme of the AMD server in the embodiment 1 of the application is shown. When the last core power on the mainboard also normally works, the PowerOK signal of CPU0 is successfully output as 1, at this time, the PowerOK signal of CPU1 is also output as 1, so that the signals of the two CPUs are normal, and the SDLE test equipment can normally work.

[0053] The server power supply time sequence test device provided in the embodiment 1 of the application completes the address recognition of the TI VR controller through the 10ms delay after the 3.3V STBY voltage is given, and facilitates the setting of the subsequent test parameters. The PowerOK signal of CPU0 is pushed after the mainboard is normally powered on, and the PowerOK signal of CPU1 is synchronously pushed, which meets the requirements of the SDLE test equipment.

[0054] The server power supply time sequence test device provided in the embodiment 1 of the application improves the efficiency and test accuracy of the server power supply SDLE test tool of the AMD platform.

[0055] Embodiment 2

[0056] Based on the server power supply time sequence test device provided in the embodiment 1 of the application, the embodiment 2 of the application further provides a server power supply time sequence test method, as Figure 6 The flow chart of the server power supply time sequence test method in the embodiment 2 of the application is shown.

[0057] In step S600, the power supply controller outputs a first PG signal to the programmable logic chip after receiving the voltage input; the first PG signal is a power supply normal signal output by the power supply controller.

[0058] In step S610, the programmable logic chip performs logical operation on all first PG signals output by the power supply controller, and then outputs a second PG signal to the load simulator. The logical operation is logical AND operation, and the second PG signal is normal when all first PG signals are normal.

[0059] In step S620, the load simulator outputs a power supply enable signal to the power supply controller after receiving the second PG signal for a preset time; the second PG signal is a signal representing whether the power supply of the central processing unit is normal. After the load simulator outputs the power supply enable signal to the current power supply controller for a preset time, the load simulator outputs the power supply enable signal to the next power supply controller for a preset time.

[0060] The method is based on a server power supply timing test device, which comprises a power supply controller, a programmable logic chip and a load simulator on a central processing unit.

[0061] The power supply controller is configured to output a first PG signal to the input end of the programmable logic chip after receiving the voltage input; the programmable logic chip is configured to perform logical operation on all first PG signals output by the power supply controller and output a second PG signal to the load simulator; and the load simulator is configured to output a power supply enable signal to the power supply controller after receiving the second PG signal for a preset time; the first PG signal is a power supply normal signal output by the power supply controller; and the second PG signal is a signal representing whether the power supply of the central processing unit is normal.

[0062] Each central processing unit comprises one or more power supply controllers; and the power supply controllers on each central processing unit are connected to the same programmable logic chip.

[0063] The power supply end of the power supply controller is connected to a 3.3V voltage.

[0064] The programmable logic chip is configured to perform logical AND operation on all first PG signals output by the power supply controller, and output a second PG signal when all first PG signals are normal.

[0065] The preset time is 10ms.

[0066] If each central processing unit comprises multiple power supply controllers, the load simulator outputs a power supply enable signal to the next power supply controller for a preset time after outputting the power supply enable signal to the current power supply controller for a preset time.

[0067] The number of central processing units can be one or more.

[0068] For servers using the AMD platform, AMD's built-in SDLE device can help resolve issues related to excessive current draw during power supply testing. However, SDLE testing requires several signals to confirm that the motherboard's power supply functions are normal before the device can be used.

[0069] The SDLE device requires three signals to initiate device testing: PowerOK, SVID0, and SVID1. SVID0 and SVID1 are determined by the status of SVID communication. The PowerOK signal is determined by whether the motherboard is powered on. It's important to note that the current server uses a dual-CPU mode, with CPU0 as the primary CPU. When all circuits on the motherboard are powered on normally, the lattice chip outputs a CPU0 PowerOK signal, which the SDLE receives for normal testing. Once all circuits on the motherboard are powered on normally, a CPU1 PowerOK signal is output.

[0070] Identifying the VR controller's address is crucial during power supply testing. A correct VR controller address ensures accurate parameter settings. For TI's VR controllers, the controller's VCC is controlled by a 3.3V STBY power supply. This means that when the motherboard powers on, the 3.3V STBY power supply operates normally, providing the VR controller with a startup voltage. However, there is a 10ms delay between the VR controller receiving this startup voltage and receiving the enable signal, allowing the VR controller time to set its unique address.

[0071] Using Texas Instruments (TI) as an example, each CPU core is controlled by three VR controllers. When the motherboard powers on normally, with the 3V3STBY voltage operating normally, the VCC of the VR controller receives input voltage, enabling the VR controller to set its own address. After a 10ms delay, the next loop voltage is enabled according to the timing sequence. This provides a sufficient time difference between the VR controller receiving the VCC voltage and the enable signal to set its address. TI stands for Texas Instruments.

[0072] Once the last power supply on the motherboard is working properly, the PowerOK signal of CPU0 is successfully output as 1. At this time, the PowerOK signal of CPU1 is also output as 1, thus ensuring that the signals of both CPUs are normal and the SDLE test equipment can work normally.

[0073] The server power timing test method provided in Embodiment 2 of the present application can complete address recognition of a TI VR controller through 10 ms delay after 3V3STBY voltage is given, and facilitate subsequent setting of test parameters. The PowerOK signal of CPU0 is normally pushed by the mainboard, and the PowerOK signal of CPU1 is synchronously pushed, thereby meeting the requirements of an SDLE test device.

[0074] The server power timing test method provided in Embodiment 2 of the present application improves the efficiency and test accuracy of an AMD platform server power SDLE test tool.

[0075] The description of the related part of the server power timing test method provided in the embodiments of the present application can refer to the detailed description of the corresponding part of the server power timing test device provided in Embodiment 1 of the present application, which will not be repeated here.

[0076] In the description of the present specification, the description of the terms "one embodiment / way", "some embodiments / ways", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment / way or example are included in at least one embodiment / way or example of the present application. In the present specification, the illustrative description of the above terms is not necessarily the same embodiment / way or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in one or more embodiments / ways or examples. In addition, the person skilled in the art can combine and combine the different embodiments / ways or examples described in the present specification and the features of the different embodiments / ways or examples without contradiction.

[0077] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0078] Those skilled in the art should understand that the above embodiments are only for the purpose of clearly illustrating the present disclosure, and are not intended to limit the scope of the present disclosure. Other changes or modifications can be made on the basis of the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A server power supply timing test device, characterized in that, This includes a power controller, programmable logic chip, and load simulator located on the central processing unit; The power controller, upon receiving a voltage input, connects its output terminal to the input terminal of a programmable logic chip via a first PG signal. The programmable logic chip performs logical operations on all the first PG signals output by the power controllers and outputs a second PG signal to the load simulator. The load simulator, upon receiving the second PG signal, outputs a power enable signal to the power controller after a preset delay. The first PG signal is a normal power signal output by the power controller, and the second PG signal is a signal indicating whether the power supply to the central processing unit is normal. The programmable logic chip is used to perform a logical AND operation on the first PG signal output by all power controllers, and outputs the second PG signal as normal only when all the first PG signals are normal.

2. The server power timing test device according to claim 1, characterized in that, Each central processing unit includes one or more power controllers; and the power controllers on each central processing unit are connected to the same programmable logic chip.

3. The server power timing test device according to claim 1, characterized in that, The power controller is connected to a 3.3V voltage.

4. The server power timing test device according to claim 1, characterized in that, The preset time is 10ms.

5. A server power timing test device according to claim 2, characterized in that, If each central processing unit includes multiple power controllers, the load simulator receives the second PG signal, delays for a preset time, outputs a power enable signal to the current power controller, and then delays for another preset time before outputting a power enable signal to the next power controller.

6. The server power timing test device according to claim 1, characterized in that, The number of central processing units is one or more.

7. A server power timing test method, implemented based on the server power timing test apparatus according to any one of claims 1 to 6, characterized in that, Includes the following steps: After receiving the voltage input, the power controller outputs the first PG signal to the programmable logic chip; the first PG signal is the normal power signal output by the power controller. The programmable logic chip performs logical operations on the first PG signal output by all power controllers, and then outputs the second PG signal to the load simulator; After receiving the second PG signal, the load simulator outputs a power enable signal to the power controller after a preset delay; the second PG signal is a signal indicating whether the power supply to the central processing unit is normal.

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