An on-chip online upgrade method, a chip device, and a computer-readable storage medium

Abstract

The present invention discloses a method for online chip upgrade, a chip device and a computer-readable storage medium. The method includes: the main chip receives a first upgrade data packet sent by the host computer, stores the upgrade file in the first upgrade data packet in a buffer queue; feeds back a reception success message to the host computer so that the host computer sends the next frame of the first upgrade data packet based on the reception success message; obtains upgrade data from the buffer queue according to the current position of the head pointer of the queue, generates a second upgrade data packet according to the upgrade data, and sends the second upgrade data packet to the slave chip to be upgraded; sends a first query message to the slave chip to be upgraded at an interval of a first duration when sending the second upgrade data packet, so that the slave chip to be upgraded responds to the first query message and feeds back the reception situation of the second upgrade data packet; when the reception situation of the second upgrade data packet is reception success, moves the head pointer according to the upgrade data, and repeats the above steps. The present invention can improve the efficiency and speed of slave chip upgrade.

Description

Technical Field

[0001] The present invention relates to the technical field of chip upgrading, and particularly to a method for on-chip upgrading, a chip device, and a computer-readable storage medium. Background Art

[0002] Currently, more and more systems adopt a master-slave chip architecture, where different tasks are assigned to suitable chips to build a stable, reliable, and powerful system. The master chip is used to handle most of the control and logical processing tasks of the entire system, while the slave chip handles some external interfaces and signal expansion auxiliary functions. At the same time, this also brings the problem of difficult online upgrading of each slave chip.

[0003] Since the slave chip can only communicate directly with the master chip, the upgrading of the slave chip needs to be relayed by the master chip to implement the operation of upgrading the slave chip by the host computer. Usually, the master chip acts as a data relay station in this process, which makes the upgrading process of the slave chip consume more time in the communication between the master and slave chips and the relay process between the master chip and the host computer, greatly reducing the upgrading speed. Summary of the Invention

[0004] Based on this, to address the above problems, a method for on-chip upgrading, a chip device, and a computer-readable storage medium are proposed, which can effectively improve the efficiency and speed of upgrading the slave chip.

[0005] A method for on-chip upgrading, the method for on-chip upgrading is applied to a chip component, the chip component includes a master chip and at least one slave chip connected to the master chip, the master chip and the at least one slave chip are connected through a Serial Peripheral Interface (SPI) bus, the master chip serves as an SPI host, the master chip can establish a question-and-answer communication mechanism with the host computer using a specific communication protocol, and the master chip can synchronously run the communication service with the host computer and the communication service with the at least one slave chip;

[0006] The method for on-chip upgrading includes:

[0007] The master chip receives a first upgrade data packet sent by the host computer and stores the upgrade file in the first upgrade data packet in a preset buffer queue, the buffer queue includes a head pointer and a tail pointer;

[0008] ]The master chip feeds back a reception success message to the host computer so that the host computer sends the next frame of the first upgrade data packet based on the reception success message;

[0009] The master chip obtains upgrade data from the buffer queue based on the current position of the head pointer, generates a second upgrade data packet according to the upgrade data, and sends the second upgrade data packet to the slave chip to be upgraded corresponding to the first upgrade data packet among the at least one slave chip, so that the slave chip to be upgraded can perform an upgrade operation according to the second upgrade data packet;

[0010] The master chip sends first query information to the slave chip to be upgraded at an interval of a first duration when sending the second upgrade data packet, so that the slave chip to be upgraded can respond to the first query information and feedback the reception status of the second upgrade data packet;

[0011] When the reception status of the second upgrade data packet is successful reception, the master chip moves the head pointer according to the upgrade data, and repeats the step of obtaining upgrade data from the buffer queue based on the current position of the head pointer and subsequent steps.

[0012] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor is caused to execute the steps of the method described above.

[0013] A chip device includes a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, the processor is caused to execute the steps of the method described above.

[0014] Adopting the embodiment of the present invention has the following beneficial effects:

[0015] The master chip can synchronously run the communication service with the host computer and the communication service with at least one slave chip. These two communication services do not interfere with each other. The master chip can simultaneously receive the data required for the slave chip upgrade from the host computer and forward this data to the slave chip. The master chip is solely responsible for the transmission of the upgrade data of the slave chip, and the master chip does not need to transmit the reception status of the upgrade data of the slave chip to the host computer. The present invention can improve the online upgrade speed of the slave chip based on the master-slave chip architecture without consuming too much resources of the master chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Among them:

[0018] Figure 1It is a schematic structural diagram of the chip component provided by the present invention;

[0019] Figure 2 It is a schematic flowchart of the first embodiment of the chip online upgrade method provided by the present invention;

[0020] Figure 3 It is a schematic flowchart of the second embodiment of the chip online upgrade method provided by the present invention;

[0021] Figure 4 It is a schematic flowchart of the third embodiment of the chip online upgrade method provided by the present invention;

[0022] Figure 5 It is a schematic flowchart of the fourth embodiment of the chip online upgrade method provided by the present invention;

[0023] Figure 6 It is a schematic structural diagram of an embodiment of the chip device provided by the present invention;

[0024] Figure 7 It is a schematic structural diagram of an embodiment of the computer-readable storage medium provided by the present invention. Detailed implementation manners

[0025] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0026] Please refer to Figure 1 , Figure 1 It is a schematic structural diagram of the chip component provided by the present invention. The chip component 10 includes a main chip 11 and at least one slave chip 12 connected to the main chip 11 (in this implementation scenario, there is 1 slave chip, and in other implementation scenarios, there can be 2, 3, or even more). The main chip 22 and each slave chip 12 are respectively connected through an SPI (Serial Peripheral Interface) bus. The chip acts as an SPI host, and the baud rate is fixed at 2.5 Mbps. Based on the bus design mechanism of SPI, all SPI communications between the master and slave must be initiated by the SPI host. The SPI slave cannot actively initiate data transmission. Therefore, the communication between the main chip 11 and the slave chip 12 can only be initiated by the main chip 11, and the slave chip 12 responds to the information of the main chip 11 and replies.

[0027] The main chip 11 can establish a question-and-answer communication mechanism with the host computer using a specific communication protocol. The specific communication protocol includes 485, 232, and USB communication protocols. The bus communication rate between the main chip 11 and the host computer is adjustable, and the default baud rate is 9600 bps. The main chip 11 can synchronously run the communication service with the host computer and the communication service with the at least one slave chip 12, and these two communication services do not interfere with each other. The main chip 11 can also communicate with multiple slave chips 12 simultaneously, and these communications do not interfere with each other.

[0028] Please refer to Figure 2 , Figure 2 which is a schematic flowchart of the first embodiment of the chip online upgrade method provided by the present invention. The chip online upgrade method provided by the present invention is applied to Figure 1 the chip component shown in

[0029] S101: The main chip receives a frame of the first upgrade data packet sent by the host computer, and stores the upgrade file in the first upgrade data packet in a preset buffer queue. The buffer queue includes a head pointer and a tail pointer.

[0030] In a specific implementation scenario, the host computer sends the first upgrade data packet for slave chip upgrade to the main chip. The first upgrade data packet includes the upgrade file for slave chip upgrade. When there are multiple slave chips that need to be upgraded and the upgrade content of each slave chip is different, the first upgrade data packet also includes the identifier of the slave chip corresponding to the first upgrade data packet. Thus, after receiving the first upgrade data packet, the main chip transfers the upgrade file in the first upgrade data packet to the corresponding slave chip.

[0031] Please refer to Table 1 in combination. Table 1 is the format table of the first upgrade data packet provided by the present invention.

[0032]

[0033] Table 1

[0034] After receiving the first upgrade data packet, the main chip extracts the upgrade file therein and stores the upgrade file in a preset buffer queue. The buffer queue is provided with a head pointer and a tail pointer. The upgrade file is stored in the buffer queue according to the position of the current tail pointer, and the tail pointer is moved to the end of the buffer queue after the upgrade file is stored.

[0035] S102: The main chip feeds back a reception success message to the host computer so that the host computer sends the next frame of the first upgrade data packet based on the reception success message.

[0036] In a specific implementation scenario, after receiving the first upgrade data packet, the main chip verifies the first upgrade data packet based on the packet sequence number and the checksum. When the verification passes, the upgrade file in the first upgrade data packet is stored in the buffer queue, and then a reception success message is fed back to the host computer. After receiving the reception success message, the host computer sends the first upgrade data packet of the next frame to the main chip. Steps S101 - S102 are repeated until all the upgrade files for the slave chip upgrade in the host computer are sent to the main chip.

[0037] S103: The main chip obtains the upgrade data from the buffer queue based on the current position of the head pointer, generates a second upgrade data packet according to the upgrade data, and sends the second upgrade data packet to the slave chip to be upgraded corresponding to the first upgrade data packet among at least one slave chip, so that the slave chip to be upgraded can perform the upgrade operation according to the second upgrade data packet.

[0038] In a specific implementation scenario, after storing the upgrade file in the first first upgrade data packet, the main chip obtains the upgrade data from the buffer queue based on the current position of the head pointer in the buffer queue, and generates a second upgrade data packet according to the upgrade data. Please refer to Table 2 for combination. Table 2 is the format table of the second upgrade data packet provided by the present invention.

[0039]

[0040] Table 2

[0041] The main chip sends the second upgrade data packet to the slave chip to be upgraded corresponding to the first upgrade data packet. For example, if the main chip is connected to two slave chips A and B, and the slave chip A needs to be upgraded, the main chip sends the second upgrade data packet to the slave chip A. Or if both the slave chips A and B need to be upgraded, there are two buffer queues, which are respectively used to store the upgrade files for the upgrade of the slave chip A and the upgrade files for the upgrade of the slave chip B. The second upgrade data packets are obtained from the two buffer queues respectively, and the second upgrade data packet for the upgrade of the slave chip A is sent to the slave chip A, and the second upgrade data packet for the upgrade of the slave chip B is sent to the slave chip B.

[0042] After receiving the second upgrade data packet, the slave chip to be upgraded can perform the upgrade operation according to the upgrade data in the second upgrade data packet.

[0043] In an implementation scenario, the main chip checks the remaining data size in the buffer queue in real time, that is, the data size to be sent to the slave chip. When the remaining data size is smaller than the size of the upgrade data, it can be in a waiting state. After the host computer sends the first upgrade data packet of the next frame, the valid data of the upgrade file in the first upgrade data packet can be stored in the buffer queue, and the remaining data size will increase. Step S103 is executed according to the increased remaining data.

[0044] S104: The main chip sends a first query message to the slave chip to be upgraded at an interval of a first duration for the second upgrade data packet, so that the slave chip to be upgraded responds to the first query message and feeds back the reception status of the second upgrade data packet.

[0045] In a specific implementation scenario, since the communication between the main chip and the slave chip can only be initiated by the main chip, in order to obtain the reception status of the second upgrade data packet by the slave chip to be upgraded, after sending the second data packet, the main chip sends a first query message to the slave chip to be upgraded at an interval of a first duration (for example, 150 ms). The slave chip to be upgraded responds to the first query message and feeds back the reception status of the second upgrade data packet, such as successful reception, reception failure, error in sending the second upgrade data packet, etc.

[0046] In an implementation scenario, after receiving the second upgrade data packet, the slave chip verifies the second packet sequence number and the second upgrade check code in the second upgrade data packet. If the verification passes, the upgrade data in the second upgrade data packet is stored in a preset space.

[0047] S105: When the reception status of the second upgrade data packet is successful reception, the main chip moves the head pointer of the queue according to the upgrade data, and repeats step S103 and subsequent steps.

[0048] In a specific implementation scenario, when the reception status of the second upgrade data packet is successful reception, the main chip moves the head pointer of the queue according to the position of the upgrade data in the successfully received second upgrade data packet. The position of the updated head pointer is used as the current position of the head pointer, and steps S104 - S105 are repeated until there is no data or valid data in the buffer queue, that is, until all the upgrade files of the slave chip are transferred to the slave chip.

[0049] In other implementation scenarios, when the reception status of the second upgrade data packet is verification failure, the main chip does not move the head pointer, re - obtains the upgrade data from the buffer queue according to the current position of the head pointer, generates a second upgrade data packet according to the upgrade data, and sends the second upgrade data packet to the slave chip to be upgraded; that is, sends the second upgrade data packet again until the verification passes.

[0050] In other implementation scenarios, when the reception status of the second upgrade data packet is upgrade failure, the main chip feeds back an upgrade failure message to the host computer. The host computer ends the upgrade operation based on the upgrade failure message.

[0051] The present invention makes use of the characteristic that the SPI transmission speed between the master chip and the slave chip is much greater than the communication speed between the host computer and the master chip, and greatly reduces the time consumption of the master chip for forwarding the upgrade data packet from the host computer and the time consumption of the master chip for forwarding the response data from the slave chip without consuming too much storage resources of the master chip. Even without changing the baud rate of the host and the host computer, by expanding the length of the buffer queue of the master chip, the time consumption of the master chip for forwarding the upgrade data packet from the slave chip and the time consumption of the master chip for forwarding the response data from the slave chip can be basically offset, and the actual perceived upgrade duration is the time for the host computer to send the upgrade data packet to the master chip.

[0052] From the above description, it can be seen that in this embodiment, the master chip can synchronously run the communication service with the host computer and the communication service with at least one slave chip. These two communication services do not interfere with each other. The master chip can receive the data required for the upgrade of the slave chip from the host computer at the same time and forward these data to the slave chip. The master chip is solely responsible for the transmission of the upgrade data of the slave chip. The master chip does not need to receive the upgrade data of the slave chip from the host computer. The present invention can improve the online upgrade speed of the slave chip based on the master-slave chip architecture without consuming too much resources of the master chip.

[0053] Please refer to Figure 3 , Figure 3 which is a schematic flowchart of the second embodiment of the chip online upgrade method provided by the present invention. The chip online upgrade method provided by the present invention is applied to Figure 1 the chip component shown, and includes the following steps:

[0054] S201: The master chip receives a frame of the first upgrade data packet sent by the host computer.

[0055] In a specific implementation scenario, step S201 is basically the same as the step of "the master chip receives a frame of the first upgrade data packet" in step S101 of the first embodiment of the chip online upgrade method provided by the present invention, and will not be elaborated here.

[0056] S202: The master chip obtains the current relative position of the head pointer and the tail pointer, and obtains the current remaining amount based on the current relative position.

[0057] In a specific implementation scenario, the size of the buffer queue in the main chip is preset, for example, 2K. If the space stored in the current buffer queue is full, or the remaining space is not enough to store the upgrade file in a frame of the first upgrade data packet (for example, 1024 bytes), then the upgrade file cannot be successfully stored in the buffer queue. After receiving a frame of the first upgrade data packet, obtain the current relative positions of the head pointer and the tail pointer, and obtain the current remaining size of the buffer queue based on the current relative positions of the head pointer and the tail pointer. For example, if the head pointer is at the 1st byte and the tail pointer is at the 1000th byte, then the size of the current remaining amount is 1000 bytes. Another example, if the head pointer is at the 1001st byte and the tail pointer is at the 1500th byte, then the size of the available storage space is 500 bytes.

[0058] S203: When the current remaining amount is less than the size of the valid data of the upgrade file in the first upgrade data packet, the main chip does not feedback a successful reception message to the host computer.

[0059] In a specific implementation scenario, when the current remaining amount is less than the size of the valid data of the upgrade file in the first upgrade data packet, the valid data in the upgrade file cannot be successfully stored in the buffer queue. Therefore, the main chip does not feedback a successful reception message to the host computer, so the communication between the main chip and the host computer is in a waiting state, and the host computer will not send the next frame of the first upgrade data packet.

[0060] Until the current remaining amount is greater than or equal to the size of the valid data of the upgrade file in the first upgrade data packet, the main chip feedbacks the successful reception message to the host computer. The head pointer in the main chip will move backward as the main chip sends the second upgrade data packet to the slave chip to be upgraded, and the relative positions of the head pointer and the tail pointer are monitored in real time. After the main chip sends enough second upgrade data packets to the slave chip, the current remaining amount in the buffer queue will be sufficient to store the valid data of the upgrade file. At this time, the valid data in the upgrade file can be stored in the buffer queue, and a successful reception message is feedback to the host computer, so that the host computer can send the next frame of the first upgrade data packet based on the successful reception message.

[0061] S204: When the current remaining amount is greater than or equal to the size of the valid data of the upgrade file in the first upgrade data packet, store the upgrade file in the first upgrade data packet in a preset buffer queue.

[0062] In a specific implementation scenario, when the current remaining amount is greater than or equal to the size of the valid data of the upgrade file in the first upgrade data packet, the valid data in the upgrade file can be stored in the buffer queue. Therefore, the host computer feedbacks a successful reception message, so that the host computer can send the next frame of the first upgrade data packet based on the successful reception message.

[0063] S205: The main chip obtains the upgrade data from the buffer queue based on the current position of the head pointer, generates a second upgrade data packet according to the upgrade data, and sends the second upgrade data packet to the slave chips to be upgraded corresponding to the first upgrade data packet among at least one slave chip, so that the slave chips to be upgraded can perform upgrade operations according to the second upgrade data packet.

[0064] S206: The main chip sends the first query information to the slave chips to be upgraded at an interval of the first time period after sending the second upgrade data packet, so that the slave chips to be upgraded can respond to the first query information and feedback the reception status of the second upgrade data packet.

[0065] S207: When the reception status of the second upgrade data packet is successful reception, the main chip moves the head pointer according to the upgrade data and repeats step S205.

[0066] In a specific implementation scenario, steps S205 - S207 are basically the same as steps S103 - S105 in the first embodiment of the chip online upgrade method provided by the present invention, and will not be elaborated here.

[0067] It can be seen from the above description that in this embodiment, the main chip obtains the current relative positions of the head pointer and the tail pointer, obtains the current remaining amount based on the current relative position. When the current remaining amount is less than the size of the valid data of the upgrade file in the first upgrade data packet, the main chip does not feedback a successful reception message to the host computer, and the communication between the host computer and the main chip is in a waiting state, avoiding the problem of missing reception of the first upgrade data packet.

[0068] Please refer to Figure 4 , Figure 4 which is the flowchart of the second embodiment of the chip online upgrade method provided by the present invention. The chip online upgrade method provided by the present invention is applied to Figure 1 the chip component shown in

[0069] S301: The main chip receives the slave chip upgrade command sent by the host computer, and forwards the slave chip upgrade command to the slave chips to be upgraded corresponding to the slave chip upgrade command among at least one slave chip, so that the slave chips to be upgraded can make upgrade preparations according to the slave chip upgrade command.

[0070] In a specific implementation scenario, the upgrade operation is initiated by the host computer. The host computer can only communicate with the main chip, and notifies the slave chips to perform upgrade operations through the main chip. Specifically, the host computer sends a slave chip upgrade command to the main chip. The slave chip upgrade command includes at least one identifier of the slave chip to be upgraded, so that the main chip can send the slave chip upgrade command to the corresponding slave chips to be upgraded. The slave chips to be upgraded make upgrade preparations after receiving the slave chip upgrade command.

[0071] S302: After sending the chip upgrade command, the master chip sends the second query data to the slave chip to be upgraded after an interval of the second duration, so as to obtain the ready-to-upgrade response data fed back by the slave chip to be upgraded based on the second query data.

[0072] In a specific implementation scenario, since the communication between the master chip and the slave chip can only be initiated by the master chip and the slave chip to be upgraded cannot actively feedback the upgrade preparation, the master chip sends the second query data to the slave chip to be upgraded after an interval of the second duration (for example, 100 ms) after sending the chip upgrade command. After receiving the feedback of the second query data, the slave chip to be upgraded feeds back the ready-to-upgrade response data to the master chip.

[0073] S303: Forward the ready-to-upgrade response data to the host computer so that the host computer sends the first upgrade data packet based on the ready-to-upgrade response data.

[0074] In a specific implementation scenario, the ready-to-upgrade response data is forwarded to the host computer so that the host computer sends the first upgrade data packet based on the ready-to-upgrade response data.

[0075] In this implementation scenario, after receiving the slave chip upgrade command, the slave chip to be upgraded jumps to the online upgrade code space after an interval of the preset jump duration (for example, 1 s) and erases the data in the flash space of the application program. The master chip needs to know the situation of the data erasing operation of the slave chip to be upgraded. After sending the second query data, the master chip sends the third query data to the slave chip to be upgraded after an interval of the third duration. After receiving the third query data, the slave chip to be upgraded feeds back the erasure completed response data to the master chip. The master chip forwards the erasure completed response data to the host computer, and the host computer sends the first upgrade data packet based on the erasure completed response data.

[0076] After receiving the erasure completed response data, the master chip prepares a preset storage space (for example, 2K bytes) for storing the buffer queue. If the erasure of the slave chip to be upgraded fails, the master chip does not perform any processing. Or wait for a certain period of time and then send the third query data again to check the data erasing operation of the slave chip. Or when the master chip receives the erasure failure data sent by the slave chip to be upgraded based on the third query data, the master chip feeds back the upgrade failure information to the host computer. The host computer can end the current upgrade operation based on the upgrade failure information, or prompt that the upgrade fails and requires powering off and restarting to re-perform the upgrade.

[0077] S304: The master chip receives one frame of the first upgrade data packet sent by the host computer and stores the upgrade file in the first upgrade data packet in a preset buffer queue. The buffer queue includes a head pointer and a tail pointer.

[0078] S305: The main chip feeds back a reception success message to the host computer, so that the host computer sends the next frame of the first upgrade data packet based on the reception success message.

[0079] S306: The main chip obtains upgrade data from the buffer queue based on the current position of the head pointer of the queue, generates a second upgrade data packet according to the upgrade data, and sends the second upgrade data packet to the slave chips to be upgraded corresponding to the first upgrade data packet among at least one slave chip, so that the slave chips to be upgraded can perform upgrade operations according to the second upgrade data packet.

[0080] S307: The main chip sends a first query message to the slave chips to be upgraded at an interval of a first duration after sending the second upgrade data packet, so that the slave chips to be upgraded can respond to the first query message and feedback the reception status of the second upgrade data packet.

[0081] S308: When the reception status of the second upgrade data packet is successful reception, the main chip moves the head pointer of the queue according to the upgrade data, and repeats step S306.

[0082] In a specific implementation scenario, steps S304 - S308 are basically the same as steps S101 - S105 in the first embodiment of the chip online upgrade method provided by the present invention, and will not be elaborated here.

[0083] It can be seen from the above description that in this embodiment, the main chip receives the slave chip upgrade command sent by the host computer and forwards the slave chip upgrade command to the slave chips to be upgraded, so that the slave chips to be upgraded are ready for upgrade. After sending the chip upgrade command, the main chip sends the second query data to the slave chips to be upgraded after an interval of a second duration to obtain the upgrade ready response data of the slave chips to be upgraded; forwards the upgrade ready response data to the host computer, so that the host computer sends the first upgrade data packet based on the upgrade ready response data, which can ensure the successful execution of the upgrade operation.

[0084] Please refer to Figure 5 , Figure 5 which is the schematic flowchart of the fourth embodiment of the chip online upgrade method provided by the present invention. The chip online upgrade method provided by the present invention is applied to Figure 1 the chip component shown, and includes the following steps:

[0085] S401: The host computer sends a slave chip upgrade command to the main chip.

[0086] S402: The main chip receives the slave chip upgrade command sent by the host computer and forwards the slave chip upgrade command to the slave chips to be upgraded.

[0087] S403: The slave chips to be upgraded make preparations for upgrade according to the slave chip upgrade command.

[0088] S404: After sending the chip upgrade command, the main chip sends the second query data to the slave chip to be upgraded after an interval of the second duration.

[0089] S405: The slave chip to be upgraded sends the ready-to-upgrade response data to the main chip based on the second query data.

[0090] S406: The main chip sends the ready-to-upgrade response data to the host computer.

[0091] S407: The slave chip to be upgraded erases the data in the flash space of the application program. If the erasure is successfully executed, go to step S409. If the erasure fails, execute step S429.

[0092] S408: After sending the second query data, the main chip sends the third query data to the slave chip to be upgraded after an interval of the third duration.

[0093] S409: The slave chip to be upgraded sends the erasure complete response data to the main chip based on the third query data.

[0094] S410: After receiving the erasure complete response data, the main chip prepares a preset storage space for storing the buffer queue.

[0095] S411: The main chip forwards the erasure complete response data to the host computer.

[0096] S412: The host computer sends a frame of the first upgrade data packet to the main chip.

[0097] S413: The main chip verifies the checksum in the first upgrade data packet. If the verification passes, execute step S414. If the verification fails, execute step S417. If the upgrade fails, execute step S418.

[0098] S414: The main chip obtains the current relative positions of the head pointer and the tail pointer, and obtains the current remaining amount based on the current relative position; when the current remaining amount is greater than or equal to the size of the valid data of the upgrade file in the first upgrade data packet, execute step S415. When the current remaining amount is less than the size of the valid data of the upgrade file in the first upgrade data packet, execute step S419.

[0099] S415: The main chip stores the valid data of the upgrade file in the verified first upgrade data packet in the preset buffer queue.

[0100] S416: The main chip moves the tail pointer according to the newly added valid data.

[0101] S417: The main chip does not move the head pointer, obtains the upgrade data from the buffer queue according to the current position of the head pointer, generates a second upgrade data packet based on the upgrade data, and sends the second upgrade data packet to the slave chip to be upgraded.

[0102] S418: The main chip feeds back the upgrade failure information to the host computer.

[0103] S419: The main chip does not feed back the reception success message to the host computer.

[0104] S420: The main chip checks the size of the remaining data in the buffer queue in real time. When the size of the remaining data is greater than or equal to the size of the upgrade data, step S421 is executed.

[0105] S421: The main chip obtains the upgrade data from the buffer queue based on the current position of the head pointer, generates a second upgrade data packet according to the upgrade data, and sends the second upgrade data packet to the slave chip to be upgraded.

[0106] S422: The slave chip to be upgraded verifies the second packet number and the second upgrade check code in the second upgrade data packet. If the verification passes, step S423 is executed; if the verification fails, step S424 is executed.

[0107] S423: The slave chip to be upgraded receives and stores the upgrade data in the second upgrade data packet, and performs the upgrade operation according to the upgrade data.

[0108] S424: The main chip sends the first query information to the slave chip to be upgraded at an interval of the first duration for the second upgrade data packet.

[0109] S425: The slave chip to be upgraded responds to the first query information and feeds back the reception status of the second upgrade data packet.

[0110] S426: When the reception status of the second upgrade data packet is reception success, the main chip moves the head pointer according to the upgrade data.

[0111] S427: When the reception status of the second upgrade data packet is verification failure, the main chip does not move the head pointer, obtains the upgrade data from the buffer queue based on the current position of the head pointer, generates a second upgrade data packet according to the upgrade data, and sends the second upgrade data packet to the slave chip to be upgraded.

[0112] S428: When the reception status of the second upgrade data packet is upgrade failure, the main chip feeds back the upgrade failure information to the host computer.

[0113] S429: The slave chip to be upgraded sends the erased failed data to the main chip.

[0114] S430: The main chip feeds back the upgrade failure information to the host computer.

[0115] The specific content of the above steps is basically the same in the descriptions of the various embodiments of the chip online upgrade method provided by the present invention, and will not be elaborated here.

[0116] Please refer toFigure 6 , Figure 6 is a schematic structural diagram of an embodiment of the chip device provided by the present invention. The chip device 20 includes a processor 21 and a memory 22. The processor 21 is coupled to the memory 22. A computer program is stored in the memory 22, and the processor 21 executes the computer program during operation to implement the method as described above. For detailed steps, please refer to the above, and details will not be repeated here.

[0117] Please refer to Figure 7 , Figure 7 is a schematic structural diagram of an embodiment of the computer-readable storage medium provided by the present invention. At least one computer program 31 is stored in the computer-readable storage medium 30, and the computer program 31 is used to be executed by a processor to implement the method as described above. For detailed steps, please refer to the above, and details will not be repeated here. In one embodiment, the computer-readable storage medium 30 may be a storage chip in a terminal, a hard disk, a mobile hard disk, a USB flash drive, an optical disc, or other writable and readable storage tools, or may also be a server, etc.

[0118] The storage medium can be implemented by any type of volatile or non-volatile storage device, or a combination thereof. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a ferromagnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as a static random access memory (SRAM), a synchronous static random access memory (SSRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM), a direct rambus random access memory (DRRAM). The storage medium described in the embodiments of the present invention is intended to include but not limited to these and any other suitable types of memory.

[0119] In several embodiments provided by the present invention, it should be understood that the disclosed systems and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the couplings, direct couplings, or communication connections between the various components shown or discussed may be through some interfaces. The indirect couplings or communication connections of devices or units can be electrical, mechanical, or other forms.

[0120] The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0121] In addition, each functional unit in the embodiments of the present invention can be all integrated in a processing unit, or each unit can be separately used as a unit, or two or more units can be integrated in a unit; the above integrated units can be implemented in the form of hardware, or in the form of hardware plus software functional units.

[0122] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above method embodiments; and the foregoing storage medium includes: mobile storage devices, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks, optical disks and other various media that can store program codes.

[0123] Alternatively, if the above integrated units of the present invention are implemented in the form of software function modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solutions of the embodiments of the present invention essentially or the parts that contribute to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the various embodiments of the present invention. And the foregoing storage medium includes: mobile storage devices, ROM, RAM, magnetic disks, optical disks and other various media that can store program codes.

[0124] In the method disclosed in several method embodiments provided by the present invention, they can be arbitrarily combined without conflict to obtain new method embodiments.

[0125] In the features disclosed in several product embodiments provided by the present invention, they can be arbitrarily combined without conflict to obtain new product embodiments.

[0126] In the features disclosed in several method or device embodiments provided by the present invention, they can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0127] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several equivalent substitutions or obvious modifications can be made, and as long as the performance or use is the same, they should all be regarded as belonging to the protection scope of the present invention.

Claims

1. A method for online chip upgrade, characterized in that, The on-chip online upgrade method is applied to a chip component, which includes a main chip and at least one slave chip connected to the main chip. The main chip and the at least one slave chip are connected through a Serial Peripheral Interface (SPI) bus. The main chip serves as the SPI host and can establish a question-and-answer communication mechanism with a host computer using a specific communication protocol. The main chip can synchronously run the communication service with the host computer and the communication service with the at least one slave chip; The on-chip online upgrade method includes: The main chip receives a frame of the first upgrade data packet sent by the host computer and stores the upgrade file in the first upgrade data packet in a preset buffer queue. The buffer queue includes a head pointer and a tail pointer; The main chip feeds back a reception success message to the host computer so that the host computer sends the next frame of the first upgrade data packet based on the reception success message; The main chip obtains upgrade data from the buffer queue based on the current position of the head pointer, generates a second upgrade data packet according to the upgrade data, and sends the second upgrade data packet to the slave chip to be upgraded corresponding to the first upgrade data packet among the at least one slave chips, so that the slave chip to be upgraded can perform an upgrade operation according to the second upgrade data packet; The main chip sends a first query message to the slave chip to be upgraded at an interval of a first duration after sending the second upgrade data packet, so that the slave chip to be upgraded responds to the first query message and feeds back the reception status of the second upgrade data packet; When the reception status of the second upgrade data packet is reception success, the main chip moves the head pointer according to the upgrade data and repeats the steps of obtaining upgrade data from the buffer queue based on the current position of the head pointer and subsequent steps.

2. The method for online chip upgrade according to claim 1, wherein Before the step of storing the upgrade file in the first upgrade data packet in the preset buffer queue, it includes: The main chip obtains the current relative position of the head pointer and the tail pointer, obtains the current remaining amount based on the current relative position. When the current remaining amount is less than the size of the valid data of the upgrade file in the first upgrade data packet, the main chip does not feed back a reception success message to the host computer; Until the current remaining amount is greater than or equal to the size of the valid data of the upgrade file in the first upgrade data packet, the main chip feeds back the reception success message to the host computer.

3. The on-chip online upgrade method according to claim 1, wherein The step of the main chip obtaining upgrade data from the buffer queue based on the current position of the head pointer includes: The main chip checks the size of the remaining data in the buffer queue in real time. When the size of the remaining data is greater than or equal to the size of the upgrade data, it executes the step of obtaining upgrade data from the buffer queue based on the current position of the head pointer and subsequent steps.

4. The method for on-chip online upgrade according to claim 1, characterized in that, Before the step of the main chip receiving a frame of the first upgrade data packet sent by the host computer, it includes: The main chip receives the slave chip upgrade command sent by the host computer, and forwards the slave chip upgrade command to the to-be-upgraded slave chip corresponding to the slave chip upgrade command among the at least one slave chip, so that the to-be-upgraded slave chip makes upgrade preparations according to the slave chip upgrade command; After the main chip sends the chip upgrade command, it sends second query data to the to-be-upgraded slave chip after a second time interval, so as to obtain the ready-to-upgrade response data fed back by the to-be-upgraded slave chip based on the second query data; The main chip forwards the ready-to-upgrade response data to the host computer, so that the host computer sends the first upgrade data packet based on the ready-to-upgrade response data.

5. The chip online upgrade method according to claim 4, wherein After the step that the to-be-upgraded slave chip makes upgrade preparations according to the slave chip upgrade command, it includes: The to-be-upgraded slave chip prepares the erase-completed response data and erases the data in the flash memory space of the application program; After the step that the main chip sends second query data to the to-be-upgraded slave chip after a second time interval after sending the chip upgrade command, it includes: After the main chip sends the second query data, it sends third query data to the to-be-upgraded slave chip after a third time interval, so as to receive the erase-completed response data sent by the to-be-upgraded slave chip based on the third query data; After the main chip receives the erase-completed response data, it prepares a preset storage space for storing the buffer queue.

6. The on-chip online upgrade method according to claim 5, wherein, After the step that the main chip sends third query data to the to-be-upgraded slave chip after a third time interval after sending the second query data, it includes: When the main chip receives the erase-failure data sent by the to-be-upgraded slave chip based on the third query data, the main chip feeds back upgrade failure information to the host computer.

7. The method for online chip upgrade according to claim 1, wherein The first upgrade data packet includes a first data header, a first packet sequence number, the upgrade file, and a first upgrade check code, and the second upgrade data packet includes a second data header, a second packet sequence number, the upgrade data, and a second upgrade check code; The step of storing the upgrade file in the first upgrade data packet in a preset buffer queue includes: The main chip verifies the check code in the first upgrade data packet, and stores the upgrade file in the first upgrade data packet that passes the verification in a preset buffer queue; The step that the to-be-upgraded slave chip can perform an upgrade operation according to the second upgrade data packet includes: The to-be-upgraded slave chip verifies the second packet sequence number and the second upgrade check code in the second upgrade data packet, and performs an upgrade operation according to the upgrade data in the second upgrade data packet that passes the verification.

8. The method for online chip upgrade according to claim 7, wherein, After the step that the main chip sends the second upgrade data packet and sends first query information to the to-be-upgraded slave chip at a first time interval, it includes: When the reception condition of the second upgrade data packet is verification failure, the main chip does not move the head pointer of the queue, obtains upgrade data from the buffer queue according to the current position of the head pointer, generates a second upgrade data packet according to the upgrade data, and sends the second upgrade data packet to the to-be-upgraded slave chip; When the reception of the second upgrade data packet fails in the upgrade, the main chip feeds back the upgrade failure information to the host computer.

9. A computer-readable storage medium storing a computer program, which when executed by a processor causes the processor to perform the steps of the method according to any one of claims 1 to 8.

10. A chip device comprising a memory and a processor, the memory storing a computer program, which when executed by the processor causes the processor to perform the steps of the method according to any one of claims 1 to 8.

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