A non-blocking memory access system and method based on data cache
By using a non-blocking memory access system, the Control FSM and AXI FSM state machines are used to control the reception and processing of memory access instructions, which solves the blocking problem caused by misses in traditional memory access designs and improves processor performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUXI ADVANCED TECH RES INST
- Filing Date
- 2022-11-30
- Publication Date
- 2026-05-01
AI Technical Summary
In traditional processor designs, a data cache miss can cause memory access instructions to be blocked, reducing the overall performance of the processor and becoming a bottleneck for performance improvement.
A non-blocking memory access system based on data caching is adopted. The memory access module, Control FSM state machine and AXI FSM state machine control the reception and processing of memory access instructions, allowing two memory access instructions to be processed at the same time, avoiding pipeline blockage caused by memory access instruction miss.
Without increasing the number of external physical memory access channels, non-blocking cache access was achieved, which improved the processor's memory access pipeline efficiency and overall performance, and reduced pipeline pauses caused by memory misses.
Smart Images
Figure CN115794672B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a non-blocking memory access system and method based on data caching, belonging to the field of chip design technology. Background Technology
[0002] Memory access technology is a crucial aspect of processor design, and the determination of the processor's memory access method directly impacts overall processing performance. Especially in the design of modern high-performance processors, research into memory access technology has become a key technique for improving processor performance.
[0003] Traditional basic processor designs typically employ a blocking assignment memory access design. Whenever a request to access the data cache (DCache) misses, the DCache blocks the next memory access instruction while waiting to retrieve the missed data from the first-level memory, thus blocking the normal operation of the entire pipeline. This memory access design severely degrades the overall processor performance, making the memory access process a bottleneck for performance improvement. Summary of the Invention
[0004] To address the problems existing in the prior art, this invention proposes a non-blocking memory access system and method based on data cache, which can achieve the function of processing two memory access instructions simultaneously without adding an additional external physical memory access channel, thus helping to improve the overall performance of the processor.
[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical means:
[0006] In a first aspect, the present invention proposes a non-blocking memory access system based on data cache, including a memory access module, which includes a memory access instruction receiving module, a memory access instruction processing status judgment module, a Control FSM state machine and an AXI FSM state machine.
[0007] The memory access instruction receiving module is used to receive memory access instructions one by one;
[0008] The memory access instruction processing status judgment module is used to judge the processing status of each memory access instruction received by the instruction receiving module. The memory access instruction processing status includes whether the memory access instruction hit or whether the memory access instruction has been processed.
[0009] The Control FSM state machine is used to control whether the memory access instruction receiving module receives new memory access instructions based on the memory access instruction processing status. When there are two missed memory access instructions in the memory access module and neither of the two missed memory access instructions has been processed, the Control FSM state machine controls the memory access instruction receiving module to stop receiving new memory access instructions. Otherwise, the Control FSM state machine controls the memory access instruction receiving module to continue receiving new memory access instructions.
[0010] The AXI FSM state machine is used to connect to an external program via the AXI bus to process missed memory access instructions in the memory access module.
[0011] In conjunction with the first aspect, further, when the memory access module can directly obtain the data required by the memory access instruction from the cache according to the memory access instruction, the memory access instruction is called a hit memory access instruction; otherwise, the memory access instruction is called a miss memory access instruction.
[0012] In conjunction with the first aspect, the Control FSM state machine further has four states: IDLE, WORK, FULL, and SAME. The IDLE state indicates that there are no pending memory misses in the memory access module, allowing the memory access instruction receiving module to receive new memory access instructions. The WORK state indicates that the memory access module is processing one memory miss, allowing the memory access instruction receiving module to receive new memory access instructions. The FULL state indicates that the memory access module is processing two memory misses, and the memory access instruction receiving module stops receiving new memory access instructions. The SAME state indicates that the memory access module is processing two memory misses with the same cacheline, and the memory access instruction receiving module stops receiving new memory access instructions.
[0013] In conjunction with the first aspect, the state transition mechanism of the Control FSM state machine is further as follows:
[0014] When there are no pending memory access instructions in the memory access module, the Control FSM state machine is in the IDLE state.
[0015] In the IDLE state, when the memory access instruction receiving module in the memory access module receives a memory miss instruction, the Control FSM state machine jumps to the WORK state.
[0016] In the WORK state, when the memory access instruction receiving module receives another memory access instruction that has missed and the previous memory access instruction has not been processed, it determines whether the cachelines of the two memory access instructions are the same. If they are the same, the Control FSM state machine jumps to the SAME state; otherwise, the Control FSM state machine jumps to the FULL state.
[0017] In the WORK state, when the memory access instruction receiving module does not receive a new memory access instruction and the previous memory access instruction has been processed, the Control FSM state machine transitions to the IDLE state.
[0018] In FULL state, when a missed memory access instruction has been processed, the Control FSM state machine transitions to WORK state.
[0019] In the SAME state, when two memory access misses have been processed, the Control FSM state machine transitions to the IDLE state.
[0020] In conjunction with the first aspect, the AXI FSM state machine further comprises six states: IDLE, READ, WRITE, WBa, OVERLAP, and WBb. The IDLE state indicates that there are no pending memory access misses in the memory access module; the READ state indicates that one read channel of the AXI bus is occupied; the WRITE state indicates that one write channel of the AXI bus is occupied; the WBa state indicates that both read and write channels of the AXI bus are occupied simultaneously; the OVERLAP state indicates that multiple read channels of the AXI bus are occupied; and the WBb state indicates that one of the read / write channels of the AXI bus has not been completed.
[0021] In conjunction with the first aspect, furthermore, the state changes of the AXI FSM state machine are influenced by the Control FSM state machine;
[0022] When the Control FSM state machine is in the WORK state:
[0023] (1) If the memory access module receives a memory access instruction that only requires the use of the read channel, the AXI FSM state machine jumps to the READ state;
[0024] (2) If the memory access module receives a memory access instruction that only requires the use of the write channel, the AXI FSM state machine jumps to the WRITE state.
[0025] (3) If the memory access module receives a memory access instruction that requires both the read channel and the write channel to be occupied, the AXI FSM state machine will jump to the WBa state.
[0026] (4) In other cases, the AXI FSM state machine remains in the IDLE state;
[0027] When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the READ state, if the current read channel request is completed, the AXI FSM state machine will transition to the IDLE state.
[0028] When the Control FSM state machine is in the FULL state and the AXI FSM state machine is in the READ state, if the memory access module receives a memory access instruction that only requires read access, the AXI FSM state machine will jump to the OVERLAP state; otherwise, the AXI FSM state machine will remain in the READ state.
[0029] When the Control FSM state machine is in the FULL state and the AXI FSM state machine is in the OVERLAP state, if a read channel request is completed, the AXI FSM state machine will transition to the READ state; otherwise, the AXI FSM state machine will remain in the OVERLAP state.
[0030] When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WRITE state, if the current write channel request is completed, the AXI FSM state machine will transition to the IDLE state; otherwise, the AXI FSM state machine will remain in the WRITE state.
[0031] When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WBa state, if the current read channel or write channel request is completed, the AXI FSM state machine will transition to the WBb state; otherwise, the AXI FSM state machine will remain in the WBa state.
[0032] When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WBb state, if the request for the remaining read or write channel is completed, the AXI FSM state machine will transition to the IDLE state; otherwise, the AXI FSM state machine will remain in the WBb state.
[0033] In conjunction with the first aspect, the system further includes a memory access register, which stores memory access instruction information. The memory access instruction information includes the entry validity bit, whether the memory access instruction has been processed, instruction ID, memory access granularity, memory access type, lock information, AXI bus occupancy status, memory access address information, and read / write data.
[0034] Secondly, based on the non-blocking memory access system described in the first aspect, this invention proposes a non-blocking memory access method based on a data cache, comprising the following steps:
[0035] The memory access instruction receiving module receives memory access instructions one by one.
[0036] Determine whether each memory access instruction has hit and whether each memory access instruction has been processed.
[0037] When there are two missed memory access instructions in the memory access module and neither of the two missed memory access instructions has been processed, the Control FSM state machine is used to control the memory access instruction receiving module to stop receiving new memory access instructions; otherwise, the Control FSM state machine is used to control the memory access instruction receiving module to continue receiving new memory access instructions.
[0038] The AXI FSM state machine is used to send the missed memory access instructions in the memory access module to the external program for processing via the AXI bus.
[0039] In conjunction with the second aspect, furthermore, the state changes of the Control FSM state machine are used to control whether the memory access instruction receiving module receives new memory access instructions. The methods include:
[0040] When there are no pending memory access instructions in the memory access module, the Control FSM state machine is in the IDLE state, allowing the memory access instruction receiving module to continue receiving new memory access instructions.
[0041] In the IDLE state, when the memory access instruction receiving module in the memory access module receives a missed memory access instruction, the Control FSM state machine jumps to the WORK state, allowing the memory access instruction receiving module to continue receiving new memory access instructions.
[0042] In the WORK state, when the memory access instruction receiving module receives another memory access instruction that has missed and the previous memory access instruction has not been processed, it determines whether the cachelines of the two memory access instructions are the same. If they are the same, the Control FSM state machine jumps to the SAME state; otherwise, the Control FSM state machine jumps to the FULL state. In the SAME or FULL state, the memory access instruction receiving module is not allowed to continue receiving new memory access instructions.
[0043] In the WORK state, when the memory access instruction receiving module does not receive a new memory access instruction and the previous memory access instruction has been processed, the Control FSM state machine transitions to the IDLE state, allowing the memory access instruction receiving module to continue receiving new memory access instructions.
[0044] In FULL state, when a memory access instruction that has missed has been processed, the Control FSM state machine transitions to WORK state, allowing the memory access instruction receiving module to continue receiving new memory access instructions.
[0045] In the SAME state, after two memory access misses have been processed, the Control FSM state machine transitions to the IDLE state, allowing the memory access instruction receiving module to continue receiving new memory access instructions.
[0046] Furthermore, in conjunction with the second aspect, the occupancy status of the read / write channels in the AXI bus is reflected through the state of the AXI FSM state machine. The state changes of the AXI FSM state machine are influenced by the Control FSM state machine, as follows:
[0047] When the Control FSM state machine is in the WORK state:
[0048] (1) If the memory access module receives a memory access instruction that only requires the use of the read channel, the AXI FSM state machine jumps to the READ state;
[0049] (2) If the memory access module receives a memory access instruction that only requires the use of the write channel, the AXI FSM state machine jumps to the WRITE state.
[0050] (3) If the memory access module receives a memory access instruction that requires both the read channel and the write channel to be occupied, the AXI FSM state machine will jump to the WBa state.
[0051] (4) In other cases, the AXI FSM state machine remains in the IDLE state;
[0052] When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the READ state, if the current read channel request is completed, the AXI FSM state machine will transition to the IDLE state.
[0053] When the Control FSM state machine is in the FULL state and the AXI FSM state machine is in the READ state, if the memory access module receives a memory access instruction that only requires read access, the AXI FSM state machine will jump to the OVERLAP state; otherwise, the AXI FSM state machine will remain in the READ state.
[0054] When the Control FSM state machine is in the FULL state and the AXI FSM state machine is in the OVERLAP state, if a read channel request is completed, the AXI FSM state machine will transition to the READ state; otherwise, the AXI FSM state machine will remain in the OVERLAP state.
[0055] When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WRITE state, if the current write channel request is completed, the AXI FSM state machine will transition to the IDLE state; otherwise, the AXI FSM state machine will remain in the WRITE state.
[0056] When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WBa state, if the current read channel or write channel request is completed, the AXI FSM state machine will transition to the WBb state; otherwise, the AXI FSM state machine will remain in the WBa state.
[0057] When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WBb state, if the request for the remaining read or write channel is completed, the AXI FSM state machine will transition to the IDLE state; otherwise, the AXI FSM state machine will remain in the WBb state.
[0058] The following advantages can be obtained by adopting the above technical means:
[0059] This invention proposes a non-blocking memory access system and method based on a high-speed data cache. It can process two memory access instructions simultaneously without increasing the number of external physical memory access channels. When the system receives a memory access miss instruction, the memory access pipeline will not be blocked and can continue to receive new memory access instructions until both received memory access instructions are misses and have not been processed. Only then will the reception of memory access instructions be paused. This invention realizes non-blocking cache access, reduces the occurrence of pipeline pauses due to memory access misses, improves the efficiency of memory access pipeline utilization, and thus improves the overall performance of the processor.
[0060] This invention controls instruction reception and memory access operations through state changes in the state machine within the memory access module. It also considers the case where missed instructions with the same memory access address belong to the same cacheline, providing a more comprehensive approach and ensuring correct execution of memory access operations. In its non-blocking pipeline design, this invention effectively utilizes the overlap function of the AXI bus read channel, thereby enabling the simultaneous processing of two missed memory access instructions occupying the read channel. Furthermore, this invention employs the cooperation of the memory access register and the state machine for recording and controlling missed memory access instruction information. Attached Figure Description
[0061] Figure 1 This is a schematic diagram of the structure of a non-blocking memory access system based on data caching according to the present invention;
[0062] Figure 2 This is a memory access model diagram of the non-blocking memory access system in an example of the present invention;
[0063] Figure 3 This is a schematic diagram of the state changes of the Control FSM state machine in an embodiment of the present invention;
[0064] Figure 4 This is a schematic diagram of the state changes of the AXI FSM state machine in an embodiment of the present invention;
[0065] Figure 5 This is a schematic diagram illustrating the information recorded in the memory access register in an embodiment of the present invention;
[0066] Figure 6This is a flowchart illustrating the steps of a non-blocking memory access method based on data caching according to the present invention. Detailed Implementation
[0067] The technical solution of the present invention will be further described below with reference to the accompanying drawings:
[0068] This invention proposes a non-blocking memory access system based on data caching, such as... Figure 1 , 2 As shown, it mainly includes a memory access module and memory access registers. The memory access module further includes a memory access instruction receiving module, a memory access instruction processing status judgment module, a Control FSM state machine, and an AXI FSM state machine. The memory access module is mainly used to implement operations such as receiving and processing memory access instructions, while the memory access registers are mainly used to store memory access instruction information.
[0069] The memory access structure of the system of the present invention is suitable for processor design architectures with out-of-order issue and sequential delivery, and the dependency problem has been handled before the instruction reaches the memory access module. Under this premise, the external conditions required for adopting a non-blocking memory access design are met, thereby improving processing performance.
[0070] In this embodiment of the invention, the memory access instruction receiving module can receive memory access instructions one by one under the control of the Control FSM state machine. The memory access instruction processing status judgment module is used to judge the processing status of each memory access instruction received by the instruction receiving module, including whether the memory access instruction has been hit and whether the memory access instruction has been processed.
[0071] This invention defines a memory hit based on whether the memory access instruction received by the memory access module can be directly obtained from the cache. When the memory access module can directly retrieve the data required by the memory access instruction from the cache, the instruction is called a memory hit instruction; otherwise, it is called a memory miss instruction. Therefore, non-cacheable instructions and I / O instructions in conventional processor design are also classified as miss instructions as defined in this invention.
[0072] The Control FSM state machine controls whether the memory access instruction receiving module accepts new memory access instructions based on the memory access instruction processing status. Initially, the memory access module receives instructions normally. When a miss instruction is received, the memory access pipeline continues to receive the next instruction. If the next instruction is a hit instruction, it will not be blocked by the first miss instruction and can fetch and commit data normally. If the next instruction is a miss instruction, the memory access pipeline pauses until the first miss instruction is processed. If there are two miss memory access instructions in the memory access module and neither of them has been processed, the Control FSM state machine controls the memory access instruction receiving module to stop receiving new memory access instructions; otherwise, the Control FSM state machine controls the memory access instruction receiving module to continue receiving new memory access instructions.
[0073] The Control FSM state machine has four states: IDLE, WORK, FULL, and SAME. The IDLE state indicates that there are no pending memory misses in the memory access module, allowing the memory instruction receiving module to receive new memory access instructions. The WORK state indicates that the memory access module is processing one memory miss, allowing the memory instruction receiving module to receive new memory access instructions. The FULL state indicates that the memory access module is processing two memory misses, and the memory instruction receiving module stops receiving new memory access instructions. The SAME state indicates that the memory access module is processing two memory misses, and the two memory misses have the same cacheline, so the memory instruction receiving module stops receiving new memory access instructions.
[0074] The state transition mechanism of the Control FSM state machine is as follows: Figure 3 As shown, the specific operation is as follows:
[0075] (1) When there are no pending memory access instructions in the memory access module, the Control FSM state machine is in the IDLE state.
[0076] (2) In the IDLE state, when the memory access instruction receiving module in the memory access module receives a miss memory access instruction, the Control FSM state machine jumps to the WORK state; otherwise, the Control FSM state machine remains in the IDLE state.
[0077] (3) In WORK state:
[0078] (301) When the memory access instruction receiving module receives another memory access instruction that has missed and the previous memory access instruction has not been processed, it determines whether the cachelines of the two memory access instructions are the same. If they are the same, the Control FSM state machine jumps to the SAME state; otherwise, the Control FSM state machine jumps to the FULL state.
[0079] (302) When the memory access instruction receiving module does not receive a new memory access instruction and the previous memory access instruction has been processed, the Control FSM state machine jumps to the IDLE state.
[0080] (303) In other cases, the Control FSM state machine remains in the WORK state.
[0081] (4) In FULL state:
[0082] (401) When a memory access instruction miss is completed, the Control FSM state machine jumps to the WORK state.
[0083] (402) In other cases, the Control FSM state machine remains in the FULL state.
[0084] (5) In SAME state:
[0085] (501) Since the memory access addresses of the two missed instructions are the same in the cacheline, the two missed memory access instructions can be processed together. When the two missed memory access instructions have been processed, the Control FSM state machine jumps to the IDLE state. The SAME state can avoid making two consecutive memory access requests for the two missed memory access instructions at the same address, thus improving memory access efficiency.
[0086] (502) In other cases, the Control FSM state machine remains in the SAME state.
[0087] The AXI FSM state machine is used to connect to an external program via the AXI bus to process missed memory access instructions in the memory access module. It can control the memory access module to send and receive missed instruction data, and its state changes are affected by the Control FSM state machine.
[0088] The AXI FSM state machine has six states: IDLE, READ, WRITE, WBa, OVERLAP, and WBb. Specifically: IDLE indicates that there are no pending memory access misses in the memory access module; READ indicates that one read channel of the AXI bus is occupied; WRITE indicates that one write channel of the AXI bus is occupied; WBa indicates that both read and write channels of the AXI bus are occupied simultaneously; OVERLAP indicates that multiple read channels of the AXI bus are occupied; and WBb indicates that one of the read or write channels of the AXI bus has not been completed.
[0089] In this embodiment of the invention, because the Control FSM state machine in the SAME state does not affect the AXI FSM state machine, and the AXI bus protocol specifies that only multiple read channel requests can be processed simultaneously, but not multiple write channel requests, this invention discusses the state changes of the AXI FSM state machine when the Control FSM state machine is in the IDLE, WORK, or FULL states, such as... Figure 4 As shown, the details are as follows:
[0090] (1) When there are no missed memory access instructions to be processed in the memory access module, the Control FSM state machine is in the IDLE state and the AXI FSM state machine is in the IDLE state.
[0091] (2) When the Control FSM state machine is in the WORK state, the memory access module receives a memory access instruction that misses.
[0092] (201) If the memory access module receives a memory access instruction that only requires the use of the read channel, the AXI FSM state machine jumps to the READ state.
[0093] (202) If the memory access module receives a memory access instruction that only requires the use of the write channel, the AXI FSM state machine jumps to the WRITE state.
[0094] (203) If the memory access module receives a memory access instruction that requires both the read channel and the write channel to be occupied, the AXI FSM state machine jumps to the WBa state.
[0095] (204) In other cases, the AXI FSM state machine remains in the IDLE state.
[0096] (3) When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the READ state, if the current read channel request is completed, the AXI FSM state machine will jump to the IDLE state.
[0097] (4) When the Control FSM state machine is in the FULL state and the AXI FSM state machine is in the READ state, the memory access module receives two memory access misses:
[0098] (401) If the memory access module receives a memory access instruction that only needs to occupy the read channel, the AXI FSM state machine jumps to the OVERLAP state. Since the AXI bus protocol provides the user with the read channel Overlap function, that is, when processing multiple consecutive requests occupying the read channel, they can be processed simultaneously to shorten the data response time. Therefore, the present invention can use the Overlap function to process two missed memory access instructions occupying the read channel at the same time.
[0099] (402) In other cases, the AXI FSM state machine remains in the READ state.
[0100] (5) When the Control FSM state machine is in the FULL state and the AXI FSM state machine is in the OVERLAP state, the memory access module receives two memory access misses:
[0101] (501) If a read channel request is completed, only one read channel remains occupied, so the AXIFSM state machine transitions to the READ state.
[0102] (502) In other cases, the AXI FSM state machine remains in the OVERLAP state.
[0103] (6) When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WRITE state:
[0104] (601) If the current write channel request is completed, the AXI FSM state machine transitions to the IDLE state.
[0105] (602) In other cases, the AXI FSM state machine remains in the WRITE state.
[0106] (7) When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WBa state:
[0107] (701) If the current read channel or write channel request is completed, the AXI FSM state machine transitions to the WBb state.
[0108] (702) In other cases, the AXI FSM state machine remains in the WBa state;
[0109] (8) When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WBb state:
[0110] (801) If the request for the remaining read or write channel is completed, the AXI FSM state machine transitions to the IDLE state.
[0111] (802) In other cases, the AXI FSM state machine remains in the WBb state.
[0112] The memory access register can record information about memory access instructions received by the memory access module and information about external memory access instructions sent to the AXI bus, such as... Figure 5 As shown, the memory access instruction information includes the entry validity bit, whether the memory access instruction has been processed, instruction ID, memory access granularity, memory access type, lock information, AXI bus usage, memory access address information, and read / write data.
[0113] Based on the non-blocking memory access system of this invention, this invention also proposes a non-blocking memory access method based on data caching, such as... Figure 6 As shown, the specific steps include the following:
[0114] Step 1: Receive memory access commands through the memory access command receiving module.
[0115] Step 2: Determine whether each memory access instruction has hit and whether each memory access instruction has been processed. If the memory access instruction hits, the memory access module directly retrieves the data from the cache and outputs it. If the memory access instruction misses, further processing is required.
[0116] Step 3: Determine how many memory access instructions have missed in the memory access module. If there are two memory access instructions missed, determine whether the first memory access instruction missed has been processed. If the first memory access instruction missed has been processed, then the next memory access instruction can be received normally. If the first memory access instruction missed has not been processed, it means that there are two memory access instructions missed in the current memory access module and neither of the two memory access instructions has been processed. In this case, the Control FSM state machine is used to control the memory access instruction receiving module to stop receiving new memory access instructions until the first instruction is processed.
[0117] Step 4: Use the AXI FSM state machine to send the missed memory access instructions in the memory access module to the external program for processing via the AXI bus.
[0118] In step 3, the present invention controls whether the memory access instruction receiving module receives new memory access instructions through the state changes of the Control FSM state machine, specifically including the following situations:
[0119] (1) When there are no pending memory access instructions in the memory access module, the Control FSM state machine is in the IDLE state, allowing the memory access instruction receiving module to continue receiving new memory access instructions.
[0120] (2) In the IDLE state, when the memory access instruction receiving module in the memory access module receives a missed memory access instruction, the Control FSM state machine jumps to the WORK state, allowing the memory access instruction receiving module to continue receiving new memory access instructions.
[0121] (3) In the WORK state, when the memory access instruction receiving module receives another memory access instruction that has missed and the previous memory access instruction has not been processed, it determines whether the cachelines of the two memory access instructions are the same. If they are the same, the ControlFSM state machine jumps to the SAME state; otherwise, the ControlFSM state machine jumps to the FULL state. In the SAME or FULL state, the memory access instruction receiving module is not allowed to continue receiving new memory access instructions.
[0122] (4) In the WORK state, when the memory access instruction receiving module does not receive a new memory access instruction and the previous memory access instruction has been processed, the Control FSM state machine jumps to the IDLE state, allowing the memory access instruction receiving module to continue receiving new memory access instructions.
[0123] (5) In the FULL state, when a memory access instruction that has missed has been processed, the Control FSM state machine jumps to the WORK state, allowing the memory access instruction receiving module to continue receiving new memory access instructions.
[0124] (6) In the SAME state, when two memory access instructions that have missed have been processed, the Control FSM state machine jumps to the IDLE state, allowing the memory access instruction receiving module to continue receiving new memory access instructions.
[0125] In step 4, the present invention can reflect the occupancy status of the read / write channels in the AXI bus through the state of the AXI FSM state machine. The state changes of the AXI FSM state machine are affected by the Control FSM state machine, and the specific changes are as follows:
[0126] (1) When there are no missed memory access instructions to be processed in the memory access module, the Control FSM state machine is in the IDLE state and the AXI FSM state machine is in the IDLE state.
[0127] (2) When the Control FSM state machine is in the WORK state:
[0128] (201) If the memory access module receives a memory access instruction that only requires the use of the read channel, the AXI FSM state machine jumps to the READ state.
[0129] (202) If the memory access module receives a memory access instruction that only requires the use of the write channel, the AXI FSM state machine jumps to the WRITE state.
[0130] (203) If the memory access module receives a memory access instruction that requires both the read channel and the write channel to be occupied, the AXI FSM state machine jumps to the WBa state.
[0131] (204) In other cases, the AXI FSM state machine remains in the IDLE state.
[0132] (3) When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the READ state, if the current read channel request is completed, the AXI FSM state machine will jump to the IDLE state.
[0133] (4) When the Control FSM state machine is in the FULL state and the AXI FSM state machine is in the READ state, if the memory access module receives a memory access instruction that only requires reading access, the AXI FSM state machine will jump to the OVERLAP state; otherwise, the AXI FSM state machine will remain in the READ state.
[0134] (5) When the Control FSM state machine is in the FULL state and the AXI FSM state machine is in the OVERLAP state, if a read channel request is completed, the AXI FSM state machine will jump to the READ state; otherwise, the AXI FSM state machine will remain in the OVERLAP state.
[0135] (6) When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WRITE state, if the current write channel request is completed, the AXI FSM state machine will jump to the IDLE state; otherwise, the AXI FSM state machine will remain in the WRITE state.
[0136] (7) When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WBa state, if the current read channel or write channel request is completed, the AXI FSM state machine will jump to the WBb state; otherwise, the AXI FSM state machine will remain in the WBa state.
[0137] (8) When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WBb state, if the request of the remaining read channel or write channel is completed, the AXI FSM state machine will jump to the IDLE state; otherwise, the AXI FSM state machine will remain in the WBb state.
[0138] Compared with existing technologies, this invention can achieve non-blocking memory access for data caching. The memory access module can still work normally when an external memory access is performed due to a missed instruction. This reduces the performance loss caused by memory access misses in the processor, effectively optimizes the transmission latency caused by memory access instructions, and improves the overall execution efficiency of the processor.
[0139] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A non-blocking memory access system based on data caching, characterized in that, It includes a memory access module, which comprises a memory access instruction receiving module, a memory access instruction processing status judgment module, a Control FSM state machine, and an AXI FSM state machine; The memory access instruction receiving module is used to receive memory access instructions one by one; The memory access instruction processing status judgment module is used to judge the processing status of each memory access instruction received by the instruction receiving module. The memory access instruction processing status includes whether the memory access instruction hit or whether the memory access instruction has been processed. The Control FSM state machine is used to control whether the memory access instruction receiving module receives new memory access instructions based on the memory access instruction processing status. When there are two missed memory access instructions in the memory access module and neither of the two missed memory access instructions has been processed, the Control FSM state machine controls the memory access instruction receiving module to stop receiving new memory access instructions. Otherwise, the Control FSM state machine controls the memory access instruction receiving module to continue receiving new memory access instructions. The Control FSM state machine includes the SAME state. The SAME state indicates that the memory access module is processing two missed memory access instructions and the two missed memory access instructions have the same cacheline. The memory access instruction receiving module stops receiving new memory access instructions. The AXI FSM state machine is used to connect to an external program via the AXI bus to process missed memory access instructions in the memory access module. The AXI FSM state machine includes the OVERLAP state, which indicates that multiple read channels in the AXI bus are occupied. The state changes of the AXI FSM state machine are affected by the Control FSM state machine.
2. The non-blocking memory access system based on data caching according to claim 1, characterized in that, When the memory access module can directly retrieve the data required by the memory access instruction from the cache, the memory access instruction is called a hit memory access instruction; otherwise, it is called a miss memory access instruction.
3. A non-blocking memory access system based on data caching according to claim 1, characterized in that, The Control FSM state machine has four states: IDLE, WORK, FULL, and SAME. The IDLE state indicates that there are no pending memory misses in the memory access module, allowing the memory instruction receiving module to receive new memory access instructions. The WORK state indicates that the memory access module is processing one memory miss, allowing the memory instruction receiving module to receive new memory access instructions. The FULL state indicates that the memory access module is processing two memory misses, and the memory instruction receiving module stops receiving new memory access instructions. The SAME state indicates that the memory access module is processing two memory misses with the same cacheline, and the memory instruction receiving module stops receiving new memory access instructions.
4. A non-blocking memory access system based on data caching according to claim 3, characterized in that, The state transition mechanism of the Control FSM state machine is as follows: When there are no pending memory access instructions in the memory access module, the Control FSM state machine is in the IDLE state. In the IDLE state, when the memory access instruction receiving module in the memory access module receives a memory miss instruction, the Control FSM state machine jumps to the WORK state. In the WORK state, when the memory access instruction receiving module receives another memory access instruction that has missed and the previous memory access instruction has not been processed, it determines whether the cachelines of the two memory access instructions are the same. If they are the same, the Control FSM state machine jumps to the SAME state; otherwise, the Control FSM state machine jumps to the FULL state. In the WORK state, when the memory access instruction receiving module does not receive a new memory access instruction and the previous memory access instruction has been processed, the Control FSM state machine transitions to the IDLE state. In FULL state, when a missed memory access instruction has been processed, the Control FSM state machine transitions to WORK state. In the SAME state, when two memory access misses have been processed, the Control FSM state machine transitions to the IDLE state.
5. A non-blocking memory access system based on data caching according to claim 1, characterized in that, The AXIFSM state machine has six states: IDLE, READ, WRITE, WBa, OVERLAP, and WBb. The IDLE state indicates that there are no pending memory access misses in the memory access module; the READ state indicates that one read channel of the AXI bus is occupied; the WRITE state indicates that one write channel of the AXI bus is occupied; the WBa state indicates that both read and write channels of the AXI bus are occupied simultaneously; the OVERLAP state indicates that multiple read channels of the AXI bus are occupied; and the WBb state indicates that one of the read or write channels of the AXI bus has not been processed.
6. A non-blocking memory access system based on data caching according to claim 4 or 5, characterized in that, The state changes of the AXI FSM state machine are affected by the Control FSM state machine; When the Control FSM state machine is in the WORK state: (1) If the memory access module receives a memory access instruction that only requires the use of the read channel, the AXI FSM state machine jumps to the READ state; (2) If the memory access module receives a memory access instruction that only requires the use of the write channel, the AXI FSM state machine jumps to the WRITE state. (3) If the memory access module receives a memory access instruction that requires both the read channel and the write channel to be occupied, the AXI FSM state machine will jump to the WBa state. (4) In other cases, the AXI FSM state machine remains in the IDLE state; When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the READ state, if the current read channel request is completed, the AXI FSM state machine will transition to the IDLE state. When the Control FSM state machine is in the FULL state and the AXI FSM state machine is in the READ state, if the memory access module receives a memory access instruction that only requires read access, the AXI FSM state machine will jump to the OVERLAP state; otherwise, the AXI FSM state machine will remain in the READ state. When the Control FSM state machine is in the FULL state and the AXI FSM state machine is in the OVERLAP state, if a read channel request is completed, the AXI FSM state machine will transition to the READ state; otherwise, the AXI FSM state machine will remain in the OVERLAP state. When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WRITE state, if the current write channel request is completed, the AXI FSM state machine will transition to the IDLE state; otherwise, the AXI FSM state machine will remain in the WRITE state. When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WBa state, if the current read channel or write channel request is completed, the AXI FSM state machine will transition to the WBb state; otherwise, the AXI FSM state machine will remain in the WBa state. When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WBb state, if the request for the remaining read or write channel is completed, the AXI FSM state machine will transition to the IDLE state; otherwise, the AXI FSM state machine will remain in the WBb state.
7. A non-blocking memory access system based on data caching according to claim 1, characterized in that, The system also includes a memory access register, which stores memory access instruction information. The memory access instruction information includes the entry validity bit, whether the memory access instruction has been processed, instruction ID, memory access granularity, memory access type, lock information, AXI bus occupancy status, memory access address information, and read / write data.
8. A non-blocking memory access method based on data caching, based on the non-blocking memory access system of claim 1, characterized in that, Includes the following steps: The memory access instruction receiving module receives memory access instructions one by one. Determine whether each memory access instruction has hit and whether each memory access instruction has been processed. When there are two missed memory access instructions in the memory access module and neither of the two missed memory access instructions has been processed, the Control FSM state machine is used to control the memory access instruction receiving module to stop receiving new memory access instructions; otherwise, the Control FSM state machine is used to control the memory access instruction receiving module to continue receiving new memory access instructions. The AXI FSM state machine is used to send the missed memory access instructions in the memory access module to the external program for processing via the AXI bus.
9. A non-blocking memory access method based on data caching according to claim 8, characterized in that, Whether the memory access instruction receiving module receives new memory access instructions is controlled by the state changes of the Control FSM state machine. The methods include: When there are no pending memory access instructions in the memory access module, the Control FSM state machine is in the IDLE state, allowing the memory access instruction receiving module to continue receiving new memory access instructions. In the IDLE state, when the memory access instruction receiving module in the memory access module receives a missed memory access instruction, the Control FSM state machine jumps to the WORK state, allowing the memory access instruction receiving module to continue receiving new memory access instructions. In the WORK state, when the memory access instruction receiving module receives another memory access instruction that has missed and the previous memory access instruction has not been processed, it determines whether the cachelines of the two memory access instructions are the same. If they are the same, the Control FSM state machine jumps to the SAME state; otherwise, the Control FSM state machine jumps to the FULL state. In the SAME or FULL state, the memory access instruction receiving module is not allowed to continue receiving new memory access instructions. In the WORK state, when the memory access instruction receiving module does not receive a new memory access instruction and the previous memory access instruction has been processed, the Control FSM state machine transitions to the IDLE state, allowing the memory access instruction receiving module to continue receiving new memory access instructions. In FULL state, when a memory access instruction that has missed has been processed, the Control FSM state machine transitions to WORK state, allowing the memory access instruction receiving module to continue receiving new memory access instructions. In the SAME state, after two memory access misses have been processed, the Control FSM state machine transitions to the IDLE state, allowing the memory access instruction receiving module to continue receiving new memory access instructions.
10. A non-blocking memory access method based on data caching according to claim 9, characterized in that, The AXI FSM state machine reflects the occupancy of read and write channels on the AXI bus. The state changes of the AXI FSM state machine are influenced by the Control FSM state machine, as follows: When the Control FSM state machine is in the WORK state: (1) If the memory access module receives a memory access instruction that only requires the use of the read channel, the AXI FSM state machine jumps to the READ state; (2) If the memory access module receives a memory access instruction that only requires the use of the write channel, the AXI FSM state machine jumps to the WRITE state. (3) If the memory access module receives a memory access instruction that requires both the read channel and the write channel to be occupied, the AXI FSM state machine will jump to the WBa state. (4) In other cases, the AXI FSM state machine remains in the IDLE state; When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the READ state, if the current read channel request is completed, the AXI FSM state machine will transition to the IDLE state. When the Control FSM state machine is in the FULL state and the AXI FSM state machine is in the READ state, if the memory access module receives a memory access instruction that only requires read access, the AXI FSM state machine will jump to the OVERLAP state; otherwise, the AXI FSM state machine will remain in the READ state. When the Control FSM state machine is in the FULL state and the AXI FSM state machine is in the OVERLAP state, if a read channel request is completed, the AXI FSM state machine will transition to the READ state; otherwise, the AXI FSM state machine will remain in the OVERLAP state. When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WRITE state, if the current write channel request is completed, the AXI FSM state machine will transition to the IDLE state; otherwise, the AXI FSM state machine will remain in the WRITE state. When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WBa state, if the current read channel or write channel request is completed, the AXI FSM state machine will transition to the WBb state; otherwise, the AXI FSM state machine will remain in the WBa state. When the Control FSM state machine is in the WORK state and the AXI FSM state machine is in the WBb state, if the request for the remaining read or write channel is completed, the AXI FSM state machine will transition to the IDLE state; otherwise, the AXI FSM state machine will remain in the WBb state.
Citation Information
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