A method for implementing vector multiplication after QR decomposition based on a vector processor

Abstract

This invention relates to a method for implementing vector multiplication after QR decomposition based on a vector processor. The QR decomposition algorithm targeted is the vsip_cqrd_f function in the VSIP library. The VSIP library is a vector, signal, and image processing library launched by GE Intelligent Platform, which is an open standard application programming interface specifically provided for developers who need to use enhanced signal and image processing. The technical solution of this invention mainly includes the following steps: Step 1, input matrix C; Step 2, preprocess matrix A to obtain vectors; Step 3, adopt different processing schemes according to the size of the data to implement vector multiplication. When the data volume is extremely small, it will be directly processed in DDR through scalar processing. When the data volume does not exceed the cache size, matrix C and vector V are transferred to the cache through DMA for multiplication. When the data volume exceeds the cache size, the multiplication operation is performed in parallel with the transmission and computation; Step 4, multiply vector cI with each row of the matrix, adopt different processing schemes according to the size of the data, and update the output matrix. This invention leverages the advantages of vector processors, such as large storage space, on-chip cache, rich instruction set, and efficient data transmission, to design and implement vector multiplication after QR decomposition, demonstrating significant advantages in related operations.

Description

Technical Field

[0001] This invention relates to code optimization for high-performance digital signal processor (DSP) chips, and more specifically, to a method for implementing vector multiplication after QR decomposition based on a vector processor. Background Technology

[0002] The VSIP library is a vector, signal, and image processing library launched by GE's intelligent platform. It is an open standard application programming interface designed for developers who need to use enhanced signal and image processing. If you directly call the original functions in the VSIP library, you will lose the excellent hardware performance of the vector processor. To take advantage of the hardware advantages of high-performance processors and improve the parallelism and efficiency of algorithms, it is a good choice to optimize the algorithms in the VSIP library and adapt them to different high-performance processors.

[0003] In modern processors, the VLIW architecture with vector processing units has increasingly become the typical structure for high-performance digital signal processors. Domestic high-performance DSPs have developed rapidly, resulting in many high-performance processors produced by different companies. These processors typically feature abundant register resources and numerous execution units. Vector processors generally consist of multiple processing units, supporting vector-based data loading, computation, and storage. Each processing unit contains multiple independent multi-functional components, typically including addition, multiplication, shifting, comparison, vector element accumulators, and scalar vector conversion units. Vector processors generally support Single Instruction Multiple Data (SIMD) operations, meaning that under the control of the same vector instruction, all processing units simultaneously perform the same operation on the corresponding local registers, achieving data-level parallelism in application development. To accelerate data access speed, vector processors typically have internal or external caches. To effectively leverage the performance advantages of DSP vector processing hardware, there is an urgent need for efficient matrix multiplication optimization algorithms. Matrix multiplication, as a crucial part frequently used in many scientific applications, is inherently computationally intensive and demanding, making the research on parallel matrix multiplication algorithms a perennial topic in the field of high-performance computing. In addition, matrix multiplication is often used to evaluate the performance and efficiency of new processor architectures, and to explore how to perform high-performance optimizations on new architectures.

[0004] Patent application CN 103294648A, published on September 11, 2013, discloses a block matrix multiplication vectorization method supporting a vector processor with multiple MAC processing units. This method expands each element of each row of the multiplicand A into a vector data and multiplies it by a row of data from matrix B. This scheme differs from the implementation method of this invention, and it also does not implement vector-matrix multiplication after QR decomposition.

[0005] Patent application CN 114090954A, published on February 25, 2022, discloses an optimization method for integer matrix multiplication kernels based on the FT-2000+. This method differentiates the design content of sub-functions based on the different lengths of the input and output matrix data. Combining the FT-2000+ architecture, it determines the register allocation strategy and matrix block strategy to optimize integer matrix multiplication. This method differs from the implementation of the proposed solution, and it also does not implement vector-matrix multiplication after QR decomposition.

[0006] This invention relates to a vector multiplication implementation method based on a vector processor after QR decomposition. The QR decomposition algorithm used is the vsip_cqrd_f function from the VSIP library. After calling the cqrd function, the output QRD structure is retrieved. This structure mainly includes a complex matrix A, a complex vector cI, and a real vector beta. The upper triangular part of the complex matrix A is the R matrix, and the lower triangular part is the Q matrix. After processing by other functions, a vector of length m is obtained and stored in DDR. , will vector The algorithm takes a complex matrix A, a complex vector cI, and an input matrix C as inputs and performs multiplication operations with the Q matrix in QR decomposition in four different cases. Summary of the Invention

[0007] To address the aforementioned technical problems, this invention proposes a method for implementing matrix multiplication after QR decomposition based on a vector processor.

[0008] The technical solution of the present invention includes the following steps: Step 1: Determine whether the input matrix C has undergone transpose and conjugate operations, and whether matrix C is on the left or right side of matrix multiplication, in order to proceed to different sub-functions for processing. The processing methods of each sub-function are largely similar; this scheme mainly describes the common processing methods.

[0009] Step 2: Preprocess matrix A by setting the elements on the diagonal to 1, the elements in the upper right part of the diagonal to 0, and leaving the elements in the lower left part unchanged. After transformation, divide matrix A into columns and name each column a vector in sequence. , For example: vectors Contains the values ​​of the first column of matrix A, and the values ​​of each component are named... , Take matrix C and vector Perform matrix multiplication, multiply the result by the first value of the beta vector, and obtain the vector. .

[0010] Step 3, with vector Multiplication of the transpose yields the matrix. , and Matrix addition operation yields ; The matrix C and vector V are transferred to the cache via DMA. Stored in DDR, the vector is converted via the Scalar Vector Transformation (SVW) unit. The first value Copy and broadcast to the vector operation unit, vector Each row of matrix C takes P numbers and passes them to the vector operation unit. Simultaneously, P multiplication instructions are executed, and the results are stored in the vector operation unit. These results are then added to the first P numbers of the first row of matrix C, with P addition instructions executed. The result is stored in the cache, overwriting the corresponding data in the first row of matrix C. The same calculation is then performed on the (P+1)th to (2P)th numbers until one row of matrix C is updated. The calculation is then performed on the second row, and so on, until all rows are calculated. The result is then named... matrix.

[0011] Step 4, Vector cI and matrix Perform multiplication on each row of the matrix, following a similar procedure to step 3, which will not be repeated here. The matrix updated n times is called... After repeating steps 2 (without repeating preprocessing steps A) n times (n being the number of columns in matrix C) and 3, the cI vector is transferred to the cache via DMA, overwriting the position of the original vector V. The matrix is ​​stored in the cache. P numbers from each row of vector cI and matrix C are taken and passed to the vector operation unit. Simultaneously, P multiplication instructions are executed, and the multiplication results are returned to the cache, overwriting the matrix. For the corresponding position in the first row, take the (P+1)th to (2P)th data points and perform the same calculation until the matrix is ​​updated. The first row; then perform the calculation on the second row, and so on, until all rows have been calculated. Name the result as... matrix.

[0012] The specific method of step 3 of the present invention includes the following steps: Step 3.1: Determine the next processing plan based on the size of the original data. If the original data is extremely small, proceed to step 3.2. If the size of the original data does not exceed the cache size, proceed to step 3.3. If the size of the original data exceeds the cache size, proceed to step 3.4. Step 3.2: When the data volume is extremely small, it will be processed directly in DDR using scalar methods. Step 3.3: If the data volume does not exceed the cache size, transfer matrix C and vector V to the cache via DMA. Stored in DDR, the vector is converted via the Scalar Vector Transformation (SVW) unit. The first value Copy and broadcast to the vector operation unit, vector Each row of matrix C takes P numbers and passes them to the vector operation unit. Simultaneously, P multiplication instructions are executed, and the results are stored in the vector operation unit. These results are then added to the first P numbers of the first row of matrix C, with P addition instructions executed. The result is stored in the cache, overwriting the corresponding data in the first row of matrix C. The same calculation is then performed on the (P+1)th to (2P)th numbers until one row of matrix C is updated. The calculation is then performed on the second row, and so on, until all rows are calculated. The result is then named... matrix; Step 3.4: When the data volume exceeds the cache size, the cache is divided into three parts. The first part is used to store vectors. The remaining space is divided into upper and lower halves. The contents of matrix C are transferred to the upper half row by row via DMA. After the data transfer is complete, the remaining rows of matrix C are transferred to the lower half. The upper half begins calculation, as in step 3.3. The transfer and calculation are performed in parallel. After the calculation in the upper half and the transfer in the lower half are completed, the calculated part is transferred back to DDR via DMA. After the transfer is completed, the remaining contents of matrix C are transferred to the upper half again, and the calculation in the lower half begins. The above steps are repeated until all calculations are completed.

[0013] The specific method of step 4 of the present invention includes the following steps: Step 4.1, Vector cI and matrix Perform multiplication on each row of matrix C, repeating n times (n is the number of columns in matrix C). After steps 2 (preprocessing matrix A without repetition) and 3, the matrix updated n times is called... The processing order is determined based on the size of the original data. When the original data is extremely small, proceed to step 4.2. When the size of the original data does not exceed the cache size, proceed to step 4.3. When the size of the original data exceeds the cache size, proceed to step 4.4. Step 4.2: When the data volume is extremely small, it will be processed directly in DDR using scalar methods. Step 4.3: When the data volume does not exceed the cache size, transfer the cI vector to the cache via DMA, overwriting the position of the original vector V. The matrix is ​​stored in the cache. P numbers from each row of vector cI and matrix C are taken and passed to the vector operation unit. Simultaneously, P multiplication instructions are executed, and the multiplication results are returned to the cache, overwriting the matrix. For the corresponding position in the first row, take the (P+1)th to (2P)th data points and perform the same calculation until the matrix is ​​updated. The first row; then perform the calculation on the second row, and so on, until all rows have been calculated. Name the result as... matrix; Step 4.4: When the data volume exceeds the cache size, the cache is divided into three parts. The first part is used to store vector cI, and the remaining space is divided into upper and lower halves. The contents of matrix C are transferred to the upper half row by row via DMA. After the data transfer is completed, the remaining rows of matrix C are transferred to the lower half. The upper half begins calculation, and the calculation process is as in step 4.3. The transfer and calculation are parallel. After the calculation in the upper half and the transfer in the lower half are completed, the calculated part is transferred back to DDR via DMA. After the transfer is completed, the remaining contents of matrix C are transferred to the upper half again, and the calculation in the lower half begins at the same time. The above steps are repeated until all calculations are completed.

[0014] Compared with the prior art, the beneficial effects of the present invention are: Based on the hardware characteristics of vector processors, this invention ported and optimized the matrix multiplication after QR decomposition in the VSIP library, making full use of the hardware performance advantages, improving the utilization efficiency of computing units, and achieving higher instruction parallelism. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of step 2 of the present invention, which involves preprocessing matrix A.

[0016] Figure 2 The matrix in step 2 of this invention with vector Perform matrix multiplication, multiply the result by the first value of the beta vector, and obtain the vector. Formula diagram.

[0017] Figure 3 For step 3 of the present invention with vector Multiplication of the transpose yields the matrix. , and Matrix addition operation yields Formula diagram.

[0018] Figure 4 This is a flowchart of step 3 of the present invention.

[0019] Figure 5 This is a schematic diagram of the calculation process in step 3 of the present invention.

[0020] Figure 6 For step 4 of this invention, the vector cI and the matrix A diagram illustrating the multiplication formula for each row. Detailed Implementation

[0021] The present invention will now be further described in conjunction with the accompanying drawings and embodiments.

[0022] Set the elements on the diagonal of matrix A to 1, the elements in the upper right part of the diagonal to 0, and the elements in the lower left part of the diagonal to remain unchanged. Figure 1 As shown. After the transformation, matrix A is divided into columns, and each column is named a vector in sequence. , For example: vectors Contains the values ​​of the first column of matrix A, and the values ​​of each component are named... , ,refer to Figure 2 Take the matrix with vector Perform matrix multiplication, multiply the result by the first value of the beta vector, and obtain the vector. .

[0023] Reference,3. Figure 4 The next processing step is determined based on the size of the original data. When the original data is extremely small, scalar processing will be performed directly in DDR. When the size of the original data does not exceed the cache size, the matrix C and vector will be transferred via DMA. Passed into the cache space, the calculation process is as follows: Figure 4 And the next paragraph explains, until all calculations are completed, the result will be named The matrix is ​​stored in the cache at the corresponding position of the C matrix. When the size of the original data exceeds the cache size, the cache is divided into three parts. The first part is used to store vectors. The remaining space is divided into upper and lower halves. The contents of matrix C are transferred to the upper half row by row via DMA. After the data transfer is complete, the remaining rows of matrix C are transferred to the lower half. The upper half begins calculation, and the transfer and calculation are carried out in parallel. After the calculation in the upper half and the transfer in the lower half are completed, the calculated part is transferred back to DDR via DMA. After the transfer is completed, the remaining contents of matrix C are transferred to the upper half again, and the calculation in the lower half begins. The above steps are repeated until all calculations are completed, and the calculation results are transferred back to DDR via DMA.

[0024] refer to Figure 5 Let vector ={ , , , , },vector ={ }, matrix C={ }, { }, { Let the vector processing unit have 4 processing units, capable of processing 4 data points simultaneously, i.e., P=4. During the first row calculation, the vector in DDR is initially... First data Four copies of the vector machine are broadcast via SVW by the scalar vector transformation unit and then transmitted to the vector operation unit, and then transferred from the cache space. }and{ These data enter the vector operation unit, where multiplication is performed to obtain { The four calculation results are then added together to obtain { The four results are returned to the cache, overwriting the data at the corresponding positions in matrix C. } respectively cover { }, and then begin the second operation, to , The data is transmitted to the vector operation unit, where multiplication is performed to obtain... Then perform the addition operation to get the result. The data at the corresponding position in matrix C is overwritten, and the first row of data is returned to DDR after calculation. The second row of calculation then begins, and the vector in DDR is processed. First data Four copies of the vector were broadcast to the vector operation unit via the scalar vector conversion unit (SVW), and the operation process was similar.

[0025] refer to Figure 6 In step 4, vector cI and matrix The diagram illustrates the multiplication formula for each row. After performing the above steps n times (n being the number of columns in the input matrix), the calculation formula in the diagram is used to... When processing the matrix, if the original data is extremely small, scalar processing will be performed directly in DDR. If the original data size does not exceed the cache size, the cI vector will be transferred to the cache via DMA, overwriting the position of the original vector V. The matrix is ​​stored in the cache. P numbers from each row of vector cI and matrix C are taken and passed to the vector operation unit. Simultaneously, P multiplication instructions are executed, and the multiplication results are returned to the cache, overwriting the matrix. For the corresponding position in the first row, take the (P+1)th to (2P)th data points and perform the same calculation until the matrix is ​​updated. The first row; then perform the calculation on the second row, and so on, until all rows have been calculated. Name the result as... The matrix is ​​transferred back to DDR via DMA. When the original data size exceeds the cache size, the cache is divided into three parts. The first part is used to store the vector cI, and the remaining space is divided into upper and lower halves. The matrix is ​​then transferred row by row via DMA. The content is passed to the upper half of the memory, and after the data transmission is complete, the matrix is ​​then transmitted to the lower half of the memory. For the remaining rows, the calculation begins in the upper half of the memory, with transmission and calculation occurring in parallel. After the calculation in the upper half and the transmission in the lower half are completed, the calculated portion is transferred back to DDR via DMA. After the transfer is complete, the matrix transmission continues to the upper half. For the remaining content, begin the calculation of the lower half of the matrix simultaneously, repeating the above steps until all calculations are completed, and then transfer the result matrix back to DDR via DMA.

[0026] In summary, after reading this invention document, those skilled in the art can make various other corresponding modifications to the technical solutions and concepts based on this invention without creative mental effort, and all of these modifications fall within the scope of protection of this invention.

Claims

1. A method for implementing vector multiplication after QR decomposition based on a vector processor, characterized in that: Includes the following steps, Step 1, based on the input matrix Whether transpose, conjugate, and matrix were performed Whether it's the left or right side of the matrix multiplication, the corresponding sub-function is entered for processing. The processing flow of each sub-function includes the following common steps; Step 2: Preprocess matrix A by setting the elements on the diagonal to 1, the elements in the upper right part of the diagonal to 0, and leaving the elements in the lower left part of the diagonal unchanged. After the transformation, divide matrix A into columns and name each column as a vector in order. , ,vector Contains the values ​​of the first column of matrix A, and the values ​​of each component are named... , Take the matrix with vector Perform matrix multiplication, multiply the result by the first value of the beta vector, and obtain the vector. ; Step 3: Transfer matrix C and vector C via DMA. The vector is passed into the cache. Stored in DDR, the vector is converted via the Scalar Vector Transformation (SVW) unit. The first value Copy and broadcast to the vector operation unit, vector P numbers are taken from each row of matrix C and passed to the vector operation unit, and P operations are executed simultaneously. The multiplication instruction, with the result stored in the vector operation unit, is added to the first P numbers of the first row of matrix C. Simultaneously, P addition instructions are executed, and the result is stored in the cache, overwriting the corresponding data in the first row of matrix C. Then, the (P+1)th to (2P)th data are retrieved and the same calculation is performed until one row of matrix C is updated. The calculation then proceeds to the second row, and so on, until all rows are calculated. The result is then named as a matrix. ; Step 4: Repeat steps 2 and 3 n times to obtain intermediate calculation results. Where n is the number of columns in matrix C, the vector cI is transferred to the cache via DMA, overwriting the original vector. Position, matrix Stored in cache, vector cI and matrix Each row takes P numbers and passes them to the vector operation unit, while simultaneously executing P multiplication instructions. The multiplication results are then returned to the cache and overwritten in the matrix. For the corresponding position in the first row, take the (P+1)th to (2P)th data points and perform the same calculation until the matrix is ​​updated. The first row is calculated; then the second row is calculated, and so on, until all rows are calculated. The result is named a matrix. ; The specific method of step 3 includes the following steps. Step 3.1: Determine the next processing plan based on the size of the original data. If the original data is extremely small, proceed to step 3.

2. If the size of the original data does not exceed the cache size, proceed to step 3.

3. If the size of the original data exceeds the cache size, proceed to step 3.

4. Step 3.2: When the data volume is extremely small, it will be processed directly in DDR using scalar methods. Step 3.3: If the data volume does not exceed the cache size, combine matrix C with vector... The vector is transferred to the cache via DMA. Stored in DDR, the vector is converted via the Scalar Vector Transformation (SVW) unit. The first value Copy and broadcast to the vector operation unit, vector Each row of matrix C takes P numbers and passes them to the vector operation unit. Simultaneously, P multiplication instructions are executed, and the results are stored in the vector operation unit. These results are then added to the first P numbers of the first row of matrix C, with P addition instructions executed. The result is stored in the cache, overwriting the corresponding data in the first row of matrix C. The same calculation is then performed on the (P+1)th to (2P)th numbers until one row of matrix C is updated. The calculation is then performed on the second row, and so on, until all rows are calculated. The result is then named matrix C. ; Step 3.4: When the data volume exceeds the cache size, the cache is divided into three parts. The first part is used to store vectors. The remaining space is divided into upper and lower halves. The contents of matrix C are transferred to the upper half row by row via DMA. After the data transfer is completed, the remaining rows of matrix C are transferred to the lower half. The upper half begins calculation, as in step 3.

3. The transfer and calculation are carried out in parallel. After the calculation in the upper half and the transfer in the lower half are completed, the calculated part is transferred back to DDR via DMA. After the transfer is completed, the remaining contents of matrix C are transferred to the upper half again, and the calculation in the lower half begins at the same time. The above steps are repeated until all calculations are completed. The specific method of step 4 includes the following steps. Step 4.1: Determine how to process the data based on its size. If the original data is extremely small, proceed to step 4.

2. If the original data size does not exceed the cache size, proceed to step 4.

3. If the original data size exceeds the cache size, proceed to step 4.

4. Step 4.2: When the data volume is extremely small, it will be processed directly in DDR using scalar methods. Step 4.3: When the data volume does not exceed the cache size, transfer the vector cI to the cache via DMA, overwriting the original vector. Position, matrix Stored in cache, vector cI and matrix Each row takes P numbers and passes them to the vector operation unit, while simultaneously executing P multiplication instructions. The multiplication results are then returned to the cache and overwritten in the matrix. For the corresponding position in the first row, take the (P+1)th to (2P)th data points and perform the same calculation until the matrix is ​​updated. The first row is calculated; then the second row is calculated, and so on, until all rows are calculated. The result is named a matrix. ; Step 4.4: When the data volume exceeds the cache size, the cache is divided into three parts. The first part is used to store the vector cI, and the remaining space is divided into upper and lower halves. The matrix is ​​then transferred row by row via DMA. The content is passed to the upper half of the memory, and after the data transmission is complete, the matrix is ​​then transmitted to the lower half of the memory. For the remaining rows, the calculation begins in the upper half of the memory, following the procedure in step 4.

3. The transfer and calculation proceed in parallel. After the calculation in the upper half and the transfer in the lower half are completed, the calculated portion is transferred back to the DDR via DMA. After the transfer is complete, the matrix is ​​transferred back to the upper half. For the remaining content, begin the calculation of the second half simultaneously, repeating the above steps until all calculations are completed.

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