Online method and system for FPGA critical path delay compensation in portable devices

Abstract

This invention relates to an online critical path delay compensation method and system for FPGAs applied to portable devices, comprising the following steps: 1) determining the critical path within the FPGA chip; 2) sampling the FPGA chip core voltage at multiple points in the time domain and performing digital low-pass filtering to eliminate noise; 3) determining the relationship between voltage and critical path delay; 4) locking the source and terminal layout of the FPGA critical path; 5) selecting and adding an appropriate number of clock delay units based on the core voltage filtering results. This invention's online critical path delay compensation method based on core voltage monitoring fully utilizes the FPGA's internal combinational logic resources, enhancing the reliability of portable devices under conditions of low battery voltage or abnormal power chip output.

Description

Technical Field

[0001] This invention relates to an online method and system for critical path delay compensation in FPGAs for portable devices, belonging to the cross-application technology fields of signal acquisition and processing, embedded development, etc. Background Technology

[0002] Currently, with the rapid development of embedded technology, portable devices are increasingly widely used in various fields such as medical, industrial inspection, and military. In the military field, to ensure the stable and reliable operation of military portable devices in various harsh environments, these devices are required to have the ability to reliably process and transmit data in real time around the clock. Only with stable operation can the corresponding military tasks be reliably completed. In civilian fields such as medical and industrial inspection, although the application environment is not as harsh as that in the military field, the diversity and complexity of their functions still place high demands on the functional reliability of portable devices.

[0003] Currently, due to the advantages of FPGAs, such as high flexibility, abundant hardware resources, high real-time performance, strong portability, and short development cycle, portable devices in various fields are increasingly using FPGA chips for development and implementation. Since the quality of the core voltage directly affects the trace delay of the critical path within the FPGA chip, which in turn affects the reliable operation of the device, as the reliability requirements of portable devices continue to increase, the FPGA chip, as the core processor, must also have stronger adaptability to harsh electrical environments such as unstable power supplies and low battery voltage.

[0004] Currently, determining whether a portable device with an FPGA chip as its processing core can function properly under conditions where the FPGA chip's core voltage supply voltage is unstable or below the standard value requires designers to perform static timing analysis in a specified mode within the development environment after the code design is completed to determine the timing margin under undervoltage conditions. However, the actual situation often differs from the prediction because the actual core voltage of the FPGA chip may be lower than the set value in the selected mode of the static timing analysis. The results of the static timing analysis are insufficient to represent the operating state of the FPGA chip under all operating conditions. Therefore, with the current design approach, it is impossible to guarantee the reliable operation of portable devices under extreme conditions beyond the scope of timing analysis. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide an online critical path delay compensation method and system for portable devices, which can stably achieve critical path delay compensation.

[0006] This invention is achieved through the following technical solution:

[0007] An online critical path delay compensation method for FPGAs applied to portable devices includes the following steps:

[0008] Step 1: Determine the critical path inside the FPGA chip;

[0009] Step 2: Sample the FPGA chip core voltage at multiple points in the time domain and perform digital low-pass filtering to eliminate noise effects;

[0010] Step 3: Determine the relationship between voltage and critical path delay;

[0011] Step 4: Determine the source and terminal register layout of the FPGA critical path;

[0012] Step 5: Select and add an appropriate number of clock delay units based on the core voltage filtering results.

[0013] Furthermore, the critical path refers to the longest-delayed combinational logic and wiring path on the FPGA from the output of the transmit register to the input of the receive register, and this critical path delay includes the combinational logic delay t. comb and routing path delay t wire .

[0014] Furthermore, the FPGA chip core voltage is sampled at multiple points in the time domain. The real-time acquisition condition for the FPGA chip core voltage is that the FPGA chip is normally loaded and running, and the acquisition points are near the core voltage pins of the FPGA chip.

[0015] Furthermore, determining the relationship between voltage and critical path delay specifically involves first measuring the critical path delay under different core voltage values, and then fitting the "voltage-critical path delay" curve using the least squares method based on the calibration results, thereby obtaining the relationship between voltage and critical path delay.

[0016] Furthermore, locking the source and terminal layout of the FPGA critical path includes locking all logic resources except for its clock trace. Specifically, this involves determining the layout positions of the source and terminal registers of the path within the resource planner of the development environment, and recording the critical path delay t displayed on the interface. worst It also locks all logic resources except for the source and end register clock traces.

[0017] Furthermore, the selection of an appropriate number of clock delay units based on the core voltage filtering results is as follows: First, the timing margin of the critical path is determined based on the routing delay information of the critical path, and then the number of clock delay units to be selected is determined based on the "voltage-critical path delay" curve and the current monitored voltage value.

[0018] Furthermore, this invention also proposes an FPGA critical path delay online compensation system, comprising:

[0019] Critical path determination module: Determines the critical path within the FPGA chip;

[0020] Sampling and filtering module: Samples the core voltage of the FPGA chip at multiple points in the time domain and performs digital low-pass filtering to eliminate noise effects;

[0021] Voltage-Critical Path Delay Curve Determination Module: Determines the relationship between voltage and critical path delay;

[0022] Layout locking module: Locks the source and end layouts of the critical path in the FPGA;

[0023] Compensation module: Select and add an appropriate number of clock delay units based on the core voltage filtering results.

[0024] This invention employs an online critical path delay compensation method for portable devices using FPGAs. Compared with existing technologies, its advantages and beneficial effects are:

[0025] (1) This invention offers higher stability. Critical path delay compensation under extreme environments can significantly improve timing characteristics, ensuring that portable devices can still operate reliably even under conditions beyond the scope of timing analysis;

[0026] (2) This invention has adaptive adjustment capability. After the resource area of ​​the critical path inside the FPGA is locked, the selection of the clock delay unit is automatically realized by the FPGA internal program after calculation based on the input core voltage value, the pre-set critical path timing margin, and the fitted "voltage-critical path delay" curve;

[0027] (3) The present invention is easy to implement in engineering. The FPGA critical path delay online compensation method for portable devices involved in the present invention only requires digital low-pass operation on the core voltage sampling output result. The "voltage-critical path delay" curve, which serves as the basis for path selection criterion calculation, is obtained by least squares fitting. The algorithm has low complexity and high real-time performance, and is easy to implement in engineering.

[0028] (4) This invention has broad application prospects in the fields of embedded systems and portable devices. Attached Figure Description

[0029] The FPGA critical path delay online compensation method of the present invention for portable devices is given by the following embodiments and figures.

[0030] Figure 1 This is a critical path diagram;

[0031] Figure 2 This is a schematic diagram of critical path delay compensation; Detailed Implementation

[0032] The following will combine Figure 1 , Figure 2 The present invention provides a further detailed description of the FPGA critical path delay online compensation method for portable devices.

[0033] The concept of this invention is as follows: Voltage values ​​are sampled near the core voltage pins of the FPGA chip within the portable device. After digital low-pass filtering, the current core voltage value of the FPGA chip is determined. Once the critical path within the FPGA is determined, its layout is locked. Based on the measured critical path delays at various voltages, a "voltage-critical path delay" curve is fitted to calculate the current critical path delay. This delay is then compared with the timing margin of the critical path in the static timing analysis results. Based on the comparison, the number of delay units added to the clock traces is determined to meet the setup time of the receiver registers and ensure the reliable operation of the portable device.

[0034] The principle of delay compensation in FPGA critical path:

[0035] like Figure 1 As shown, the critical path refers to the longest on-chip combinational logic and wiring path from the output of the transmit register to the input of the receive register, and this path delay includes the combinational logic delay t. comb and routing path delay t wire If the path is too long, the signal delay through the path will be too high, which will not meet the setup time of the receive register under the specified clock domain. The receive register will enter a metastable state, resulting in signal acquisition errors at the receiving end and causing malfunctions in the portable device.

[0036] To meet the setup time requirements of the receive register, delay compensation must be performed on the critical path where latency is too high. Inserting combinational logic on the clock traces of the transmit and receive registers on the critical path is the most effective compensation method. For example... Figure 2 As shown, the delay length of this compensation combination logic should be selected to be consistent with the delay variation of the critical path as much as possible, so that the arrival time of the clock and data signals of the receiving register is consistent with that of the voltage under normal conditions, satisfying the receiving register setup time and enabling the FPGA to operate normally.

[0037] Typically, delay compensation for critical paths in an FPGA is not performed online by the FPGA itself, but rather manually through repetitive analysis and synthesis, placement and routing, and static timing analysis. Once the resource layout within the FPGA is determined, automatic removal of clock delay units is not possible, which can lead to functional abnormalities in extreme environments where the development environment cannot perform analysis.

[0038] This invention proposes an online critical path delay compensation method for portable devices using FPGAs, which specifically includes the following steps:

[0039] Step 1: Determine the critical path within the FPGA chip; the critical path refers to the longest-delay combinational logic and wiring path within the FPGA chip, from the output of the transmit register to the input of the receive register. This critical path delay includes the combinational logic delay t. comb and routing path delay t wire .

[0040] Step 2: Sample the FPGA chip core voltage at multiple points in the time domain and perform digital low-pass filtering to eliminate noise interference;

[0041] The FPGA chip core voltage is sampled at multiple points in the time domain. The real-time acquisition condition for the FPGA chip core voltage is that the FPGA chip is normally loaded and running, and the acquisition points are near the core voltage pins of the FPGA chip.

[0042] Step 3: Determine the relationship between voltage and critical path delay;

[0043] Specifically, the critical path delay is first measured under different core voltage values, and then the "voltage-critical path delay" curve is fitted using the least squares method based on the calibration results to obtain the relationship between voltage and critical path delay.

[0044] Step 4: Determine the source and terminal layouts of the FPGA critical path;

[0045] Locking the source and termination layout of the FPGA critical path includes locking all logic resources except for its clock trace. Specifically, this involves determining the layout positions of the source and termination registers within the resource planner of the development environment and recording the critical path delay t displayed on the interface. worst It also locks all logic resources except for the source and end register clock traces.

[0046] Step 5: Select and add an appropriate number of clock delay units based on the core voltage filtering results.

[0047] The method of selecting an appropriate number of clock delay units based on the core voltage filtering results is as follows: First, determine the timing margin of the critical path based on the routing delay information of the critical path, and then determine the number of clock delay units to be selected based on the "voltage-critical path delay" curve and the current monitored voltage value.

[0048] Furthermore, this invention also proposes an online delay compensation system for critical paths in FPGAs, comprising:

[0049] Critical path determination module: Determines the critical path within the FPGA chip;

[0050] Sampling and filtering module: Samples the core voltage of the FPGA chip at multiple points in the time domain and performs digital low-pass filtering to eliminate noise effects;

[0051] Voltage-Critical Path Delay Curve Determination Module: Determines the relationship between voltage and critical path delay;

[0052] Layout locking module: Locks the source and end layouts of the critical path in the FPGA;

[0053] Compensation module: Select and add an appropriate number of clock delay units based on the core voltage filtering results.

[0054] Example:

[0055] The online delay compensation method for critical paths in FPGAs applied to portable devices mainly proceeds through the following process:

[0056] 1) Place a small serial port AD converter chip near the core voltage pin of the FPGA in the portable device, making the input voltage of the AD chip as close as possible to the actual core voltage of the FPGA, and use the FPGA chip to drive the chip to collect the AD conversion result data Y. Ucore This value reflects the current core voltage, with a sampling frequency of not less than 10KHz and an AD conversion data bit width of not less than 8 bits;

[0057] 2) Add FFT, low-pass filtering, and IFFT functional modules inside the FPGA chip. Implement them in the form of IP cores as much as possible. Alternatively, you can specify the logic area of ​​the functional module using logic-lock to ensure that the path related to the functional module is not a critical path.

[0058] The FFT conversion length is no less than 256, and the data precision is consistent with that of the AD conversion chip. The FFT output data is piped into a low-pass filter module with a transfer function W to filter out high-frequency components above 10Hz. The data is then restored by an IFFT module to obtain the low-pass filtered core voltage U. core The calculation process is shown in the following formula;

[0059] U core =IFFT(FFT(Y) Ucore )·W)

[0060] 3) Assuming no violations are found in the static timing analysis, review the relevant reports within the FPGA development environment to determine the longest combinational logic delay path, i.e., the critical path. In the development environment's resource planner, determine the placement of the source and end registers for this path, and record the critical path delay t displayed on this interface. worst And lock all logic resources except for the source and end register clock traces;

[0061] 4) Although global clock line resources are limited, their delay is largely unaffected by voltage variations, making them suitable for testing critical path delays relative to voltage. Based on the fixed source and terminal layout of the FPGA critical path, the output of the source register and the input of the terminal register are respectively led out to the top-level pin via global clock lines. By monitoring the outputs of these two pins with an oscilloscope, the delay Δt between waveform changes can be observed. The resource planner in the development environment can then determine the delay Δt of connecting the output of the source register and the input of the terminal register to the global clock line of the top-level pin. o , Δt I Therefore, the change in critical path delay Δt worst U can be obtained using the following formula. core The range of values ​​is (U core (-0.3V)~U core ', where U core 'This refers to the nominal core voltage value;

[0062] Δt worst (U core )=Δt(U core )-Δt o -Δt I -t worst

[0063] 5) According to step 4), Δt worst The test results were fitted to Δt using the least squares method in Matlab. worst ——U core The straight line ultimately yields the critical path delay change Δt. worst With the current core voltage U core The linear relationship is shown in the following formula;

[0064] Δt worst =G(U core )=k·U core +b

[0065] 6) Add a delay change calculation module and a clock buffer unit gating module to the FPGA. The delay change calculation module first determines the delay change based on U... core The critical path delay change Δt is obtained by combining the values ​​of k and b pre-set. worst The clock buffer unit gating module's input is connected to the transmit register's clock input, and its output includes multiple ports. The delay range between the output and input ports is min{Δt}. worst}~max{Δt worst The increased delay is achieved by cascading combinational logic units with a precision of 0.1 ns. Under these conditions, the number of output ports depends on Δt.worst The range of values ​​for . Based on Δt worst By switching the input port signal to the corresponding output port of the module, the automatic delay of the critical path clock is realized, thereby completing the online compensation of the critical path delay.

[0066] The present invention provides an online delay compensation method for critical paths of FPGAs in portable devices. This method is applied to a portable infrared staring imaging device to improve the timing characteristics of the critical path of the FPGA under extreme voltage conditions, and to achieve stable operation of the FPGA chip as the core processor under undervoltage conditions, thereby improving the reliability of the portable infrared staring imaging device.

[0067] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. An online delay compensation method for critical paths in FPGAs applied to portable devices, characterized in that, include: Identify the critical paths within the FPGA chip; The core voltage of the FPGA chip is sampled at multiple points in the time domain and digital low-pass filtered to eliminate noise. Determine the relationship between voltage and critical path delay; Lock in the source and terminal layouts of the FPGA critical path; Based on the core voltage filtering results, select and add an appropriate number of clock delay units.

2. The FPGA critical path delay online compensation method for portable devices according to claim 1, characterized in that: The critical path refers to the longest-delayed combinational logic and wiring path on the FPGA from the output of the transmit register to the input of the receive register. This critical path delay includes the combinational logic delay t. comb and routing path delay t wire .

3. The FPGA critical path delay online compensation method for portable devices according to claim 1, characterized in that: The FPGA chip core voltage is sampled at multiple points in the time domain. The real-time acquisition condition for the FPGA chip core voltage is that the FPGA chip is normally loaded and running, and the acquisition points are near the core voltage pins of the FPGA chip.

4. The FPGA critical path delay online compensation method for portable devices according to claim 2, characterized in that: The determination of the relationship between voltage and critical path delay is specifically achieved by first measuring the critical path delay under different core voltage values, and then fitting the "voltage-critical path delay" curve using the least squares method based on the calibration results, thereby obtaining the relationship between voltage and critical path delay.

5. The FPGA critical path delay online compensation method for portable devices according to claim 1, characterized in that: Locking the source and termination layout of the FPGA critical path includes locking all logic resources except for its clock trace. Specifically, this involves determining the layout positions of the source and termination registers within the resource planner of the development environment and recording the critical path delay t displayed on the interface. worst It also locks all logic resources except for the source and end register clock traces.

6. The FPGA critical path delay online compensation method for portable devices according to claim 1, characterized in that, The method of selecting an appropriate number of clock delay units based on the core voltage filtering results is as follows: First, determine the timing margin of the critical path based on the routing delay information of the critical path, and then determine the number of clock delay units to be selected based on the "voltage-critical path delay" curve and the current monitored voltage value.

7. An FPGA critical path delay online compensation system based on the FPGA critical path delay online compensation method for portable devices as described in claim 1, characterized in that, include: Critical path determination module: Determines the critical path within the FPGA chip; Sampling and filtering module: Samples the core voltage of the FPGA chip at multiple points in the time domain and performs digital low-pass filtering to eliminate noise effects; Voltage-Critical Path Delay Curve Determination Module: Determines the relationship between voltage and critical path delay; Layout locking module: Locks the source and end layouts of the critical path in the FPGA; Compensation module: Select and add an appropriate number of clock delay units based on the core voltage filtering results.

8. The FPGA critical path delay online compensation system according to claim 7, characterized in that: The critical path refers to the longest-delayed combinational logic and wiring path on the FPGA from the output of the transmit register to the input of the receive register. This critical path delay includes the combinational logic delay t. comb and routing path delay t wire .

9. The FPGA critical path delay online compensation system according to claim 7, characterized in that: The FPGA chip core voltage is sampled at multiple points in the time domain. The real-time acquisition condition for the FPGA chip core voltage is that the FPGA chip is normally loaded and running, and the acquisition points are near the core voltage pins of the FPGA chip.

10. The FPGA critical path delay online compensation system according to claim 8, characterized in that: The determination of the relationship between voltage and critical path delay specifically involves first measuring the critical path delay under different core voltage values, and then fitting the "voltage-critical path delay" curve using the least squares method based on the calibration results to obtain the relationship between voltage and critical path delay. Locking the source and termination layout of the FPGA critical path includes locking all logic resources except for its clock trace. Specifically, this involves determining the layout positions of the source and termination registers within the resource planner of the development environment and recording the critical path delay t displayed on the interface. worst And lock all logic resources except for the source and end register clock traces; The method of selecting an appropriate number of clock delay units based on the core voltage filtering results is as follows: First, determine the timing margin of the critical path based on the routing delay information of the critical path, and then determine the number of clock delay units to be selected based on the "voltage-critical path delay" curve and the current monitored voltage value.

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