Adjustable light drive circuit

Abstract

The application provides a dimmable driving circuit, comprising: a front-stage converter coupled with an external power supply and outputting a first voltage; a dimming driving module coupled with the front-stage converter and an external load, receiving the first voltage, outputting a second voltage, and driving the external load to work; a first detection circuit coupled with the front-stage converter, receiving the first voltage, and outputting a first detection signal representing the first voltage; a second detection circuit coupled with the dimming driving module, receiving the second voltage, and outputting a second detection signal representing the second voltage; and a main control module receiving the first detection signal and the second detection signal, outputting an adjustment signal, and sending the adjustment signal to the front-stage converter, so that the front-stage converter adjusts the value of the first voltage, and the ratio of the second voltage to the first voltage is maintained at a preset value. The dimmable driving circuit can minimize the discontinuity in the dimming process.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, specifically to a dimmable driving circuit. Background Technology

[0002] The development of smart lighting has accelerated rapidly in the past two years, with dimming functionality being particularly sought after. Now, an excellent smart lighting system requires its dimming driver circuit to have a silky-smooth dimming effect, resulting in a more comfortable overall visual experience and better meeting the optical requirements of the human eye. In other words, the dimming effect must remain consistent at any brightness level and throughout the dimming process, as flickering light can create a sense of danger. PWM chopper dimming is a highly cost-effective dimming driver solution, capable of achieving dimming depths of one-thousandth or even one-ten-thousandth, thus meeting various dimming needs.

[0003] However, researchers noted that if the changes in the two consecutive PWM dimming signals happen to fall during the inductor's discharge period, the inductor current will not actually increase, and the lamp's brightness will not change. Please see [link / reference]. Figure 1 As shown in the diagram below, the effective high level of the previous PWM dimming signal lasts until position a, and the effective high level of the subsequent PWM dimming signal lasts until position b. That is, the length of the effective high level of the two PWM dimming signals changes from position a to position b, increasing the brightness. Theoretically, the lamp's brightness should increase slightly. However, because the changes in these two PWM dimming signals fall precisely during the inductor's discharge period, as shown by the dashed line in the diagram (the inductor's operating frequency is determined separately), the inductor current (which is also the current flowing through the LED) does not actually increase at this time, so the LED's brightness does not change. Therefore, it is only when the effective high level of the subsequent PWM dimming signal falls during the inductor's charging period that the inductor's current directly operates according to the current corresponding to the subsequent PWM dimming signal. That is, the current jumps directly, and the LED's brightness jumps directly to become brighter. This is the jitter (dither) in dimming. If multiple consecutive changes in PWM dimming signals fall during the inductor's discharge period, this jitter becomes even more pronounced.

[0004] One direct solution is to detect and determine the effective high-level time of the PWM dimming signal, as well as the charging and discharging periods of the inductor, so that the effective high-level time of the PWM dimming signal falls as close as possible to the charging period of the inductor. However, it is clear that implementing this solution is exceptionally difficult. The inventors of this application propose that if the duty cycle of the PWM chopper dimming circuit is increased as much as possible, for example, to 100% in an ideal scenario, i.e., increasing the ratio of the output voltage to the input voltage of the PWM chopper dimming circuit, the discharging period of the inductor can be minimized. Please refer to [link to relevant documentation]. Figure 2As shown by the dashed line, this makes it easier to avoid changes in the PWM dimming signal falling during the inductor's discharge period, thereby reducing dimming jerks. Therefore, the inventors of this application have proposed the solution described in this application. Summary of the Invention

[0005] The purpose of this application is to provide a dimmable drive circuit that can minimize the stuttering during the dimming process.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] This application provides a dimmable driving circuit, including:

[0008] The pre-converter is coupled to an external power supply and outputs the first voltage;

[0009] The dimming drive module is coupled to both the pre-stage converter and the external load, receives the first voltage, outputs the second voltage, and drives the external load to work.

[0010] A first detection circuit is coupled to the front-end converter, receives the first voltage, and outputs a first detection signal characterizing the first voltage.

[0011] The second detection circuit is coupled to the dimming drive module, receives the second voltage, and outputs a second detection signal characterizing the second voltage;

[0012] The main control module is coupled to the first detection circuit, the second detection circuit, and the pre-stage converter. It receives the first detection signal and the second detection signal, outputs an adjustment signal, and sends it to the pre-stage converter. The pre-stage converter adjusts the value of the first voltage, and the ratio of the second voltage to the first voltage is maintained at a preset value.

[0013] In one embodiment, the dimmable driving circuit further includes a voltage reference and a feedback loop. The voltage reference and the feedback loop are coupled to the main control module and the pre-converter. The circuit receives the adjustment signal output by the main control module, generates a feedback signal, and sends it to the pre-converter. The pre-converter adjusts the value of the first voltage according to the feedback signal.

[0014] In one embodiment, the main control module includes a main control chip. The main control chip has a first pin as a power supply pin, coupled to a working power supply; a second pin as a first detection pin, coupled to a first detection circuit, to receive the first detection signal output by the first detection circuit; a third pin as a second detection pin, coupled to a second detection circuit, to receive the second detection signal output by the second detection circuit; a third pin as an adjustment signal output pin, to output the adjustment signal; and an eighth pin as a ground pin, coupled to signal ground.

[0015] In one embodiment, the main control chip has a seventh pin as a dimming signal output pin, which is coupled to the dimming drive module and outputs a dimming signal to the dimming drive module.

[0016] In one embodiment, the dimming drive module includes a dimming chip. The dimming chip has a second pin as a dimming signal input pin, which is coupled to signal ground via a second resistor. The dimming chip has a third pin as a power supply pin, which is coupled to signal ground via a first capacitor and to the pre-amplifier via a first resistor to receive the first voltage. The dimming chip has a fifth pin as a drive pin, which is coupled to the external load via a second inductor and to the pre-amplifier via a first diode. The anode of the first diode is coupled to the first voltage, and the cathode of the first diode is coupled to the fifth pin of the dimming chip. The dimming chip has a seventh pin as a ground pin, which is coupled to signal ground.

[0017] In one embodiment, the dimming drive module is a PWM chopper dimming drive circuit, and the dimming signal is a PWM signal.

[0018] In one embodiment, the first detection circuit includes a ninth resistor and an eleventh resistor connected in series. The free end of the ninth resistor is coupled to the pre-converter and receives the first voltage. The free end of the eleventh resistor is coupled to signal ground. The coupling point of the ninth and eleventh resistors outputs the first detection signal. The second detection circuit includes a fourth resistor and a tenth resistor connected in series. The free end of the fourth resistor is coupled to the dimming drive module and receives the second voltage. The free end of the tenth resistor is coupled to signal ground. The coupling point of the fourth and tenth resistors outputs the second detection signal.

[0019] In one embodiment, the voltage reference and feedback loop includes a reference voltage chip and an optocoupler. The reference voltage chip has a third pin as a ground pin, coupled to signal ground; the reference voltage chip has a second pin as a power supply pin, coupled to the pre-amplifier via a series sixteenth and seventeenth resistors, to receive the first voltage; the reference voltage chip has a first pin as an adjustment pin, coupled to the main control module via a twenty-third resistor, to receive the adjustment signal; the first pin of the reference voltage chip is also coupled to signal ground via a twentyth resistor, coupled to the pre-amplifier via an eighteenth resistor, and coupled to the second pin of the reference voltage chip via a series eighth capacitor and a twenty-first resistor; the optocoupler has a first pin and a second pin, connected in parallel across the seventeenth resistor; the optocoupler has a third pin coupled to power ground; the optocoupler has a fourth pin coupled to the pre-amplifier, outputting the feedback signal and sending it to the pre-amplifier.

[0020] In one embodiment, the front-end converter includes an auxiliary control chip, a power transistor, and a transformer. The auxiliary control chip has an eighth pin as a feedback pin, coupled to the voltage reference and the feedback loop, to receive feedback signals provided by the voltage reference and the feedback loop. The eighth pin of the auxiliary control chip is also coupled to power ground via a third capacitor. The auxiliary control chip has a second pin as a power supply pin, coupled to the transformer via a sixth resistor and a third diode connected in series, and also coupled to power ground via a third electrolytic capacitor. The auxiliary control chip has a seventh pin as a ground pin, coupled to power ground. The auxiliary control chip has a fifth pin as a control pin, coupled to the transformer via the power transistor.

[0021] In one embodiment, the front-end converter further includes a rectifier bridge, the input of which is coupled to the external power supply, and a first electrolytic capacitor is connected in parallel between the two ends of the output of the rectifier bridge, which is then coupled to the transformer.

[0022] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0023] The dimmable driving circuit described in this application acquires the first voltage output by the pre-converter (i.e., the input voltage of the dimming driving module) and the second voltage output by the dimming driving module (i.e., the output voltage of the dimming driving module, i.e., the load voltage). Based on different load voltages (e.g., different external loads, i.e., the second voltage) and a preset value of the ratio of the second voltage to the first voltage (the highest value of the duty cycle of the dimming driving module), the circuit adjusts the value of the first voltage output by the pre-converter to maintain the ratio of the second voltage to the first voltage at the preset value. This reduces the discharge period of the inductor in the dimming driving module, thus minimizing the probability that changes in the dimming signal fall within the discharge period of the inductor, thereby reducing the jerking during dimming and improving the user experience. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the current in the inductor and the waveform of the dimming signal in a prior art dimmable drive circuit.

[0026] Figure 2 This is a waveform diagram of the current in the inductor in the dimmable drive circuit described in this application;

[0027] Figure 3 This is a schematic diagram of a dimmable driving circuit provided in the first embodiment of this application. Detailed Implementation

[0028] The technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] This application provides a dimmable driving circuit, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments of this application. Furthermore, in the following embodiments, the descriptions of each embodiment have their own emphasis; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments.

[0030] Please see Figure 3As shown, the first embodiment of this application provides a dimmable driving circuit, including:

[0031] The pre-converter 10 is coupled to an external power supply and outputs a first voltage V1;

[0032] The dimming drive module 20 is coupled to both the pre-stage converter 10 and the external load 70. It receives the first voltage V1, outputs the second voltage V2, and drives the external load 70 to work.

[0033] The first detection circuit 30 is coupled to the front-end converter 10, receives the first voltage V1, and outputs a first detection signal ADC_V1 characterizing the first voltage V1.

[0034] The second detection circuit 40 is coupled to the dimming drive module 20, receives the second voltage V2, and outputs a second detection signal ADC_V2 characterizing the second voltage V2;

[0035] The main control module 50 is coupled to the first detection circuit 30, the second detection circuit 40, and the pre-stage converter 10. It receives the first detection signal ADC_V1 and the second detection signal ADC_V2, and outputs an adjustment signal DAC_ADJ, which is sent to the pre-stage converter 10. The pre-stage converter 10 adjusts the value of the first voltage V1, and the ratio of the second voltage V2 to the first voltage V1 is maintained at a preset value.

[0036] The first voltage V1 is provided to the dimming drive module 20 and can also be referred to as the input voltage of the dimming drive module 20. The second voltage V2 is output from the dimming drive module 20 and can also be referred to as the output voltage of the dimming drive module 20, applied to the external load 70 and can also be referred to as the load voltage. In one embodiment, the external load 70 is an LED chip, and multiple or multiple groups of LED chips can be connected in series and / or in parallel; the second voltage V2 is applied to the negative terminal of the LED chip, and the positive terminal of the LED chip is coupled to the first voltage V1. The ratio of the second voltage V2 to the first voltage V1 can also be referred to as the duty cycle D of the dimming drive module 20. Generally speaking, the maximum value of the duty cycle D of a dimming drive module 20 can be determined during the design based on the various parameter requirements of the dimming drive module 20 and subsequent testing and verification, and this determined maximum value of the duty cycle D is used as the preset value and stored in the dimming drive module 20. For example, in one specific embodiment, the maximum value of the duty cycle D can be 94% or 95%. Generally, a duty cycle D greater than 80%, especially greater than 90%, is preferable. This application adjusts the first voltage V1 (the input voltage of the dimming drive module 20) by detecting the load voltage (the second voltage V2, which varies when coupled to different external loads 70), so that the ratio of the second voltage V2 to the first voltage V1 is maintained at a preset value, i.e., a higher duty cycle D, such as 94% or 95%. In this way, regardless of what kind of external load 70 is coupled to the dimmable drive circuit described in this application, the discharge period of the inductor in the dimming drive module 20 will be minimized, thereby avoiding changes in the dimming signal falling within the discharge period of the inductor, thus reducing dimming jitter and providing users with a better user experience.

[0037] In one embodiment, the main control module 50 includes a main control chip U5. The main control chip U5 has a first pin as a power supply pin, coupled to the operating power supply; the main control chip U5 has a second pin as a first detection pin CS / PA7, coupled to the first detection circuit 30, and receives the first detection signal ADC_V1 output by the first detection circuit 30; the main control chip U5 has a third pin as a second detection pin TKS / PA6, coupled to the second detection circuit 40, and receives the second detection signal ADC_V2 output by the second detection circuit 40; the main control chip U5 has a third pin as an adjustment signal output pin RSTB / PA5, and outputs the adjustment signal DAC_ADJ; the main control chip U5 has an eighth pin as a ground pin, coupled to signal ground SGND. As mentioned above, the main control module 50 stores a preset value for the ratio of the second voltage V2 to the first voltage V1, which is the highest value of the duty cycle D of the dimming drive module 20. Furthermore, the acquired first detection signal ADC_V1 actually represents the actual value of the first voltage V1, and the acquired second detection signal ADC_V2 actually represents the actual value of the second voltage V2. Through judgment, comparison, and calculation, an adjustment signal DAC_ADJ can be output to represent the ideal value that the first voltage V1 should achieve. For example, in a specific embodiment, the current actual value of the first voltage V1 is 24V, but by comparing and calculating with the second voltage V2 and the highest value (preset value) of the duty cycle D, it is determined that the ideal value of the first voltage V1 should be 22V. Thus, the output adjustment signal DAC_ADJ represents this 22V.

[0038] In one embodiment, the adjustment signal DAC_ADJ is an analog signal. This analog signal cannot directly control the pre-amplifier 10 to change the output first voltage V1. Therefore, in one embodiment, the dimmable drive circuit further includes a voltage reference and a feedback loop 60. The voltage reference and feedback loop 60 are coupled to the main control module 50 and the pre-amplifier 10, receive the adjustment signal DAC_ADJ output by the main control module 50, generate a feedback signal FB, and send it to the pre-amplifier 10. The pre-amplifier 10 adjusts the value of the first voltage V1 according to the feedback signal FB. The adjustment signal DAC_ADJ is converted by the voltage reference and feedback loop 60 to generate the feedback signal FB, which is then sent to the pre-amplifier 10. The pre-amplifier 10 can then adjust the value of the first voltage V1 according to the feedback signal FB.

[0039] In one embodiment, the voltage reference and feedback loop 60 includes a reference voltage chip U2 and an optocoupler U3. The reference voltage chip U2 has a third pin as a ground pin, coupled to signal ground SGND; the reference voltage chip U2 has a second pin as a power supply pin, coupled to the pre-converter 10 via a series sixteenth resistor R16 and a seventeenth resistor R17, to receive the first voltage V1; the reference voltage chip U2 has a first pin as an adjustment pin, coupled to the main control module 50 via a twenty-third resistor R23, to receive the adjustment signal DAC_ADJ. The first pin of voltage chip U2 is also coupled to signal ground SGND via the twentieth resistor R20, and to the pre-converter 10 via the eighteenth resistor R18. It is also coupled to the second pin of the reference voltage chip U2 via the eighth capacitor C8 and the twenty-first resistor R21 connected in series. Optocoupler U3 has a first pin and a second pin connected in parallel across the seventeenth resistor R17. Optocoupler U3 has a third pin coupled to power ground PGND, and a fourth pin coupled to the pre-converter 10, outputting the feedback signal FB, which is sent to the pre-converter 10. In one specific embodiment, the reference voltage chip U2 is a TL431M. The adjustment signal DAC_ADJ, as an analog signal, is converted by the voltage reference and feedback loop 60 to generate the feedback signal FB, which can be used to control the pre-converter 10 to change the output first voltage V1.

[0040] In one embodiment, the front-end converter 10 includes an auxiliary control chip U1, a power transistor Q1, and a transformer T1. The auxiliary control chip U1 has an eighth pin as a feedback pin, coupled to the voltage reference and feedback loop 60, receiving the feedback signal FB provided by the voltage reference and feedback loop 60. The eighth pin of the auxiliary control chip U1 is also coupled to power ground PGND via a third capacitor C3. The auxiliary control chip U1 has a second pin as a power supply pin, coupled to the transformer T1 via a sixth resistor D6 and a third diode D3 connected in series, and also coupled to power ground PGND via a third electrolytic capacitor EC3. The auxiliary control chip U1 has a seventh pin as a ground pin, coupled to power ground PGND. The auxiliary control chip U1 has a fifth pin as a control pin, coupled to the transformer T1 via the power transistor Q1. In a specific embodiment, the auxiliary control chip U1 is model HFC0100HS. The value of the output first voltage V1 can be adjusted according to the different feedback signals FB.

[0041] More specifically, in one embodiment, the pre-converter 10 further includes a rectifier bridge DB1. The input terminal of the rectifier bridge DB1 is coupled to the external power supply. In one specific embodiment, the external power supply is alternating current (AC). The two ends of the input terminal of the rectifier bridge DB1 are coupled to the AC power supply through a live wire L and a neutral wire N, respectively. A first electrolytic capacitor EC1 is connected in parallel between the two ends of the output terminal of the rectifier bridge DB1, and then coupled to the transformer T1. The transformer T1 has a first pin, a third pin, a fifth pin, a sixth pin, a ninth pin, and a tenth pin. The first pin and the third pin of the transformer T1 form the primary winding of the transformer T1. The ninth pin and the tenth pin of the transformer T1 form the secondary winding of the transformer T1. The fifth pin and the sixth pin of the transformer T1 form the auxiliary winding of the transformer T1. The first pin of transformer T1 is coupled to the first output terminal of rectifier bridge DB1, the second output terminal of rectifier bridge DB1 is coupled to power ground PGND, and the third pin of transformer T1 is coupled to the drain of power transistor Q1. A fourth diode D4 and a fourth electrolytic capacitor EC4 are connected in series between the ninth and tenth pins of transformer T1, and the tenth pin of transformer T1 is coupled to signal ground SGND. The coupling point of the fourth diode D4 and the fourth electrolytic capacitor EC4 outputs the first voltage V1. The fifth pin of transformer T1 is coupled to power ground PGND, and the sixth pin of transformer T1 is coupled to the second pin of auxiliary control chip U1 via the third diode D3 and the sixth resistor D6 connected in series. The auxiliary control chip U1 also has a first pin as a valley detection pin, coupled to the sixth pin of transformer T1 via a seventh resistor R7, and coupled to power ground PGND via a fifth capacitor C5. The auxiliary control chip U1 also has a fourth pin, the voltage power supply pin HV, which is coupled to the first terminal of the output of the rectifier bridge DB1 via a fifth resistor R5. The auxiliary control chip U1 also has a sixth pin, the sampling pin CS, which is coupled to the power ground PGND via a fourth capacitor C4, and further coupled to the power ground PGND via a twelfth resistor R12, and is also coupled to the source of the power transistor Q1. The fifth pin of the auxiliary control chip U1 is coupled to the gate of the power transistor Q1. Thus, the front-end converter 10 can operate more completely and safely, adjusting the value of the first output voltage V1 according to the different feedback signals FB, and performing various sampling and detection operations, ensuring safe and stable circuit operation.

[0042] In one embodiment, the dimming drive module 20 includes a dimming chip U6. The dimming chip U6 has a second pin as a dimming signal input pin, coupled to signal ground SGND via a second resistor R2. The dimming chip U6 has a third pin as a power supply pin, coupled to signal ground SGND via a first capacitor C1, and coupled to the pre-converter 10 via a first resistor R1, receiving the first voltage V1. The dimming chip U6 has a fifth pin as a drive pin, coupled to the external load 70 via a second inductor T2, and coupled to the pre-converter 10 via a first diode D1. The anode of the first diode D1 is coupled to the first voltage V1, and the cathode of the first diode D1 is coupled to the fifth pin of the dimming chip U6. The dimming chip U6 has a seventh pin as a ground pin, coupled to signal ground SGND. The dimming signal is provided by the main control module 50. The main control chip U5 has a seventh pin as a dimming signal output pin, coupled to the dimming drive module 20, outputting a dimming signal to the dimming drive module 20. That is, the second pin of the dimming chip U6 is coupled to the seventh pin of the main control chip U5, receiving the dimming signal output from the seventh pin of the main control chip U5. In one embodiment, the dimming signal is a PWM signal, meaning the dimming drive module 20 is a PWM chopper dimming drive circuit. More specifically, the dimming chip U6 has an eighth pin as a ground pin, coupled to the seventh pin of the dimming chip U6; the dimming chip U6 has a sixth pin, also a drive pin, coupled to the fifth pin of the dimming chip U6; and the dimming chip U6 has a first pin, also a voltage regulator pin (LD), coupled to the third pin of the dimming chip U6.

[0043] In one embodiment, the first detection circuit 30 includes a ninth resistor R9 and an eleventh resistor R11 connected in series. The free end of the ninth resistor R9 is coupled to the pre-converter 10 and receives the first voltage V1. The free end of the eleventh resistor R11 is coupled to signal ground SGND. The coupling point of the ninth resistor R9 and the eleventh resistor R11 outputs the first detection signal ADC_V1. The second detection circuit 40 includes a fourth resistor R4 and a tenth resistor R10 connected in series. The free end of the fourth resistor R4 is coupled to the dimming drive module 20 and receives the second voltage V2. The free end of the tenth resistor R10 is coupled to signal ground SGND. The coupling point of the fourth resistor R4 and the tenth resistor R10 outputs the second detection signal ADC_V2.

[0044] Finally, it should be noted that the first pin of the main control chip U5 is coupled to the preamplifier 10 via a voltage conversion chip U4, converting the first voltage V1 output by the preamplifier 10 into the operating voltage required by the main control chip U5. For example, if the first voltage V1 is 24V and the operating voltage required by the main control chip U5 is 5V, the conversion is completed by the voltage conversion chip U4.

[0045] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0046] The dimmable driving circuit described in this application acquires the first voltage output by the pre-converter (i.e., the input voltage of the dimming driving module) and the second voltage output by the dimming driving module (i.e., the output voltage of the dimming driving module, i.e., the load voltage). Based on different load voltages (e.g., different external loads, i.e., the second voltage) and a preset value of the ratio of the second voltage to the first voltage (the highest value of the duty cycle of the dimming driving module), the circuit adjusts the value of the first voltage output by the pre-converter to maintain the ratio of the second voltage to the first voltage at the preset value. This reduces the discharge period of the inductor in the dimming driving module, thus minimizing the probability that changes in the dimming signal fall within the discharge period of the inductor, thereby reducing the jerking during dimming and improving the user experience.

[0047] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the claims. Furthermore, specific examples have been used in the specification to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application, and the content of this specification should not be construed as a limitation of this application.

Claims

1. A dimmable driving circuit, characterized in that, include: The pre-converter (10) is coupled to an external power supply and outputs a first voltage (V1); The dimming drive module (20) is coupled to both the pre-amplifier (10) and the external load (70), receives the first voltage (V1), outputs the second voltage (V2), and drives the external load (70) to work. The first detection circuit (30) is coupled to the front-end converter (10), receives the first voltage (V1), and outputs a first detection signal (ADC_V1) characterizing the first voltage (V1). The second detection circuit (40) is coupled to the dimming drive module (20), receives the second voltage (V2), and outputs a second detection signal (ADC_V2) characterizing the second voltage (V2); The main control module (50) is coupled to the first detection circuit (30), the second detection circuit (40), and the front-end converter (10). It receives the first detection signal (ADC_V1) and the second detection signal (ADC_V2), outputs the adjustment signal (DAC_ADJ), and sends it to the front-end converter (10). The voltage reference and feedback loop (60) are coupled to the main control module (50) and the pre-amplifier (10), receive the adjustment signal (DAC_ADJ), generate a feedback signal (FB), and send it to the pre-amplifier (10). The pre-amplifier (10) adjusts the value of the first voltage (V1) according to the feedback signal (FB) so that the ratio of the second voltage (V2) to the first voltage (V1) is maintained at a preset value greater than 90%.

2. The dimmable driving circuit according to claim 1, characterized in that, The main control module (50) includes a main control chip (U5). The main control chip (U5) has a first pin as a power supply pin, coupled to the working power supply; the main control chip (U5) has a second pin as a first detection pin (CS / PA7), coupled to the first detection circuit (30), and receives the first detection signal (ADC_V1) output by the first detection circuit (30); the main control chip (U5) has a third pin as a second detection pin (TKS / PA6), coupled to the second detection circuit (40), and receives the second detection signal (ADC_V2) output by the second detection circuit (40); the main control chip (U5) has a third pin as an adjustment signal output pin (RSTB / PA5), and outputs the adjustment signal (DAC_ADJ); the main control chip (U5) has an eighth pin as a ground pin, coupled to signal ground (SGND).

3. The dimmable driving circuit according to claim 2, characterized in that, The main control chip (U5) has a seventh pin as a dimming signal output pin, which is coupled to the dimming drive module (20) and outputs a dimming signal to the dimming drive module (20).

4. The dimmable driving circuit according to claim 3, characterized in that, The dimming drive module (20) includes a dimming chip (U6), which has a second pin as a dimming signal input pin and is coupled to signal ground (SGND) via a second resistor (R2); the dimming chip (U6) has a third pin as a power supply pin, which is coupled to signal ground (SGND) via a first capacitor (C1) and to the pre-converter (10) via a first resistor (R1) to receive the first voltage (V1); the dimming chip (U6) has a fifth pin as a drive pin, which is coupled to the external load (70) via a second inductor (T2) and to the pre-converter (10) via a first diode (D1), the anode of the first diode (D1) being coupled to the first voltage (V1) and the cathode of the first diode (D1) being coupled to the fifth pin of the dimming chip (U6); the dimming chip (U6) has a seventh pin as a ground pin, which is coupled to signal ground (SGND).

5. The dimmable driving circuit according to claim 4, characterized in that, The dimming drive module (20) is a PWM chopper dimming drive circuit, and the dimming signal is a PWM signal.

6. The dimmable driving circuit according to claim 1, characterized in that, The first detection circuit (30) includes a ninth resistor (R9) and an eleventh resistor (R11) connected in series. The free end of the ninth resistor (R9) is coupled to the pre-converter (10) and receives the first voltage (V1). The free end of the eleventh resistor (R11) is coupled to signal ground (SGND). The coupling point of the ninth resistor (R9) and the eleventh resistor (R11) outputs the first detection signal (ADC_V1). The second detection circuit (40) includes a fourth resistor (R4) and a tenth resistor (R10) connected in series. The free end of the fourth resistor (R4) is coupled to the dimming drive module (20) and receives the second voltage (V2). The free end of the tenth resistor (R10) is coupled to signal ground (SGND). The coupling point of the fourth resistor (R4) and the tenth resistor (R10) outputs the second detection signal (ADC_V2).

7. The dimmable driving circuit according to claim 1, characterized in that, The voltage reference and feedback loop (60) includes a reference voltage chip (U2) and an optocoupler (U3). The reference voltage chip (U2) has a third pin as a ground pin, coupled to signal ground (SGND); the reference voltage chip (U2) has a second pin as a power supply pin, coupled to the pre-converter (10) via a series sixteenth resistor (R16) and a seventeenth resistor (R17), to receive the first voltage (V1); the reference voltage chip (U2) has a first pin as an adjustment pin, coupled to the main control module (50) via a twenty-third resistor (R23), to receive the adjustment signal (DAC_ADJ). The first pin of U2 is also coupled to signal ground (SGND) via the twentieth resistor (R20), and to the pre-converter (10) via the eighteenth resistor (R18). It is also coupled to the second pin of the reference voltage chip (U2) via the eighth capacitor (C8) and the twenty-first resistor (R21) connected in series. The optocoupler (U3) has a first pin and a second pin connected in parallel across the seventeenth resistor (R17). The optocoupler has a third pin coupled to power ground (PGND). The optocoupler (U3) has a fourth pin coupled to the pre-converter (10) and outputs the feedback signal (FB) to the pre-converter (10).

8. The dimmable driving circuit according to claim 7, characterized in that, The front-end converter (10) includes an auxiliary control chip (U1), a power transistor (Q1), and a transformer (T1). The auxiliary control chip (U1) has an eighth pin as a feedback pin, which is coupled to the voltage reference and feedback loop (60) to receive the feedback signal (FB) provided by the voltage reference and feedback loop (60). The eighth pin of the auxiliary control chip (U1) is also coupled to the power supply ground (PGND) via a third capacitor (C3). The auxiliary control chip (U1) has a second pin as a power supply pin, which is coupled to the transformer (T1) via a sixth resistor (D6) and a third diode (D3) connected in series, and is also coupled to the power supply ground (PGND) via a third electrolytic capacitor (EC3). The auxiliary control chip (U1) has a seventh pin as a ground pin, which is coupled to the power supply ground (PGND). The auxiliary control chip (U1) has a fifth pin as a control pin, which is coupled to the transformer (T1) via the power transistor (Q1).

9. The dimmable driving circuit according to claim 8, characterized in that, The pre-converter (10) further includes a rectifier bridge (DB1), the input of which is coupled to the external power supply, and a first electrolytic capacitor (EC1) is connected in parallel between the two ends of the output of the rectifier bridge (DB1), which is then coupled to the transformer (T1).

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