Display panel, preparation method thereof and display device

Abstract

Embodiments of the present application provide a display panel, a preparation method thereof and a display device, and relate to the technical field of display. The display panel is used to improve the reliability of the display panel and / or reduce the power consumption of the display panel. The display area includes first wires and second wires; the non-display area includes third wires and fourth wires; the first wires include first wires of a first type, the first wires of the first type include first sub-wires and second sub-wires which are arranged at intervals between the third wires and the fourth wires; the second wires include second wires of a first type; the third wires include first repair lines; the fourth wires include second repair lines; the first sub-wires and the second sub-wires are electrically connected through the first repair lines, the second wires of the first type and the second repair lines; and / or the first wires include first wires of a second type, the first wires of the second type are continuously arranged between the third wires and the fourth wires; the second wires include second wires of a second type, and the second wires of the second type transmit a first common signal.

Description

[0001] The present application relates to the technical field of display, in particular to a display panel, a preparation method thereof and a display device.

[0002] With the continuous development of display technology, consumers' requirements for display screens are constantly increasing. At present, various types of displays including liquid crystal display screens and organic light emitting display screens are emerging in an endless stream and are developing rapidly. On this basis, 3D display, touch display technology, curved display, ultra-high resolution display and anti-peep display and other display technologies are constantly emerging.

[0003] However, the current display panel has problems such as poor brightness uniformity and / or signal line easy to break, which affect the display quality.

[0004] Therefore, the embodiments of the present application provide a display panel, a preparation method thereof and a display device to improve the display quality of the display panel.

[0005] In one aspect, the embodiments of the present application provide a display panel, comprising a display area and a non-display area;

[0006] The display area comprises a plurality of first wires and a plurality of second wires;

[0007] The non-display area comprises at least one third wire and at least one fourth wire, and the third wire and the fourth wire are respectively located on both sides of the first wire along the extension direction of the first wire;

[0008] The first wire comprises a first type of first wire, the first type of first wire comprises a first sub-wire and a second sub-wire arranged at intervals between the third wire and the fourth wire; the second wire comprises a first type of second wire; the third wire comprises a first repair line; the fourth wire comprises a second repair line; the first sub-wire and the second sub-wire are electrically connected through the first repair line, the first type of second wire and the second repair line;

[0009] And / or,

[0010] The first wire comprises a second type of first wire, and the second type of first wire is continuously arranged between the third wire and the fourth wire; the second wire comprises a second type of second wire, and the second type of second wire transmits a first common signal.

[0011] In another aspect, the embodiments of the present application provide a preparation method of a display panel, the display panel comprising a display area and a non-display area; the preparation method comprises:

[0012] forming a plurality of first wires and a plurality of second wires in the display area;

[0013] ​​​Form at least one third wiring and at least one fourth wiring in the non-display area, and the third wiring and the fourth wiring are respectively located on both sides of the first wiring along the extension direction of the first wiring;

[0014] Detect whether the first wiring includes a first type of first wiring, and the first type of first wiring includes a first sub-wiring and a second sub-wiring arranged at intervals between the third wiring and the fourth wiring;

[0015] If the first wiring includes the first type of first wiring:

[0016] Select a second wiring as a first type of second wiring; and cut the third wiring to obtain a first repair line, and cut the fourth wiring to obtain a second repair line;

[0017] The first sub-wiring and the second sub-wiring are electrically connected through the first repair line, the first type of second wiring and the second repair line.

[0018] In another aspect, the embodiment of the present application provides a display device comprising the display panel.

[0019] The display panel, the preparation method thereof and the display device provided by the embodiment of the present application can improve the display quality of the display panel by arranging the first wiring and the second wiring in the display panel, and making the first wiring include the first type of first wiring and / or the first type of second wiring, making the second wiring include the first type of second wiring and / or the second type of second wiring, and electrically connecting the first sub-wiring and the second sub-wiring in the first type of first wiring through the first repair line, the first type of second wiring and the second repair line. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can also be obtained according to these drawings without creative labor for those skilled in the art.

[0021] Figure 1 A schematic diagram of a display panel provided by the embodiment of the present application;

[0022] Figure 2 An equivalent circuit schematic diagram of a sub-pixel provided by the embodiment of the present application;

[0023] Figure 3 A working timing schematic diagram of a pixel driving circuit provided by the embodiment of the present application;

[0024] Figure 4 A schematic diagram of another display panel provided by the embodiment of the present application;

[0025] Figure 5 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0026] Figure 6 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0027] Figure 7 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0028] Figure 8 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0029] Figure 9 A schematic diagram of wiring of a display panel provided by an embodiment of the present invention;

[0030] Figure 10 for Figure 9 A schematic cross-sectional view along BB';

[0031] Figure 11 A schematic top view of a semiconductor layer provided by an embodiment of the present invention;

[0032] Figure 12 A schematic top view of a first metal layer provided in an embodiment of the present invention;

[0033] Figure 13 A schematic top view of a second metal layer provided in an embodiment of the present invention;

[0034] Figure 14 A schematic top view of a third metal layer provided in an embodiment of the present invention;

[0035] Figure 15 A schematic top view of a fourth metal layer provided in an embodiment of the present invention;

[0036] Figure 16 A schematic cross-sectional view of another display panel provided by an embodiment of the present invention;

[0037] Figure 17 A schematic diagram of a method for manufacturing a display panel provided by an embodiment of the present invention;

[0038] Figure 18 A schematic diagram of the positional relationship of a first-type first wiring, a first-type second wiring, a third wiring, and a fourth wiring provided in an embodiment of the present invention;

[0039] Figure 19 A schematic diagram of a display device provided by an embodiment of the present invention. [Specific implementation method]

[0040] For better understanding of the technical solutions of the present application, the embodiments of the present application are described in detail below in conjunction with the drawings.

[0041] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0042] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0043] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0044] It should be understood that although the terms first, second, third, etc. may be used to describe the wires in the embodiments of the present application, these wires should not be limited to these terms. These terms are only used to distinguish the wires from each other. For example, the first wire can also be referred to as the second wire without departing from the scope of the embodiments of the present application, and similarly, the second wire can also be referred to as the first wire.

[0045] The embodiments of the present application provide a display panel, such as Figure 1 as shown, Figure 1 A schematic diagram of a display panel provided by the embodiments of the present application is shown in FIG. 1. The display panel 100 includes a display area AA and a non-display area NA. The display area AA includes a plurality of pixel units 1. The pixel unit 1 includes a plurality of sub-pixels. The sub-pixel includes a pixel driving circuit 11 and a light emitting element (not shown) electrically connected. Figure 1

[0046] Exemplarily, as shown in FIG. 2, Figure 2 Figure 2 ​​Schematic diagram of an equivalent circuit of a sub-pixel provided in an embodiment of the present invention. The pixel driving circuit 11 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C. Optionally, the fourth transistor T4, the fifth transistor T5, or the seventh transistor T7 may be a dual-gate transistor. The fifth transistor T5 and the seventh transistor T7 may be electrically connected to the same reference voltage signal line to receive the same reference voltage, or may be electrically connected to different reference voltage signal lines to receive different reference voltages.

[0047] like Figure 1 As shown, the display area AA further includes a first scan line S1, a second scan line S2, a light emitting control signal line E, a data line Data, a first power supply voltage line PVDD, a second power supply voltage line ( Figure 1 not shown) and a reference voltage signal line Vref.

[0048] Combine Figure 2 As shown, the control terminal of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3; the control terminal of the first transistor T1 is electrically connected to the light emitting control signal line E, and the first terminal of the first transistor T1 is electrically connected to the first power supply voltage line PVDD; the control terminal of the second transistor T2 is electrically connected to the second scan line S2, and the first terminal of the second transistor T2 is electrically connected to the data line Data; the second terminal of the first transistor T1 and the second terminal of the second transistor T2 are both electrically connected to the second node N2; the control terminal of the fourth transistor T4 is electrically connected to the second scan line S2; the first terminal of the fourth transistor T4 is electrically connected to the third node N3 is electrically connected to the first node N1, the second end of the fourth transistor T4 is electrically connected to the first node N1; the control end of the fifth transistor T5 is electrically connected to the first scan line S1; the first end of the fifth transistor T5 is electrically connected to the reference voltage signal line Vref; the second end of the fifth transistor T5 is electrically connected to the first node N1; the control end of the sixth transistor T6 is electrically connected to the light emitting control signal line E, the first end of the sixth transistor T6 is electrically connected to the third node N3, and the second end of the sixth transistor T6 is electrically connected to the fourth node N4; the control end of the seventh transistor T7 is electrically connected to the second scan line S2, the first end of the seventh transistor T7 is electrically connected to the reference voltage signal line Vref, and the second end of the seventh transistor T7 is electrically connected to the fourth node N4. The first electrode of the light emitting element 12 is electrically connected to the fourth node N4, and the second electrode is electrically connected to the second power supply voltage line PVEE. The first plate of the storage capacitor C is electrically connected to the first power supply voltage line PVDD, and the second plate of the storage capacitor C is electrically connected to the first node N1.

[0049] When the pixel driving circuit 11 is working, Figure 2and Figure 3 As shown, Figure 3 This is a schematic diagram of the working timing of a pixel driving circuit provided by an embodiment of the present invention. The working process of the pixel driving circuit includes a reset phase t1, a charging phase t2 and a light emitting phase t3.

[0050] In the reset phase t1 , the first scan line S1 controls the fifth transistor T5 and the seventh transistor T7 to be turned on, and the reference voltage provided by the reference voltage signal line Vref resets the first node N1 and the fourth node N4 through the fifth transistor T5 and the seventh transistor T7 .

[0051] In the charging phase t2, the second scan line S2 controls the second transistor T2 and the fourth transistor T4 to be turned on, and the data voltage V provided by the data line Data is data The second node N2 is written through the second transistor T2. At this stage, the third transistor T3 is turned on. The potential of the first node N1 changes continuously until the potential of the first node N1 reaches V N1 Change to V N1 =V data -|V th |, V data is the data voltage provided by the data line Data, V th is the threshold voltage of the third transistor T3.

[0052] In the light-emitting stage t3, the first transistor T1, the sixth transistor T6 and the third transistor T3 are turned on. Under the action of the first power supply voltage provided by the first power supply voltage line PVDD and the second power supply voltage provided by the second power supply voltage line PVEE, the current path between the first power supply voltage line PVDD and the second power supply voltage line PVEE is turned on, and the light-emitting element 12 electrically connected to the pixel driving circuit 11 is lit.

[0053] Optional, such as Figure 1 As shown, the first scan line S1, the second scan line S2, and the light-emission control signal line E all extend along the first direction h1, and multiple first scan lines S1, second scan lines S2, and light-emission control signal lines E are arranged along the second direction h2. One first scan line S1 is electrically connected to multiple pixel driving circuits 11 arranged along the first direction h1. One second scan line S2 is electrically connected to multiple pixel driving circuits 11 arranged along the first direction h1. One light-emission control signal line E is electrically connected to multiple pixel driving circuits 11 arranged along the first direction h1. Data lines Data extend along the second direction h2, and multiple data lines Data are arranged along the first direction h1. One data line Data is electrically connected to multiple pixel driving circuits 11 arranged along the second direction h2.

[0054] Exemplarily, in the embodiment of the present application, the first power supply voltage, the second power supply voltage and the reference voltage required for the operation of the different pixel driving circuits 11 can be the same. That is, the first power supply voltage transmitted by the first power supply voltage line PVDD, the second power supply voltage transmitted by the second power supply voltage line PVEE and the reference voltage transmitted by the reference voltage signal line Vref can be common signals shared by the plurality of pixel driving circuits 11.

[0055] In the embodiment of the present application, optionally, at least one of the first scan line S1, the second scan line S2, the light-emitting control signal line E and the data line Data includes the first wiring. Figure 1 An example in which the data line Data includes the first wiring 21.

[0056] In the embodiment of the present application, the first wiring 21 includes the first wiring of the first type and / or the first wiring of the second type. As shown in Figure 1 An example in which the first wiring of the first type 211 and the first wiring of the second type 212 are arranged in the display area AA. The first wiring of the first type 211 includes the first sub-wiring 2111 and the second sub-wiring 2112 arranged at intervals. The arrangement at intervals means that there is a gap G between the first sub-wiring 2111 and the second sub-wiring 2112. That is, the first sub-wiring 2111 and the second sub-wiring 2112 are disconnected at the interval position, and the signal of one of the first sub-wiring 2111 and the second sub-wiring 2112 cannot be transmitted to the other at the interval position. Exemplarily, the first wiring of the first type 211 can be an abnormal wiring including a breakpoint due to a process, and the gap between the first sub-wiring 2111 and the second sub-wiring 2112 can be the breakpoint due to the process. The first wiring of the second type 212 is the first wiring 21 arranged continuously without including a breakpoint in the display area AA.

[0057] As shown in Figure 1 The display area AA further includes a plurality of second wirings 22. In the embodiment of the present application, the second wiring 22 includes the second wiring of the first type and / or the second wiring of the second type. As shown in Figure 1 An example in which the second wiring of the first type 221 and the second wiring of the second type 222 are arranged in the display area AA. Specifically, the second wiring of the first type 221 is electrically connected to the first wiring of the first type 211, and the signals transmitted by the second wiring of the first type 221 and the first wiring of the first type 211 electrically connected to each other are the same. The second wiring of the second type 222 is used to transmit the first common signal. The first common signal includes any one of the first power supply voltage, the second power supply voltage and the reference voltage.

[0058] Specifically, continuing to refer to Figure 1The non-display area NA includes at least one third wiring 23 and at least one fourth wiring 24. Along the extension direction of the first wiring 21, the third wiring 23 and the fourth wiring 24 are respectively located on both sides of the first wiring 21. For the first type of first wiring 211, the first sub-wiring 2111 and the second sub-wiring 2112 are arranged at intervals between the third wiring 23 and the fourth wiring 24. The second type of first wiring 212 is arranged continuously between the third wiring 23 and the fourth wiring 24.

[0059] As shown in Figure 1 , the third wiring 23 includes a first repair line 231, and the fourth wiring 24 includes a second repair line 241. The first sub-wiring 2111 and the second sub-wiring 2112 are electrically connected through the first repair line 231, the first type of second wiring 221, and the second repair line 241. Among them, the electrical connection means that after any one of the first sub-wiring 2111, the second sub-wiring 2112, the first repair line 231, the first type of second wiring 221, and the second repair line 241 is turned on, the electrical signal can be transmitted to the other wiring. That is, the electrical signal can form a current path between the first sub-wiring 2111, the second sub-wiring 2112, the first repair line 231, the first type of second wiring 221, and the second repair line 241. For example, the first repair line 231 can be in contact with the first sub-wiring 2111 and the first type of second wiring 221 respectively, and the second repair line 241 can be in contact with the second sub-wiring 2112 and the first type of second wiring 221 respectively.

[0060] For example, as shown in Figure 4 , Figure 4 , another schematic diagram of a display panel provided by the embodiment of the present application is shown, wherein the first wiring 21 only includes the first type of first wiring 211 as an example. For example, as shown in Figure 4 , each second wiring 22 is a first type of second wiring 221 electrically connected to the corresponding first type of first wiring 211.

[0061] As shown in Figure 4 , the third wiring 23 includes a plurality of first repair lines 231, and the plurality of first repair lines 231 are arranged at intervals. Different first repair lines 231 are electrically connected to different first sub-wirings 2111. The fourth wiring 24 includes a plurality of second repair lines 241, and the plurality of second repair lines 241 are arranged at intervals. Different second repair lines 241 are electrically connected to different second sub-wirings 2112.

[0062] For example, as shown in Figure 5 , Figure 5 , another schematic diagram of a display panel provided by the embodiment of the present application is shown, wherein the first wiring 21 only includes the first type of first wiring 211 as an example. As Figure 4The difference is that, in Figure 5 the second wiring 22 includes the second wiring 221 of the first type electrically connected with the first wiring 21 of the first type, and further includes the second wiring 222 of the second type for transmitting the first common signal. For example, the number of the second wiring 221 of the first type can be the same as the number of the first wiring 21, i.e., the number of the second wiring 221 of the first type is the same as the number of the first wiring 211 of the first type.

[0063] For example, as shown in Figure 6 , Figure 6 a schematic diagram of another display panel provided by the embodiment of the present application is shown, in which only the second wiring 212 of the first type arranged continuously between the third wiring 23 and the fourth wiring 24 is included in the first wiring 21. In Figure 6 , the second wiring 22 only includes the second wiring 222 of the second type for transmitting the first common signal, i.e., each second wiring 22 is not connected with the first wiring 21.

[0064] In the manufacturing of the display panel, each signal line including the first wiring 21 can be formed in the display panel first, and then it is checked whether the first wiring 211 of the first type exists in the first wiring 21. When the first wiring 211 of the first type exists, the embodiment of the present application can set a repair step in the manufacturing process of the display panel. In the repair step, the first sub-wiring 2111 in the first wiring 211 of the first type can be electrically connected with the second sub-wiring 2112 in the first wiring 211 of the first type through the first repair line 231, the second wiring 221 of the first type and the second repair line 241, so as to ensure that the pixel driving circuit 11 connected with the first sub-wiring 2111 and the second sub-wiring 2112 can normally receive the required signal, and the situation that the sub-pixel cannot be lighted or is abnormally lighted can be avoided, and the display quality of the display panel can be improved.

[0065] In addition to the second wiring 221 of the first type for repair, the embodiment of the present application can further set the second wiring 222 of the second type for transmitting the first common signal in the second wiring 22, and the setting of the second wiring 222 of the second type can increase the transmission path of the first common signal, which is beneficial to reduce the voltage drop loss of the first common signal in the transmission process and improve the brightness uniformity of the display panel.

[0066] The display panel provided by the embodiment of the present application can set the second wiring 22, the third wiring 23 and the fourth wiring 24 in the display panel, set the first type first wiring 221 in the second wiring 22, set the first repair line 231 in the third wiring 23, and set the second repair line 241 in the fourth wiring 24 to repair the first type first wiring 211 when the first wiring 21 comprises the first type first wiring 211. Specifically, the first sub-wiring 2111 and the second sub-wiring 2112 can be electrically connected through the first repair line 231, the first type second wiring 221 and the second repair line 241, so as to ensure the normal work of the pixel driving circuit 11 connected by the first sub-wiring 2111 and the second sub-wiring 2112.

[0067] In addition, the embodiment of the present application can set the second type second wiring 222 in the second wiring 22 to transmit the first common signal, so as to reduce the voltage drop loss of the first common signal in the transmission process and improve the brightness uniformity of the display panel.

[0068] It should be noted that, Figure 2 the structure of the pixel driving circuit and Figure 3 the working timing of the pixel driving circuit is only an example, and the embodiment of the present application can also design the pixel driving circuit in other forms. For example, the pixel driving circuit 11 can be designed in the form of 2T1C including two thin film transistors and one storage capacitor, and the like, and the embodiment of the present application does not limit the specific structure of the pixel driving circuit 11 and the working timing thereof.

[0069] For example, Figure 1 , Figure 4 and Figure 5 the first wiring 21 comprises the first type first wiring 211; the first sub-wiring 2111 is located on the side of the second sub-wiring 2112 close to the first repair line 231, and the second sub-wiring 2112 is located on the side of the first sub-wiring 2111 close to the second repair line 241.

[0070] In the embodiment of the present application, in the non-display area NA, at least one of the first sub-wiring 2111 and the first type second wiring 221 overlaps with the first repair line 231 along the thickness direction h3 of the display panel 100; and / or, at least one of the second sub-wiring 2112 and the first type second wiring 221 overlaps with the second repair line 241. For example, the thickness direction h3 of the display panel is perpendicular to the first direction h1 and the second direction h2.

[0071] For example, Figure 1 , Figure 4 and Figure 5The diagram shows a diagram illustrating that, along the thickness direction h3 of the display panel 100, both the first sub-wiring 2111 and the first-type second-wiring 221 overlap with the first repair line 231; and both the second sub-wiring 2112 and the first-type second-wiring 221 overlap with the second repair line 241. In this embodiment of the present invention, by overlapping at least one of the first sub-wiring 2111 and the first-type second-wiring 221 with the first repair line 231 and / or overlapping at least one of the second sub-wiring 2112 and the first-type second-wiring 221 with the second repair line 241, the first repair line 231 can be more conveniently electrically connected to the first sub-wiring 2111 and the first-type second-wiring 221, respectively, and the second repair line 241 can be more conveniently electrically connected to the first-type second-wiring 221.

[0072] For example, Figure 1 As shown, the non-display area NA also includes a pad area PA, and the pad area PA includes a first pad 31 electrically connected to the first wiring 21; optionally, the first pad 31 can be bound and connected to a driver chip (not shown) to receive a drive signal provided by the driver chip. In an embodiment of the present invention, the first sub-wiring 2111 and the second sub-wiring 2112 are electrically connected to the same first pad 31. With this setting, the number of first pads 31 can be reduced. When repairing the first type of first wiring 211 with a breakpoint, there is no need to additionally set a repair pad electrically connected to the first type of second wiring 211. On the one hand, the number of required pads can be reduced, and on the other hand, it is also beneficial to reduce the requirements for the driver chip and reduce the cost of the driver chip. Exemplarily, the first type of first wiring 211 and the second type of first wiring 212 can be electrically connected to different first pads 31.

[0073] like Figure 1 、 Figure 4 、 Figure 5 and Figure 6 As shown, the non-display area NA further includes a first common signal bus 61, and the pad area PA further includes a second pad 32. In the non-display area NA, the second-type second wiring 222 is electrically connected to the second pad 32 via the first common signal bus 61. For example, when the first common signal is any one of the first power supply voltage, the second power supply voltage, and the reference voltage, based on the configuration provided in the embodiments of the present invention, it is not necessary to electrically connect the second-type second wiring 222 to the routing lines transmitting the aforementioned signals in the display area AA, thereby avoiding increasing the wiring complexity within the display area AA.

[0074] For example, the first common signal bus 61 may at least partially surround the display area AA. Figure 1 、 Figure 4 、 Figure 5 and Figure 6In the example shown in FIG. 1, one first common signal bus 61 is arranged on each side of the display area AA along the second direction h2.

[0075] As shown in Figure 1 , Figure 5 and Figure 6 , the second wiring 22 includes a plurality of second wiring of the second type 222. The arrangement of the plurality of second wiring of the second type 222 can increase the transmission path of the first common signal, which is conducive to further reducing the voltage drop loss of the first common signal.

[0076] As shown in Figure 1 , Figure 4 and Figure 5 , the third wiring 23 further includes a first functional line 232 arranged apart from the first repair line 231, and the first functional line 232 and the first repair line 231 are insulated from each other. The fourth wiring 24 further includes a second functional line 242 arranged apart from the second repair line 241, and the second functional line 242 and the second repair line 241 are insulated from each other. Optionally, at least one of the first functional line 232 and the second functional line 242 transmits a second common signal. As an example, the second common signal includes any one of a first power supply voltage, a second power supply voltage, and a reference voltage. With the above arrangement, it is conducive to reducing the voltage drop of the second common signal and improving the brightness consistency of the display panel. Moreover, based on the arrangement, the space of the non-display area NA where the first repair line 231 and the second repair line 241 are located can be fully utilized.

[0077] As shown in Figure 1 , Figure 4 and Figure 5 , the non-display area NA further includes a second common signal bus 62, and the first functional line 232 and / or the second functional line 242 are electrically connected to the second common signal bus 62.

[0078] Optionally, in the manufacturing process of the display panel, the third and fourth wirings 23 and 24 with a relatively long length can be formed first, and at least one of the third and fourth wirings 23 and 24 is connected to the second common signal bus 62. After detecting that the first wiring 21 includes the first-type first wiring 211, the third wiring 23 can be cut to obtain the first repair wiring 231 and the first functional wiring 232 which are insulated from each other, wherein the connection between the first repair wiring 231 and the second common signal bus 62 is disconnected, and at least part of the first functional wiring 232 remains connected to the second common signal bus 62. The first repair wiring 231 is connected to the first-type first wiring 211 and the first-type second wiring 221 respectively. That is, in the embodiment of the present application, the first functional wiring 232 and the first repair wiring 231 can be formed by the same process. Similarly, after detecting that the first wiring 21 includes the first-type first wiring 211, the fourth wiring 24 can also be cut to obtain the second repair wiring 241 and the second functional wiring 242 which are insulated from each other, wherein the connection between the second repair wiring 241 and the second common signal bus 62 is disconnected, and at least part of the second functional wiring 242 remains connected to the second common signal bus 62. The second repair wiring 241 is connected to the first-type first wiring 211 and the first-type second wiring 221 respectively. That is, in the embodiment of the present application, the second functional wiring 242 and the second repair wiring 241 can be formed by the same process.

[0079] Figure 1 、 Figure 4 、 Figure 5 and Figure 6 is a schematic view of arranging two second common signal buses 62 on opposite sides of the display area AA along the first direction h1. In Figure 1 , the first repair wiring 231 is located between the two first functional wirings 232, and both of the first functional wirings 232 are connected to the second common signal bus 62. The second repair wiring 241 is located between the two second functional wirings 242, and both of the second functional wirings 242 are connected to the second common signal bus 62.

[0080] When the second wiring 22 includes a plurality of first-type second wirings 221, as shown in Figure 4 and Figure 5 , the third wiring 23 includes a plurality of first repair wirings 231, and the fourth wiring 24 includes a plurality of second repair wirings 241. Different first repair wirings 231 are insulated from each other, and different second repair wirings 241 are insulated from each other. As shown in Figure 4 and Figure 5As shown, along the extending direction of the third wiring 23, the first functional lines 232 and the first repair lines 231 are arranged alternately. Two first functional lines 232 arranged near the two ends of the third wiring 23 are connected with the second common signal bus 62, and the rest of the first functional lines 232 are floating. Along the extending direction of the fourth wiring 24, the second functional lines 242 and the second repair lines 241 are arranged alternately. Two second functional lines 242 arranged near the two ends of the fourth wiring 24 are connected with the second common signal bus 62, and the rest of the second functional lines 242 are floating. When the display panel 100 is working, the floating first functional lines 232 and the floating second functional lines 242 can not receive electrical signals.

[0081] When it is detected that the first wiring 21 does not include the first type of first wiring 211, the embodiment of the present application can not cut the third wiring 23 and the fourth wiring 24, and does not form the above-mentioned first repair line in the third wiring 23 and does not form the above-mentioned second repair line in the fourth wiring 24. In this case, as shown in FIG. 6, the third wiring 23 is the first functional line 232, and the fourth wiring 24 is the second functional line 242. The two ends of the third wiring 23 are connected with the second common signal bus 62. The two ends of the fourth wiring 24 are connected with the second common signal bus 62. Figure 6

[0082] The embodiment of the present application can reduce the voltage drop of the second common signal in the transmission process by arranging the first functional line 232 for transmitting the second common signal, which is beneficial to improve the brightness consistency of the display panel. Moreover, the embodiment of the present application can improve the process efficiency of the display panel by making the first functional line 232 and the first repair line 231 both obtained by cutting the third wiring 23, and / or making the second functional line 242 and the second repair line 241 both obtained by cutting the fourth wiring 24.

[0083] For example, as shown in FIG. 5, Figure 7 Figure 7 For another example, as shown in FIG. 6, Figure 7 As shown in FIG. 5, the third sub-wiring 2113 and the first sub-wiring 2111 are spaced apart by a first gap G1, and the third sub-wiring 2113 and the second sub-wiring 2112 are spaced apart by a second gap G2. The first gap G1 and the second gap G2 can be a breakpoint caused by process reasons.

[0084] Figure 7 ​​​As shown, the display area AA further includes a third repair line 4 connected with the third sub-wiring 2113 and the second type second wiring 222 respectively. Based on the setting mode provided by the embodiment of the present application, the third sub-wiring 2113 can be electrically connected with the first sub-wiring 2111 and the second sub-wiring 2112 through the third repair line 4, thereby ensuring the normal operation of the pixel driving circuit 11 connected with the third sub-wiring 2113.

[0085] As shown, the first type first wiring 211 and the first type second wiring 221 electrically connected therewith have a distance d1 less than or equal to the shortest distance d2 between the first type first wiring 211 and any second wiring 222. That is, the first type second wiring 221 electrically connected with the first type first wiring 211 is the second wiring 222 closest to the first type first wiring 211. In this way, the transmission path of the signal in the first type first wiring 211 can be shortened, thereby reducing the voltage drop loss of the signal transmitted by the first wiring 21 during transmission. Figure 1 As shown, the first type first wiring 211 and the first type second wiring 221 electrically connected therewith have a distance d1 less than or equal to the shortest distance d2 between the first type first wiring 211 and any second wiring 222. That is, the first type second wiring 221 electrically connected with the first type first wiring 211 is the second wiring 222 closest to the first type first wiring 211. In this way, the transmission path of the signal in the first type first wiring 211 can be shortened, thereby reducing the voltage drop loss of the signal transmitted by the first wiring 21 during transmission.

[0086] Figure 1 As shown, the first type first wiring 211 and the first type second wiring 221 electrically connected therewith have a distance d1 less than or equal to the shortest distance d2 between the first type first wiring 211 and any second wiring 222. That is, the first type second wiring 221 electrically connected with the first type first wiring 211 is the second wiring 222 closest to the first type first wiring 211. In this way, the transmission path of the signal in the first type first wiring 211 can be shortened, thereby reducing the voltage drop loss of the signal transmitted by the first wiring 21 during transmission.

[0087] As shown, the first type first wiring 211 and the first type second wiring 221 electrically connected therewith have a distance d1 less than or equal to the shortest distance d2 between the first type first wiring 211 and any second wiring 222. That is, the first type second wiring 221 electrically connected with the first type first wiring 211 is the second wiring 222 closest to the first type first wiring 211. In this way, the transmission path of the signal in the first type first wiring 211 can be shortened, thereby reducing the voltage drop loss of the signal transmitted by the first wiring 21 during transmission. Figure 8 Figure 8 As shown, the first type first wiring 211 and the first type second wiring 221 electrically connected therewith have a distance d1 less than or equal to the shortest distance d2 between the first type first wiring 211 and any second wiring 222. That is, the first type second wiring 221 electrically connected with the first type first wiring 211 is the second wiring 222 closest to the first type first wiring 211. In this way, the transmission path of the signal in the first type first wiring 211 can be shortened, thereby reducing the voltage drop loss of the signal transmitted by the first wiring 21 during transmission. Figure 1 As shown, the first type first wiring 211 and the first type second wiring 221 electrically connected therewith have a distance d1 less than or equal to the shortest distance d2 between the first type first wiring 211 and any second wiring 222. That is, the first type second wiring 221 electrically connected with the first type first wiring 211 is the second wiring 222 closest to the first type first wiring 211. In this way, the transmission path of the signal in the first type first wiring 211 can be shortened, thereby reducing the voltage drop loss of the signal transmitted by the first wiring 21 during transmission.

[0088] The film layer structure of the display panel provided by the embodiment of the present application will be described below in combination with Figure 9 and Figure 10 The wiring diagram of a display panel provided by the embodiment of the present application is shown in Figure 9 The wiring diagram of a display panel provided by the embodiment of the present application is shown in Figure 10 The wiring diagram of a display panel provided by the embodiment of the present application is shown in Figure 9 ​​A cross-sectional view along BB' is shown in Figure 9 Fig. 2, showing two pixel driving circuit groups 110 arranged along a second direction h2, and four pixel driving circuits 11 arranged along a first direction hi in each pixel driving circuit group 110. Each pixel driving circuit 11 can have a circuit structure as shown in Figure 2 Fig. 3.

[0089] As shown in Figure 10 Fig. 4, the display panel 100 includes a substrate 500, a semiconductor layer S, a first insulating layer IS1, a first metal layer M1, a second insulating layer IS2, a second metal layer M2, a third insulating layer IS3, a third metal layer M3, a fourth insulating layer IS4, and a fourth metal layer M4. The semiconductor layer S is located on one side of the substrate 500, the first insulating layer IS1 is located on the side of the semiconductor layer S away from the substrate 500, the first metal layer M1 is located on the side of the first insulating layer IS1 away from the semiconductor layer S, the second insulating layer IS2 is located on the side of the first metal layer M1 away from the semiconductor layer S, the second metal layer M2 is located on the side of the second insulating layer IS2 away from the first metal layer M1, the third insulating layer IS3 is located on the side of the second metal layer M2 away from the second insulating layer IS2, the third metal layer M3 is located on the side of the third insulating layer IS3 away from the second metal layer M2, the fourth insulating layer IS4 is located on the side of the third metal layer M3 away from the third insulating layer IS3, and the fourth metal layer M4 is located on the side of the fourth insulating layer IS4 away from the third metal layer M3.

[0090] For example, as shown in Figure 9 , Figure 10 and Figure 11 Figure 11 ​A top view of a semiconductor layer is provided in an embodiment of the present application. The semiconductor layer S includes a first channel region S10, a first doped region S11 and a second doped region S12 located on two sides of the first channel region S10, a second channel region S20, a third doped region S21 and a fourth doped region S22 located on two sides of the second channel region S20, a third channel region S30, a fifth doped region S31 and a sixth doped region S32 located on two sides of the third channel region S30, a fourth channel region S40, a seventh doped region S41 and an eighth doped region S42 located on two sides of the fourth channel region S40, a fifth channel region S50, a ninth doped region S51 and a tenth doped region S52 located on two sides of the fifth channel region S50, a sixth channel region S60, an eleventh doped region S61 and a twelfth doped region S62 located on two sides of the sixth channel region S60, and a seventh channel region S70, a thirteenth doped region S71 and a fourteenth doped region S72 located on two sides of the seventh channel region S70. One of the two doped regions located on two sides of each channel region is a source region, and the other is a drain region. Impurities are doped in the source region and the drain region. The impurities include P-type impurities or N-type impurities. For example, the semiconductor layer S includes any one or more of low-temperature polysilicon, amorphous silicon, and oxide semiconductor layers.

[0091] As shown in Figure 9 and Figure 11 , the semiconductor layer S further includes a reference voltage signal line Vref. For example, the reference voltage signal line Vref is connected to the ninth doped region S51 and the thirteenth doped region S71, respectively. In this way, compared with using a metal layer to form the reference voltage signal line Vref, it is beneficial to reduce the leakage current of the fifth transistor T5 and the seventh transistor T7 electrically connected to the gate of the third transistor T3.

[0092] As shown in Figure 9 and Figure 12 , the semiconductor layer S further includes a reference voltage signal line Vref. For example, the reference voltage signal line Vref is connected to the ninth doped region S51 and the thirteenth doped region S71, respectively. In this way, compared with using a metal layer to form the reference voltage signal line Vref, it is beneficial to reduce the leakage current of the fifth transistor T5 and the seventh transistor T7 electrically connected to the gate of the third transistor T3. Figure 12 A top view of a first metal layer is provided in an embodiment of the present application. The first metal layer M1 includes the above-mentioned light-emitting control signal line E, a first plate C1 of a storage capacitor C, a gate G2 of the second transistor T2, a gate G4 of the fourth transistor T4, a gate G5 of the fifth transistor T5, and a gate G7 of the seventh transistor T7. The gate G2 of the second transistor T2 and the gate G4 of the fourth transistor T4 are connected.

[0093] As shown in Figure 11 and Figure 12As shown, along the thickness direction h3 of the display panel, the gate G2 of the second transistor T2 overlaps with the second channel region S20. The gate G4 of the fourth transistor T4 overlaps with the fourth channel region S40. The gate G5 of the fifth transistor T5 overlaps with the fifth channel region S50. The gate G7 of the seventh transistor T7 overlaps with the seventh channel region S70. The portions of the light-emitting control signal line E that overlap with the first channel region S10 and the sixth channel region S60 respectively form the gate G1 of the first transistor T1 and the gate G6 of the sixth transistor T6. The portion of the first plate C1 of the storage capacitor C that overlaps with the third channel region S30 forms the gate G3 of the third transistor T3.

[0094] Combine Figure 9 and Figure 13 As shown, Figure 13 This is a schematic top view of a second metal layer provided in an embodiment of the present invention. The second metal layer M2 includes a second electrode plate C2 of a storage capacitor C.

[0095] Combine Figure 9 and Figure 14 As shown, Figure 14 The third metal layer M3 is a top view of a third metal layer according to an embodiment of the present invention. The third metal layer M3 includes a first scan line S1, a second scan line S2, and a first sub-power voltage line PVDD1. The first sub-power voltage line PVDD1 is used to transmit the first power voltage.

[0096] Combine Figure 9 、 Figure 11 and Figure 14 As shown, in the third metal layer M3, two first scan lines S1 are provided corresponding to one pixel driving circuit group 110, wherein one first scan line S1 overlaps with the fifth channel region S50 in the semiconductor layer S in the thickness direction h3 of the display panel, and the region where the first scan line S1 overlaps with the fifth channel region S50 forms another gate of the fifth transistor. Figure 12 As shown, the first scanning line S1 passes through the second insulating layer ( Figure 14 Not shown) and the third insulating layer ( Figure 14 The first via hole K1 (not shown) is electrically connected to the gate G5 of the fifth transistor T5 located in the first metal layer M1. Figure 14 In other related drawings, the positions of the first via hole K1 and other via holes are indicated by dotted lines.

[0097] Combine Figure 9 、 Figure 12 and Figure 14As shown, another first scan line S1 overlaps with the gate G7 of the seventh transistor T7 located in the first metal layer M1 in the thickness direction h3 of the display panel, and the first scan line S1 is electrically connected with the gate G7 of the seventh transistor T7 located in the first metal layer M1 through the second via K2 penetrating the second insulating layer and the third insulating layer.

[0098] As shown, Figure 12 and Figure 14 As shown, the second scan line S2 located in the third metal layer M3 is electrically connected with the gate G2 of the second transistor T2 and the gate G4 of the fourth transistor T4 located in the first metal layer M1 through the third via K3 penetrating the second insulating layer and the third insulating layer.

[0099] As shown, Figure 9 and Figure 15 As shown, Figure 15 is a top view schematic diagram of a fourth metal layer provided by an embodiment of the present application, the fourth metal layer M4 includes a data line Data and a second sub power voltage line PVDD2. The second sub power voltage line PVDD2 intersects with the extension direction of the first sub power voltage line PVDD1. And, the second sub power voltage line PVDD2 is used to transmit the first power voltage.

[0100] As shown, Figure 9 and Figure 14 As shown, the third metal layer M3 further includes a first connecting part X1. As shown, Figure 15 As shown, the data line Data located in the fourth metal layer M4 is electrically connected with one end of the first connecting part X1 through the fourth via K4 penetrating the fourth insulating layer (not shown).

[0101] As shown, Figure 9 , Figure 11 and Figure 14 As shown, the other end of the first connecting part X1 is electrically connected with the third doped region S21 in the semiconductor layer S through the fifth via K5 penetrating the third insulating layer (not shown), the second insulating layer (not shown) and the first insulating layer (not shown), so as to transmit the data voltage to the source or the drain of the second transistor T2.

[0102] As shown, Figure 10 and Figure 14 As shown, the second sub power voltage line PVDD2 located in the fourth metal layer M4 is electrically connected with the first sub power voltage line PVDD1 located in the third metal layer M3 through the sixth via K6 penetrating the fourth insulating layer (not shown). Figure 14 (not shown).

[0103] As shown, Figure 11 and Figure 13As shown, the first sub power voltage line PVDD1 located at the third metal layer M3 is electrically connected with the first doped region S11 located at the semiconductor layer S through a seventh via hole K7 penetrating through the third insulating layer (not shown), the second insulating layer (not shown) and the first insulating layer (not shown), so as to transmit the first power voltage to the source or the drain of the first transistor T1.

[0104] As shown in Figure 14 , the third metal layer M3 further comprises a second connecting part X2. In combination with Figure 8 and Figure 14 , one end of the second connecting part X2 is electrically connected with the seventh doped region S41 and the tenth doped region S52 located at the semiconductor layer S through an eighth via hole K8 penetrating through the third insulating layer (not shown), the second insulating layer (not shown) and the first insulating layer (not shown).

[0105] In combination with Figure 12 and Figure 14 , the other end of the second connecting part X2 is electrically connected with the first plate C1 of the capacitor C located at the first metal layer M1 through a ninth via hole K9 penetrating through the third insulating layer, the second metal layer and the second insulating layer, wherein the part of the first plate C1 overlapping with the third channel region S30 is reused as the gate G3 of the third transistor T3.

[0106] In combination with Figure 13 , the second plate C2 of the capacitor C located at the second metal layer M2 comprises an opening O, and the ninth via hole K9 and the opening O overlap along the thickness direction h3 of the display panel.

[0107] Exemplarily, the area of the opening O is greater than or equal to the area of the ninth via hole K9, Figure 13 and the area of the opening O is greater than the area of the ninth via hole K9 as an example. The normal projection of the ninth via hole K9 on the plane where the substrate is located is located in the opening O.

[0108] In combination with Figure 9 , Figure 13 and Figure 14 , the first sub power voltage line PVDD1 located at the third metal layer M3 is electrically connected with the second plate C12 of the capacitor C located at the second metal layer M2 through a tenth via hole K10 penetrating through the third insulating layer (not shown).

[0109] Optionally, in the embodiment of the present application, the first wiring 21 and the second wiring 22 can be arranged in the same layer to simplify the manufacturing process of the display panel.

[0110] Exemplarily, when the data line Data comprises the first wiring 21, as shown in Figure 9 and Figure 15 , the fourth metal layer M4 further comprises the second wiring 22 arranged in the same layer as the first wiring 21.

[0111] As shown in Figure 1 , Figure 9 and Figure 15 , the first wiring 21 and the second wiring 22 do not overlap in the thickness direction h3 of the display panel.

[0112] Optionally, in combination with Figure 7 and Figure 16 , Figure 16 Another cross-sectional schematic view of a display panel is provided for an embodiment of the present application. When the display area AA includes a third repair line 4, the third repair line 4 is located on the side of the first wiring 21 away from the substrate 500. Figure 16 To set the third sub-wiring 2113 and the first type of second wiring 221 in the fourth metal layer M4, the third repair line 4 is set in the fifth metal layer M5, which is located on the side of the fourth metal layer M4 away from the substrate 500. The fifth insulating layer IS5 is included between the fourth metal layer M4 and the fifth metal layer M5. The third repair line 4 is electrically connected to the third sub-wiring 2113 and the first type of second wiring 221 through two through holes KK penetrating the fifth insulating layer IS5. In this way, the influence on the existing wiring in the display area AA is reduced.

[0113] The present application also provides a display panel manufacturing method. In combination with Figure 1 and Figure 17 , Figure 17 A display panel manufacturing method is provided for an embodiment of the present application. The display panel includes a display area AA and a non-display area NA. The manufacturing method includes:

[0114] Step S1: Forming a pixel driving circuit 11, a first scan line S1, a second scan line S2, a light-emitting control signal line E, a first power voltage line PVDD, a second power voltage line, a reference voltage signal line Vref, a data line Data, and a plurality of second wirings 22 in the display area AA. At least one of the first scan line S1, the second scan line S2, the light-emitting control signal line E, the data line Data includes the first wiring 21. At least one third wiring 23 and at least one fourth wiring 24 are formed in the non-display area NA. Along the extension direction of the first wiring 21, the third wiring 23 and the fourth wiring 24 are respectively located on both sides of the first wiring 21.

[0115] Step S2: detecting whether the first wiring 21 includes a first wiring 211 of the first type, which includes a first sub-wiring 2111 and a second sub-wiring 2112 arranged at intervals between the third wiring 23 and the fourth wiring 24. If yes, i.e., if the first wiring 21 includes the first wiring 211 of the first type, step S3 is performed. Optionally, the detection method includes providing respective electrical signals to each signal line in the display panel 100, including the first wiring 21, and detecting whether there are sub-pixels in the display area that cannot be normally lighted. If there are, it indicates that the first wiring 21 connected to these sub-pixels is the first wiring 211 of the first type.

[0116] Step S3: selecting a second wiring 22 as a first wiring 221 of the second type; cutting the third wiring 23 to obtain a first repair line 231, and cutting the fourth wiring 24 to obtain a second repair line 241; and electrically connecting the first sub-wiring 2111 and the second sub-wiring 2112 through the first repair line 231, the first wiring 221 of the second type, and the second repair line 241. Optionally, the electrical connection between the first repair line 231, the first wiring 211 of the first type, and the first wiring 221 of the second type can be achieved by welding. Exemplarily, the cutting process includes laser cutting, and the welding process includes laser welding.

[0117] The preparation method of the display panel provided by the embodiment of the present application can ensure the normal operation of the pixel driving circuit 11 connected to the first sub-wiring 2111 and the second sub-wiring 2112 by arranging the second wiring 22, the third wiring 23, and the fourth wiring 24 in the display panel, arranging the first wiring 221 of the first type in the second wiring 22 when it is detected that the first wiring 21 includes the first wiring 211 of the first type, cutting the third wiring 23 to obtain the first repair line 231, cutting the fourth wiring 24 to obtain the second repair line 241, and electrically connecting the first sub-wiring 2111 and the second sub-wiring 2112 through the first repair line 231, the first wiring 221 of the second type, and the second repair line 241.

[0118] When the display panel includes a plurality of second wirings 22, the first wiring 221 of the second type electrically connected to the first wiring 211 of the first type is exemplarily the second wiring 22 closest to the first wiring 211 of the first type. In this way, when the first sub-wiring 2111 is electrically connected to the second sub-wiring 2112 through the first repair line 231 and the first wiring 221 of the second type, i.e., when the first wiring 211 of the first type is repaired by breaking and connecting through the first wiring 221 of the second type, the transmission path of the signal in the first wiring 211 of the first type can be shortened, which is conducive to reducing the voltage drop loss of the signal transmitted by the first wiring 211 of the first type.

[0119] Exemplarily, the method of forming the plurality of first wirings 21 and the plurality of second wirings 22 in the display area AA, cutting the third wiring 23 to obtain the first repair line 231, and cutting the fourth wiring 24 to obtain the second repair line 241 includes:

[0120] In the non-display area NA, the first repair line 231 is overlapped with at least one of the first wiring 21 and the second wiring 22 in a direction perpendicular to a plane where the display panel is located; and / or, the second repair line 241 is overlapped with at least one of the first wiring 21 and the second wiring 22.

[0121] Optionally, in combination with Figure 1 As shown, the preparation method provided by the embodiment of the present application further includes: forming a first common signal bus 61 in the non-display area NA; and connecting the second wiring 22 except the first type of second wiring 221 as a second type of second wiring 222, and connecting the second type of second wiring 222 with the first common signal bus 61. In this way, the pressure drop loss of the first common signal in the transmission process can be reduced, and the brightness uniformity of the display panel can be improved.

[0122] Optionally, in combination with Figure 1 As shown, the preparation method further includes: forming a second common signal bus 62 in the non-display area NA, the second common signal bus 62 being used for transmitting a second common signal;

[0123] Cutting the third wiring 23 to obtain a first functional line 232, and cutting the fourth wiring 24 to obtain a second functional line 242;

[0124] Connecting the first functional line 232 and the second functional line 242 with the second common signal bus 62, and insulating the first repair line 231 and the second repair line 241 from the second common signal bus 62.

[0125] The first functional line 232 and the second functional line 242 are beneficial to increase the transmission path of the second common signal, reduce the pressure drop of the second common signal, and improve the display uniformity of the display panel. Moreover, by obtaining the first functional line 232 by cutting the third wiring 23 and obtaining the second functional line 242 by cutting the fourth wiring 24, the preparation process of the first repair line 231, the first functional line 232, the second repair line 241 and the second functional line 242 can be simplified, and the process efficiency can be improved.

[0126] Exemplarily, when it is detected that the first wiring 21 does not include the first type of first wiring 211, the embodiment of the present application can not cut the third wiring 23 and the fourth wiring 24, and does not form the first repair line in the third wiring 23 and does not form the second repair line in the fourth wiring 24. In this case, as shown in Figure 6As shown, the third wiring 23 is the first functional line 232, and the fourth wiring 24 is the second functional line 242. Figure 6 As shown, both ends of the third wiring 23 are connected with the second common signal bus 62. Both ends of the fourth wiring 24 are connected with the second common signal bus 62.

[0127] Optionally, in combination with Figure 18 As shown, Figure 18 A first type of first wiring, a first type of second wiring, a third wiring and a fourth wiring provided by the embodiment of the present application are shown in a schematic diagram of a positional relationship. The method of cutting the third wiring 23 to obtain the first repair line 231 comprises:

[0128] A first connection position W1 electrically connected with the first sub-wiring 2111 and a second connection position W2 electrically connected with the first type of second wiring 221 are determined in the third wiring 23. Exemplarily, the first connection position W1 can be a position where the third wiring 23 overlaps with the first sub-wiring 2111 along a thickness direction h3 of the display panel. The second connection position W2 can be a position where the third wiring 23 overlaps with the first type of second wiring 221 along the thickness direction h3 of the display panel. Furthermore, a first cutting point D1 and a second cutting point D2 are determined in the third wiring 23, and the first connection position W1 and the second connection position W2 are both located between the first cutting point D1 and the second cutting point D2. Then, the third wiring 23 is cut at the first cutting point D1 and the second cutting point D2 to obtain the first repair line 231.

[0129] Exemplarily, the first cutting point D1 and / or the second cutting point D2 away from one side of the first repair line 231 is / are the first functional line 232.

[0130] In combination with Figure 17 As shown, the method of cutting the fourth wiring 24 to obtain the second repair line 241 comprises:

[0131] A third connection position W3 electrically connected with the second sub-wiring 2112 and a fourth connection position W4 electrically connected with the first type of second wiring 221 are determined in the fourth wiring 24. Exemplarily, the third connection position W3 can be a position where the fourth wiring 24 overlaps with the second sub-wiring 2112 along a thickness direction h3 of the display panel. The fourth connection position W4 can be a position where the fourth wiring 24 overlaps with the first type of second wiring 221 along the thickness direction h3 of the display panel. Furthermore, a third cutting point D3 and a fourth cutting point D4 are determined in the fourth wiring 24, and the third connection position W3 and the fourth connection position W4 are both located between the third cutting point D3 and the fourth cutting point D4. Then, the fourth wiring 24 is cut at the third cutting point D3 and the fourth cutting point D4 to obtain the second repair line 241.

[0132] For example, the third cutting point D3 is away from one side of the second repair line 241 and / or the fourth cutting point D4 is away from one side of the second repair line 241 is the second functional line 242.

[0133] The embodiment of the present application further provides a display device, such as Figure 19 As shown in the drawings, Figure 19 A schematic diagram of a display device provided by the embodiment of the present application is shown in the drawings, which comprises the display panel 100 described above. The specific structure of the display panel 100 has been described in detail in the above embodiment, which will not be described here again. Of course, Figure 19 The display device shown in the drawings is only for illustrative purposes, and the display device can be any electronic device with display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper or a television.

[0134] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: Including display area and non-display area; The display area includes a plurality of first wirings and a plurality of second wirings; The non-display area includes at least one third wiring and at least one fourth wiring, and along the extension direction of the first wiring, the third wiring and the fourth wiring are respectively located on both sides of the first wiring; The first wiring includes a first-type first wiring, the first-type first wiring includes a first sub-wiring and a second sub-wiring arranged between the third wiring and the fourth wiring; the second wiring includes a first-type second wiring; the third wiring includes a first repair line; the fourth wiring includes a second repair line; the first sub-wiring and the second sub-wiring are electrically connected via the first repair line, the first-type second wiring, and the second repair line; The third wiring further includes a first functional line spaced apart from the first repair line, and the fourth wiring further includes a second functional line spaced apart from the second repair line; At least one of the first functional line and the second functional line transmits a second common signal; and / or, The third wiring further includes a first functional line spaced apart from the first repair line, and the fourth wiring further includes a second functional line spaced apart from the second repair line; The first wiring includes a second-type first wiring, which is continuously arranged between the third wiring and the fourth wiring; the second wiring includes a second-type second wiring, which transmits a first common signal; and at least one of the first functional line and the second functional line transmits a second common signal.

2. The display panel according to claim 1, wherein: The first wiring includes a first type of first wiring; In the non-display area, along the thickness direction of the display panel, at least one of the first-type first wiring and the first-type second wiring overlaps with the first repair line; And / or, at least one of the first-type first wiring and the first-type second wiring overlaps with the second repair line.

3. The display panel according to claim 1, wherein: The first wiring includes the first type of first wiring; The non-display area further includes a pad area, wherein the pad area includes a first pad electrically connected to the first wiring; The first sub wiring and the second sub wiring are electrically connected to the same first pad.

4. The display panel according to claim 1, wherein: The first wiring includes the first type of first wiring; The first type of first wiring further includes a third sub-wiring located between the first sub-wiring and the second sub-wiring, and the third sub-wiring is spaced apart from the first sub-wiring and the second sub-wiring respectively; The display area further includes a third repair line, and the third sub-wiring is electrically connected to the second sub-wiring through the third repair line, the first-type second wiring, and the second repair line.

5. The display panel according to claim 4, wherein: The display panel includes a substrate, and the third repair line is located on a side of the first wiring away from the substrate.

6. The display panel according to claim 1, wherein: The first wiring includes the second-type first wiring; The non-display area further includes a pad area, the pad area includes a first pad and a second pad, the first pad is electrically connected to the second-type first wiring; The non-display area further includes a first common signal bus. In the non-display area, the second-type second wiring is electrically connected to the second pad through the first common signal bus.

7. The display panel according to claim 6, wherein: The second wiring includes a plurality of second-type second wirings.

8. The display panel according to claim 1, wherein: The first wiring includes the first-type first wiring and the second-type first wiring; The distance between the first-type first wiring and the first-type second wiring electrically connected thereto is less than or equal to the shortest distance between the first-type first wiring and the second-type second wiring.

9. The display panel according to claim 1, wherein: The first wiring and the second wiring are provided in the same layer.

10. The display panel according to claim 1, wherein The first wiring and the second wiring do not overlap along a thickness direction of the display panel.

11. The display panel according to claim 1, wherein The display area includes a plurality of pixel units, each pixel unit includes N sub-pixels, where N is an integer; and N first wirings are located between two adjacent second wirings. Alternatively, along a direction parallel to the plane where the display panel is located, a plurality of the first wirings and a plurality of the second wirings are alternately arranged.

12. A method for preparing a display panel, characterized in that: The display panel includes a display area and a non-display area; the preparation method includes: forming a plurality of first wirings and a plurality of second wirings in the display area; forming at least one third wiring, at least one fourth wiring, and a second common signal bus in the non-display area, wherein along the extending direction of the first wiring, the third wiring and the fourth wiring are respectively located on both sides of the first wiring; detecting whether a first type of first wiring exists in the first wiring, where the first type of first wiring includes a first sub-wiring and a second sub-wiring spaced apart between the third wiring and the fourth wiring; If the first wiring includes the first-type first wiring: Selecting one of the second wirings as a first type of second wiring; and cutting the third wiring to obtain a first repair line and a first functional line, and cutting the fourth wiring to obtain a second repair line and a second functional line; The first sub-wiring and the second sub-wiring are electrically connected through the first repair line, the first type second wiring and the second repair line; the first functional line and the second functional line are electrically connected to the second common signal bus, and the first repair line and the second repair line are insulated from the second common signal bus.

13. The preparation method according to claim 12, characterized in that The first-type second wiring is a second wiring that is closest to the first-type first wiring.

14. The preparation method according to claim 12, characterized in that The method of forming a plurality of first wirings and a plurality of second wirings in the display area, cutting the third wiring to obtain the first repair line, and cutting the fourth wiring to obtain the second repair line includes: In the non-display area, along a direction perpendicular to the plane where the display panel is located, the first repair line is overlapped with at least one of the first wiring and the second wiring; and / or the second repair line is overlapped with at least one of the first wiring and the second wiring.

15. The preparation method according to claim 12, characterized in that Also includes: forming a first common signal bus in the non-display area; The second wirings other than the first-type second wirings are defined as second-type second wirings, and the second-type second wirings are electrically connected to the first common signal bus line.

16. The preparation method according to claim 12, characterized in that The method of cutting the third wiring to obtain the first repair line includes: Determining, in the third wiring, a first connection position electrically connected to the first sub-wiring and a second connection position electrically connected to the first-type second wiring, and determining, in the third wiring, a first cutting point and a second cutting point, wherein the first connection position and the second connection position are both located between the first cutting point and the second cutting point; cutting the third wiring at the first cutting point and the second cutting point to obtain the first repair line; The method of cutting the fourth wiring to obtain the second repair line includes: Determining, in the fourth wiring, a third connection position electrically connected to the second sub-wiring and a fourth connection position electrically connected to the first-type second wiring, and determining, in the fourth wiring, a third cutting point and a fourth cutting point, wherein the third connection position and the fourth connection position are both located between the third cutting point and the fourth cutting point; The fourth wiring is cut at the third cutting point and the fourth cutting point to obtain the second repair line.

17. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 11.

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