Pixel unit, array substrate and display panel

Abstract

The present application provides a pixel unit, an array substrate and a display panel. The pixel unit is used for a display panel, and the pixel unit has a sub-pixel area formed by two scan lines and two data lines; the pixel unit includes a first pixel electrode, an insulating protective layer, a second pixel electrode and a DBS common electrode which are stacked in sequence. The distribution density of the first pixel electrode is different from that of the second pixel electrode; the DBS common electrode is arranged corresponding to the scan line and the data line, and covers the scan and data lines; one of the first pixel electrode and the second pixel electrode is arranged in the same layer with the DBS common electrode to define a first gap, and the projection of the other on the plane where the DBS common electrode is located covers the first gap; the projection of the first gap on the first metal layer where the scan line is located is misaligned with the first metal layer, and the projection of the first gap on the second metal layer where the data line is located is misaligned with the second metal layer. The pixel unit can improve the pixel aperture ratio and penetration rate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel unit, an array substrate and a display panel. Background Art

[0002] Currently, liquid crystal display (LCD) devices are widely used in flat panel display fields such as LCD TVs, mobile phones, computer screens, laptop screens, and tablets because of their many advantages such as power saving, no radiation, and long service life.

[0003] In the prior art, when the pixel unit is in the dark state, in order to prevent the liquid crystal corresponding to the area between the DBS (Data BMLess) common electrode and the adjacent pixel electrode in the pixel structure of the display panel from being deflected by the data line or the scan line and causing light leakage, a shielding metal layer is generally provided under the area between the DBS common electrode and the adjacent pixel electrode for shielding and blocking. However, providing a shielding metal layer under the area between the DBS common electrode and the adjacent pixel electrode will not only reduce the pixel aperture ratio, but also generate a large parasitic capacitance between the shielding metal layer and the data line, resulting in an increased load on the data line. Summary of the invention

[0004] The pixel unit, array substrate and display panel provided in the present application are intended to solve the problem that the pixel unit of the existing display panel sets a shielding metal layer under the area between the DBS common electrode and the adjacent pixel electrode, resulting in a reduced pixel aperture ratio and a larger parasitic capacitance causing an increase in the negative load of the data line.

[0005] In order to solve the above technical problems, the first technical solution adopted by the present application is: to provide a pixel unit. The pixel unit is used for a display panel, and the pixel unit has a sub-pixel area, and the sub-pixel area is formed by two scanning lines and two data lines; the pixel unit includes:

[0006] A first pixel electrode is disposed on one side of the scan line and the data line and is located in a sub-pixel area;

[0007] an insulating protection layer, disposed on a side of the first pixel electrode away from the scanning line and the data line, and covering the first pixel electrode;

[0008] a second pixel electrode, disposed on a side of the insulating protection layer away from the first pixel electrode; a distribution density of the first pixel electrode is different from a distribution density of the second pixel electrode;

[0009] DBS common electrodes are arranged corresponding to the scan lines and the data lines and cover the scan lines and the data lines;

[0010] Among them, one of the first pixel electrode and the second pixel electrode is arranged in the same layer as the DBS common electrode to define a first gap, and the projection of the other pixel electrode on the plane where the DBS common electrode is located covers the first gap; and the projection of the first gap on the first metal layer where the scan line is located is misaligned with the first metal layer, and the projection of the first gap on the second metal layer where the data line is located is misaligned with the second metal layer.

[0011] The DBS common electrode is disposed in the same layer as the first pixel electrode and is spaced apart from the first pixel electrode to define the first gap; adjacent edges of the DBS common electrode and the first pixel electrode are overlapped with a projection of the second pixel electrode on the plane where the DBS common electrode is located; or,

[0012] The DBS common electrode is arranged in the same layer as the second pixel electrode and is spaced apart from the second pixel electrode to define the first gap; adjacent edges of the DBS common electrode and the second pixel electrode are overlapped with the projection of the first pixel electrode on the plane where the DBS common electrode is located.

[0013] The line width of the DBS common electrode in a portion corresponding to the scan line is greater than the width of the scan line, and the line width of the DBS common electrode in a portion corresponding to the data line is greater than the width of the data line.

[0014] Wherein, the pixel unit also includes a transistor, which is located on a side of the first pixel electrode close to the scan line, the scan line is electrically connected to the gate of the transistor, the source of the transistor is electrically connected to the corresponding data line, and the drain of the transistor is electrically connected to the first pixel electrode and / or the second pixel electrode; the DBS common electrode also covers the transistor.

[0015] Among them, the second pixel electrode includes a first trunk electrode, a second trunk electrode and a plurality of branch electrodes, the first trunk electrode intersects with the second trunk electrode to divide the sub-pixel area into a plurality of domains, a plurality of branch electrodes are arranged at intervals in the plurality of domains, one end of each branch electrode is connected to the first trunk electrode or the second trunk electrode; a second gap is formed between adjacent branch electrodes; and a projection of the second gap on the plane where the first pixel electrode is located is located within the first pixel electrode.

[0016] The first pixel electrode includes a plurality of sub-electrodes, the sub-electrodes are arranged corresponding to the second gap, and a projection of the second gap on the plane where the first pixel electrode is located is located within the sub-electrodes.

[0017] Wherein, the first pixel electrode is a continuous and seamless planar electrode;

[0018] The projection of the first pixel electrode on the plane where the second pixel electrode is located is located within the outer contour of the second pixel electrode; or,

[0019] A projection of the second pixel electrode on the plane where the first pixel electrode is located is located within an outer contour of the first pixel electrode.

[0020] wherein the first trunk electrode is perpendicular to the second trunk electrode so as to equally divide the sub-pixel region into four domains, the plurality of branch electrodes in each domain are parallel to each other, the angle between the branch electrode and the first trunk electrode or the second trunk electrode is 45°, and the width of each of the gaps is the same; and / or

[0021] The second pixel electrode further includes a side electrode, which surrounds the branch electrode and is connected to an end of the branch electrode away from the first trunk electrode or the second trunk electrode.

[0022] To solve the above technical problem, the second technical solution adopted in the present application is to provide an array substrate, which includes a substrate and a pixel unit, wherein the pixel unit is the pixel unit involved in the above technical solution, and the second pixel electrode is located on a side of the first pixel electrode away from the substrate.

[0023] In order to solve the above technical problems, the third technical solution adopted by the present application is to provide a display panel. The display panel includes:

[0024] An array substrate, which is the array substrate involved in the above technical solution;

[0025] a counter substrate, arranged opposite to the array substrate;

[0026] The liquid crystal layer is arranged between the array substrate and the counter substrate. Beneficial effects of the present application: Different from the prior art, the present application provides a pixel structure, an array substrate and a display panel. The pixel unit is used for a display panel, and the pixel unit has a sub-pixel area, and the sub-pixel area is formed by two scanning lines and two data lines. The pixel unit includes a first pixel electrode, an insulating protective layer, a second pixel electrode and a DBS common electrode which are stacked in sequence; wherein the distribution density of the first pixel electrode is different from the distribution density of the second pixel electrode, so that the liquid crystals corresponding to different areas in the sub-pixel area have different orientations, so as to increase the viewing angle of the display panel and reduce the color deviation problem under a large viewing angle; the present application defines a first gap by making one of the first pixel electrode and the second pixel electrode spaced apart from the DBS common electrode in the same layer, and making the projection of the other on the plane where the DBS common electrode is located cover the first gap, so that the liquid crystal corresponding to the first gap can be displayed by the first pixel electrode or the second pixel electrode corresponding to the first gap. The electrode is controlled to prevent the liquid crystal corresponding to the first gap from being affected by the signal of the data line or the scan line due to being close to the data line or the scan line, resulting in disordered arrangement of the liquid crystal, and causing light leakage at the edge of the sub-pixel area; at the same time, by making the projection of the first gap on the first metal layer where the scan line is located misaligned with the first metal layer, and making the projection of the first gap on the second metal layer where the data line is located misaligned with the second metal layer, that is, no metal layer is arranged under the first gap, so that there is no metal layer blocking the edge of the sub-pixel area, thereby increasing the pixel aperture ratio of the pixel unit, thereby effectively improving the transmittance of the display panel; and, by making no metal layer arranged under the first gap, it is possible to avoid the formation of a large parasitic capacitance between the metal layer and the scan line or the data line, effectively reducing the load of the data line, thereby reducing power consumption and improving the brightness of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 is a schematic diagram of a top view of the array substrate provided in the first embodiment of the present application;

[0029] Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure along line AA;

[0030] Figure 3 yes Figure 1 The schematic diagram of the cross-sectional structure along the BB line;

[0031] Figure 4ais a schematic structural diagram of a second pixel electrode provided in an embodiment of the present application;

[0032] Figure 4b It corresponds to Figure 4a A schematic structural diagram of a first pixel electrode and a second pixel electrode;

[0033] Figure 4c yes Figure 4a The second pixel electrode in Figure 4b A schematic diagram of the structure of the first pixel electrodes cooperating with each other;

[0034] Figure 5 is a schematic structural diagram of a first pixel electrode and a second pixel electrode provided in another embodiment of the present application;

[0035] Figure 6 is a schematic diagram of a top view of the structure of an array substrate provided in the second embodiment of the present application;

[0036] Figure 7 yes Figure 6 Schematic diagram of the cross-sectional structure along the CC line;

[0037] Figure 8 yes Figure 6 Schematic diagram of the cross-sectional structure along the DD line;

[0038] Fig. 9 yes Figure 6 A schematic structural diagram of a first pixel electrode and a second pixel electrode;

[0039] Fig.10 It is a schematic diagram of the structure of a display panel provided in one embodiment of the present application.

[0040] Reference numerals:

[0041] 1-array substrate; 2-opposite substrate; 3-liquid crystal layer; 10-scanning line; 11-first insulating layer; 20-data line; 21-second insulating layer; 30-first pixel electrode; 31-sub-electrode; 40-second pixel electrode; 41-first trunk electrode; 42-second trunk electrode; 43-branch electrode; 44-second gap; 45-side electrode; 50-DBS common electrode; 51-first gap; 60-insulating protection layer; 70-transistor; 80-substrate; 101-sub-pixel area; 1011-main pixel area; 1012-sub-pixel area. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0043] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0044] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0045] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0046] See also Figure 1-3 , Figure 1 is a schematic diagram of a top view of an array substrate provided in an embodiment of the present application. Figure 2 yes Figure 1 The cross-sectional structure diagram along the AA line is shown in the figure. Figure 3 yes Figure 1 In this embodiment, an array substrate 1 is provided, which is used to cooperate with a color filter substrate to drive the liquid crystal in the liquid crystal layer 3 to rotate, so as to control the light transmission amount of each sub-pixel area 101, thereby performing mixed light display image.

[0047] Specifically, the array substrate 1 includes a substrate 80 and a pixel unit 100, the pixel unit 100 is arranged on one side of the substrate 80, and the pixel unit 100 has a sub-pixel area 101, and the sub-pixel area 101 is formed by two scanning lines 10 and two data lines 20; specifically, the projection of the data line 20 on the plane where the scanning line 10 is located is perpendicular to the scanning line 10, so that the scanning line 10 and the data line 20 form a rectangular sub-pixel area 101.

[0048] Specifically, the pixel unit 100 includes a first pixel electrode 30, an insulating protective layer 60, a second pixel electrode 40 and a DBS common electrode 50. The first pixel electrode 30 is arranged on one side of the scan line 10 and the data line 20 and is located in the sub-pixel area 101. The insulating protective layer 60 is arranged on the side of the first pixel electrode 30 away from the scan line 10 and the data line 20 and covers the first pixel electrode 30. The second pixel electrode 40 is arranged on the side of the insulating protective layer 60 away from the first pixel electrode 30, and the distribution density of the first pixel electrode 30 is different from that of the second pixel electrode 40; that is, the first pixel electrode 30 and the second pixel electrode 40 are insulated by the insulating protective layer 60, and the distribution density of the first pixel electrode 30 and the second pixel electrode 40 in the sub-pixel area 101 is different, so that the liquid crystals in different areas of the sub-pixel area 101 correspond to the first pixel electrode 30 and the second pixel electrode 40 respectively, so that the liquid crystals in different areas have different inversions, so as to increase the viewing angle of the display panel.

[0049] The first pixel electrode 30 and the second pixel electrode 40 can be made of transparent conductive materials to allow light to pass through, such as indium tin oxide (ITO). The insulating protection layer 60 can be made of transparent insulating materials to allow light to pass through, such as glass, resin, quartz, organic glass or other organic polymer materials.

[0050] The DBS is arranged corresponding to the scan line 10 and the data line 20, and covers the scan line 10 and the data line 20; specifically, the line width of the portion of the DBS common electrode 50 corresponding to the scan line 10 is greater than the width of the scan line 10, and the line width of the portion of the DBS common electrode 50 corresponding to the data line 20 is greater than the width of the data line 20, so that the projection of the DBS common electrode 50 on the plane where the scan line 10 is located covers the scan line 10, and the projection of the DBS common electrode 50 on the plane where the data line 20 is located covers the data line 20; and the DBS common electrode 50 is applied to the substrate 2 (see Fig.10) makes the potential of the DBS common electrode 50 the same as the potential of the common electrode of the opposite substrate 2, so that the liquid crystal in the area corresponding to the scan line 10 and the data line 20 is not deflected, and light cannot pass through the area, so as to realize the function of the black matrix and avoid the problem of color deviation caused by the displacement of the black matrix. Specifically, the DBS common electrode 50 can be made of indium tin oxide.

[0051] In a specific embodiment, Figure 2 and Figure 3 As shown, the scan line 10 is disposed on one side of the substrate 80, a first insulating layer 11 is further disposed between the data line 20 and the scan line 10, and a second insulating layer 21 is further disposed between the data line 20 and the first pixel electrode 30, so that each layer is relatively independent to avoid short circuit between layers. Of course, the first insulating layer 11 and the second insulating layer 21 are also made of transparent insulating materials to achieve insulation while allowing light to pass through.

[0052] Specifically, one of the first pixel electrode 30 and the second pixel electrode 40 is arranged at the same layer as the DBS common electrode 50 to define a first gap 51, and the projection of the other on the plane where the DBS common electrode is located covers the first gap 51; that is, the DBS common electrode 50 and the first pixel electrode 30 or the second pixel electrode 40 are formed by patterning the same transparent conductive layer, and the gap between the DBS common electrode 50 and the first pixel electrode 30 or the second pixel electrode 40 arranged at the same layer is defined as the first gap 51; it can be seen that the first gap 51 is located at the edge of the sub-pixel area 101 domain, and by making the projection of the other first pixel electrode 30 or the second pixel electrode 40 that is not arranged at the same layer as the DBS common electrode 50 on the plane where the DBS common electrode 50 is located cover the first gap 51, so that the liquid crystal corresponding to the first gap 51 can be controlled by the first pixel electrode 30 or the second pixel electrode 40 corresponding to the first gap 51, thereby avoiding the liquid crystal corresponding to the first gap 51 from being affected by the signal of the data line 20 or the scan line 10 due to being close to the data line 20 or the scan line 10, resulting in disordered arrangement of the liquid crystal, causing light leakage at the edge of the sub-pixel area 101 domain.

[0053] Furthermore, the projection of the first gap 51 on the first metal layer where the scanning line 10 is located is misaligned with the first metal layer, and the projection of the first gap 51 on the second metal layer where the data line 20 is located is misaligned with the second metal layer, that is, there is no metal layer arranged below the first gap 51, so that there is no metal layer blocking the edge of the sub-pixel area 101, thereby increasing the pixel aperture ratio of the pixel unit 100, thereby effectively improving the transmittance of the display panel; and, by ensuring that there is no metal layer arranged below the first gap 51, a large parasitic capacitance can be avoided from being formed between the metal layer and the scanning line 10 or the data line 20, thereby effectively reducing the load of the data line 20, thereby reducing power consumption and improving the brightness of the display panel.

[0054] See also Figure 2-3 In this embodiment, the DBS common electrode 50 is arranged in the same layer as the first pixel electrode 30, and is spaced apart from the first pixel electrode 30 to define a first gap 51, that is, the gap between the first pixel electrode 30 and the DBS common electrode 50 is defined as the first gap 51, and the first gap 51 is located at the edge of the sub-pixel. The adjacent edges of the DBS common electrode 50 and the first pixel electrode 30 overlap with the projection of the second pixel electrode 40 on the plane where the DBS common electrode 50 is located, that is, the side of the first pixel electrode 30 close to the first gap 51 overlaps with the projection of the second pixel electrode 40 on the DBS common electrode 50, and the side of the DBS common electrode 50 close to the first gap 51 overlaps with the projection of the second pixel electrode 40 on the DBS common electrode 50, so that the projection of the second pixel electrode 40 on the plane where the DBS common electrode 50 is located covers the first gap 51, so that the liquid crystal corresponding to the first gap 51 can be controlled by the second pixel electrode 40 corresponding to the first gap 51, thereby avoiding the liquid crystal corresponding to the first gap 51 being affected by the signal of the data line 20 or the scan line 10 due to being close to the data line 20 or the scan line 10, resulting in disordered arrangement of the liquid crystal, causing light leakage at the edge of the sub-pixel area 101.

[0055] For further information, see Figure 4a , 4b , 4c and Figure 5 The projection of the first pixel electrode 30 on the plane where the second pixel electrode 40 is located is located within the outer contour of the second pixel electrode 40, so that the first pixel electrode 30 can cover the first gap 51 at the edge of the sub-pixel area 101, further improving the light leakage prevention effect at the edge of the sub-pixel area 101 of the pixel unit 100.

[0056] like Figure 2 As shown, the DBS common electrode 50 covering the data line 20 is in the same layer as the first pixel electrode 30 and is arranged at intervals. The gap between the DBS common electrode 50 and the first pixel electrode 30 is defined as a first gap 51. The first gap 51 is located between the first pixel electrode 30 and the data line 20. The projection of the second pixel electrode 40 on the plane where the DBS common electrode 50 is located covers the first gap 51, so that the liquid crystal corresponding to the gap between the first pixel electrode 30 and the data line 20 can be controlled by the corresponding second pixel electrode 40, so that the liquid crystal corresponding to the edge of the data line 20 of the pixel unit 100 is affected by the signal of the data line 20 due to its proximity to the data line 20, resulting in a disordered arrangement of the liquid crystal, causing light leakage at the edge of the sub-pixel area 101.

[0057] like Figure 3As shown, the DBS common electrode 50 covering the scan line 10 is in the same layer as the first pixel electrode 30 and is arranged at intervals. The gap between the DBS common electrode 50 and the first pixel electrode 30 is defined as a first gap 51, and the first gap 51 is located between the first pixel electrode 30 and the scan line 10. The projection of the second pixel electrode 40 on the plane where the DBS common electrode 50 is located covers the first gap 51, so that the liquid crystal corresponding to the gap between the first pixel electrode 30 and the scan line 10 can be controlled by the corresponding second pixel electrode 40, so that the liquid crystal corresponding to the edge of the scan line 10 of the pixel unit 100 is affected by the signal of the scan line 10 due to its proximity to the scan line 10, resulting in a disordered arrangement of the liquid crystal, causing light leakage at the edge of the sub-pixel area 101.

[0058] Please refer again Figure 1 In this embodiment, the second pixel electrode 40 includes a first trunk electrode 41, a second trunk electrode 42 and a plurality of branch electrodes 43. The first trunk electrode 41 intersects with the second trunk electrode 42, and has divided the sub-pixel area 101 into a plurality of domains. The plurality of branch electrodes 43 are arranged at intervals in the plurality of domains. One end of each branch electrode 43 is connected to the first trunk electrode 41 or the second trunk electrode 42. A second gap 44 is formed between adjacent branch electrodes 43. The projection of the second gap 44 on the plane where the first pixel electrode 30 is located is located in the first pixel electrode 30, that is, the projection of the first pixel electrode 30 on the plane where the first pixel electrode 30 is located covers the second gap 44, so that the first pixel electrode 30 corresponds to the liquid crystal in the area where the second gap 44 is located, so as to control the liquid crystal in the area where the second gap 44 is located. Specifically, the driving voltage of the first pixel electrode 30 is connected to the second pixel electrode 30. The driving voltage of the second pixel electrode 40 is different, so that a main pixel area 1011 and a sub-pixel area 1012 are formed in the sub-pixel area 101, respectively. The main pixel area 1011 is the area corresponding to the second pixel electrode 40, and the sub-pixel area 1012 is the area where the second gap 44 is located, so that the rotation angle of the liquid crystal corresponding to the main pixel area 1011 is different from the rotation angle of the liquid crystal corresponding to the sub-pixel area 1012, so that the gamma characteristics under a large viewing angle are mixed and compensated to improve the color deviation; at the same time, by setting the area where the second gap 44 is located as the sub-pixel area 1012, the main pixel area 1011 and the sub-pixel area 1012 are alternately merged together, not only when the sub-pixel area 101 is large, but also by setting the area where the second gap 44 is located as the sub-pixel area 1012, the aperture ratio and the transmittance of the pixel unit 100 are effectively improved, and the display brightness is effectively improved. Specifically, the width of the second gap 44 and the width of the branch electrode 43 can be set according to actual needs, and there is no specific limitation on this.

[0059] Furthermore, the first trunk electrode 41 is perpendicular to the second trunk electrode 42 to equally divide the sub-pixel area 101 into four domains, and the multiple branch electrodes 43 in each domain are parallel to each other, and the angle between the branch electrode 43 and the first trunk electrode 41 or the second trunk electrode 42 is 45°, and the width of each second gap 44 is the same. According to the liquid crystal efficiency calculation formula:

[0060]

[0061] Wherein, T represents the liquid crystal efficiency, φ represents the pretilt angle of the liquid crystal, Δn represents the birefringence difference of the liquid crystal, d represents the liquid crystal thickness, and λ represents the wavelength of the incident light.

[0062] It can be seen from formula (1) that, for the display panel, Δn, d and λ are generally fixed values, so when the pre-tilt angle of the liquid crystal is 45°, the liquid crystal efficiency can reach the maximum value. In this embodiment, by making the angle between the branch electrode 43 and the first trunk electrode 41 or the second trunk electrode 42 45°, the pre-tilt angle of the liquid crystal in the main pixel area 1011 and the sub-pixel area 1012 of each domain area can be closer to 45°, that is, the liquid crystal in the sub-pixel area 101 is closer to 45° as a whole, which can effectively improve the liquid crystal efficiency, thereby effectively improving the transmittance of the pixel unit 100. At the same time, by making the width of each second gap 44 the same, the width of the sub-pixel area 1012 is the same, which can further improve the distribution balance of the sub-pixel area 1012, thereby making the light field distribution more balanced, and further improving the display quality.

[0063] Furthermore, the second pixel electrode 40 further includes a side electrode 45 , which surrounds the branch electrode 43 and is connected to an end of the branch electrode 43 away from the first trunk electrode 41 or the second trunk electrode 42 , so that the edge of the sub-pixel region 101 is more neat during display.

[0064] See also Figure 4a , 4b and Figure 4c In this embodiment, the second pixel electrode 40 is arranged on the upper layer of the first pixel electrode 30, and the first pixel electrode 30 includes a plurality of sub-electrodes 31, each sub-electrode 31 is arranged corresponding to the second gap 44, and the projection of the second gap 44 on the plane where the first pixel electrode 30 is located is located in the sub-electrode 31, so that the first pixel electrode 30 can control the liquid crystal corresponding to the second gap 44, thereby forming a sub-pixel area 1012, so that the main pixel area 1011 and the sub-pixel area 1012 are alternately merged together, not only can better viewing angle characteristics be maintained when the sub-pixel area 101 is larger, but also by setting the area where the second gap 44 is located as the sub-pixel area 1012, the aperture ratio and the transmittance of the pixel unit 100 are effectively improved, and the display brightness is effectively improved.

[0065] See also Figure 5 , Figure 5 : is a schematic diagram of the structure of the first pixel electrode and the second pixel electrode provided by another embodiment of the present application. In this embodiment, the first pixel electrode 30 is a continuous and seamless planar electrode. Specifically, the first pixel electrode 30 is a rectangular planar electrode. The portion of the first pixel electrode 30 corresponding to the second gap 44 can be used to control the liquid crystal corresponding to the second gap 44, thereby forming a sub-pixel area 1012; the portion of the first pixel electrode 30 corresponding to the second pixel electrode 40 is shielded by the second pixel electrode 40, and the second pixel electrode 40 is used to control the liquid crystal located at the second pixel electrode 40 to form a main pixel area 1011, so that the main pixel area 1011 and the sub-pixel area 1012 are alternately merged together, not only when the sub-pixel area 101 is large, but also by setting the area where the second gap 44 is located as the sub-pixel area 1012, the aperture ratio and the transmittance of the pixel unit 100 are effectively improved, and the display brightness is effectively improved; in addition, by setting the first pixel electrode 30 as a continuous and seamless planar electrode, the structure is simpler and more conducive to production and preparation.

[0066] Specifically, the pixel unit 100 further includes a transistor 70, which is located on a side of the first pixel electrode 30 close to the scan line 10, the scan line 10 is electrically connected to the gate of the transistor 70, the source of the transistor 70 is electrically connected to the corresponding data line 20, and the drain of the transistor 70 is electrically connected to the first pixel electrode 30 and / or the second pixel electrode 40, so that the transistor 70 drives the pixel unit 100 and provides a driving voltage to the first pixel electrode 30 and the second pixel electrode 40 respectively; specifically, the pixel unit 100 can drive the pixel unit 100 through a switching transistor 70, using a capacitive voltage division driving method; or in other embodiments, the first pixel electrode 30 and the second pixel electrode 40 can drive the pixel unit 100 through two switching transistors 70, respectively, using a resistive voltage division driving method, which can be set according to actual needs, and there is no specific limitation on this. Specifically, the DBS common electrode 50 also covers the transistor 70 to prevent light leakage in the area where the transistor 70 is located.

[0067] See also Figure 6-8 , Figure 6 is a schematic diagram of a top view structure of a pixel unit provided in the second embodiment of the present application, Figure 7 yes Figure 6 Schematic diagram of the cross-sectional structure along the CC line. Figure 8 yes Figure 6Different from the first embodiment, in this embodiment, the DBS common electrode 50 is arranged in the same layer as the second pixel electrode 40, and is spaced from the second pixel electrode 40 to define a first gap 51, that is, the gap between the second pixel electrode 40 and the DBS common electrode 50 is defined as the first gap 51, and the first gap 51 is located at the edge of the sub-pixel. The adjacent edges of the DBS common electrode 50 and the second pixel electrode 40 overlap with the projection of the first pixel electrode 30 on the plane where the DBS common electrode 50 is located, that is, the side of the second pixel electrode 40 close to the first gap 51 overlaps with the projection of the first pixel electrode 30 on the DBS common electrode 50, and the side of the DBS common electrode 50 close to the first gap 51 overlaps with the projection of the first pixel electrode 30 on the DBS common electrode 50, so that the projection of the first pixel electrode 30 on the plane where the DBS common electrode 50 is located covers the first gap 51, so that the liquid crystal corresponding to the first gap 51 can be controlled by the first pixel electrode 30 corresponding to the first gap 51, thereby avoiding that the liquid crystal corresponding to the first gap 51 is affected by the signal of the data line 20 or the scan line 10 due to being close to the data line 20 or the scan line 10, resulting in disordered arrangement of the liquid crystal, causing light leakage at the edge of the sub-pixel area 101.

[0068] For further information, see Fig. 9 , Fig. 9 yes Figure 6 The projection of the second pixel electrode 40 on the plane where the first pixel electrode 30 is located is located within the outer contour of the first pixel electrode 30, so that the second pixel electrode 40 can cover the first gap 51 at the edge of the sub-pixel area 101, further improving the light leakage prevention effect at the edge of the sub-pixel area 101 of the pixel unit 100.

[0069] like Figure 7 As shown, the DBS common electrode 50 covering the data line 20 is in the same layer as the second pixel electrode 40 and is arranged at intervals. The gap between the DBS common electrode 50 and the second pixel electrode 40 is defined as a first gap 51, and the first gap 51 is located between the second pixel electrode 40 and the data line 20. The projection of the first pixel electrode 30 on the plane where the DBS common electrode 50 is located covers the first gap 51, so that the liquid crystal corresponding to the gap between the second pixel electrode 40 and the data line 20 can be controlled by the corresponding first pixel electrode 30, so that the liquid crystal corresponding to the edge of the data line 20 of the pixel unit 100 is affected by the signal of the data line 20 due to its proximity to the data line 20, resulting in a disordered arrangement of the liquid crystal, causing light leakage at the edge of the sub-pixel area 101.

[0070] like Figure 8As shown, the DBS common electrode 50 covering the scan line 10 is in the same layer as the first pixel electrode 30 and is arranged at intervals. The gap between the DBS common electrode 50 and the second pixel electrode 40 is defined as a first gap 51. The first gap 51 is located between the second pixel electrode 40 and the scan line 10. The projection of the second pixel electrode 40 on the plane where the DBS common electrode 50 is located covers the first gap 51, so that the liquid crystal corresponding to the gap between the second pixel electrode 40 and the scan line 10 can be controlled by the corresponding second pixel electrode 40, so that the liquid crystal corresponding to the edge of the scan line 10 of the pixel unit 100 is affected by the signal of the scan line 10 due to its proximity to the scan line 10, resulting in a disordered arrangement of the liquid crystal, causing light leakage at the edge of the sub-pixel area 101.

[0071] In the above embodiment, the second pixel electrode 40 is located on the side of the first pixel electrode 30 away from the substrate 80, so that the second pixel electrode 40 is located above the first pixel electrode 30, so as to realize the alternating fusion of the main pixel area 1011 and the sub-pixel area 1012, so that the pixel unit 100 can realize the display effect of the previous eight-domain area with four-domain areas.

[0072] See also Fig.10 , Fig.10 1 is a schematic diagram of a display panel according to an embodiment of the present application. In this embodiment, a display panel is provided, the display panel comprising an array substrate 1 , an opposing substrate 2 and a liquid crystal layer 3 .

[0073] Among them, the specific structure and function of the array substrate 1 are the same or similar to the specific structure and function of the array substrate 1 involved in the above embodiment, and can achieve the same technical effect. Please refer to the specific introduction above and will not be repeated here.

[0074] The opposing substrate 2 is arranged opposite to the array substrate 1, and the opposing substrate 2 forms a containing cavity for containing the liquid crystal layer 3. The opposing substrate 2 can be specifically a color filter substrate, which is used to form a corresponding electric field of the main pixel area 1011 and an electric field of the sub-pixel area 1012 between the array substrate 1, thereby driving the liquid crystal deflection of the liquid crystal layer 3, controlling the light transmission, and further making the light of the sub-pixel area 101 of the pixel unit 100 emit the corresponding color after filtering by the filter layer of the color filter substrate, and then mixed with the corresponding color light emitted by the adjacent sub-pixel area 101 to display different colors, thereby realizing the image display function.

[0075] The display panel provided in the present application can effectively improve the aperture ratio and transmittance, and can reduce power consumption, increase brightness, and increase viewing angle.

[0076] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A pixel unit for a display panel, the pixel unit having a sub-pixel region, the sub-pixel region being surrounded by two scan lines and two data lines; the pixel unit comprising: A first pixel electrode is disposed on one side of the scan line and the data line and is located in a sub-pixel area; an insulating protection layer, disposed on a side of the first pixel electrode away from the scan line and the data line, and covering the first pixel electrode; a second pixel electrode, disposed on a side of the insulating protection layer away from the first pixel electrode; a distribution density of the first pixel electrode is different from a distribution density of the second pixel electrode; A DBS common electrode is arranged corresponding to the scan line and the data line and covers the scan line and the data line; It is characterized in that one of the first pixel electrode and the second pixel electrode is arranged at the same layer as the DBS common electrode and is spaced apart to define a first gap, and the projection of the other first pixel electrode or the second pixel electrode which is not arranged at the same layer as the DBS common electrode on the plane where the DBS common electrode is located covers the first gap, so that the liquid crystal corresponding to the first gap is controlled by the first pixel electrode or the second pixel electrode corresponding to the first gap; and the projection of the first gap on the first metal layer where the scan line is located is misaligned with the first metal layer, the projection of the first gap on the second metal layer where the data line is located is misaligned with the second metal layer, and there is no metal layer arranged under the first gap; the first pixel electrode and the second pixel electrode are made of transparent conductive material.

2. The pixel unit according to claim 1, characterized in that: The DBS common electrode is disposed in the same layer as the first pixel electrode and is spaced apart from the first pixel electrode to define the first gap; adjacent edges of the DBS common electrode and the first pixel electrode are overlapped with a projection of the second pixel electrode on the plane where the DBS common electrode is located; or, The DBS common electrode is arranged in the same layer as the second pixel electrode and is spaced apart from the second pixel electrode to define the first gap; adjacent edges of the DBS common electrode and the second pixel electrode are overlapped with the projection of the first pixel electrode on the plane where the DBS common electrode is located.

3. The pixel unit according to claim 1, characterized in that: The line width of the DBS common electrode in a portion corresponding to the scan line is greater than the width of the scan line, and the line width of the DBS common electrode in a portion corresponding to the data line is greater than the width of the data line.

4. The pixel unit according to claim 1, characterized in that: It also includes a transistor, which is located on a side of the first pixel electrode close to the scan line, the scan line is electrically connected to the gate of the transistor, the source of the transistor is electrically connected to the corresponding data line, and the drain of the transistor is electrically connected to the first pixel electrode and / or the second pixel electrode; the DBS common electrode also covers the transistor.

5. The pixel unit according to claim 1, characterized in that: The second pixel electrode includes a first trunk electrode, a second trunk electrode and a plurality of branch electrodes, the first trunk electrode intersects with the second trunk electrode to divide the sub-pixel area into a plurality of domains, a plurality of branch electrodes are arranged at intervals in the plurality of domains, one end of each branch electrode is connected to the first trunk electrode or the second trunk electrode; a second gap is formed between adjacent branch electrodes; a projection of the second gap on the plane where the first pixel electrode is located is located within the first pixel electrode.

6. The pixel unit according to claim 5, characterized in that: The first pixel electrode includes a plurality of sub-electrodes, the sub-electrodes are arranged corresponding to the second gap, and a projection of the second gap on a plane where the first pixel electrode is located is located within the sub-electrodes.

7. The pixel unit according to claim 5, characterized in that: The first pixel electrode is a continuous and seamless planar electrode; The projection of the first pixel electrode on the plane where the second pixel electrode is located is located within the outer contour of the second pixel electrode; or, A projection of the second pixel electrode on the plane where the first pixel electrode is located is located within an outer contour of the first pixel electrode.

8. The pixel unit according to claim 5, characterized in that: The first trunk electrode is perpendicular to the second trunk electrode to equally divide the sub-pixel area into four domains, the multiple branch electrodes in each domain are parallel to each other, the angle between the branch electrode and the first trunk electrode or the second trunk electrode is 45°, and the width of each of the second gaps is the same; and / or The second pixel electrode further includes a side electrode, which surrounds the branch electrode and is connected to an end of the branch electrode away from the first trunk electrode or the second trunk electrode.

9. An array substrate, characterized in that: The method comprises a substrate and a pixel unit, wherein the pixel unit is the pixel unit according to any one of claims 1 to 8, and the second pixel electrode is located on a side of the first pixel electrode away from the substrate.

10. A display panel, characterized in that: include: An array substrate, which is the array substrate as claimed in claim 9; a counter substrate, arranged opposite to the array substrate; The liquid crystal layer is arranged between the array substrate and the counter substrate.

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