Disk device

Abstract

A disk device that provides good read efficiency for data on a disk is provided. The disk device includes a disk, a buffer memory, and a control circuit. The disk has a plurality of bands, and each of the plurality of bands is a storage area where data is written in the SMR method. The control circuit receives a read request from the outside. When the data requested to be read is the first data to be updated stored in the first band among the plurality of bands, the control circuit reads the first data from the first band and stores it in the buffer memory, and updates the first data in the buffer memory. Further, the control circuit transmits the first data in the buffer memory to the outside, and writes the first data in the buffer memory to one of the plurality of bands.

Description

[0001] Related Application

[0002] This application claims priority to Japanese Patent Application No. 2021-152184 (filing date: September 17, 2021). This application incorporates by reference the entire contents of the prior application. Technical Field

[0003] This embodiment relates to a disk device. Background Art

[0004] In recent years, as a method of writing data to a disk, a technique called SMR (Shingled Magnetic Recording) has been developed. According to SMR, when writing data to a disk, data of the next track amount is written in such a way as to overlap a part of the data of one track that has already been written. As a result, the width of the track (i.e., the track pitch) is narrower than the width of the writing element, and the recording density of data on the disk is increased.

[0005] In SMR, the track pitch is narrower than the writing element. Therefore, in order to prevent the unintentional erasure of the data that has already been written, writing of new data is sequentially performed on the disk positions. More specifically, in SMR, the disk is divided into a plurality of partial regions in the radial direction, and data is sequentially written at the positions of the respective partial regions. Each partial region is called a band. The writing pattern in which data is continuously written in position is called sequential writing. The data of band unit stored in each band is called band data.

[0006] When a part of the band data stored in a band is rewritten, the band data is read from the band and stored in the buffer memory, and the rewriting of the band data is performed on the buffer memory. Then, the rewritten band data is written into one band. Summary of the Invention

[0007] An object of one embodiment is to provide a disk device with good read efficiency of data from a disk.

[0008] According to one embodiment, a disk device includes: a disk, a buffer memory, and a control circuit. The disk has a plurality of bands, and each of the plurality of bands is a storage area in which data is written in the SMR manner. The control circuit receives a read request from the outside. When the data requested to be read is the first data to be updated stored in the first band among the plurality of bands, the control circuit reads the first data from the first band and stores it in the buffer memory, and updates the first data in the buffer memory. Then, the control circuit sends the first data in the buffer memory to the outside, and writes the first data in the buffer memory into one of the plurality of bands. Brief Description of the Drawings

[0009] Figure 1 FIG. is an example of the configuration of a disk device showing an embodiment.

[0010] Figure 2 FIG. is a diagram for explaining the recording surface of each disk of the embodiment.

[0011] Figure 3 FIG. is a schematic diagram for explaining the SMR mode writing performed in the disk device of the embodiment.

[0012] Figure 4 FIG. is a schematic diagram for explaining various areas allocated to the first RAM in the embodiment.

[0013] Figure 5 FIG. is a schematic diagram for explaining the operation of reading tape data performed in the disk device of the embodiment.

[0014] Figure 6 FIG. is a schematic diagram for explaining the operation of updating data performed in the disk device of the embodiment.

[0015] Figure 7 FIG. is a schematic diagram for explaining the operation after data update in the disk device of the embodiment.

[0016] Figure 8 FIG. is a schematic diagram for explaining an example of data that is the object of a shared read operation in the disk device of the embodiment.

[0017] Figure 9 FIG. is a schematic diagram for explaining another example of data that is the object of a shared read operation in the disk device of the embodiment.

[0018] Figure 10 FIG. is a flowchart showing an example of an operation for setting an object of update processing performed by the disk device of the embodiment.

[0019] Figure 11 FIG. is a flowchart showing an example of a series of operations related to a shared read operation performed by the disk device of the embodiment.

[0020] Figure 12 FIG. is a schematic diagram for explaining an example of the operation of the disk device of the embodiment.

[0021] Figure 13 FIG. is a schematic diagram for explaining an example of the operation of the disk device of the embodiment when writing tape data fails.

[0022] Figure 14It is a schematic diagram showing an example of the operation of a disk device for explaining a modified example of an embodiment. Detailed Embodiment

[0023] Hereinafter, with reference to the accompanying drawings, the disk device of the embodiment will be described in detail. In addition, the present invention is not limited by this embodiment.

[0024] (Embodiment)

[0025] The technology of the embodiment can be applied to a disk device having one or more actuator systems. Hereinafter, a case where the technology of the embodiment is applied to a disk device having two actuator systems will be described.

[0026] Figure 1 It is a diagram showing an example of the configuration of the disk device 1 of the embodiment. The disk device 1 can be connected to the host 2. The standard of the communication path between the disk device 1 and the host 2 is not limited to a specific standard. In one example, SAS (Serial Attached SCSI) can be adopted as the standard of the communication path between the disk device 1 and the host 2.

[0027] The host 2 is, for example, a processor, a personal computer, or a server, etc. The disk device 1 can receive access commands (read commands and write commands) from the host 2.

[0028] The disk device 1 includes a plurality of disks 10. Here, as an example, the disk device 1 includes two disks 10a and 10b. The two disks 10 rotate integrally about the rotation axis 11 by a spindle motor (not shown).

[0029] Recording surfaces capable of recording data are formed on the front and back of each disk 10. That is, the two disks 10 have four recording surfaces. In order to access each of the four recording surfaces, the disk device 1 includes four magnetic heads HD corresponding to the four recording surfaces.

[0030] A pair of first magnetic heads HDa among the four magnetic heads HD face a pair of recording surfaces of the first disk 10a. Another pair of second magnetic heads HDb among the four magnetic heads HD face a pair of recording surfaces of the second disk 10b. Each magnetic head HD performs access to the recording surface it faces, that is, writing and reading of data. Each magnetic head HD uses the writing element it has to write data. Each magnetic head HD uses the reading element it has to read data.

[0031] The disk device 1 includes two actuator systems 12 that are individually driven. The first actuator system 12a among the two actuator systems 12 includes an actuator arm 13a and a voice coil motor 14a. A pair of first magnetic heads HDa are mounted at the front end of the actuator arm 13a.

[0032] The second actuator system 12b among the two actuator systems 12 includes an actuator arm 13b and a voice coil motor 14b. A pair of second magnetic heads HDb are mounted at the front end of the actuator arm 13b.

[0033] The two actuator systems 12 can rotate individually about the rotation axis 15. The rotation axis 15 is provided at a position parallel to the rotation axis 11 and separated from the rotation axis 11. The voice coil motor 14a rotates the first actuator system 12a about the rotation axis 15 within a predetermined range. Thereby, the pair of first magnetic heads HDa perform relative movement in the radial direction with respect to each recording surface of the first magnetic disk 10a. The voice coil motor 14b rotates the second actuator system 12b about the rotation axis 15 within a predetermined range. Thereby, the pair of second magnetic heads HDb perform relative movement in the radial direction with respect to each recording surface of the second magnetic disk 10b.

[0034] In addition, the disk device 1 can include three or more magnetic disks 10. In this case, a plurality of first magnetic heads HDa for accessing each recording surface of a part of the three or more magnetic disks 10 are provided at the front end of the actuator arm 13a included in the first actuator system 12a, and a plurality of second magnetic heads HDb for accessing each recording surface of the other magnetic disks 10 among the three or more magnetic disks 10 are provided at the front end of the actuator arm 13b included in the second actuator system 12b.

[0035] The disk device 1 further includes a control circuit 20. The control circuit 20 communicates with the host 2 via an interface such as a connection pin (not shown) provided in the housing of the disk device 1 for external connection. The control circuit 20 controls each part of the disk device 1 according to commands from the host 2. As described above, the commands from the host 2 include a write command for requesting writing and a read command for requesting reading.

[0036] The control circuit 20 has a preamplifier (Pre Amp) 21 and an RDC (ReadWrite Chanel) 22 for each actuator system 12. That is, the control circuit 20 includes a preamplifier 21a and an RDC 22a corresponding to the first actuator system 12a. In addition, the control circuit 20 includes a preamplifier 21b and an RDC 22b corresponding to the second actuator system 12b.

[0037] The control circuit 20 further has a DSP (Digital Signal Processor) 23, a first RAM (Random Access Memory) 24, an HDC (Hard Disk Controller) 25, an MPU (Micro Processing Unit) 26, and a second RAM 27.

[0038] The preamplifier 21a amplifies the signal read from the recording surface of the first magnetic disk 10a by the reading element of each first head HDa and supplies it to the RDC 22a. Further, the preamplifier 21a amplifies the signal supplied from the RDC 22a and supplies it to the first head HDa facing the recording surface to be written.

[0039] The RDC 22a encodes the data written to the first magnetic disk 10a, supplies the encoded data as a signal to the preamplifier 21a. Further, the RDC 22a decodes the signal read from the first magnetic disk 10a and supplied from the preamplifier 21a. The RDC 22a outputs the decoded signal as digital data to the HDC 25.

[0040] The preamplifier 21b amplifies the signal read from the second magnetic disk 10b by the reading element of each second head HDb and supplies it to the RDC 22b. Further, the preamplifier 21b amplifies the signal supplied from the RDC 22b and supplies it to the second head HDb.

[0041] The RDC 22b encodes the data written to the second magnetic disk 10b, supplies the encoded data as a signal to the preamplifier 21b. Further, the RDC 22b decodes the signal read from the second magnetic disk 10b and supplied from the preamplifier 21b. The RDC 22b outputs the decoded signal as digital data to the HDC 25.

[0042] The DSP 23 controls the spindle motor and each voice coil motor 14 to perform positioning control of each head HD such as seek and following.

[0043] The first RAM 24 is a buffer memory that temporarily stores data and the like transferred between the host 2 and each magnetic disk 10. For example, the data received from the host 2 is written to any one of the magnetic disks 10 via the first RAM 24. Further, the data read from the two magnetic disks 10 is output to the host 2 via the first RAM 24. Details of the function of the buffer memory as the first RAM 24 will be described later.

[0044] The first RAM 24 is composed of a memory capable of high-speed operation. Further, the first RAM 24 is a dual-port memory or the like capable of multiple simultaneous accesses. In addition, the first RAM 24 may be a single-port memory. The first RAM 24 may be composed of, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), or a combination thereof. In addition, the position where the first RAM 24 is provided may not be within the control circuit 20. The first RAM 24 may be provided outside the control circuit 20.

[0045] HDC25 performs communication with host 2. HDC25 saves the data received from RDC22a and 22b in the first RAM 24. Moreover, HDC25 transfers the data from RDC22a and 22b saved in the first RAM 24 to host 2.

[0046] In addition, HDC25 saves the data received from host 2 together with a write command in the first RAM 24. Moreover, HDC25 outputs the data from host 2 saved in the first RAM 24 to RDC22a and 22b.

[0047] MPU26 is a processor that executes a firmware program. MPU26 analyzes the commands received from host 2 by HDC25, monitors the state of the disk device 1, controls each part of the disk device 1, etc.

[0048] The second RAM 27 functions as an area for firmware and saving various management information, etc. The second RAM 27 is composed of a volatile memory, a non-volatile memory, or a combination of these. The volatile memory can be, for example, SRAM, DRAM, or a combination of these. The non-volatile memory can be a flash memory, etc.

[0049] As described above, a pair of first magnetic heads HDa are provided at the front end of the first actuator system 12a, and a pair of second magnetic heads HDb are provided at the front end of the second actuator system 12b that is independently controlled from the first actuator system 12a. In addition, the preamplifier 21 and the RDC22 are provided for each actuator system 12.

[0050] Thereby, the control circuit 20 can independently control the access to the first disk 10a using the first actuator system 12a and the pair of first magnetic heads HDa, and the access to the second disk 10b using the second actuator system 12b and the pair of second magnetic heads HDb. Therefore, the control circuit 20 can execute the access using the first actuator system 12a and the access using the second actuator system 12b in parallel.

[0051] Figure 2 This is a diagram for explaining the recording surfaces of the respective disks 10 of the embodiment. The configurations of the recording surfaces of the two disks 10 are common. This figure shows one of the front and back surfaces of a certain disk 10.

[0052] On the surface of the disk 10, a recording surface 100 is provided. The recording surface 100 is divided into a plurality of storage areas 110 in a concentric circle shape centered on the rotation center of the disk 10. That is, the recording surface 100 is divided into a plurality of storage areas 110 in the radial direction. The plurality of storage areas 110 include one media cache area 120 and a plurality of bands 130. A region where data writing is prohibited, called a guard region, is provided between the storage areas 110, but the illustration of the guard region is omitted in this figure.

[0053] In Figure 2 In the example shown, the storage area 110 provided on the outermost side in the radial direction within the recording surface 100, that is, the outermost (outer) side, belongs to the media cache area 120. The position of the media cache area 120 is not limited to this. The media cache area 120 provided on one recording surface 100 is not limited to one.

[0054] In addition, the recording surface 100 has four bands 130 as the plurality of bands 130. The number of bands 130 provided on the recording surface 100 is not limited to this.

[0055] Data is written in each band 130 in the SMR (Shingled Magnetic Recording) method. Figure 3 It is a schematic diagram for explaining the writing in the SMR method executed in the disk device 1 in the embodiment.

[0056] According to SMR, when writing data to each band 130, the next track amount of data is written in a manner overlapping a part of the data of the already written one track amount. Therefore, as Figure 3 shown, the track pitch (TP) is narrower than the core width (WHw) of the writing element of the magnetic head HD. As a result, the recording density is increased.

[0057] In addition, in SMR, in order to prevent the data of the already written track from becoming difficult to read due to the writing of the data of the new track, within the band 130, the data of each track is written in any one of the direction from the outer side of the disk 10 toward the radial inner side (that is, the inner side) and the opposite direction. The writing direction in one band 130 does not change during the writing.

[0058] According to SMR, the track pitch is narrower than the core width WHw of the writing element. Therefore, if a part of the data in the plurality of tracks written in sequence in position in the SMR method is rewritten, the data in the track adjacent to the track including the data to be rewritten may be damaged. In order to prevent such data damage, the data rewriting is performed in units of bands 130.

[0059] For example, in a state where a certain tape 130 stores certain data (marked as old data), when new data corresponding to the old data is sent, the new data is temporarily stored in a storage area different from the tape 130 (for example, the media cache area 120). Moreover, when a predetermined condition is satisfied, all the data (i.e., tape data) in the tape 130 is written to the same tape or another tape 130. At this time, the old data included in the tape data is replaced with the new data. Replacement can also be described as update. The process of reading such tape data and replacing a part of the tape data with new data is marked as an update process.

[0060] In addition to being a buffer memory for data between the first RAM 24 and the host 2, the first RAM 24 also functions as a buffer memory for performing update processing. Figure 4 It is a schematic diagram for explaining various areas allocated to the first RAM 24 in the embodiment. As shown in this figure, a plurality of areas including a first cache area 241 and a second cache area 242 are allocated to the first RAM 24.

[0061] The data read from the disk 10 in response to a read command request from the host 2 through the read command is temporarily stored in the first cache area 241. In addition, the action corresponding to the read command from the host 2 is marked as host read. That is, the first cache area 241 is used for host read.

[0062] The tape data that is the object of the update process is temporarily stored in the second cache area 242.

[0063] Here, the technology compared with the embodiment is described. The technology compared with the embodiment is marked as a comparative example. In the comparative example, the control circuit individually executes the reading of the tape data from the disk for performing update processing and the reading of the data from the disk for performing host read. Therefore, even when the same data is the object of both update processing and host read, the control circuit reads the same data from the disk twice. Thus, the efficiency of reading data from the disk deteriorates.

[0064] In the embodiment, in order to improve the efficiency of reading data from the disk 10 compared with the comparative example, the control circuit 20 executes the reading of the tape data to be updated at the timing when a part or all of the reading of the tape data is requested from the host 2. Hereinafter, Figures 5 to 7 The update process of the embodiment is described.

[0065] Figure 5 It is a schematic diagram for explaining the operation of reading the tape data executed in the disk device 1 of the embodiment.

[0066] In Figure 5In the example shown, in a state where the tape data in a certain tape 130a provided in the first disk 10a is preset as an update target, the host 2 sends a read command for requesting the reading of the tape data to the disk device 1. In such a case, the control circuit 20 reads the tape data 300a stored in the tape 130a using the first actuator system 12a. The control circuit 20 stores the tape data 300a read from the tape 130a in both the first buffer area 241 and the second buffer area 242. One of the tape data 300 stored in the first buffer area 241 and the tape data 300 stored in the second buffer area 242 is a copy of the other. That is, the control circuit 20 reads the tape data 300 from the tape 130a once, copies the read tape data 300 to obtain two tape data 300, stores one of the two tape data 300 in the first buffer area 241, and stores the other of the two tape data 300 in the second buffer area 242.

[0067] Before or after the reading of the tape data 300a, at a timing, the control circuit 20 reads new data 400b for rewriting the tape data 300a from, for example, the media cache area 120 of the disk 10 and stores it in a predetermined storage area (here, as an example, the first RAM 24). When there are multiple new data for rewriting the tape data 300a, the control circuit 20 reads all the new data for rewriting the tape data 300a from the disk 10 and stores it in a predetermined storage area.

[0068] In addition, Figure 5 The data 400b shown is new data for rewriting the tape data 300a. The data 400a included in the tape data 300a is the part to be rewritten by the data 400b, that is, the old data. In Figure 5 the example shown, the old data to be rewritten does not exist outside the data 400a.

[0069] Figure 6 is a schematic diagram for explaining the operation of data update performed in the disk device 1 of the embodiment. As shown in this figure, the control circuit 20 replaces the data 400a with the data 400b for both the tape data 300a stored in the first buffer area 241 and the tape data 300a stored in the second buffer area 242. Thereby, the tape data 300a stored in the first buffer area 241 and the tape data 300a stored in the second buffer area 242 each become the tape data in the latest state ( Figure 7 the tape data 300b shown).

[0070] Figure 7 is a schematic diagram for explaining the operation after the data update of the disk device 1 of the embodiment.

[0071] The control circuit 20 sends the tape data 300b in the first buffer area 241 to the host 2. In addition, the control circuit 20 writes the tape data 300b in the second buffer area 242 to the disk 10. Here, as an example, the control circuit 20 uses the second actuator system 12b to write the tape data 300b to a certain tape 130b of the second disk 10b.

[0072] In this way, when the tape data 300a that is the object of the update process is the object to be read by the host, the control circuit 20 reads the tape data 300a from the disk 10 only once into the first RAM 24. Then, the control circuit 20 updates the tape data 300a stored in the first RAM 24, and sends the updated tape data 300b to the host 2 and writes it to the disk 10.

[0073] Thus, according to the embodiment, the number of reads is reduced compared to the comparative example. That is, the efficiency of reading data from the disk is improved compared to the comparative example.

[0074] The Figure 5 operation of reading the tape data that is both the update object and the host read object from the disk 10 once is marked as the shared read operation.

[0075] In addition, in the above description, the shared read operation is performed when the tape data that is the update object is also the object to be read by the host. The shared read operation can also be performed when a part of the tape data that is the update object is the object to be read by the host.

[0076] For example, as Figure 8 shown, when the tape data 300c is in the state of being the update object, and the data 500a in the central part of the tape data 300c is the object to be read by the host, and the data 501 and the data 502 are not the objects to be read by the host, the shared read operation can be performed on the tape data 300c. However, the data sent to the host 2 after the shared read operation is the data 500a, and the data 501 and the data 502 are not sent to the host 2.

[0077] In addition, for example, as Figure 9 shown, when both the tape data 300d and the tape data 300e are in the state of being the update object, and the data 500b from the middle of the tape data 300d across the boundary between the tape data 300d and the tape data 300e to the middle of the tape data 300e is the object to be read by the host, and the other parts ( Figure 9When the data 503 and data 504) are not objects to be read by the host, the shared read operation can be performed on the tape data 300d and the tape data 300e. After the shared read operation, the data 500b is sent to the host 2. After the shared read operation, neither the data 503 nor the data 504 is sent to the host 2.

[0078] Figure 10 It is a flowchart showing an example of an operation that is the object of the setting update process executed by the disk device 1 of the embodiment.

[0079] The control circuit 20 selects one of one or more tapes 130 in which data has been written (S101). Then, the control circuit 20 determines whether the tape data stored in the selected tape 130 satisfies the condition for executing the update process (S102).

[0080] The condition for executing the update process is arbitrarily set. In one example, the amount of old data to be rewritten included in the tape data, or the amount of new data rewritten to the tape data exceeding a threshold value can be set as the condition for executing the update process.

[0081] In another example, the condition that the elapsed time since the tape data was written to the disk 10 exceeds a threshold value can be set as the condition for executing the update process.

[0082] In another example, the condition that the number of errors occurring during the reading of the tape data exceeds a threshold value can be set as the condition for executing the update process.

[0083] When the tape data stored in the selected tape 130 does not satisfy the condition for executing the update process (S102: No), the control moves to S101, and the control circuit 20 selects another tape 130.

[0084] When the tape data stored in the selected tape 130 satisfies the condition for executing the update process (S102: Yes), the control circuit 20 sets the tape data stored in the selected tape as the object of the update process (S103). Then, the control moves to S101, and the control circuit 20 selects another tape 130.

[0085] In this way, the control circuit 20 sequentially selects one or more tapes 130 in which data is stored, and performs the process of S102 on the selected tapes 130, thereby searching for tape data that satisfies the condition for executing the update process. The control circuit 20 can set all one or more tape data that satisfy the condition for executing the update process as the object of the update process by executing Figure 10 the loop process shown.

[0086] In addition, Figure 10The execution interval and timing of the loop process shown can be arbitrarily set. The control circuit 20 can also execute the loop process shown one or more times at a timing when it does not process commands from the host 2. Figure 10 The loop process shown. The control circuit 20 can also execute it at a predetermined time interval. Figure 10 The loop process shown.

[0087] Figure 11 FIG. is a flowchart showing an example of a series of operations related to the shared reading operation performed by the disk device 1 of the embodiment.

[0088] When the control circuit 20 receives a read command from the host 2 (S201), it determines whether the data requested to be read by the read command belongs to the tape data set as the object of the update process (S202).

[0089] When the data requested to be read belongs to the tape data set as the object of the update process (S202: YES), the control circuit 20 reads new data for rewriting the tape data from the medium cache area 120 and stores it in the first RAM 24 (S203).

[0090] Next, the control circuit 20 reads the tape data from the disk 10 and stores it in the first RAM 24 (S204). More precisely, the control circuit 20 obtains two tape data including the original tape data by copying the tape data read from the disk 10. Then, the control circuit 20 stores one of the two tape data in the first cache area 241 and stores the other of the two tape data in the second cache area 242.

[0091] The control circuit 20 performs replacement using the new data on each tape data stored in the first RAM 24 (S205). That is, the control circuit 20 updates each tape data stored in the first RAM 24.

[0092] Then, the control circuit 20 performs transmission of data to the host 2 and writing to the disk 10 of the tape data (S206). In S206, the control circuit 20 transmits the data of the part of the tape data for which reading is requested in the first cache area 241 to the host 2. In addition, the control circuit 20 writes the tape data in the second cache area 242 to any tape 130 in the disk 10. Then, a series of operations is completed.

[0093] When the data requested to be read does not belong to the data with a tape that is set as an object of the update process (S202: No), the control circuit 20 reads the data requested to be read from the disk 10 and stores it in the first RAM 24 (more specifically, the first cache area 241) (S207). Then, the control circuit 20 sends the data in the first RAM 24 to the host (S208). Then, a series of operations ends.

[0094] Figure 12 It is a schematic diagram for explaining an example of the operation of the disk device 1 according to the embodiment. This figure illustrates the data stored in the first cache area 241, the data stored in the second cache area 242, the content of the operation using the first actuator system 12a, and the content of the operation using the second actuator system 12b. In addition, the horizontal axis represents the elapsed time based on the start time of the host reading (that is, when the read command is received).

[0095] In Figure 12 In the example shown, both the tape data BD1 and the tape data BD2 are the data requested to be read, and the tape data BD1 and the tape data BD2 are recorded on the first disk 10a.

[0096] First, the control circuit 20 reads the tape data BD1 from the first disk 10a using the first actuator system 12a (S301). The control circuit 20 copies the tape data BD1 read from the first disk 10a into two, stores one tape data BD1 in the first cache area 241 (S302), and stores the other tape data BD1 in the second cache area 242 (S303). The control circuit 20 sends the tape data BD1 in the first cache area 241 to the host 2 after replacement with new data (S304). In addition, the control circuit 20 writes the tape data BD1 in the second cache area 242 to any unused tape 130 of the second disk 10b using the second actuator system 12b after replacement with new data (S305). The control circuit 20 keeps the tape data BD1 in the second cache area 242 until the writing of the tape data BD1 to the second disk 10b is completed.

[0097] When the reading of the tape data BD1 using the first actuator system 12a (S301) ends, the control circuit 20 reads the tape data BD2 from the first disk 10a using the first actuator system 12a (S306). The first actuator system 12a and the second actuator system 12b can be independently driven. Therefore, the process of S306 and the process of S305 are executed in parallel. In addition, the parallel execution of process N and process M means that at least a part of the execution period of process N and the execution period of process M overlap.

[0098] The control circuit 20 copies the tape data BD2 read from the second disk 10b into two, saves one tape data BD2 in the first cache area 241 (S307), and saves the other tape data BD2 in the second cache area 242 (S308). The control circuit 20 sends the tape data BD2 in the first cache area 241 to the host 2 after replacement with new data (S309). In addition, the control circuit 20 writes the tape data BD2 in the second cache area 242 to any unused tape 130 of the second disk 10b using the second actuator system 12b after replacement with new data (S310). The control circuit 20 keeps the tape data BD2 in the second cache area 242 until the writing of the tape data BD2 to the second disk 10b is completed.

[0099] Thus, in the disk device 1 of the embodiment, the control circuit 20 can execute in parallel: the writing to the disk 10 for updating one tape data using one actuator system 12 (e.g., S305), and the shared reading operation of other tape data using the other actuator system 12 (e.g., S306).

[0100] In addition, the control circuit 20 can execute in parallel: the sending of a certain tape data stored in the first RAM 24 to the host 2 (e.g., S304), and the writing of the same tape data as the tape data to the disk 10 (e.g., S305).

[0101] There is a case where the writing of the tape data to the disk 10 fails. The control circuit 20 confirms that the data can be correctly read by reading the data of the track after narrowing the track pitch every time a predetermined amount of data (e.g., the data of one track amount) is written to the disk 10. If the data cannot be correctly read, it is regarded as a failure in writing the data. In addition, the failure pattern of the writing of the data is not limited to this. When the writing of one tape data to the disk 10 fails, the control circuit 20 retries the writing of the tape data to the disk 10.

[0102] Figure 13 It is a schematic diagram for explaining an example of the operation of the disk device 1 of the embodiment when the writing of the tape data BD1 fails. In this figure, the same steps as the Figure 12 shown operation are labeled with the Figure 12 same step numbers. In addition, for the operations that are the same as the Figure 12 shown operations, the description is omitted or briefly described.

[0103] First, the control circuit 20 is the same as Figure 12Similarly in the example shown, the processes of S301 to 304 are executed. Then, the control circuit 20 writes the tape data BD1 in the second cache area 242 to any unused tape 130 of the second disk 10b using the second actuator system 12b after replacement with new data (S305).

[0104] In S305, when the writing of the tape data BD1 to the second disk 10b fails, the control circuit 20 retries writing the tape data BD1 to the second disk 10b (S401). In S401, the control circuit 20 writes the tape data BD1 that remains un-erased in the second cache area 242 to the second disk 10b. The tape 130 to be written can be the tape 130 regarded as the writing target in S305 or any other unused tape 130. The control circuit 20 keeps the tape data BD1 in the second cache area 242 until the writing of the tape data BD1 to the first disk 10a is completed.

[0105] When the reading of the tape data BD1 using the first actuator system 12a (S301) ends, the control circuit 20 reads the tape data BD2 from the first disk 10a using the first actuator system 12a (S306). The process of S306 can be executed in parallel with the process of S305 or S401.

[0106] After S306, the control circuit 20 executes the processes of S307 to S309. In addition, after the process of S401 is completed, the control circuit 20 writes the tape data BD2 in the second cache area 242 to the second disk 10b using the second actuator system 12b (S310). The tape data BD2 can be written to any unused tape 130. The control circuit 20 executes the writing of the tape data BD2 after replacement with new data. The control circuit 20 keeps the tape data BD2 in the second cache area 242 until the writing of the tape data BD2 to the second disk 10b is completed.

[0107] In this way, in the disk device 1 of the embodiment, the control circuit 20 keeps the tape data in the second cache area 242 until the writing of the tape data to the disk 10 is completed. Therefore, even when the writing of the tape data to the disk 10 fails, the control circuit 20 can retry writing the tape data to the disk 10.

[0108] The tape data is held in the second cache area 242 until the writing to the disk 10 is completed. Therefore, the tape data in the first cache area 241 is no longer needed when the transmission of data to the host 2 is completed. The control circuit 20 invalidates the unnecessary tape data in the first cache area 241, and can use the area where the tape data is stored in the first cache area 241 for storing other tape data.

[0109] In addition, in the above description, the first RAM 24 is individually provided with the first cache area 241 for host reading and the second cache area 242 for update processing. It is also possible that one cache area is commonly used for host reading and update processing. Hereinafter, a technique in which one cache area is commonly used for host reading and update processing will be described as a modification example of the embodiment.

[0110] Figure 14 It is a schematic diagram showing an example of the operation of the disk device 1 for explaining a modification example of the embodiment. The cache area in the first RAM 24 that is commonly used for host reading and update processing is marked as the third cache area. The data stored in the third cache area, the content of the operation using the first actuator system 12a, and the content of the operation using the second actuator system 12b are illustrated in this figure. In addition, the horizontal axis is the same as Figure 12 and Figure 13 It represents the elapsed time based on the start time of host reading (that is, when the read command is received).

[0111] In addition, in Figure 14 the example shown, both the tape data BD3 and the tape data BD4 are data requested to be read, and the tape data BD3 and the tape data BD4 are recorded on the first disk 10a.

[0112] First, the control circuit 20 reads the tape data BD3 from the first disk 10a using the first actuator system 12a (S501). The control circuit 20 stores the tape data BD3 read from the first disk 10a in the third cache area (S502). The control circuit 20 transmits the tape data BD3 in the third cache area to the host 2 after replacement with new data (S503). In addition, the control circuit 20 writes the tape data BD3 in the third cache area after replacement with new data to any unused tape 130 of the second disk 10b using the second actuator system 12b (S504). The control circuit 20 keeps the tape data BD3 in the third cache area until the writing to the first disk 10a of the tape data BD3 is completed.

[0113] In S504, when the writing of the tape data BD3 to the second disk 10b fails, the control circuit 20 retries writing the tape data BD3 to the second disk 10b (S505). In S505, the control circuit 20 writes the tape data BD3 that remains un-erased and held in the third cache area to the second disk 10b. The tape 130 to be written can be the tape 130 regarded as the writing target in S504 or any other unused tape 130.

[0114] After the reading of the tape data BD3 using the first actuator system 12a (S501) is completed, the control circuit 20 reads the tape data BD4 from the first disk 10a using the first actuator system 12a (S506). The first actuator system 12a and the second actuator system 12b can be driven independently. Therefore, the process of S506 can be executed in parallel with the process of S504 or the process of S505.

[0115] The control circuit 20 stores the tape data BD4 read from the second disk 10b in the third cache area (S507). Then, the control circuit 20 sends the tape data BD4 in the third cache area to the host 2 after replacement with new data (S508). In addition, after the writing of the tape data BD3 using the second actuator system 12b (S505) is completed, the control circuit 20 writes the tape data BD4 in the third cache area after replacement with new data to any unused tape 130 of the second disk 10b using the second actuator system 12b (S509).

[0116] In this way, dedicated areas can be allocated in the first RAM 24 as a buffer memory for each of the host reading and update processes, or one area shared by the host reading and update processes can be allocated.

[0117] In addition, in the embodiment and its modification, the control circuit 20 pre-determines the tape 130 to be updated before receiving the read command by using the Figure 10 described operations. The process of determining the tape 130 to be updated can also be executed after receiving the read command. That is, the control circuit 20 can also determine, when receiving the read command, whether the tape data requested to be read by the read command satisfies the conditions for executing the update process.

[0118] In the above description, the disk device 1 having two actuator systems 12a and 12b is taken as an example for description. If the number of actuator systems provided in the disk device is one or more, the shared reading operation of the embodiment can be realized.

[0119] That is, when the data requested to be read from the host is the data determined to be updated (labeled as the first data) stored in a certain tape among multiple tapes (labeled as the first tape), the control circuit reads the first data stored in the first tape using one of the one or more actuator systems and stores it in the buffer memory. The control circuit updates the first data in the buffer memory. The control circuit sends the data requested to be read from the host among the first data in the buffer memory to the host, and writes the first data in the buffer memory to one of the multiple tapes using one of the one or more actuator systems.

[0120] Thus, compared with individually performing the reading of data from the disk for host reading and the reading of data from the disk for update processing, the number of times of reading data from the disk is reduced. That is, the efficiency of reading data from the disk can be improved.

[0121] When the disk device has two or more actuator systems, the disk device can also execute, for example, Figure 12 the processing of S305 and the processing of S306 in parallel.

[0122] That is, when the data requested to be read is the first data and the data determined to be updated (labeled as the second data) stored in another tape among the multiple tapes (labeled as the second tape), the control circuit writes the first data in the buffer memory to one of the multiple tapes using one of the multiple actuator systems (labeled as the third actuator system). Moreover, in parallel with the writing of the first data using the third actuator system, the control circuit reads the second data from the second tape using a fourth actuator system different from the third actuator system among the multiple actuator systems and stores it in the buffer memory.

[0123] Thus, by making use of two actuator systems, the execution period of the update processing can be overlapped as much as possible with the execution period of the host reading. That is to say, the disk device can execute the update processing efficiently.

[0124] In addition, the disk device can, for example, as Figure 4 shown, be equipped with a buffer memory that individually allocates a first cache area for host reading and a second cache area for update processing of tape data.

[0125] In such a case, the control circuit holds the tape data in the second cache area until the writing of the tape data is completed. When the writing of the tape data fails, the control circuit retries the writing of the tape data using the tape data held in the second cache area.

[0126] In addition, in the disk device according to the embodiment, the tape data stored in the buffer memory by sharing the read operation is sent to the host and written to the disk. The control circuit can execute the transmission of the tape data stored in the buffer memory to the host and the writing to the disk in parallel.

[0127] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention and are included in the invention described in the scope of the claims and the scope equivalent thereto.

[0128] Reference Signs Explanation

[0129] 1 Disk device, 2 Host, 10 Disk, 10a First disk, 10b Second disk, 11, 15 Rotating shaft, 12 Actuator system, 12a First actuator system, 12b Second actuator system, 13a Actuator arm, 13b Actuator arm, 14a Voice coil motor, 14b Voice coil motor, 20 Control circuit, 21, 21a, 21b Preamplifier, 22, 22a, 22b RDC, 23 DSP, 24 First RAM, 25 HDC, 26 MPU, 27 Second RAM, 100 Recording surface, 110 Storage area, 120 Media cache area, 130 Tape, 241 First cache area, 242 Second cache area, 300, 300a, 300b, 300c, 300d, 300e, BD1, BD2, BD3, BD4 Tape data, 400a, 400b, 500a, 500b, 501, 502, 503, 504 Data, HD, HDa, HDb Head.

Claims

1. A disk device, comprising: a disk having a plurality of bands, each of the plurality of bands having a storage area in which data is written in a SMR (Shingled Magnetic Recording) manner; a buffer memory; and a control circuit, the control circuit, receives a read request from the outside, when the data requested to be read is first data to be updated stored in a first band among the plurality of bands, reads the first data only once from the first band and stores it in the buffer memory, updates the first data in the buffer memory, sends the first data in the buffer memory to the outside, and writes the first data in the buffer memory to one of the plurality of bands.

2. The disk device according to claim 1, further comprising a plurality of actuator systems, each of the plurality of actuator systems having a magnetic head at the front end, the control circuit, when the data requested to be read is second data to be updated stored in a second band different from the first band among the plurality of bands and the first data, uses a first actuator system which is one of the plurality of actuator systems to write the first data in the buffer memory to one of the plurality of bands, and in parallel with the writing of the first data using the first actuator system, uses a second actuator system different from the first actuator system among the plurality of actuator systems to read the second data from the second band and store it in the buffer memory.

3. The disk device according to claim 1 or 2, the buffer memory includes a first cache area and a second cache area, the control circuit obtains two pieces of first data by copying the first data read from the first band, stores a third data which is one of the two pieces of first data in the first cache area, stores a fourth data which is the other of the two pieces of first data in the second cache area, sends the third data in the first cache area to the outside, and writes the fourth data in the second cache area to one of the plurality of bands.

4. The disk device according to claim 3, when the writing of the fourth data fails, the control circuit retries the writing of the fourth data and holds the fourth data in the second cache area until the writing of the fourth data is completed.

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