Multiphase switching converter, control circuit and fault detection method thereof

Abstract

The present invention discloses a multi-phase switching converter and its control circuit and fault detection method. The multi-phase switching converter includes a plurality of switching circuits with output ends, and the output ends of the plurality of switching circuits are coupled together to supply power to a load. The fault detection method includes: comparing a current sampling signal representing a current flowing through a corresponding phase switching circuit with a current reference signal to generate a corresponding comparison signal; detecting the duration of the comparison signal maintaining a first state to generate a corresponding duration detection signal; generating a first mode signal indicating whether the corresponding phase switching circuit is performing power operation and a second mode signal indicating operation in DCM or CCM; and generating a corresponding fault signal based on the duration detection signal, the first and second mode signals to determine whether the corresponding phase switching circuit is faulty. The fault detection method can accurately detect whether each phase switching circuit in a multi-phase switching converter under different operating modes is faulty.

Description

Technical Field

[0001] The invention relates to electronic circuits, and in particular to a multi-phase switching converter and a control circuit and a fault detection method thereof. Background Art

[0002] Multiphase switching converters have been widely used due to their superior performance. In the operation process of multiphase switching converters, in order to optimize efficiency, automatic phase shedding is usually performed, and the number of phases for power operation is determined according to the size of the load current. For example, as the load current increases, the multiphase switching converter can operate in a variety of different operating modes such as one-phase DCM (Discontinuous Conduction Mode), one-phase CCM (Continuous Conduction Mode) or multi-phase CCM. In some applications with high reliability requirements, such as CPU power supplies, it is very important to accurately detect that a phase or some phase switching circuits in a multiphase switching converter have failed and take corresponding measures so that the entire circuit can continue to work. Therefore, how to quickly and accurately detect whether a multiphase switching converter in different operating modes has failed is an urgent problem to be solved. Summary of the invention

[0003] In view of the problems existing in the prior art, the present invention proposes a multi-phase switching converter and a control circuit and a fault detection method thereof to detect whether a fault occurs in each phase switching circuit of the multi-phase converter in different working modes.

[0004] According to one embodiment of the present invention, a control circuit for a multi-phase switching converter is disclosed. The multi-phase switching converter includes a plurality of switching circuits having output terminals, the output terminals of the plurality of switching circuits being coupled together to supply power to a load, and the control circuit includes: a comparison circuit including a plurality of comparison units, each of which receives a current sampling signal representing a current flowing through a corresponding phase switching circuit, and compares the current sampling signal with a current reference signal to generate a corresponding comparison signal; a duration detection circuit including a plurality of duration detection units, each of which is coupled to a corresponding comparison unit to receive a comparison signal, and detects the duration for which the comparison signal maintains a first state, and generates a corresponding duration detection signal; and a mode judgment circuit, which generates a comparison signal. Generate multiple first mode signals respectively indicating whether the corresponding phase switch circuit is performing power operation and multiple second mode signals respectively indicating that the corresponding phase switch circuit is operating in DCM or CCM; a fault judgment circuit, including multiple fault judgment units, each fault judgment unit is coupled to the corresponding duration detection unit to receive the duration detection signal, and is coupled to the mode judgment circuit to receive the corresponding first mode signal and the second mode signal, the fault judgment unit generates a corresponding fault signal based on the duration detection signal, the first mode signal and the second mode signal; and a switch control circuit, coupled to the fault judgment circuit to receive multiple fault signals, and generates multiple switch control signals based on the multiple fault signals to control the operation of the multiple switch circuits.

[0005] According to another embodiment of the present invention, a multi-phase switching converter is disclosed, wherein the multi-phase switching converter includes: a plurality of switching circuits, each switching circuit having an output end, the output ends of the plurality of switching circuits being coupled together to supply power to a load; and the control circuit as described above.

[0006] According to another embodiment of the present invention, a fault detection method for a multi-phase switching converter is disclosed, the multi-phase switching converter includes a plurality of switching circuits having output ends, the output ends of the plurality of switching circuits are coupled together to supply power to a load, the fault detection method includes: comparing a current sampling signal representing a current flowing through a corresponding phase switching circuit with a current reference signal to generate a corresponding comparison signal; detecting a time length for which the comparison signal maintains a first state to generate a corresponding time length detection signal; generating a first mode signal indicating whether the corresponding phase switching circuit is performing power operation and a second mode signal indicating that the corresponding phase switching circuit is operating in DCM or CCM; and generating a corresponding fault signal based on the time length detection signal, the first mode signal, and the second mode signal to determine whether a fault occurs in the corresponding phase switching circuit.

[0007] According to the embodiment of the present invention, it is possible to accurately detect whether a fault occurs in a switching circuit of each phase in a multi-phase switching converter in different working modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to better understand the present invention, the present invention will be described in detail according to the following drawings:

[0009] Figure 1 is a block diagram of a multi-phase switching converter 100 according to an embodiment of the present invention;

[0010] Figure 2 is a circuit schematic diagram of a multi-phase switching converter 100A according to an embodiment of the present invention;

[0011] Figure 3 is a circuit schematic diagram of a multi-phase switching converter 100B according to yet another embodiment of the present invention;

[0012] Figure 4 is a circuit schematic diagram of a control circuit 102C according to an embodiment of the present invention;

[0013] Figure 5 is a flowchart of a fault judgment unit 107-i according to an embodiment of the present invention;

[0014] Figure 6 is a flowchart of a fault judgment unit 107-i according to another embodiment of the present invention;

[0015] Fig. 7A is a working waveform diagram 700A of the multi-phase switching converter 100 according to an embodiment of the present invention;

[0016] Figure 7B is a working waveform diagram 700B of the multi-phase switching converter 100 according to yet another embodiment of the present invention;

[0017] Figure 8 FIG. 8 is a flow chart of a fault detection method 800 for a multi-phase switching converter 100 according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] Specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described here are only used for illustration and are not intended to limit the present invention. In the following detailed description of the present invention, a large number of details are described in order to better understand the present invention. However, it will be appreciated by those skilled in the art that the present invention can be implemented without these specific details. In order to clearly describe the present invention, the detailed description of some specific structures and functions is simplified herein. In addition, similar structures and functions that have been described in detail in some embodiments will not be repeated in other embodiments. Although the various terms of the present invention are described one by one in conjunction with specific exemplary embodiments, these terms should not be construed as being limited to the exemplary implementations described herein.

[0019] Throughout the specification, references to "one embodiment", "an embodiment", "an example" or "an example" mean that a particular feature, structure or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment", "in an embodiment", "an example" or "an example" that appear in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, particular features, structures or characteristics may be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes and that the drawings are not necessarily drawn to scale. It should be understood that when an "element" is said to be "connected to" or "coupled" to another element, it may be directly connected or coupled to another element or there may be an intermediate element. In contrast, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The same reference numerals indicate the same element. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0020] Figure 1 1 is a block diagram of a multiphase switching converter 100 according to an embodiment of the present invention. The multiphase switching converter 100 includes a multiphase power conversion circuit 101 and a control circuit 102. The multiphase power conversion circuit 101 includes N switching circuits, where N is an integer greater than or equal to 2. The input ends of the N switching circuits receive an input voltage Vin, and the output ends are coupled together to provide an output voltage Vout to a load. The switching circuit in the multiphase power conversion circuit 101 can adopt any DC / DC or AC / DC conversion topology, such as a synchronous or asynchronous boost, buck converter, and a forward, flyback converter, etc.

[0021] exist Figure 1 In the illustrated embodiment, the multiphase power conversion circuit 101 includes three switch circuits 101-1 to 101-3 to form a three-phase switching converter. It will be appreciated by those skilled in the art that the multiphase power conversion circuit 101 may also include switch circuits having any other number to form a multiphase switching converter having any other number of phases. In one embodiment, each switch circuit 101-i (i=1, 2, 3) is a single integrated circuit chip.

[0022] Each switch circuit 101-i has a plurality of pins, including a pin VIN for receiving an input voltage Vin, a pin VOUT for providing an output voltage Vout, a pin CS for reporting current information, and a pin PWM for receiving a switch control signal. Each switch circuit 101-i includes a power switch having a first end coupled to the pin VIN and a second end coupled to the pin VOUT through an energy storage element, wherein the power switch connects the pin VIN to the pin VOUT through the energy storage element when the first switch circuit is enabled. The pin CS is used to report information about the current flowing through the switch circuit 101-i.

[0023] exist Figure 1 In the illustrated embodiment, the control circuit 102 has a plurality of pins, including pins CS1 to CS3 for receiving current information, pins PWM1 to PWM3 for providing switch control signals, and an output voltage detection pin VOSEN. The pins CS1 to CS3 of the control circuit 102 are respectively coupled to the pins CS of the switch circuits 101-1 to 101-3 to receive current information representing the current flowing through the switch circuits 101-1 to 101-3, wherein the current information may represent the current flowing through the energy storage element in the switch circuit or the current flowing through the power switch.

[0024] Figure 2 FIG. 1 is a circuit diagram of a multi-phase switching converter 100A according to an embodiment of the present invention. Figure 2 As shown, the multi-phase switching converter 100A includes a multi-phase power conversion circuit 101A and a control circuit 102A. Figure 2 In the illustrated embodiment, the multiphase power conversion circuit 101A includes three-phase switching circuits, namely, switching circuits 101A-1 to 101A-3. It is understood that in other embodiments, the multiphase power conversion circuit 101A may include any number of switching circuits.

[0025] Each switch circuit 101A-i has the same circuit structure. In one embodiment, each switch circuit 101A-i has a pin VIN, a pin VOUT, a pin CS for outputting current information, and a pin PWM for receiving a switch control signal, and also includes at least one power switch (e.g., a high-side power switch HS and a low-side power switch LS) and a drive circuit for driving the power switch. The drive circuit can control the on and off of the power switch. In one embodiment, when the switch circuit is enabled, the high-side power switch HS is connected to the input power supply of the pin VIN, and is connected to the load connected to the pin VOUT through the inductor L.

[0026] exist Figure 2In the illustrated embodiment, the control circuit 102A has at least pins CS1 to CS3 for receiving current information of the switch circuit 101A, a pin VOSEN for receiving output voltage Vout information, and pins PWM1 to PWM3 for providing switch control signals. In addition, the control circuit 102A also includes a current information circuit 103, a comparison circuit 104, a duration detection circuit 105, a mode judgment circuit 106, a fault judgment circuit 107, and a switch control circuit 108.

[0027] Pins CS1 to CS3 of the control circuit 102A are respectively coupled to pins CS of the switch circuits 101A-1 to 101A-3 to receive current information from the switch circuits 101A-1 to 101A-3. The current information circuit 103 generates current sampling signals ics1 to ics3 representing the current flowing through the corresponding phase switch circuits based on the received current information. In one embodiment, the current information circuit 103 also generates a load current signal ISEN representing the load current. In one embodiment, the current information circuit 103 sums, filters, and scales up / down the current sampling signals ics1 to ics3 to obtain the load current signal ISEN.

[0028] exist Figure 2 In the illustrated embodiment, the comparison circuit 104 is coupled to the current information circuit 103 to receive the current sampling signals ics1-ics3, and compares the current sampling signals ics1-ics3 with the current reference signals iref1-iref3 respectively to generate comparison signals Ca1-Ca3, wherein the comparison signals Ca1-Ca3 have a first state and a second state.

[0029] The duration detection circuit 105 is coupled to the comparison circuit 104 to receive the comparison signals Ca1-Ca3, and respectively detects the duration of the comparison signals Ca1-Ca3 maintaining the first state, and generates duration detection signals Td1-Td3. In one embodiment, each duration detection signal Tdi is a numerical value representing the duration of the comparison signal Cai maintaining the first state. In another embodiment, each duration detection signal Tdi is a pulse signal, and the pulse width thereof represents the duration of the comparison signal Cai maintaining the first state.

[0030] The mode determination circuit 106 generates first mode signals Mo1-1 to Mo1-3 and second mode signals Mo2-1 to Mo2-3, wherein the first mode signals Mo1-1 to Mo1-3 respectively indicate whether the switch circuits 101A-1 to 101A-3 are in power operation, and the second mode signals Mo2-1 to Mo2-3 respectively indicate whether the switch circuits 101A-1 to 101A-3 are in DCM or CCM. In one embodiment, each first mode signal Mo1-i (i=1, 2, 3) and each second mode signal Mo2-i are one-bit digital signals stored in a register.

[0031] In one embodiment, the mode determination circuit 106 generates the first mode signals Mo1-1 to Mo1-3 and the second mode signals Mo2-1 to Mo2-3 according to the received instructions. For example, the multi-phase switching converter 100A determines whether each phase switching circuit performs power operation and whether each phase switching circuit operates in DCM or CCM according to the instructions sent by the CPU or GPU.

[0032] In another embodiment, the mode determination circuit 106 generates the first mode signals Mo1-1 to Mo1-3 and the second mode signals Mo2-1 to Mo2-3 according to the load current signal ISEN. For example, the mode determination circuit 106 compares the load current signal ISEN with the threshold voltages Vth_1ph to Vth_3ph respectively to determine whether each phase switch circuit performs power operation and whether each phase switch circuit operates in DCM or CCM. In a further embodiment, the comparison of the load current signal ISEN with the threshold voltages Vth_1ph to Vth_3ph respectively includes hysteresis comparison. According to the comparison result, the operation mode of the multi-phase switching converter 100A is shown in the following table, where VHYS is the hysteresis voltage.

[0033] condition Working Mode ISEN>Vth_3ph+VHYS 3-phase CCM Vth_2ph+VHYS<ISEN≤Vth_3ph 2-phase CCM Vth_1ph+VHYS<ISEN≤Vth_2ph 1-phase CCM ISEN≤Vth_1ph 1-phase DCM or multi-phase DCM

[0034] The fault judgment circuit 107 is coupled to the duration detection circuit 105 to receive the duration detection signals Td1~Td3, and is also coupled to the mode judgment circuit 106 to receive the first mode signals Mo1-1~Mo1-3 and the second mode signals Mo2-1~Mo2-3, and generates fault signals Fault1~Fault3 based on the duration detection signals Td1~Td3, the first mode signals Mo1-1~Mo1-3 and the second mode signals Mo2-1~Mo2-3.

[0035] The switch control circuit 108 is coupled to the fault determination circuit 107 to receive the fault signals Fault1 - Fault3 , and generates switch control signals PWM1 - PWM3 based on the fault signals Fault1 - Fault3 to control the operations of the switch circuits 101A- 1 - 101A- 3 , respectively.

[0036] Although Figure 2 The switch circuit in the illustrated embodiment adopts a synchronous buck topology, but this is not intended to limit the present invention, and other suitable topologies are also applicable.

[0037] Figure 3 FIG. 1 is a circuit schematic diagram of a multi-phase switching converter 100B according to another embodiment of the present invention. Different from the control circuit 102A, the control circuit 102B further includes a reference current generating circuit 109 for generating current reference signals iref1 to irefN. In one embodiment, the current reference signals iref1 to irefN are preset according to actual applications. In another embodiment, the current reference signals iref1 to irefN are changed and updated in real time according to the working process of the multi-phase switching converter 100B.

[0038] The control circuit 102B also includes a transient detection circuit 110 for generating an enable signal En. When the transient detection circuit 110 detects that the multi-phase switching converter 100B is in a transient state, the enable signal En is in an invalid state, and fault detection is stopped. In a further embodiment, when the enable signal En is in an invalid state, the comparison circuit 104, the duration detection circuit 105, the fault judgment circuit 107, and the reference current generation circuit 109 are not enabled, and fault detection of the multi-phase switching converter 100B is not performed. In one embodiment, the multi-phase switching converter 100B is in a transient state when the load jumps and a period of time after the load jump ends.

[0039] Figure 4 FIG. 1 is a circuit diagram of a control circuit 102C according to an embodiment of the present invention. Figure 4 As shown, pins CS1-CS3 of the control circuit 102C receive current information from the switch circuits 101-1-101-3 respectively. The current information circuit 103 generates current sampling signals ics1-ics3 representing the current flowing through the switch circuits 101-1-101-3 based on the current information.

[0040] The comparison circuit 104 includes comparison units 104-1 to 104-3, and each comparison unit 104-i compares the current sampling signal icsi with the current reference signal irefi to generate a comparison signal Cai. In one embodiment, each comparison unit 104-i includes a comparator CMP, which provides a comparison signal Cai at its output terminal based on the current sampling signal icsi and the current reference signal irefi. In one embodiment, the comparator CMP receives the current sampling signal icsi at its non-inverting input terminal and receives the current reference signal irefi at its inverting input terminal, wherein when the current sampling signal icsi is greater than the current reference signal irefi, the comparison signal Cai has a first state (e.g., a high level state); when the current sampling signal icsi is less than the current reference signal irefi, the comparison signal Cai has a second state (e.g., a low level state). In another embodiment, the non-inverting input terminal of the comparator CMP receives a current reference signal irefi, and the inverting input terminal receives a current sampling signal icsi, wherein when the current sampling signal icsi is greater than the current reference signal irefi, the comparison signal Cai has a first state (e.g., a low level state); when the current sampling signal icsi is less than the current reference signal irefi, the comparison signal Cai has a second state (e.g., a high level state).

[0041] The duration detection circuit 105 includes duration detection units 105-1 to 105-3, each duration detection unit 105-i is coupled to a corresponding comparison unit 104-i to receive a comparison signal Cai, and detects the duration for which the comparison signal Cai maintains the first state, and generates a duration detection signal Tdi. In one embodiment, each duration detection unit 105-i includes a timer, which counts the time for which the comparison signal Cai maintains the first state, and generates a duration detection signal Tdi.

[0042] The mode determination circuit 106 generates first mode signals Mo1-1-Mo1-3 indicating whether the switch circuits 101-1-101-3 are operating in power mode and second mode signals Mo2-1-Mo2-3 indicating whether the switch circuits 101-1-101-3 are operating in DCM or CCM.

[0043] The fault judgment circuit 107 includes fault judgment units 107-1 to 107-3. Each fault judgment unit 107-i is coupled to the corresponding duration detection unit 105-i to receive the duration detection signal Tdi, and is coupled to the mode judgment circuit 106 to receive the corresponding first mode signal Mo1-i and second mode signal Mo2-i. The fault judgment unit 107-i generates a fault signal Faulti based on the duration detection signal Tdi, the first mode signal Mo1-i and the second mode signal Mo2-i.

[0044] In one embodiment, the fault judgment unit 107-i includes a comparator CP. When the first mode signal Mo1-i indicates that the i-phase switch circuit is in power operation, and the second mode signal Mo2-i indicates that the i-phase switch circuit is operating in CCM, the comparator CP compares the duration detection signal Tdi with the first time threshold Tth1 and the second time threshold Tth2, respectively, and judges whether the i-phase switch circuit is faulty based on the comparison result. When the first mode signal Mo1-i indicates that the i-phase switch circuit is in power operation, and the second mode signal Mo2-i indicates that the i-phase switch circuit is operating in DCM, the comparator CP compares the duration detection signal Tdi with the first time threshold Tth1 and the third time threshold Tth3, respectively, and judges whether the i-phase switch circuit is faulty based on the comparison result.

[0045] In one embodiment, each fault judgment unit 107-i also receives a switching cycle signal Ts, and calculates the ratio of the duration detection signal Tdi to the switching cycle signal Ts to generate a duty cycle signal Di. The fault judgment unit 107-i generates a fault signal Faulti based on the duty cycle signal Di, the first mode signal Mo1-i and the second mode signal Mo2-i, wherein the switching cycle signal Ts represents the switching cycle of the corresponding phase switching circuit when operating in CCM.

[0046] In one embodiment, the duration detection signal Tdi is the average of the duration that the comparison signal Cai maintains the first state in multiple switching cycles. For example, when the i-th phase switching circuit performs power operation, multiple duration signals are generated in multiple switching cycles, and the multiple duration signals are filtered using a sliding average filter to generate the duration detection signal Tdi, wherein each of the multiple duration signals represents the duration that the comparison signal Cai maintains the first state in a corresponding switching cycle.

[0047] The switch control circuit 108 is coupled to the fault determination circuit 107 to receive the fault signals Fault1 - Fault3 , and generates switch control signals PWM1 - PWM3 based on the fault signals Fault1 - Fault3 to control the operation of the switch circuits 101 - 1 - 101 - 3 .

[0048] In one embodiment, the reference current generating circuit 109 includes filters 109 - 1 to 109 - 3 , and each filter 109 - i filters the current sampling signal icsi to remove the high frequency portion of the current sampling signal icsi to generate a current reference signal irefi.

[0049] In one embodiment, the comparison circuit 104, the duration detection circuit 105, the fault judgment circuit 107 and the reference current generating circuit 109 all have N sub-units, which correspond to the N-phase switching circuits of the N-phase switching converter one by one. For example, the comparison circuit 104 includes N comparison units 104-1 to 104-N, which receive the current sampling signals ics1 to icsN of the N-phase switching circuits respectively and generate comparison signals Ca1 to Ca2. The fault judgment circuit 107 includes N fault judgment units 107-1 to 107-N, which judge whether the N-phase switching circuits have faults respectively.

[0050] In another embodiment, the above circuit has less than N sub-units, for example, the fault judgment circuit 107 includes M fault judgment units 107-1~107-M, where M is less than N, and the M fault judgment units 107-1~107-M are time-division multiplexed to determine whether a fault occurs in the N-phase switching circuit.

[0051] Although the aforementioned multi-phase switching converters are described by taking a three-phase switching converter as an example, a person skilled in the art should understand that the present invention is applicable to switching converters with any number of phases.

[0052] Figure 5 FIG. 1 is a flowchart of the fault judgment unit 107-i according to an embodiment of the present invention. Figure 5 As shown, the workflow diagram includes steps S501 to S509.

[0053] In step S501, determine whether the i-th phase switch circuit is performing power operation, if so, proceed to step S503; otherwise, proceed to step S502.

[0054] In step S502, fault detection of the i-th phase switching circuit is not performed.

[0055] In step S503, it is determined whether the i-th phase switch circuit operates in CCM. If so, the process goes to step S504; otherwise, the process goes to step S505.

[0056] In step S504, it is determined whether the duration detection signal Tdi is between the first time threshold Tth1 and the second time threshold Tth2. If so, the process proceeds to step S506; otherwise, the process proceeds to step S507.

[0057] In step S506, it is determined that no fault occurs in the phase switch circuit.

[0058] In step S507, it is determined whether a fault occurs in the phase switch circuit.

[0059] In step S505, the i-th phase switch circuit operates in DCM to determine whether the duration detection signal Tdi is between the first time threshold Tth1 and the third time threshold Tth3. If so, proceed to step S508; otherwise, proceed to step S509.

[0060] In step S508, it is determined that no fault occurs in the phase switch circuit.

[0061] In step S509, it is determined whether a fault occurs in the phase switch circuit.

[0062] In one embodiment, the first time threshold Tth1 = tc-to, the second time threshold Tth2 = tc+to, and the third time threshold Tth3 = 2*tc. Among them, the time reference value tc = 1 / 2*Ts, Ts represents the switching period when the corresponding phase switch circuit works in CCM, Ts can be preset according to the actual application, and can also be changed and updated in real time with the working process of the multi-phase switching converter. The time offset value to can be set according to the actual application situation, and can also be changed by programming.

[0063] Figure 6 FIG. 1 is a flowchart of a fault judgment unit 107-i according to another embodiment of the present invention. Figure 6 As shown, the workflow diagram includes steps S601 to S610.

[0064] In step S601, determine whether the i-th phase switch circuit is performing power operation, if so, proceed to step S603; otherwise, proceed to step S602.

[0065] In step S602, fault detection of the i-th phase switching circuit is not performed.

[0066] In step S603, the ratio of the duration detection signal Tdi and the switching period signal Ts is calculated to generate a duty cycle signal Di, wherein Ts represents the switching period when the corresponding phase switching circuit operates in CCM.

[0067] In step S604, it is determined whether the i-th phase switch circuit operates in CCM. If so, the process proceeds to step S605; otherwise, the process proceeds to step S606.

[0068] In step S605, it is determined whether the duty cycle signal Di falls within the first range, if so, the process goes to step S607; otherwise, the process goes to step S608.

[0069] In step S607, it is determined that no fault occurs in the phase switch circuit.

[0070] In step S608, it is determined whether a fault occurs in the phase switch circuit.

[0071] In step S606, the i-th phase switch circuit operates in DCM to determine whether the duty cycle signal Di falls within the second range. If so, proceed to step S609; otherwise, proceed to step S610.

[0072] In step S609, it is determined that no fault occurs in the phase switch circuit.

[0073] In step S610, it is determined whether a fault occurs in the phase switch circuit.

[0074] In one embodiment, the first range is (0.5-Δ, 0.5+Δ), and the second range is (0.5-Δ, 1), where Δ can be set according to the actual situation of the user and can also be changed by programming.

[0075] Fig. 7A FIG. 700 is a working waveform diagram 700A of the multi-phase switching converter 100 according to an embodiment of the present invention. Fig. 7A Taking a two-phase switching converter as an example, the duration detection signals Td1 and Td2 respectively represent the values ​​of the duration of the comparison signals Ca1 and Ca2 maintaining the first state (high level state). In the time period t1 to t2, the first phase switch circuit performs power operation and works in DCM, and the duration detection signal Td1 is between the first time threshold Tth1 and the third time threshold Tth3, so it is judged that the first phase switch circuit has not failed. After the moment t3, the first phase switch circuit works in CCM, and the duration detection signal Td1 is between the first time threshold Tth1 and the second time threshold Tth2, and it is judged that the first phase switch circuit has not failed. Similarly, after the moment t4, the second phase switch circuit performs power operation and works in CCM, and the duration detection signal Td2 is between the first time threshold Tth1 and the second time threshold Tth2, and it is judged that the second phase switch circuit has not failed.

[0076] Figure 7B FIG7 is a working waveform diagram 700B of a multi-phase switching converter 100 according to another embodiment of the present invention. The duration detection signals Td1 and Td2 are respectively numerical values ​​indicating the duration of the comparison signals Ca1 and Ca2 maintaining the first state (high level state). As shown in FIG7 , in the time period t1 to t2, the first phase switch circuit performs power operation and operates in DCM, and the duration detection signal Td1 is less than the first time threshold Tth1, so it is determined that the first phase switch circuit has a fault. After time t4, the second phase switch circuit performs power operation and operates in CCM. At this time, the duration detection signal Td2 is zero, which is less than the first time threshold Tth1, so it is determined that the second phase switch circuit has a fault.

[0077] Figure 81 is a flow chart of a fault detection method 800 for a multi-phase switching converter 100 according to an embodiment of the present invention. The multi-phase switching converter 100 includes a plurality of switching circuits having output terminals, and the output terminals of the plurality of switching circuits are coupled together to supply power to a load. The fault detection method 800 includes steps S801 to S804.

[0078] In step S801 , a current sampling signal representing a current flowing through a corresponding phase switch circuit is compared with a current reference signal to generate a corresponding comparison signal.

[0079] In step S802, the duration that the comparison signal maintains the first state is detected, and a corresponding duration detection signal is generated.

[0080] In step S803, a first mode signal indicating whether the corresponding phase switch circuit performs power operation and a second mode signal indicating whether the corresponding phase switch circuit operates in DCM or CCM are generated.

[0081] In step S804, a corresponding fault signal is generated based on the duration detection signal, the first mode signal and the second mode signal to determine whether a fault occurs in the corresponding phase switch circuit.

[0082] Note that in the flowchart described above, the functions marked in the blocks may also occur in an order different from that shown in the figure. For example, two blocks represented in succession may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the specific functions involved.

[0083] In the specification and claims of the present application, relevant terms such as first and second, etc. may be used only to distinguish one entity or action from another entity or action, without necessarily or implying the existence of such an order between these entities or actions. Numerical sequences such as first, second and third, etc., refer only to different individuals in a plurality and do not imply any order or sequence unless specifically defined in the claim language. The order of the text in any claim does not mean that the processing steps must be performed in such an order or logical order unless specifically defined in the claim language. Without departing from the scope of the present invention, these processing steps may be interchanged in any order, as long as such interchange does not cause the claim language to contradict and does not appear logically absurd.

[0084] Although the present invention has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present invention can be embodied in a variety of forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A control circuit for a multi-phase switching converter, the multi-phase switching converter comprising a plurality of switching circuits having output terminals, the output terminals of the plurality of switching circuits being coupled together to supply power to a load, the control circuit comprising: A comparison circuit, comprising a plurality of comparison units, each comparison unit receiving a current sampling signal representing a current flowing through a corresponding phase switch circuit, and comparing the current sampling signal with a current reference signal to generate a corresponding comparison signal; The duration detection circuit includes a plurality of duration detection units, each of which is coupled to a corresponding comparison unit to receive a comparison signal, and detects a duration for which the comparison signal maintains a first state, and generates a corresponding duration detection signal; A mode determination circuit generates a plurality of first mode signals respectively indicating whether the corresponding phase switch circuit is operating in power mode and a plurality of second mode signals respectively indicating whether the corresponding phase switch circuit is operating in DCM or CCM; A fault judgment circuit includes a plurality of fault judgment units, each of which is coupled to a corresponding duration detection unit to receive a duration detection signal, and is coupled to a mode judgment circuit to receive a corresponding first mode signal and a second mode signal, and the fault judgment unit generates a corresponding fault signal based on the duration detection signal, the first mode signal and the second mode signal; as well as The switch control circuit is coupled to the fault judgment circuit to receive a plurality of fault signals and generates a plurality of switch control signals based on the plurality of fault signals to control the operation of the plurality of switch circuits.

2. The control circuit according to claim 1, wherein: When the corresponding phase switch circuit performs power operation and works in CCM, the corresponding fault judgment unit compares the corresponding duration detection signal with the first time threshold and the second time threshold respectively, and judges whether the corresponding phase switch circuit fails based on the comparison result.

3. The control circuit as described in claim 2, wherein the first time threshold is equal to the difference between the time reference value and the time offset value, and the second time threshold is equal to the sum of the time reference value and the time offset value, wherein the time reference value is half of the switching period when the corresponding phase switching circuit operates in CCM.

4. The control circuit according to claim 1, wherein: When the corresponding phase switch circuit performs power operation and works in DCM, the corresponding fault judgment unit compares the corresponding duration detection signal with the first time threshold and the third time threshold respectively, and judges whether the corresponding phase switch circuit fails based on the comparison result.

5. The control circuit as claimed in claim 4, wherein the first time threshold is equal to the difference between the time reference value and the time offset value, and the third time threshold is equal to twice the time reference value, wherein the time reference value is half of the switching period when the corresponding phase switching circuit operates in CCM.

6. The control circuit of claim 1, wherein each fault judgment unit further receives a switching cycle signal representing a switching cycle of a corresponding phase switching circuit when the corresponding phase switching circuit operates in CCM, and calculates a ratio of a corresponding duration detection signal to the switching cycle signal to generate a corresponding duty cycle signal, wherein: When the corresponding phase switch circuit performs power operation and works in CCM, the corresponding fault judgment unit judges whether the corresponding duty cycle signal falls within the first range, and determines whether the corresponding phase switch circuit fails based on the judgment result. 7 . The control circuit as claimed in claim 1 , wherein the duration detection signal is an average value of durations during which the corresponding comparison signal maintains the first state in a plurality of consecutive switching cycles.

8. A multi-phase switching converter, wherein the multi-phase switching converter comprises: A plurality of switch circuits, each of which has an output terminal, and the output terminals of the plurality of switch circuits are coupled together to supply power to a load; as well as A control circuit as claimed in any one of claims 1 to 7.

9. A fault detection method for a multi-phase switching converter, the multi-phase switching converter comprising a plurality of switching circuits having output terminals, the output terminals of the plurality of switching circuits being coupled together to supply power to a load, the fault detection method comprising: comparing a current sampling signal representing a current flowing through a corresponding phase switch circuit with a current reference signal to generate a corresponding comparison signal; Detecting the duration of the comparison signal maintaining the first state, and generating a corresponding duration detection signal; generating a first mode signal indicating whether the corresponding phase switch circuit is in power operation and a second mode signal indicating whether the corresponding phase switch circuit is in DCM or CCM; as well as A corresponding fault signal is generated based on the duration detection signal, the first mode signal and the second mode signal to determine whether a fault occurs in the corresponding phase switch circuit.

10. The fault detection method according to claim 9, wherein: When the corresponding phase switch circuit performs power operation and works in CCM, the corresponding duration detection signal is compared with the first time threshold and the second time threshold respectively, and whether the corresponding phase switch circuit fails is determined based on the comparison result.

11. The fault detection method according to claim 9, wherein: When the corresponding phase switch circuit performs power operation and works in DCM, the corresponding duration detection signal is compared with the first time threshold and the third time threshold respectively, and it is determined whether the corresponding phase switch circuit fails based on the comparison result.

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