memory and dynamic random access memory

Abstract

A storage bank and dynamic random access memory, the storage bank comprising: N latch circuits, N word line address decoding circuits and a dynamic random access memory (DRAM) memory array, the latch circuits can be arranged in the storage bank (Bank), and the latch circuits can enable the word line address decoding circuits in the Bank to perform different activation operations according to different enable signals from a controller. Wherein, when the latch circuit receives an in-memory operation mode enable signal from the controller, a plurality of word line address decoding circuits in the Bank can be enabled to activate the word lines in the corresponding sub-array, and in turn the word lines in a plurality of sub-arrays can be activated at the same time to realize the bit logical inversion of a batch of sub-arrays in the Bank.

Description

Technical Field

[0001] This application relates to the field of memory, and more particularly to a storage repository and dynamic random access memory. Background Technology

[0002] In-memory computation refers to computation performed directly within memory. Because it eliminates the need for data exchange between the processor and memory, in-memory computation saves on latency and energy consumption. Bitwise NOT is a fundamental operator in in-memory computation and is called multiple times during the computation process. Batch bitwise NOT operations can improve computational efficiency and increase the intra-die bandwidth of memory.

[0003] Current dynamic random access memory (DRAM) consists of multiple banks, each containing multiple memory cells. Each memory cell is a 1T-1C structure consisting of a transistor and a capacitor. Currently, a transistor can be added to the memory cell to form a 2T-1C structure. When this newly added transistor is turned on, the bit lines in the memory cell can charge or discharge the capacitor, increasing or decreasing the charge in the capacitor. This enables bit logic inversion operations within the memory cell, allowing for batch bit logic inversion operations across the entire bank.

[0004] If the demand repository implements a batch bit logic inversion operation, a transistor can be added to each memory cell in the repository, resulting in a mixture of 1T-1C and 2T-1C structures in the DRAM repository, which in turn causes poor consistency in the DRAM process technology. Summary of the Invention

[0005] This application provides a bank and a dynamic random access memory that can simultaneously activate word lines in multiple DRAM subarrays, thereby enabling bit logic inversion operations on batch subarrays in the bank.

[0006] In a first aspect, embodiments of this application provide a storage bank, Bank, comprising: N latch circuits, N word line address decoding circuits, and a dynamic random access memory (DRAM) array. The DRAM array comprises N subarrays, with adjacent subarrays connected. Each latch circuit, word line address decoding circuit, and subarray corresponds one-to-one. Each latch circuit is connected to its corresponding word line address decoding circuit, and each word line address decoding circuit is connected to its corresponding subarray via a word line in that subarray. N is an integer greater than or equal to 1.

[0007] In this embodiment, the target word lines in multiple subarrays can be activated simultaneously. That is, for each of at least three adjacent subarrays, the first latch circuit and the first word line address decoding circuit corresponding to each subarray are activated simultaneously, wherein:

[0008] The first latch circuit is used to send a multi-subarray word line activation signal to the corresponding first word line address decoding circuit according to the in-memory operation mode enable signal from the controller, wherein the controller is connected to the Bank; the first word line address decoding circuit is used to activate the target word line in the subarray corresponding to the first word line address decoding circuit according to the multi-subarray word line activation signal, thereby inverting the bit logic of the middle array of any three adjacent subarrays among the at least three adjacent subarrays. It should be understood that the first latch circuit and the first word line address decoding circuit here are the first latch circuit and the first word line address decoding circuit corresponding to each subarray among the at least three adjacent subarrays, respectively.

[0009] In current technical solutions, a word line address decoding circuit activates a word line in the corresponding subarray to perform read and / or write operations, and only after that word line is deactivated can the next word line address decoding circuit activate the corresponding word line in the subarray. Because in the storage bank structure, adjacent subarrays are connected by logically inverted bit lines, if word lines in multiple adjacent subarrays can be activated simultaneously, bit-logic inversion of a batch of subarrays can be achieved through logically inverted bit lines. Therefore, in this embodiment, a latch circuit can be set in the storage bank (Bank). The latch circuit can enable the word line address decoding circuits in the Bank to perform different activation actions based on different enable signals from the controller. Specifically, when the latch circuit receives an in-memory operation mode enable signal from the controller, it can enable multiple word line address decoding circuits in the Bank to activate the corresponding word lines in the subarrays, thereby simultaneously activating word lines in multiple subarrays to achieve bit-logic inversion of a batch of subarrays in the Bank. Because the structure of the Bank in the DRAM is not changed in this embodiment, but the batch bit logic inversion operation of the Bank is implemented through the logic control of the latch circuit, the problem of poor process consistency caused by changing the structure of the Bank by adding transistors can be avoided.

[0010] The following describes how the first latch circuit in this embodiment enables multiple word line address decoding circuits in the Bank to activate word lines in the corresponding subarrays. The first latch circuit may include a latch and a multiplexer, the latch being connected to the multiplexer, and the multiplexer being connected to the first word line address decoding circuit corresponding to the first latch circuit. The latch is used to send the multi-subarray word line activation signal to the multiplexer based on the in-memory operation mode enable signal from the controller; the multiplexer is used to receive the multi-subarray word line activation signal from the latch and the address of the target word line from the controller, and select which subarray word line activation signal to send to the first word line address decoding circuit corresponding to the first latch circuit.

[0011] In another possible implementation, if the latch does not receive an in-memory operation mode enable signal from the controller, the latch cannot receive a multi-subarray word line activation signal from the latch. In this implementation, the multiplexer can receive the address of the target word line from the controller and send a single-subarray word line activation signal to the first word line address decoding circuit corresponding to the first latch circuit.

[0012] In other words, when the latch receives an in-memory operation mode enable signal from the controller, the multiplexer can choose to send a multi-subarray word line activation signal to the first word line address decoding circuit corresponding to the first latch circuit, thereby enabling the activation of target word lines in multiple subarrays. When the latch does not receive an in-memory operation mode enable signal from the controller, the multiplexer can choose to send a single-subarray word line activation signal to the first word line address decoding circuit corresponding to the first latch circuit, thereby enabling the activation of target word lines in one subarray. Therefore, the storage library in this embodiment can simultaneously activate target word lines in multiple subarrays, or simultaneously activate target word lines in one subarray.

[0013] In one possible implementation, the first latch circuit is further configured to send the address of the target word line to a first word line address decoding circuit corresponding to the first latch circuit, based on the address of the target word line from the controller. Correspondingly, the first word line address decoding circuit is configured to activate the target word line in the subarray corresponding to the first word line address decoding circuit, based on the multi-subarray word line activation signal and the address of the target word line.

[0014] It should be understood that, in order to accurately determine the target subarray to be activated in this embodiment of the application, the repository further includes: at least one subarray address decoding circuit, which is connected to the N latch circuits. The controller can send the addresses of at least three adjacent subarrays to the at least one subarray address decoding circuit. Each subarray address decoding circuit is used to send a strobe signal to the first latch circuit corresponding to each of the at least three adjacent subarrays based on the addresses of the at least three adjacent subarrays from the controller. The strobe signal is used to indicate the activation of the subarray corresponding to the first latch circuit. In this manner, the subarray address decoding circuit can determine the target subarray to be activated, and then send a strobe signal to the first latch circuit corresponding to the target subarray, enabling the first latch circuit corresponding to the target subarray to send a multi-subarray word line activation signal to the first word line address decoding circuit corresponding to the first latch circuit according to the in-memory operation mode enable signal, thereby enabling the activation of the target word line in multiple subarrays.

[0015] The structure of the subarrays in the embodiments of this application is described below. Here, we take at least three adjacent subarrays as an example: the i-th subarray, the (i+1)-th subarray, and the (i+2)-th subarray among the N subarrays, where i is an integer greater than or equal to 1 and less than or equal to N-2. The i-th subarray is connected to the (i+1)-th subarray via its first bit line, the i-th row sensitive amplifier SA, and the second bit line of the (i+1)-th subarray. The (i+1)-th subarray is connected to the (i+2)-th subarray via its first bit line, the (i+1)-th row SA, and the second bit line of the (i+2)-th subarray. The first bit line and the second bit line are inverted bit lines.

[0016] The SA is used to output a first level signal from the level signal generator to the first bit line connected to the SA, and to output a second level signal from the level signal generator to the second bit line connected to the SA. The SA includes the i-th row SA and the (i+1)-th row SA, and the first level signal and the second level signal are logically inverted level signals. In this structure, when the word line address decoding circuit corresponding to the i-th subarray activates the target word line in the i-th subarray, the signal on the first bit line in the i-th subarray is inverted with the signal on the second bit line in the (i+1)-th subarray; when the word line address decoding circuit corresponding to the (i+2)-th subarray activates the target word line in the (i+2)-th subarray, the signal on the second bit line in the (i+2)-th subarray is inverted with the signal on the first bit line in the (i+1)-th subarray.

[0017] The repository provided in this embodiment can be applied to different subarray structures. Based on the above, the i-th subarray in this embodiment is connected to the (i+1)-th subarray through the m-th first bit line, the i-th row SA, and the n-th second bit line of the (i+1)-th subarray. The (i+1)-th subarray is connected to the (i+2)-th subarray through the x-th first bit line, the (i+1)-th row SA, and the y-th second bit line of the (i+2)-th subarray. Here, m, n, x, and y are all integers greater than or equal to 1.

[0018] In one possible implementation, m is equal to n, x is equal to y, and m and x are consecutive integers. In another possible implementation, m is equal to x, n is equal to y, and m and n are consecutive integers.

[0019] Wherein, when m is an odd number, and when the word line address decoding circuit corresponding to the i-th subarray activates the target word line in the i-th subarray, the signal on the first bit line of the odd-numbered position in the i-th subarray is the inverted signal of the signal on the second bit line in the (i+1)-th subarray; when the word line address decoding circuit corresponding to the (i+2)-th subarray activates the word line in the (i+2)-th subarray, the signal on the second bit line of the even-numbered position in the (i+2)-th subarray is the inverted signal of the signal on the first bit line in the (i+1)-th subarray.

[0020] Wherein, when m is an even number, and when the word line address decoding circuit corresponding to the i-th subarray activates the target word line in the i-th subarray, the signal on the first bit line of the even-numbered position in the i-th subarray is the inverted signal of the signal on the second bit line in the (i+1)-th subarray; when the word line address decoding circuit corresponding to the (i+2)-th subarray activates the word line in the (i+2)-th subarray, the signal on the second bit line of the odd-numbered position in the (i+2)-th subarray is the inverted signal of the signal on the first bit line in the (i+1)-th subarray.

[0021] In one possible implementation, the at least three adjacent subarrays are illustrated using the i-th subarray, the (i+1)-th subarray, and the (i+2)-th subarray among the N subarrays as an example. When the first latch circuit receives the in-memory operation mode enable signal, it can acquire a vector and write the vector to the target word line in the i-th subarray and the (i+2)-th subarray. The vector is associated with the column address of the first bit line in the target subarray's target word line. When m is equal to x, n is equal to y, and m and n are adjacent integers, because the arrangement of the first and second bit lines in the i-th and (i+1)-th subarrays is alternately odd and even, and the arrangement of the first and second bit lines in the (i+1)-th and (i+2)-th subarrays is also alternately odd and even, the column address corresponding to the vector acquired by the first latch circuit in this case is the column address after parity bit swapping.

[0022] In this embodiment, the subarray batch bit logic inversion operation can be implemented for different DRAM memory array structures, making it widely applicable.

[0023] Secondly, embodiments of this application provide a system for performing an inversion operation. This system may include the repository and controller described in the first aspect above.

[0024] Thirdly, embodiments of this application provide a dynamic random access memory (DRAM), which may include at least one bank as described in the first aspect above and a memory input / output device, wherein the memory input / output device is connected to at least one bank.

[0025] Fourthly, embodiments of this application provide an electronic device. This electronic device may include a dynamic random access memory (DRAM) and a controller as described in the third aspect above. The controller is coupled to each bank in the DRAM, and the controller can perform the actions described in the first aspect above to implement a batch bit logic inversion operation in the DRAM.

[0026] Fifthly, embodiments of this application also provide a method for performing an inversion operation, which is applied to the system for performing an inversion operation as described in the second aspect above. The method may include:

[0027] The controller sends the address of the target subarray to the subarray address decoding circuit, and sends the target word line address, word line activation enable signal, and in-memory operation mode enable signal to the first latch circuit corresponding to each of at least three adjacent subarrays. The subarray address decoding circuit receives the address of the target subarray, determines the target subarray, and sends a strobe signal to the first latch circuit corresponding to the target subarray.

[0028] For each of at least three adjacent subarrays, the first latch circuit receives a strobe signal and, based on the target word line address, word line activation enable signal, and in-memory operation mode enable signal, sends a multi-subarray word line activation signal and the target word line address to the corresponding first word line address decoding circuit. Specifically, the first latch circuit acquires a vector and writes it to the target word line in the i-th subarray and the target word line in the (i+2)-th subarray. The first word line address decoding circuit activates the target word line in the corresponding target subarray based on the multi-subarray word line activation signal and the target word line address.

[0029] After activating the target word in each of at least three adjacent subarrays, each of the at least three adjacent subarrays performs a read and / or write operation. The first word line address decoding circuit corresponding to each of the at least three adjacent subarrays disables the target word line in the target subarray. After disabling the target word line in the target subarray, a precharge operation can be performed, which can be referred to the relevant description in the current technical solution.

[0030] This application provides a storage bank and a dynamic random access memory (DRAM). The storage bank includes N latch circuits, N word line address decoding circuits, and a DRAM memory array. In this application embodiment, latch circuits are provided in the storage bank (Bank). These latch circuits can enable the word line address decoding circuits in the Bank to perform different activation actions based on different enable signals from the controller. Specifically, when the latch circuit receives an in-memory operation mode enable signal from the controller, it can enable multiple word line address decoding circuits in the Bank to activate word lines in corresponding subarrays, thereby simultaneously activating word lines in multiple subarrays to achieve bit logic inversion of a batch of subarrays in the Bank. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a storage cell structure in a DRAM subarray of a current dynamic random access memory.

[0032] Figure 2 This is a schematic diagram of the current interconnection structure of multiple storage units;

[0033] Figure 3 This is a schematic diagram of the structure of a sensitive amplifier;

[0034] Figure 4 This is a schematic diagram of another structure of the memory cell in the DRAM subarray of current dynamic random access memory;

[0035] Figure 5 This is a schematic diagram of the current repository Bank structure;

[0036] Figure 6 This is a schematic diagram of the current activation process for word lines in DRAM;

[0037] Figure 7 A schematic diagram of the structure of a repository provided in an embodiment of this application;

[0038] Figure 8 Another schematic diagram of the structure of the repository provided in the embodiments of this application;

[0039] Figure 9 This is a schematic diagram of the latch circuit in the embodiments of this application;

[0040] Figure 10 A schematic diagram of bit line connection provided in an embodiment of this application;

[0041] Figure 11 Another schematic diagram of bit line connection provided in the embodiments of this application;

[0042] Figure 12 A flowchart illustrating a method for performing batch bit logic operations within a Bank, as provided in an embodiment of this application;

[0043] Figure 13 This is a schematic diagram illustrating the inversion of column addresses of bit lines in a subarray, as provided in an embodiment of this application.

[0044] Figure 14 This is a schematic diagram of the structure of a system for performing an inversion operation provided in an embodiment of this application;

[0045] Figure 15 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0046] In traditional von Neumann computing architectures, programs (instruction sequences) and data are stored in memory. When the processor performs calculations, it retrieves the corresponding program and data from memory and then runs the program to perform calculations on the data. In this architecture, data and programs need to be exchanged between the processor and memory, which causes significant computational latency and energy consumption. To address this issue, new non-von Neumann computing architectures have emerged, enabling in-memory computation. That is, data and programs do not need to be exchanged between the processor and memory; calculations can be performed directly within memory. Therefore, new non-von Neumann computing architectures can save computational latency and energy consumption.

[0047] Data is stored in binary form in memory, and bitwise logic operations are operations performed on this binary data. Bitwise logic operations include NOT, OR, XOR, and AND. NOT performs a logical NOT operation on each bit of a binary data set, such as inverting 1 to 0 and 0 to 1, for example, NOT(0111) = 1000. OR operates on two binary data sets of the same length; if at least one bit is 1, the result for that bit is 1, for example, (0101) OR (0011) = 0111. XOR performs a bitwise XOR operation on each bit of two binary data sets of the same length; the result is 1 if the bits are different, otherwise the result is 0, for example, (0101) XOR (0011) = 0110. The bitwise AND operation processes two binary data of the same length. The result value of a bit is 1 only if both corresponding binary bits are 1; otherwise, it is 0. For example, (0101) and (0011) = 0001. It should be understood that the embodiments of this application describe the bitwise logical NOT operation, which can also be called the bitwise logical NOT operation, logical NOT operation, or the bitwise operation of logical NOT, etc.

[0048] Bitwise logic operations are fundamental operators in in-memory computation and are frequently invoked during in-memory calculations. Therefore, implementing batch bitwise inversion operations in memory can improve the efficiency of in-memory computations and increase the bandwidth of the memory die. It should be understood that memory refers to memory chips, and die refers to the bare die of the memory chip. Figure 1 This is a schematic diagram of a memory cell structure in a DRAM subarray of a current dynamic random access memory (DRAM). Current dynamic random access memory (DRAM) can include, for example... Figure 1The diagram shows multiple DRAM subarrays, with adjacent subarrays connected by bit lines. Each subarray can include multiple memory cells, each consisting of a transistor and a capacitor, i.e., a 1T (transistor)-1C (capacitance) structure. The transistor's gate is connected to the word line (WL) in the subarray, its source is connected to the bit line (BL), and its drain is connected to the first terminal of the capacitor, with the second terminal grounded. To perform read and write operations in the memory, the word line in the subarray must first be activated. Activating the word line can be understood as outputting a high-level signal to the word line. For example, during a read operation, activating the word line turns on the transistor, allowing the reading of the level signal on the bit line. During a write operation, the level signal to be written can be pre-set in the bit line, then the word line is activated to turn on the transistor, changing the level inside the capacitor via the bit line to complete the write operation.

[0049] Figure 2 This is a schematic diagram of the current interconnection structure of multiple storage units. (Example) Figure 2 As shown, two adjacent subarrays can be connected via a sense amplifier (SA). One end of the sense amplifier is connected to the bit line BL of one subarray, and the other end is connected to the bit line !BL of the other subarray. It should be understood that BL and !BL are inverted bit lines, and the level signals on them are logically inverted. For example, if the level signal on BL is high, then the level signal on !BL is low. It should be understood that in this embodiment, 0.5-1 is used as the high-level signal range, and 0-0.5 is used as the low-level signal range. Note that the principle behind the logical inversion of the signals on BL and !BL lies in the structure of the SA.

[0050] Figure 3 This is a schematic diagram of a sensitive amplifier. Figure 3As shown, SA consists of two N-type metal-oxide-semiconductor (NMOS) transistors and two P-type metal-oxide-semiconductor (PMOS) transistors. SA can sense tiny signals in BL and amplify them for subsequent read / write operations. Since the higher the voltage applied to the gate of an NMOS transistor (the higher the signal level), the stronger its conduction, while for a PMOS transistor, the higher the voltage applied to the gate (the higher the signal level), the weaker its conduction. For example, if the logic voltage on WL is 1 and the initial voltage on BL is 1 / 2 Vdd, after activating WL, the charge in the capacitor will share with BL, and the voltage on BL will be greater than 1 / 2 Vdd. Here, Vdd is the voltage inside the memory cell. When the voltage on BL is greater than its initial voltage of 1 / 2 Vdd, based on the conduction principle of NMOS and PMOS, the voltage on BL will gradually stabilize to the logic voltage value of 1, and then gradually stabilize to the logic voltage value of 0.

[0051] The two NMOS transistors in SA are Tn1 and Tn2, and the two PMOS transistors in SA are Tp1 and Tp2. As shown above, when the voltage on BL is greater than its initial voltage value of 1 / 2 Vdd, Tn2 will be more conductive than Tn1, and Tp1 will be more conductive than Tp2. The voltage on BL will then gradually stabilize to the logic voltage value 1, and so on, until it stabilizes to the logic voltage value 0.

[0052] Based on the above Figures 1-3 In the current DRAM structure, if you want to implement batch bit logic inversion operations in DRAM, you can currently do so in the above-mentioned... Figure 2 Adding a transistor to the structure of the memory cell shown transforms the current 1T-1C memory cell structure into a 2T-1C structure. Figure 4 This is a schematic diagram illustrating another structural configuration of a memory cell in a DRAM subarray of a current dynamic random access memory. (See diagram below.) Figure 4 As shown, compared to the above Figure 1 A transistor has been added to the memory cell, and the gate of this transistor is connected to another WL in the subarray, which is connected to the aforementioned... Figure 1 The WL transistors shown can be arranged adjacently or non-adjacently, and the source of the transistor is related to the above. Figure 1 The drain of the transistor in the above is connected, and the drain of this transistor is connected to BL in SA. For easy distinction, the above... Figure 1The WL shown is designated as WL1, and the WL connected to the newly added transistor is designated as WL2.

[0053] because Figure 4 The WL shown refers to the WL in the same subarray, so both WL can be activated simultaneously. When WL1 is activated, based on the above, the voltage value on BL will be greater than 1 / 2 Vdd. Under the action of SA, the voltage value on BL will gradually stabilize to the logic voltage value 1, and the voltage value on !BL will gradually stabilize to the logic voltage value 0. However, because the newly added transistor is connected to !BL, after activating WL2, !BL will force the capacitor in 2T-1C to discharge, reducing its stored charge, i.e., the logic voltage value of the capacitor is 0, thus enabling the memory cell to perform bit logic inversion operation. Similarly, if the logic voltage value on WL is 0, and the initial voltage value on BL is 1 / 2 Vdd, after activating WL, the charge in the capacitor will be shared with BL, and the voltage value on BL will be less than 1 / 2 Vdd. Based on the conduction principle of NMOS and PMOS, the voltage value on BL will gradually stabilize to the logic voltage value 0, and the voltage value on !BL will gradually stabilize to the logic voltage value 1. Correspondingly, because the newly added transistor is connected to !BL, !BL will gradually stabilize to the logic voltage value 1. The BL connection means that after WL2 is activated, !BL will force the capacitor in 2T-1C to be charged, increasing its stored charge, i.e., the logic voltage value of the capacitor is 1, thereby enabling the storage cell to perform a bit logic inversion operation.

[0054] Adding a transistor to a memory cell allows for the bit-logic inversion operation of the memory cell, as described above. Figure 4 While the structure can achieve batch bit logic inversion operations, it requires adding several rows of 2T-1C structures to the traditional DRAM array, which leads to poor process consistency and consequently reduces the yield of DRAM products.

[0055] In order to explain the structure of the storage bank Bank, the structure of the DRAM, and the principle of implementing the batch bit logic inversion operation in the Bank provided in the embodiments of this application, the current DRAM structure will be further explained below. Figure 5 This is a schematic diagram of the current repository bank structure. It should be understood that a DRAM typically comprises multiple banks, such as... Figure 5 As shown, each Bank may include subarray address decoding circuitry, word line address decoding circuitry, and dynamic random access memory (DRAM) memory arrays (subarrays), with each word line address decoding circuit corresponding one-to-one with a subarray. The DRAM memory array may include multiple subarrays. Figure 5Examples are given using subarray(i-1), subarrayi, subarray(i+1), and subarray(i+2). Figure 5 As shown, the subarray address decoding circuit is connected to multiple word line address decoding circuits. Each word line address decoding circuit is connected to its corresponding subarray through word lines in the subarray. For example, word line address decoding circuit (i+1) is connected to subarray (i+1) through word lines in subarray (i+1). Each subarray includes multiple word lines and multiple bit lines. Figure 5 Word lines are shown as solid lines, and bit lines are shown as dashed lines. The identifiers for word lines in each subarray can be the same; for example, subarrayi can include word line 1, word line 2, etc., and subarray(i+1) can also include word line 1, word line 2, etc. It should be noted that... Figure 5 The specific structure of the subarray in the following embodiments can be as described above. Figure 1 The diagram shows the structure of 1T-1C.

[0056] in accordance with Figure 5 , Figure 6 This is a schematic diagram illustrating the current activation process for word lines in DRAM. For example... Figure 6 As shown, the current activation process for word lines in DRAM can include:

[0057] S601, The controller sends the address of the target subarray to the subarray address decoding circuit and the address of the target word line to the word line address decoding circuit.

[0058] The controller can be a processor, such as a central processing unit (CPU) in an electronic device. When the controller activates word lines in a subarray, the subarray to be activated is the target subarray, and the word lines in the target subarray are the target word lines. Accordingly, the processor can send the address of the target subarray to the subarray address decoding circuit and the address of the target word line to each word line address decoding circuit. It should be understood that when the controller sends the address of the target subarray and the address of the target word line, it can encode the address of the target subarray and the address of the target word line, and send the encoded address of the target subarray and the encoded address of the target word line.

[0059] S602, the subarray address decoding circuit receives the address of the target subarray, determines the target subarray, and sends a strobe signal to the word line address decoding circuit corresponding to the target subarray.

[0060] Upon receiving the address of the target subarray, the subarray address decoding circuit decodes the address to obtain the target subarray to be activated, and then sends a strobe signal to the word line address decoding circuit corresponding to the target subarray. This strobe signal instructs the word line address decoding circuit corresponding to the target subarray to activate the word lines in the target subarray.

[0061] S603, the word line address decoding circuit receives the strobe signal and determines the target word line according to the address of the target word line, and activates the target word line in the target subarray.

[0062] It should be understood that after the word line address decoding circuit receives the strobe signal from the subarray address decoding circuit, it can determine to activate the word line in the subarray corresponding to that word line address decoding circuit. Therefore, the word line address decoding circuit can decode the received address of the target word line to obtain the target word line to be activated. The word line address decoding circuit can activate the target word line in the target subarray according to the address of the target word line.

[0063] For example, if the controller needs to activate word lines 1 and 2 in subarray i, the controller can send the address of subarray i to the subarray address decoding circuit, and send the "address of word line 1 and address of word line 2" to each word line address decoding circuit. The subarray address decoding circuit determines that the subarray to be activated is subarray i, and then sends a strobe signal to the word line address decoding circuit i corresponding to subarray i. After receiving the strobe signal, the word line address decoding circuit i can decode the received address of the target word line to obtain the "address of word line 1 and address of word line 2", thereby activating word lines 1 and 2 in subarray i.

[0064] It should be noted that current technical solutions cannot simultaneously activate word lines in different subarrays. However, after activating a word line in one subarray, the following steps can be performed:

[0065] The S604 word line address decoding circuit performs read and / or write operations.

[0066] S605, the word line address decoding circuit shuts down the target word line in the target subarray.

[0067] S606, Pre-charged.

[0068] It should be understood that the steps in S604-S606 above can be referred to the relevant descriptions in the current technical solutions, and will not be repeated here. That is to say, in the current technical solutions, if it is necessary to activate the word lines in subarrayi, subarray(i+1), and subarray(i+2), then after activating the word lines in subarrayi, the above S604-S606 can be executed, and then the word lines in subarray(i+1) can be activated. Similarly, after executing the above S604-S606, the word lines in subarray(i+1) can be activated.

[0069] Based on the above Figure 5 Because in the structure of the repository, adjacent subarrays are connected by logically inverted bit lines. For example, subarrayi is connected to SA through BL in subarrayi, and subarray(i+1) is connected to SA through ! BL in subarray(i+1). If word lines in multiple adjacent subarrays can be activated simultaneously, the bit logic inversion of a batch of subarrays can be achieved through logically inverted bit lines. For example, if the word lines in subarrayi, subarray(i+1), and subarray(i+2) can be activated simultaneously, then the bit lines in subarrayi and subarray(i+1) connected to the SA in row i are logically inverted bit lines. This allows the signals on the bit lines in subarray(i+1) connected to subarrayi to be inverted signals, and the bit lines in subarray(i+1) and subarray(i+2) connected to the SA in row i+1 are logically inverted bit lines. This allows the signals on the bit lines in subarray(i+1) connected to subarray(i+2) to be inverted signals, thereby enabling the inversion of all bit lines in subarray(i+1), achieving the purpose of bit-logic inversion of subarray(i+1) and achieving batch logical inversion operation. It should be understood that the SA in row i is the SA used to connect subarrayi and subarray, and the SA in row i+1 can be the SA used to connect subarray(i+1) and subarray(i+2).

[0070] Based on this, to address the issue of decreased process consistency caused by transforming the 1T-1C structure into a 2T-1C structure, this application provides a storage bank. By incorporating a latch circuit within the storage bank, the latch circuit can enable different activation actions of the word line address decoding circuits in the bank based on different enable signals from the controller. Specifically, when the latch circuit receives an in-memory operation mode enable signal from the controller, it can enable multiple word line address decoding circuits in the bank to activate the corresponding word lines in the subarrays. This allows for the simultaneous activation of word lines in multiple subarrays, enabling batch bit logic inversion operations on the subarrays within the bank.

[0071] The structure of the repository Bank provided in this application will be described below with reference to specific embodiments. These embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. Figure 7 This is a schematic diagram of a repository structure provided in an embodiment of this application. For example... Figure 7 As shown, the repository Bank provided in this application embodiment may include: N latch circuits, N word line address decoding circuits, and a dynamic random access memory (DRAM) memory array.

[0072] The DRAM memory array comprises N subarrays, with adjacent subarrays connected, where N is an integer greater than or equal to 1. In this embodiment, the latch circuit, word line address decoding circuit, and subarray correspond one-to-one. Each latch circuit is connected to its corresponding word line address decoding circuit, and each word line address decoding circuit is connected to its corresponding subarray via word lines in that subarray. It should be understood that the Bank in this embodiment can be connected to a controller. Optionally, the controller can be connected to the N latch circuits in the Bank, and the controller can be referenced to the relevant description above. Figure 5 The difference lies in that the Bank in this embodiment may include a latch circuit. This latch circuit can enable the word line address decoding circuit in the Bank to perform different activation actions based on different enable signals from the controller. In one possible implementation, the latch circuit can enable one word line address decoding circuit to activate the word lines in the corresponding subarray, or the latch circuit can enable multiple word line address decoding circuits to simultaneously activate the word lines in the corresponding subarrays, thereby achieving a batch bit logic inversion operation of the subarrays.

[0073] Since the main purpose of this application's embodiments is to implement batch bit logic inversion operations, this section first describes an implementation method where the latch circuit enables multiple word line address decoding circuits to simultaneously activate word lines in corresponding subarrays. In this implementation, it is required that target word lines in multiple subarrays be activated simultaneously; therefore, the controller can output an in-memory operation mode enable signal. This in-memory operation mode enable signal is used to indicate the simultaneous activation of target word lines in multiple subarrays. Optionally, the controller can output the in-memory operation mode enable signal to the latch circuit through an interface command circuit in the DRAM.

[0074] As described above, activating the target word lines in subarrayi, subarray(i+1), and subarray(i+2) simultaneously enables the bitwise NOT operation of subarray(i+1). If the bitwise NOT operation of subarrayi is also required, subarray(i-1) can be activated simultaneously. Here, the bit lines in subarray(i-1) and subarrayi connected to the SA of row i-1 are logically inverted bit lines, and the bit lines in subarrayi and subarray(i+1) connected to the SA of row i are logically inverted bit lines, thus enabling the bitwise NOT operation of subarray(i-1). In this embodiment, if the bitwise NOT operation of multiple subarrays is required, the target word lines in these multiple subarrays and adjacent subarrays can be activated.

[0075] Therefore, for the first latch circuit and the first word line address decoding circuit corresponding to each of the multiple subarrays in the N subarrays, the first latch circuit and the first word line address decoding circuit corresponding to each subarray can perform the following operations. It should be understood that, in order to distinguish the latch circuit and word line address decoding circuit corresponding to each of the multiple subarrays to be activated, and the latch circuit and word line address decoding circuit corresponding to other subarrays that are not activated, in the embodiments of this application, the latch circuit and word line address decoding circuit corresponding to each of the multiple subarrays to be activated are respectively referred to as the first latch circuit and the first word line address decoding circuit.

[0076] The first latch circuit can be used to receive an in-memory operation mode enable signal from the controller, and send a multi-subarray word line activation signal to the corresponding first word line address decoding circuit according to the in-memory operation mode enable signal from the controller. It should be understood that by receiving the in-memory operation mode enable signal from the controller, the first latch circuit can determine that word lines in multiple subarrays can be activated simultaneously, and therefore can generate a multi-subarray word line activation signal to instruct the first word line address decoding circuit corresponding to the first latch circuit to take steps different from those described in S604-S606.

[0077] The first word line address decoding circuit in this embodiment can be used to receive a multi-subarray word line activation signal from the first latch circuit corresponding to the first word line address decoding circuit, thereby activating the target word line in the subarray corresponding to the first word line address decoding circuit. Unlike S604-S606 described above, because the first word line address decoding circuit can receive the multi-subarray word line activation signal, which indicates that word lines in multiple subarrays can be activated simultaneously, the first word line address decoding circuit can execute the steps in S604-S606 separately after activating the target word lines in multiple subarrays among N subarrays. In other words, in this embodiment, the target word lines in multiple subarrays among N subarrays can be activated simultaneously, thus inverting the bit logic of the intermediate array of any three adjacent subarrays among the multiple subarrays.

[0078] In other words, for the first latch circuit and the first word line address decoding circuit corresponding to each of the at least three adjacent subarrays in the embodiments of this application, the first latch circuit and the first word line address decoding circuit can perform the same steps as described above, thereby realizing the bit logic inversion of the intermediate array of any three adjacent subarrays in the at least three adjacent subarrays, so as to achieve the purpose of batch bit logic inversion operation.

[0079] For example, such as Figure 7As shown, when the bit logic inversion operation of subarrayi is required, the controller can send an in-memory operation mode enable signal to the first latch circuits corresponding to subarray(i-1), subarrayi, and subarray(i+1). The first latch circuits corresponding to subarray(i-1), subarrayi, and subarray(i+1) can all receive the in-memory operation mode enable signal from the controller, and then send a multi-subarray word line activation signal to the corresponding first word line address decoding circuit. Correspondingly, after receiving the multi-subarray word line activation signal, the first word line address decoding circuits corresponding to subarray(i-1), subarrayi, and subarray(i+1) can simultaneously activate the target word lines in subarray(i-1), subarrayi, and subarray(i+1). In this context, because the bit lines connected to the SA in row i of subarray i and subarray (i+1) are logically inverted bit lines, activating the target word line in subarray i and subarray (i+1) will make the signal on the bit line connected to subarray i in subarray (i+1) an inverted signal. Similarly, because the bit lines connected to the SA in row i-1 of subarray (i-1) and subarray i are logically inverted bit lines, activating the target word line in subarray (i-1) will make the signal on the bit line connected to subarray i in subarray (i-1) an inverted signal. This allows for the inversion of all bit lines in subarray i, achieving the purpose of batch logical inversion operations.

[0080] For example, when the bit logic inversion operation of subarrayi and subarray(i+1) is required, the controller can send an in-memory operation mode enable signal to the first latch circuits corresponding to subarray(i-1), subarray, subarray(i+1), and subarray(i+2). The first latch circuits corresponding to subarray(i-1), subarrayi, subarray(i+1), and subarray(i+2) can all receive the in-memory operation mode enable signal from the controller. Then, the first latch circuits corresponding to subarray(i-1), subarrayi, subarray(i+1), and subarray(i+2) respectively send a multi-subarray word line activation signal to the corresponding first word line address decoding circuit, thereby activating the target word lines in subarray(i-1), subarrayi, subarray(i+1), and subarray(i+2). Based on the same principle as above, the bit logic inversion operation of subarrayi and subarray(i+1) can be implemented.

[0081] The storage bank (Bank) in this embodiment may include N latch circuits, N word line address decoding circuits, and a dynamic random access memory (DRAM) array. The latch circuits, word line address decoding circuits, and subarrays are one-to-one. Each latch circuit is connected to its corresponding word line address decoding circuit, and each word line address decoding circuit is connected to its corresponding subarray via word lines in the subarray. Specifically, for each of at least three adjacent subarrays, the first latch circuit and the first word line address decoding circuit are configured as follows: the first latch circuit sends a multi-subarray word line activation signal to the corresponding first word line address decoding circuit based on an in-memory operation mode enable signal from the controller; the controller is connected to the Bank. The first word line address decoding circuit activates the target word line in the subarray corresponding to the first word line address decoding circuit based on the multi-subarray word line activation signal, thereby inverting the bit logic of the intermediate array of any three adjacent subarrays. In this embodiment, a latching circuit can be set in the Bank. The latching circuit can enable the word line address decoding circuit in the Bank to perform different activation actions according to different enable signals from the controller. Specifically, when the latching circuit receives an in-memory operation mode enable signal from the controller, it can enable multiple word line address decoding circuits in the Bank to activate the word lines in the corresponding subarrays. This allows for the simultaneous activation of word lines in multiple subarrays, enabling the bit logic of the intermediate array of any three adjacent subarrays in at least three adjacent subarrays to be inverted, thereby achieving the purpose of batch bit logic inversion.

[0082] The following is combined Figure 8 The Bank provided in the embodiments of this application will be further described. Figure 8 This is another schematic diagram of the structure of the repository provided in an embodiment of this application. Based on the above embodiments, as... Figure 8 As shown in the embodiments of this application, the Bank may further include at least one subarray address decoding circuit. This at least one subarray address decoding circuit is connected to N latch circuits, and the controller mentioned in the above embodiments may be connected to this at least one subarray address decoding circuit. Figure 8 The example given is a Bank containing a subarray address decoding circuit. Figure 8 The connection between the controller and the bank is represented by different linear representations.

[0083] In this embodiment, each subarray address decoding circuit has the same function and purpose. The following description uses one subarray address decoding circuit as an example. This subarray address decoding circuit can receive addresses from at least three adjacent subarrays under control, and, based on these addresses, send a strobe signal to the first latch circuit corresponding to each of the at least three adjacent subarrays. The strobe signal is used to indicate the selection of the subarray corresponding to the first latch circuit, i.e., to activate the target word line in the subarray corresponding to the first latch circuit.

[0084] When the Bank includes multiple subarray address decoding circuits, these circuits can divide the work of sending strobe signals to the first latch circuit corresponding to each of at least three adjacent subarrays, thereby improving the decoding efficiency of the subarray addresses. For example, if the Bank includes two subarray address decoding circuits, and the controller sends the addresses of subarray(i-1), subarrayi, and subarray(i+1) to these two circuits, then one subarray address decoding circuit can decode the address of subarray(i-1) and send a strobe signal to the first latch circuit corresponding to subarray(i-1), while the other subarray address decoding circuit can decode the address of subarrayi and send a strobe signal to the first latch circuit corresponding to subarrayi. It should be noted that after one subarray address decoding circuit sends a strobe signal to the first latch circuit corresponding to subarray(i-1), it can also decode the address of subarray(i+1) and send a strobe signal to the first latch circuit corresponding to subarray(i+1).

[0085] In one possible implementation, the controller can send the address of the target word line to the first latch circuit, so that the first word line address decoding circuit can determine which word lines in the target subarray are activated, i.e., the target word lines. In this implementation, for each of at least three adjacent subarrays, the first latch circuit is further configured to receive the address of the target word line from the controller and, based on the address of the target word line, send the address of the target word line to the corresponding first word line address decoding circuit.

[0086] Optionally, in combination with the above Figure 7 In the example provided, the first latch circuit in this embodiment can be used to receive the address of the target word line and the in-memory operation mode enable signal from the controller, and send the address of the target word line and the multi-subarray word line activation signal to the first word line address decoding circuit corresponding to the first latch circuit according to the address of the target word line and the in-memory operation mode enable signal. Optionally, the address of the target word line and the in-memory operation mode enable signal can be sent in a single message.

[0087] Optionally, the controller can also send a word line activation enable signal to the first latch circuit, which instructs the first latch circuit to determine that a word line needs to be activated. The first latch circuit is further configured to receive the word line activation enable signal from the controller and, based on the word line activation enable signal, determine that the corresponding first word line address decoding circuit needs to be notified to activate the target word line in the target subarray. That is, in this embodiment, the first latch circuit can be configured to receive the target word line address, in-memory operation mode enable signal, and word line activation enable signal from the controller, and, based on the target word line address, in-memory operation mode enable signal, and word line activation enable signal, send the target word line address and multi-subarray word line activation signal to the first word line address decoding circuit corresponding to the first latch circuit. Optionally, the target word line address, in-memory operation mode enable signal, and word line activation enable signal can be sent in one piece of information, or the in-memory operation mode enable signal and word line activation enable signal can be sent in one piece of information, and the target word line address can be sent in another piece of information.

[0088] Correspondingly, the first word line address decoding circuit in this embodiment can receive the multi-subarray word line activation signal and the address of the target word line from the first latch circuit, thereby activating the target word line in the subarray corresponding to the first word line address decoding circuit. The process by which the first word line address decoding circuit activates the target word line in the subarray corresponding to the first word line address decoding circuit can be referred to the above. Figure 7 The relevant description in the document.

[0089] In one possible implementation, Figure 9This is a schematic diagram of the latch circuit in an embodiment of this application. Figure 9 As shown, the first latch circuit includes a latch and a multiplexer. The latch is connected to the multiplexer, the multiplexer is connected to the first word line address decoding circuit corresponding to the first latch circuit, and the latch is also connected to the subarray decoding address decoding circuit.

[0090] Based on the above embodiments, the latch can be used to send a multi-subarray word line activation signal to the multiplexer according to the in-memory operation mode enable signal from the controller. Optionally, the latch can specifically be used to send a multi-subarray word line activation signal and the address of the target word line to the multiplexer according to the in-memory operation mode enable signal, the word line activation enable signal, and the address of the target word line from the controller. The multiplexer is used to send a multi-subarray word line activation signal to the first word line address decoding circuit corresponding to the first latch circuit according to the multi-subarray word line activation signal from the latch. Optionally, the multiplexer is specifically used to send the multi-subarray word line activation signal and the address of the target word line to the first word line address decoding circuit corresponding to the first latch circuit.

[0091] like Figure 9 As shown, the latch includes a first input terminal D, a second input terminal EN, and a first output terminal Q. The multiplexer includes a third input terminal, a fourth input terminal, a second output terminal Z, and a third output terminal S. The third input terminal is... Figure 9 The port corresponding to logic voltage value 0 and the fourth input port corresponding to logic voltage value 1 are specified. The controller can output an in-memory operation mode enable signal and a word line activation enable signal to the second input port of the latch; the subarray address decoding circuit can output a strobe signal to the second input port; and the controller can also output the address of the target word line to the first input port of the latch. In this embodiment, when the latch receives the in-memory operation mode enable signal from the controller, it can send a multi-subarray word line activation signal to the multiplexer; for example, the latch can send a logic voltage value of 1 to the multiplexer. When the latch does not receive the in-memory operation mode enable signal from the controller, but receives the word line activation enable signal and the address of the target word line from the controller, it can choose not to send the multi-subarray word line activation signal to the multiplexer, i.e., it will not send a logic voltage value of 1.

[0092] In this embodiment, the controller is also connected to a multiplexer, and the controller can output the address of the target word line to the multiplexer. Specifically, on one hand, when the latch receives an in-memory operation mode enable signal from the controller, the fourth input of the multiplexer can receive both the multi-subarray word line activation signal from the latch and the address of the target word line (e.g., logic voltage value 1), and the third input can also receive the address of the target word line from the controller. In this case, the multiplexer can choose to output the signal from the fourth input, such as the multi-subarray word line activation signal and the address of the target word line. On the other hand, when the latch does not receive an in-memory operation mode enable signal from the controller, the third input of the multiplexer can receive the address of the target word line from the controller, but the fourth input cannot receive the multi-subarray word line activation signal and the address of the target word line from the latch. In this case, the multiplexer can choose to output the signal from the third input, such as the address of the target word line. Alternatively, the multiplexer can also send a single-subarray word line activation signal (e.g., logic voltage value 0) to the first word line address decoding circuit corresponding to the first latch circuit. Specifically, the single subarray word line activation signal is used to instruct the first word line address decoding circuit to activate the target word line in the corresponding subarray, thereby executing the steps in S604-S606 described above. Furthermore, unlike the multi-subarray sub-word line activation signal, this single subarray word line activation signal is also used to instruct the simultaneous activation of the target word line in one subarray, thus preventing the implementation of batch bit logic inversion operations.

[0093] Based on the aforementioned principles, the latch circuit in this embodiment can, according to different signals from the controller (including or excluding the in-memory operation mode enable signal), enable multiple word line address decoding circuits to simultaneously activate the target word lines in the corresponding subarrays when the signal from the controller includes the in-memory operation mode enable signal, achieving the purpose of batch bit logic inversion operations. When the signal from the controller does not include the in-memory operation mode enable signal, the latch circuit can enable a single word line address decoding circuit to activate the target word lines in the corresponding subarray, achieving the purpose of activating word lines in a single subarray.

[0094] The above embodiments describe the process and principle of enabling multiple word line address decoding circuits to simultaneously activate the target word lines in the corresponding subarrays using a latch circuit. The following embodiments, in conjunction with the specific structure of a DRAM memory array, illustrate the principle of implementing batch bit logic operations in the Bank provided in this application. As in the above embodiments... Figure 8 As shown, the following explanation will be based on the example of activating three adjacent subarrays as the i-th subarray, the (i+1)-th subarray, and the (i+2)-th subarray in N subarrays, where i is an integer greater than or equal to 1 and less than or equal to N-2.

[0095] In this embodiment, the i-th subarray is connected to the (i+1)-th subarray via the first bit line of the i-th subarray, the i-th row sensitive amplifier SA, and the second bit line of the (i+1)-th subarray. It should be understood that the i-th row sensitive amplifier SA may include one or more SAs. When the i-th row sensitive amplifier SA includes multiple SAs, the i-th subarray can be connected to the (i+1)-th subarray via the first first bit line of the i-th subarray, the first SA in the i-th row SA, and the first second bit line of the (i+1)-th subarray. It should be noted that the first bit line and the second bit line are inverted bit lines. For example, if the first bit line is BL, then the second bit line is !BL; if the first bit line is !BL, then the second bit line is BL. Similarly, in the embodiments of this application, the (i+1)th subarray is connected to the (i+2)th subarray through the first bit line in the (i+1)th subarray, the (i+1)th row SA, and the second bit line in the (i+2)th subarray. The (i+1)th row SA can be referred to the relevant description of the (i)th row SA above.

[0096] SA (including SA in row i and SA in row i+1, the function of which is described here) is used to output the first level signal from the level signal generator to the first bit line connected to SA, and to output the second level signal from the level signal generator to the second bit line connected to SA. It should be noted that the first and second level signals are logically inverted level signals. For example, the first level signal is a high level signal and the second level signal is a low level signal. The division of the high and low level signal intervals in this embodiment can be referred to the above description. That is, SA (SA in row i) can output the logically inverted level signals from the level signal generator to the first bit line in the i-th subarray and the second bit line in the (i+1)-th subarray, respectively. SA (SA in row i+1) can also output the logically inverted level signals from the level signal generator to the first bit line in the (i+1)-th subarray and the second bit line in the (i+2)-th subarray, thereby enabling the (i+1)-th subarray to perform bit logic inversion.

[0097] Specifically, when the word line address decoding circuit corresponding to the i-th subarray activates the target word line in the i-th subarray, the signal on the first bit line of the i-th subarray is inverted by the signal on the second bit line of the (i+1)-th subarray. When the word line address decoding circuit corresponding to the (i+2)-th subarray activates the target word line in the (i+2)-th subarray, the signal on the second bit line of the (i+2)-th subarray is inverted by the signal on the first bit line of the (i+1)-th subarray. In other words, in this embodiment, when the target word lines in the i-th, (i+1)-th, and (i+2)-th subarrays are activated simultaneously, the (i+1)-th subarray can perform a bit logic inversion operation.

[0098] The above describes the specific process of implementing bit logic inversion in subarrays. The following section will illustrate this with reference to the specific structures of the following two DRAM memory arrays:

[0099] The first possible structure of a DRAM memory array: For the i-th subarray, the (i+1)-th subarray, and the (i+2)-th subarray mentioned above, the i-th subarray is connected to the (i+1)-th subarray via the m-th first bit line, the i-th row SA, and the n-th second bit line of the (i+1)-th subarray. The (i+1)-th subarray is connected to the (i+2)-th subarray via the x-th first bit line, the (i+1)-th row SA, and the y-th second bit line of the (i+2)-th subarray. m, n, x, and y are all integers greater than or equal to 1. Specifically, m and n are equal, x and y are equal, and m and x are consecutive integers. In other words, in the first structure, the first bit line in the i-th subarray connected by the SA in the i-th row and the second bit line in the (i+1)-th subarray have the same parity bit, and the first bit line in the (i+1)-th subarray connected by the SA in the (i+1)-th row and the second bit line in the (i+2)-th subarray have the same parity bit, but the first bit line in the i-th subarray and the second bit line in the (i+2)-th subarray have different parity bits.

[0100] In this case, m can be either odd or even. For example, Figure 10 This is a schematic diagram of a bitline connection provided in an embodiment of this application. For example... Figure 10 As shown, when m is odd, the i-th subarray is connected to the (i+1)-th subarray through the first first bit line of the i-th subarray, the i-th row SA, and the first second bit line of the (i+1)-th subarray; the (i+1)-th subarray is connected to the (i+2)-th subarray through the second first bit line of the (i+1)-th subarray, the i+1-th row SA, and the second second bit line of the (i+2)-th subarray; the i-th subarray is connected to the (i+1)-th subarray through the third first bit line of the i-th subarray, the i-th row SA, and the third second bit line of the (i+1)-th subarray; the (i+1)-th subarray is connected to the (i+2)-th subarray through the fourth first bit line of the (i+1)-th subarray, the i+1-th row SA, and the fourth second bit line of the (i+2)-th subarray, and so on.

[0101] Specifically, when m is odd, and the word line address decoding circuit corresponding to the i-th subarray activates the target word line in the i-th subarray, the signal on the first bit line of the odd-numbered positions in the i-th subarray is the inverted signal of the signal on the second bit line of the (i+1)-th subarray. When the word line address decoding circuit corresponding to the (i+2)-th subarray activates the word line in the (i+2)-th subarray, the signal on the second bit line of the even-numbered positions in the (i+2)-th subarray is the inverted signal of the signal on the first bit line of the (i+1)-th subarray.

[0102] When m is even, and when the word line address decoding circuit corresponding to the i-th subarray activates the target word line in the i-th subarray, the signal on the first bit line of the even-numbered positions in the i-th subarray is the inverted signal of the signal on the second bit line of the (i+1)-th subarray. Specifically, the signal on the first bit line of the even-numbered positions in the i-th subarray is the inverted signal of the signal on the second bit line of the even-numbered positions in the (i+1)-th subarray. When the word line address decoding circuit corresponding to the (i+2)-th subarray activates the word line in the (i+2)-th subarray, the signal on the second bit line of the odd-numbered positions in the (i+2)-th subarray is the inverted signal of the signal on the first bit line of the (i+1)-th subarray. Specifically, the signal on the second bit line of the odd-numbered positions in the (i+2)-th subarray is the inverted signal of the signal on the first bit line of the odd-numbered positions in the (i+1)-th subarray.

[0103] Optionally, when there are multiple SAs in each row, in one possible implementation, the i-th subarray is connected to the (i+1)-th subarray through the first first bit line of the i-th subarray, the first SA of the i-th row SA, and the first second bit line of the (i+1)-th subarray; the (i+1)-th subarray is connected to the (i+2)-th subarray through the second first bit line of the (i+1)-th subarray, the first SA of the (i+1)-th row SA, and the second second bit line of the (i+2)-th subarray; the i-th subarray is connected to the (i+1)-th subarray through the third first bit line of the i-th subarray, the second SA of the i-th row SA, and the third second bit line of the (i+1)-th subarray; the (i+1)-th subarray is connected to the (i+2)-th subarray through the fourth first bit line of the (i+1)-th subarray, the second SA of the (i+1)-th row SA, and the fourth second bit line of the (i+2)-th subarray, and so on.

[0104] A second possible structure for the DRAM memory array: Based on the bit line connections of the i-th, (i+1)-th, and (i+2)-th subarrays mentioned above, m is equal to x, n is equal to y, and m and n are consecutive integers. That is, in this second structure, the parity bit of the first bit line in the i-th subarray connected by the SA in the i-th row is different from that of the second bit line in the (i+1)-th subarray; the parity bit of the first bit line in the (i+1)-th subarray connected by the SA in the (i+1)-th row is different from that of the second bit line in the (i+2)-th subarray; however, the parity bit of the first bit line in the i-th subarray and the second bit line in the (i+2)-th subarray are the same.

[0105] In this case, m can be either odd or even. Specifically, when m is odd, Figure 11 This is another schematic diagram of bit line connections provided in an embodiment of this application. (See diagram below.) Figure 11 As shown, for example, the i-th subarray is connected to the (i+1)-th subarray through the first bit line, the i-th row SA, and the second bit line of the (i+1)-th subarray; the (i+1)-th subarray is connected to the (i+2)-th subarray through the first bit line, the i+1-th row SA, and the second bit line of the (i+2)-th subarray; the i-th subarray is connected to the (i+1)-th subarray through the third bit line, the i-th row SA, and the fourth bit line of the (i+1)-th subarray; the (i+1)-th subarray is connected to the (i+2)-th subarray through the third bit line, the i+1-th row SA, and the fourth bit line of the (i+2)-th subarray... and so on.

[0106] When m is odd, and when the word line address decoding circuit corresponding to the i-th subarray activates the target word line in the i-th subarray, the signal on the first bit line of the odd-numbered positions in the i-th subarray is the inverted signal of the signal on the second bit line of the (i+1)-th subarray. Specifically, the signal on the first bit line of the odd-numbered positions in the i-th subarray is the inverted signal of the second bit line of the even-numbered positions in the (i+1)-th subarray. When the word line address decoding circuit corresponding to the (i+2)-th subarray activates the word line in the (i+2)-th subarray, the signal on the second bit line of the even-numbered positions in the (i+2)-th subarray is the inverted signal of the signal on the first bit line of the (i+1)-th subarray. Specifically, the signal on the second bit line of the even-numbered positions in the (i+2)-th subarray is the inverted signal of the signal on the first bit line of the odd-numbered positions in the (i+1)-th subarray.

[0107] When m is even, and when the word line address decoding circuit corresponding to the i-th subarray activates the target word line in the i-th subarray, the signal on the first bit line of the even-numbered positions in the i-th subarray is the inverted signal of the signal on the second bit line of the (i+1)-th subarray. Specifically, the signal on the first bit line of the even-numbered positions in the i-th subarray is the inverted signal of the second bit line of the odd-numbered positions in the (i+1)-th subarray. When the word line address decoding circuit corresponding to the (i+2)-th subarray activates the word line in the (i+2)-th subarray, the signal on the second bit line of the odd-numbered positions in the (i+2)-th subarray is the inverted signal of the signal on the first bit line of the (i+1)-th subarray. Specifically, the signal on the second bit line of the odd-numbered positions in the (i+2)-th subarray is the inverted signal of the signal on the first bit line of the even-numbered positions in the (i+1)-th subarray.

[0108] Optionally, when there are multiple SAs in each row, in one possible implementation, the i-th subarray is connected to the (i+1)-th subarray through the first first bit line of the i-th subarray, the first SA of the i-th row SA, and the second second bit line of the (i+1)-th subarray; the (i+1)-th subarray is connected to the (i+2)-th subarray through the first first bit line of the (i+1)-th subarray, the first SA of the (i+1)-th row SA, and the second second bit line of the (i+2)-th subarray; the i-th subarray is connected to the (i+1)-th subarray through the third first bit line of the i-th subarray, the second SA of the i-th row SA, and the fourth second bit line of the (i+1)-th subarray; the (i+1)-th subarray is connected to the (i+2)-th subarray through the third first bit line of the (i+1)-th subarray, the second SA of the (i+1)-th row SA, and the fourth second bit line of the (i+2)-th subarray, and so on.

[0109] In this embodiment, the subarray batch bit logic inversion operation can be implemented for different DRAM memory array structures, making it widely applicable.

[0110] Based on the Bank structure provided in the above embodiments, and the DRAM memory array structure in the two types of Banks, the process of implementing batch bit logic operations in the Bank in the embodiments of this application will be explained. Figure 12 This is a flowchart illustrating a method for performing batch bit logic operations within a Bank, as provided in an embodiment of this application. Figure 12 As shown, methods for performing batch bit logic operations within a Bank may include:

[0111] S1201, The controller sends the address of the target subarray to the subarray address decoding circuit, and sends the address of the target word line, the word line activation enable signal and the in-memory operation mode enable signal to the first latch circuit corresponding to each of the at least three adjacent subarrays.

[0112] S1202, the subarray address decoding circuit receives the address of the target subarray, determines the target subarray, and sends a strobe signal to the first latch circuit corresponding to the target subarray.

[0113] S1203. For the first latch circuit corresponding to each of the at least three adjacent subarrays, the first latch circuit receives the strobe signal and sends the multi-subarray word line activation signal and the target word line address to the corresponding first word line address decoding circuit according to the target word line address, word line activation enable signal and in-memory operation mode enable signal.

[0114] S1204. The first latch circuit acquires the vector and writes the vector to the target word line in the i-th subarray and the target word line in the (i+2)-th subarray.

[0115] S1205, the first word line address decoding circuit activates the target word line in the corresponding target subarray based on the multi-subarray word line activation signal and the address of the target word line.

[0116] S1206, Each of at least three adjacent subarrays performs read and / or write operations.

[0117] S1207, The first word line address decoding circuit corresponding to each of the at least three adjacent subarrays turns off the target word line in the target subarray.

[0118] S1208, Pre-charge.

[0119] It should be understood that S1201-S1203 can refer to the relevant descriptions in the above embodiments, and the process of each subarray performing read and / or write operations and performing pre-charge in S1206-S1208 can refer to the relevant descriptions in the current technical solutions.

[0120] In S1204 above, in this embodiment of the application, the vector obtained by the first latch circuit is related to the column address of the first bit line in the target subarray in the target word line of the target subarray. Optionally, the column address of the target word line in the subarray can be stored in the address storage unit. After determining that the target word line in the i-th subarray needs to be activated, the first latch circuit can obtain the vector related to the column address of the first bit line in the i-th subarray in the target word line of the i-th subarray in the address storage unit, and obtain the vector related to the column address of the first bit line in the (i+2)-th subarray in the (i+2)-th subarray in the target word line of the i-th subarray in the address storage unit. In this embodiment of the application, the vector related to the column address of the first bit line in the i-th subarray in the target word line of the i-th subarray and the vector related to the column address of the first bit line in the i-th subarray in the target word line of the i-th subarray can be the same.

[0121] Specifically, when m equals n, x equals y, and m and x are consecutive integers, the first bit line in the i-th subarray connected by the SA in the i-th row and the second bit line in the (i+1)-th subarray have the same parity bit. Similarly, the first bit line in the (i+1)-th subarray connected by the SA in the (i+1)-th row and the second bit line in the (i+2)-th subarray have the same parity bit. In this case, the first and second bit lines connected by the SA are arranged in an odd-odd and even-even correspondence, thus the address storage unit can generate the corresponding vector based on the column address of the bit lines in the subarray.

[0122] Specifically, when m equals x, n equals y, and m and n are consecutive integers, the parity bit of the first bit line in the i-th subarray connected by SA in the i-th row is different from that of the second bit line in the (i+1)-th subarray, and the parity bit of the first bit line in the (i+1)-th subarray connected by SA in the (i+1)-th row is different from that of the second bit line in the (i+2)-th subarray. In this case, the parity bits of the first and second bit lines connected by SA are interleaved. Therefore, the address storage unit can invert the column addresses of the bit lines (BL and !BL) in the subarray and then generate the corresponding vector, i.e., the column address is the column address after parity bit swapping. Specifically, in this embodiment, the address storage unit can invert the last column address of the bit lines in the subarray to generate the corresponding vector.

[0123] For example, Figure 13 This is a schematic diagram illustrating the inversion of column addresses of bit lines in a subarray, as provided in an embodiment of this application. Figure 13 As shown, the column address of the bit line in the subarray is Ya[H-1:1]. The new address after inverting the last address of this column address is Ya*[H-1:0]. A vector can then be generated based on this new column address Ya*[H-1:0]. In other words, in this case, the column address associated with the vector is the column address after parity bit swapping.

[0124] In the above S1205, if at least three adjacent subarrays include the i-th subarray, the (i+1)-th subarray, and the (i+2)-th subarray, then S1205 may include:

[0125] S12051, the first word line address decoding circuit corresponding to the i-th subarray, activates the target word line in the i-th subarray.

[0126] S12052, the first word line address decoding circuit corresponding to the (i+1)th subarray, activates the target word line in the (i+1)th subarray.

[0127] S12053, the first word line address decoding circuit corresponding to the (i+2)th subarray, activates the target word line in the (i+2)th subarray.

[0128] S12051-S12053 can be executed simultaneously.

[0129] In this embodiment, based on the structure of different DRAM memory arrays, different vectors corresponding to the structure of the DRAM memory array can be obtained, and then the vectors are written into the i-th subarray and the (i+2)-th subarray. Then the latch circuit can enable multiple word line address decoding circuits to activate the target address in the corresponding target subarray, thereby achieving the purpose of batch bit logic inversion operation in the (i+1)-th subarray.

[0130] Figure 14 This is a schematic diagram of the structure of a system for performing an inversion operation provided in an embodiment of this application. Figure 14 As shown, the system performing the inversion operation may include a repository 1401 and a controller 1402 as described in the above embodiments. The specific structure of the repository 1401 can be found in the relevant descriptions in the above embodiments.

[0131] This application also provides a dynamic random access memory (DRAM), which may include at least one bank and a memory input / output (I / O) device as described in the above embodiments, with the I / O device connected to at least one bank. The layout and connection method of the bank in the DRAM can be referred to relevant descriptions in current DRAM implementations.

[0132] This application also provides an electronic device. Figure 15 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 15 As shown, the electronic device may include a dynamic random access memory 1501 and a controller 1402 as described in the above embodiments. The controller is coupled to each bank in the dynamic random access memory, and can perform the actions of the controller in the above embodiments to implement a batch bit logic inversion operation in the DRAM.

[0133] It should be understood that the controller in the embodiments of this application may include, but is not limited to, a processor. For example, the processor may be a separately established processing element, such as a central processing unit (CPU) or other processor capable of calling program code. Alternatively, it may be integrated into a chip in the aforementioned device. Furthermore, it may be stored as program code in the memory of the aforementioned device, and called and executed by a processing element in the electronic device. The processing element here may be an integrated circuit with signal processing capabilities.

[0134] The term "multiple" in this article refers to two or more. The term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Furthermore, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects; in formulas, the character " / " indicates a "division" relationship between the preceding and following related objects.

[0135] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application.

[0136] It is understood that, in the embodiments of this application, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

Claims

1. A bank, characterized in that, include: The system comprises N latch circuits, N word line address decoding circuits, and a dynamic random access memory (DRAM) array. The DRAM array includes N subarrays, with adjacent subarrays connected together. The latch circuits, word line address decoding circuits, and subarrays are in one-to-one correspondence. Each latch circuit is connected to its corresponding word line address decoding circuit, and each word line address decoding circuit is connected to its corresponding subarray through a word line in the subarray. N is an integer greater than or equal to 1. For the first latch circuit and the first word line address decoding circuit corresponding to each of at least three adjacent subarrays, where: The first latch circuit is used to send a multi-subarray word line activation signal to the corresponding first word line address decoding circuit according to the in-memory operation mode enable signal from the controller, wherein the controller is connected to the Bank; The first word line address decoding circuit is used to activate the target word line in the subarray corresponding to the first word line address decoding circuit according to the multi-subarray word line activation signal, so that the bit logic of the middle array of any three adjacent subarrays in the at least three adjacent subarrays is inverted.

2. The repository Bank according to claim 1, characterized in that, The first latch circuit includes a latch and a multiplexer, the latch is connected to the multiplexer, and the multiplexer is connected to the first word line address decoding circuit corresponding to the first latch circuit. The latch is used to send the multi-subarray word line activation signal to the multiplexer according to the in-memory operation mode enable signal from the controller. The multiplexer is configured to receive the multi-subarray word line activation signal from the latch and the address of the target word line from the controller, and to select the first word line address decoding circuit corresponding to the first latch circuit to send the multi-subarray word line activation signal.

3. The repository Bank according to claim 2, characterized in that, The multiplexer is also connected to the controller; If the latch does not receive an in-memory operation mode enable signal from the controller, the multiplexer is also used to receive the address of the target word line from the controller and send a single-array word line activation signal to the first word line address decoding circuit corresponding to the first latch circuit.

4. The repository Bank according to claim 1 or 2, characterized in that, The first latch circuit is further configured to send the address of the target word line to the first word line address decoding circuit corresponding to the first latch circuit according to the address of the target word line from the controller; The first word line address decoding circuit is used to activate the target word line in the subarray corresponding to the first word line address decoding circuit according to the multi-subarray word line activation signal and the address of the target word line.

5. The bank according to any one of claims 1-3, characterized in that, The repository further includes: at least one subarray address decoding circuit, the at least one subarray address decoding circuit being connected to the N latch circuits; The subarray address decoding circuit is configured to send a strobe signal to a first latch circuit corresponding to each of the at least three adjacent subarrays based on the addresses of the at least three adjacent subarrays from the controller. The strobe signal is used to indicate the selection of the subarray corresponding to the first latch circuit.

6. The bank according to any one of claims 1-3, characterized in that, The at least three adjacent subarrays include: the i-th subarray, the (i+1)-th subarray, and the (i+2)-th subarray among the N subarrays, where i is an integer greater than or equal to 1 and less than or equal to N-2; the i-th subarray is connected to the (i+1)-th subarray through the first bit line of the i-th subarray, the i-th row sensitive amplifier SA, and the second bit line of the (i+1)-th subarray; the (i+1)-th subarray is connected to the (i+2)-th subarray through the first bit line of the (i+1)-th subarray, the i+1-th row SA, and the second bit line of the (i+2)-th subarray; the first bit line and the second bit line are inverted bit lines of each other. The SA is used to output a first level signal from the level signal generator to the first bit line connected to the SA, and to output a second level signal from the level signal generator to the second bit line connected to the SA. The SA includes the i-th row SA and the (i+1)-th row SA, and the first level signal and the second level signal are logically inverted level signals. When the word line address decoding circuit corresponding to the i-th subarray activates the target word line in the i-th subarray, the signal on the first bit line in the i-th subarray and the signal on the second bit line in the (i+1)-th subarray are inverted signals. When the word line address decoding circuit corresponding to the (i+2)th subarray activates the target word line in the (i+2)th subarray, the signal on the second bit line in the (i+2)th subarray is the inverted signal of the signal on the first bit line in the (i+1)th subarray.

7. The repository Bank according to claim 6, characterized in that, The i-th subarray is connected to the (i+1)-th subarray through the m-th first bit line, the i-th row SA, and the n-th second bit line of the (i+1)-th subarray. The (i+1)-th subarray is connected to the (i+2)-th subarray through the x-th first bit line, the (i+1)-th row SA, and the y-th second bit line of the (i+2)-th subarray. Where m, n, x, and y are all integers greater than or equal to 1. Wherein, m is equal to n, x is equal to y, and m and x are consecutive integers; or, The m is equal to the x, the n is equal to the y, and the m and the n are consecutive integers.

8. The repository Bank according to claim 7, characterized in that, m is an odd number; When the word line address decoding circuit corresponding to the i-th subarray activates the target word line in the i-th subarray, the signal on the first bit line of the odd-numbered bits in the i-th subarray and the signal on the second bit line of the (i+1)-th subarray are inverted signals. When the word line address decoding circuit corresponding to the (i+2)th subarray activates the word line in the (i+2)th subarray, the signal on the second bit line of the even-numbered position in the (i+2)th subarray is the inverted signal of the signal on the first bit line of the (i+1)th subarray.

9. The repository Bank according to claim 7, characterized in that, The number m is even. When the word line address decoding circuit corresponding to the i-th subarray activates the target word line in the i-th subarray, the signal on the first bit line of the even-numbered bits in the i-th subarray and the signal on the second bit line of the (i+1)-th subarray are inverted signals. When the word line address decoding circuit corresponding to the (i+2)th subarray activates the word line in the (i+2)th subarray, the signal on the second bit line of the odd-numbered position in the (i+2)th subarray is the inverted signal of the signal on the first bit line in the (i+1)th subarray.

10. The bank according to any one of claims 7-9, characterized in that, The first latch circuit is further configured to acquire a vector and write the vector to the target word line in the i-th subarray and the target word line in the (i+2)-th subarray, wherein the vector is related to the column address of the first bit line in the target subarray in the target word line of the target subarray; Wherein, when m is equal to x, n is equal to y, and m and n are adjacent integers, the column address is the column address after parity bit swapping.

11. A system for performing an inversion operation, characterized in that, include: The repository Bank and controller as described in any one of claims 1-10 above.

12. A dynamic random access memory, characterized in that, include: At least one bank and memory input / output device as described in any one of claims 1-10 above, wherein the memory input / output device is connected to at least one bank.

13. An electronic device, characterized in that, include: The dynamic random access memory and controller as described in claim 12 above, wherein the controller is coupled to each repository Bank in the dynamic random access memory.

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