A circuit and method for capacitance detection

Abstract

The present invention relates to a circuit and method for capacitance detection, comprising: a capacitance to be measured, a quantization unit, an integrator, a comparator, and a counting unit, wherein the first end of the capacitance to be measured is connected to the quantization unit, and the second end of the capacitance to be measured is connected to the ground; the quantization unit comprises a first quantization device and a second quantization device; the first end of the second quantization device is connected to a power supply, and the second end of the second quantization device is connected to the first input end of the integrator; the first end of the first quantization device is connected to the first input end of the integrator, and the second end of the first quantizer is connected to the ground; the output end of the integrator is connected to the input end of the comparator, and the output end of the comparator is connected to the input end of the counting unit. The present invention reduces the complexity of the capacitance quantization system, reduces the system power consumption, and improves the speed and accuracy of quantization.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitance detection, and in particular to a circuit and method for capacitance detection. Background Art

[0002] Traditional capacitance detection uses a reference voltage to charge the capacitor to be detected, then uses an integrator to convert the capacitance information into voltage information output by the integrator, and finally uses an ADC to convert the voltage into a digital output. The working principle of this structure is clear and it is conducive to analyzing the impact of each part, but the process is complicated and it is necessary to wait for the previous stage to be completed before the next stage can be processed, which will reduce the operating speed of the system and increase the average power consumption of the system. In addition, the output voltage of the integrator is related to the integral capacitor, and the integral capacitor will have process deviations, resulting in gain errors in the corresponding relationship between voltage and capacitance. Summary of the invention

[0003] The purpose of the present invention is to reduce the complexity of a capacitance quantization system, reduce system power consumption, improve the speed and accuracy of quantization, and provide a circuit and method for capacitance detection.

[0004] In order to achieve the above-mentioned object of the invention, the embodiment of the present invention provides the following technical solutions:

[0005] A circuit for capacitance detection includes: a capacitance to be measured, a quantization unit, an integrator, a comparator, and a counting unit, wherein:

[0006] The first end of the capacitor to be measured is connected to the quantization unit, and the second end of the capacitor to be measured is connected to the ground;

[0007] The quantization unit comprises a first quantization device and a second quantization device; the first end of the second quantization device is connected to a power supply, and the second end of the second quantization device is connected to a first input end of an integrator; the first end of the first quantization device is connected to a first input end of the integrator, and the second end of the first quantization device is connected to a ground;

[0008] The output end of the integrator is connected to the input end of the comparator, and the output end of the comparator is connected to the input end of the counting unit.

[0009] Furthermore, the integrator further comprises an integrating capacitor Cint, a first end of the integrating capacitor Cint is connected to the first input end of the integrator, and a second end of the integrating capacitor Cint is connected to the output end of the integrator.

[0010] Furthermore, the first quantization device includes a first switch CK_S1 and a first current detector; the first end of the first switch CK_S1 is connected to the first input end of the integrator, the second end of the first switch CK_S1 is connected to the first end of the first current detector, and the second end of the first current detector is connected to the ground.

[0011] Furthermore, the second quantization device includes a second switch CK_S2 and a second current detector; a first end of the second current detector is connected to the power supply AVDD, a second end of the second current detector is connected to the first end of the second switch CK_S2, and a second end of the second switch CK_S2 is connected to the first input end of the integrator.

[0012] Furthermore, the first end of the capacitor to be measured is connected to a reference voltage Vref through a third switch CK_CG.

[0013] A method for capacitance detection, applied to any of the above circuits, comprises the following steps:

[0014] Step 1, the remaining charge after the capacitor to be measured is compensated is transferred to the integrating capacitor of the integrator;

[0015] Step 2, controlling the first quantization device to quantize the charge in the integration capacitor until the charge in the integration capacitor is negative, stopping the quantization of the first quantization device, and recording the quantization times m1 of the first quantization device;

[0016] Step 3, controlling the second quantization device to continue quantizing the charge in the integration capacitor until the charge in the integration capacitor is positive, stopping the quantization of the second quantization device, and recording the quantization times m2 of the second quantization device;

[0017] Step 4, repeat steps 1 to 3 multiple times until the resolution of the circuit reaches a preset standard.

[0018] Furthermore, the step 2 of obtaining the quantization order m1 includes:

[0019] The first quantization device is controlled to quantize the charge amount in the integral capacitor, where the charge amount in the integral capacitor is the charge amount Q remaining after the capacitor to be measured is compensated N times. N , until the charge amount in the integrating capacitor becomes negative, the quantization of the first quantization device is stopped, and the count value of the counting unit is recorded as the quantization number m1;

[0020] The first quantization device is used to measure the charge Q on the integral capacitor. N The quantization process includes: repeatedly closing the first switch CK_S1 for a time period of Δt and then opening it until the charge on the integration capacitor is negative, and recording the count value of the counting unit as the quantization number m1.

[0021] Furthermore, the step of obtaining the quantization order m2 in step 3 includes:

[0022] Control the second quantization unit to continue quantizing the charge in the integration capacitor until the charge in the integration capacitor is positive, stop quantizing the second quantization device, and record the count value of the counting unit as the quantization number m2;

[0023] The process of the second quantization device quantizing the charge on the integration capacitor includes: repeatedly closing the second switch CK_S2 for a period of Δt and then opening it until the charge on the integration capacitor is positive, and recording the count value of the counting unit as the quantization number m2.

[0024] Furthermore, the resolution of the circuit in step 4 reaches a preset standard:

[0025] ΔQ=Vcm·C LSB ·M

[0026] Among them, C LSB is the preset standard for resolution; Vcm is the voltage at the second input terminal of the integrator; ΔQ is the amount of charge quantized by the first quantization device and / or the second quantization device; M is the number of complete quantization times, and performing m1 quantization of the first quantization device once and m2 quantization of the second quantization device once represents one complete quantization.

[0027] Furthermore, after each complete quantization, an error charge Δq is retained on the integration capacitor Cint. The error charge Δq is equal to the charge Q on the integration capacitor Cint during the next complete quantization process. N quantified together.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The present invention reduces the complexity of the capacitance quantization system, reduces the system power consumption, and improves the speed and accuracy of quantization. At the same time, it reduces the gain error introduced by the integral capacitance with process deviation and the current detector IDAC with voltage change, eliminates the influence of interference signals on the capacitor pin port during the quantization process, and improves the signal-to-noise ratio of the system.

[0030] The present invention is different from the traditional solution in that:

[0031] (1) The quantization position of the current detector IDAC is before the integrator. The quantized current passes through the integrator's integrating capacitor, directly changing the voltage output by the integrator. Therefore, only a comparator needs to be connected to the output of the integrator. The level of the comparator output can be used to determine the charge on the integrating capacitor.

[0032] (2) The current detector IDAC is located at the input of the integrator. Due to the virtual short of the op amp, the quantized charge on the integrating capacitor is equal each time the current is connected, avoiding the nonlinearity in the process of quantizing the current at the output of the integrator, and ensuring the accuracy of the system.

[0033] (3) The charge on the capacitor Cs to be measured is compensated and stored on the integrating capacitor Cint. At this time, the switch K1 connecting the capacitor Cs to be measured and the internal circuit can be disconnected, thereby ensuring that the quantization process will not be affected by the coupling interference on the path of the capacitor Cs to be measured on the PCB board, thereby ensuring the accuracy of the quantization.

[0034] (4) This circuit multiplexes the switch K6 with the integrator, which reduces the circuit area, power consumption and complexity and speeds up the quantization speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 1 is a circuit diagram of Embodiment 1 of the present invention;

[0037] Figure 2 This is a circuit schematic diagram of compensating the measuring capacitance in Embodiment 1 of the present invention;

[0038] Figure 3 A circuit schematic diagram for obtaining the quantization order m1 according to Embodiment 1 of the present invention;

[0039] Figure 4 A circuit schematic diagram for obtaining the quantization order m2 according to Embodiment 1 of the present invention;

[0040] Figure 5 2 is a circuit diagram of Embodiment 2 of the present invention;

[0041] Figure 6 This is a circuit diagram of the capacitance compensation circuit according to Embodiment 1 of the present invention for compensating the capacitance to be measured. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

[0043] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance, or implying any such actual relationship or order between these entities or operations. In addition, the terms "connected", "connected", etc. can be directly connected between elements, or indirectly connected via other elements.

[0044] Embodiment 1:

[0045] The present invention is achieved through the following technical solutions: Figure 1 As shown, a circuit for capacitance detection includes a capacitance to be measured Cs, a quantization unit, an integrator (an amplifier is used in some embodiments), a comparator, and a counting unit, wherein the capacitance to be measured Cs is a self-capacitance, wherein:

[0046] The first end of the capacitor Cs to be measured is connected to the quantization unit, and the second end of the capacitor Cs to be measured is connected to the ground. The first end of the capacitor Cs to be measured is connected to the reference voltage Vref through the third switch CK_CG.

[0047] The quantization unit includes a first quantization device and a second quantization device; the first quantization device includes a first switch CK_S1 and a first current detector; the first end of the first switch CK_S1 is connected to the first input end of the integrator, the second end of the first switch CK_S1 is connected to the first end of the first current detector, and the second end of the first current detector is connected to the ground. The second quantization device includes a second switch CK_S2 and a second current detector; the first end of the second current detector is connected to the power supply AVDD, the second end of the second current detector is connected to the first end of the second switch CK_S2, and the second end of the second switch CK_S2 is connected to the first input end of the integrator.

[0048] The output end of the integrator is connected to the input end of the comparator, and the output end of the comparator is connected to the input end of the counting unit. The integrator also includes an integrating capacitor Cint, a first end of the integrating capacitor Cint is connected to the first input end of the integrator, and a second end of the integrating capacitor Cint is connected to the output end of the integrator. When the charge on the integrating capacitor Cint is positive, the comparator outputs a high level; when the charge on the integrating capacitor Cint is negative, the comparator outputs a low level.

[0049] The input end of the integrator is connected to a switch K5, and the integrating capacitor Cint is connected in parallel to a switch K6. When the reference voltage Vref charges the capacitor Cs to be measured, the switch K5 is disconnected. When the switch K6 is closed, the integrator is not connected to the circuit; when the switch K6 is disconnected, the integrator is connected to the circuit.

[0050] See also Figure 2 , and also includes a capacitance compensation unit for compensating the capacitance Cs to be measured. In one embodiment, the capacitance compensation unit includes a switch CK_COMP_N, a switch CK_COMP_P, and a compensation capacitor Cd; the first end of the switch CK_COMP_N is connected to the first end of the capacitance to be measured, the second end of the switch CK_COMP_N is connected to the first end of the switch CK_COMP_P and the first end of the compensation capacitor Cd, respectively, and the second end of the switch CK_COMP_P and the second end of the compensation capacitor Cd are both connected to the ground.

[0051] Before compensating the capacitance Cs to be measured, it is necessary to determine the number of compensation times N. The circuit further includes an initial capacitor C, a first end of which is connected to the first end of the capacitance Cs to be measured, and a second end of which is connected to the ground. The initial capacitor C is connected in parallel with the capacitance Cs to be measured, and is used to assist in determining the number of compensation times N of the capacitance compensation unit for the capacitance Cs to be measured.

[0052] Based on the above circuit, this scheme also proposes a method for capacitance detection, including the following steps:

[0053] Step 1: the remaining charge of the capacitor to be measured after compensation is transferred to the integrating capacitor of the integrator.

[0054] In this embodiment, the capacitance Cs to be measured is the self-capacitance, see Figure 2 Before testing, the capacitor Cs to be measured needs to be compensated, and the remaining charge after compensation is transferred to the integrating capacitor. After determining the compensation times N for the capacitor Cs to be measured, the capacitor Cs to be measured can be compensated N times before testing the capacitors Cs to be measured in the same batch, without determining the compensation times N again.

[0055] An applicable compensation method can be selected. In one embodiment, the compensation method is: closing switch K2 to connect the initial capacitor C to the circuit, and opening switch K1 to disconnect the capacitor Cs to be measured from the circuit, closing switch CK_CG to charge the initial capacitor C with the reference voltage Vref, and after charging, the charge stored on the initial capacitor C is Q, and the charge Q on the initial capacitor C is quantized by the first quantization device, at which time switch K5 is closed and switch K6 is closed until the voltage on the initial capacitor C is the common mode voltage Vcm, and the common mode voltage Vcm is the access potential of the second input terminal of the comparator.

[0056] The current of the first current detector in the first quantization device is I, and each time the first switch CK_S1 is closed, the first quantization device quantizes the charge ΔQ on the initial capacitor C, and ΔQ=I·Δt, where Δt is the time for which the switch CK_S1 is continuously closed. The process of the first quantization device quantizing the charge Q on the initial capacitor C includes: repeatedly closing the first switch CK_S1 for a period of Δt and then disconnecting it until the voltage on the initial capacitor C is the common mode voltage Vcm, and recording the count value of the counting unit as the initial number of times n1, which is the number of times the first switch CK_S1 is closed.

[0057] The switch K1 is closed to connect the capacitor Cs to be measured to the circuit, and the switch K2 is opened to disconnect the initial capacitor C from the circuit. The switch CK_CG is closed to charge the capacitor Cs to be measured with the reference voltage Vref. After the charging is completed, the charge stored on the capacitor Cs to be measured is Q0. The capacitor compensation circuit compensates the capacitor Cs to be measured. The principle of the capacitor compensation circuit is as follows: Figure 6 As shown, there are:

[0058] Q0=Cs×Vref

[0059] The capacitance compensation circuit compensates the capacitance Cs to be measured:

[0060] Q0=(Cs+Cd)×V1

[0061]

[0062] Q1=Cs×V1

[0063] Wherein, Cd is the compensation capacitor; V1 is the voltage at the intersection of the capacitor Cs to be measured and the compensation capacitor Cd after the capacitor Cs to be measured is compensated once; Q1 is the remaining charge on the capacitor Cs to be measured after the capacitor Cs to be measured is compensated once;

[0064] After the capacitance compensation circuit compensates the capacitance Cs to be measured N times:

[0065]

[0066] QN =Cs×V N

[0067] Among them, V N Q is the voltage at the intersection of the measured capacitance Cs and the compensation capacitance Cd after the measured capacitance Cs is compensated N times; N It is the remaining charge on the capacitor Cs to be measured after the capacitor to be measured is compensated N times.

[0068] The remaining charge Q on the capacitor Cs to be measured after the first quantization device performs N compensations N Quantization is performed until the voltage on the capacitor Cs to be measured reaches the common mode voltage Vcm.

[0069] The remaining charge Q on the capacitor Cs to be measured after the first quantization device performs N compensations N The quantization process includes: repeatedly closing the first switch CK_S1 for a time period of Δt and then opening it until the voltage on the capacitor Cs to be measured reaches the common mode voltage Vcm, and recording the count value of the counting unit as the quantization number n2.

[0070] If n2 is greater than n1, the compensation times N are readjusted so that the remaining charge Q after the capacitor Cs to be measured is compensated N times N After the quantization unit completes the quantization, the obtained quantization number n2 is less than the initial number n1; at the same time, the compensation number N for the capacitance Cs to be measured is obtained when the quantization number n2 is less than the initial number n1.

[0071] After the compensation is completed, the switch K5 is closed and the switch K6 is opened. The remaining charge QN after the capacitor Cs to be measured is compensated N times is transferred to the integrating capacitor Cint, and then the switch K1 is opened. After that, before testing the capacitors Cs to be measured in the same batch, the capacitors Cs to be measured can be directly compensated N times.

[0072] Step 2, control the first quantization device to quantize the charge in the integration capacitor until the charge in the integration capacitor is negative, stop the quantization of the first quantization device, and record the quantization times m1 of the first quantization device.

[0073] See also Figure 3 , at this time the charge on the integrating capacitor Cint is Q N There are two cases: one is that before the test, when the charge on the capacitor Cs to be measured is normal, the charge on the integral capacitor Cint is Q N is positive; the second case is that before the detection, the charge on the capacitor Cs to be measured suddenly decreases from the normal value to a very small value. At this time, the charge on the integrating capacitor Cint is Q N is negative.

[0074] For the first case, the first quantization device controls the charge Q in the integral capacitor Cint. N Quantization is performed, and the first current detector in the first quantization device quantizes negative charges, and each time the charge amount ΔQ is quantized. After m1 times of quantization, the charge amount on the integration capacitor Cint becomes negative, and the quantization of the first quantization device is stopped at this time.

[0075] When the charge on the integrating capacitor Cint is positive, the comparator outputs a high level; when the charge on the integrating capacitor Cint is negative, the comparator outputs a low level. Therefore, the level output by the comparator can be used to determine whether the charge on the integrating capacitor Cint is positive or negative.

[0076] Therefore, when the comparator outputs a low level, the first quantization device stops working, and then the counting unit outputs the quantization times m1 of the first quantization device.

[0077] For the second case, the first quantization device quantizes the charge QN in the integral capacitor Cint. N It is originally negative. After the first quantization device performs one quantization, the comparator outputs a low level, so the quantization of the first quantization device is stopped at this time, and then the counting unit outputs the quantization times m1 of the first quantization device, and usually m1=1.

[0078] Step 3, control the second quantization device to continue quantizing the charge in the integration capacitor until the charge in the integration capacitor is positive, stop the quantization of the second quantization device, and record the quantization times m2 of the second quantization device.

[0079] See also Figure 4 , following the first case, the second quantization device continues to quantize the charge in the integration capacitor Cint. The second current detector in the second quantization device quantizes the positive charge. Similarly, each time the charge is quantized, ΔQ. After m2 quantizations, the charge on the integration capacitor Cint is positive. Since the charge on the integration capacitor Cint has just changed from positive to negative after the first quantization device quantizes the integration capacitor Cint m1 times, the charge on the integration capacitor Cint can change from negative to positive after the second quantization device quantizes once, and the comparator outputs a high level. At this time, the quantization of the second quantization device is stopped, and then the counting unit outputs the quantization times m2 of the second quantization device, and usually m2=1.

[0080] Next, in the second case, the second quantization device quantizes the charge in the integrating capacitor Cint. After m2 quantizations, the charge on the integrating capacitor Cint changes from negative to positive, the comparator outputs a high level, the second quantization device stops working, and then the counting unit outputs the quantization times m2 of the second quantization device.

[0081] Step 4, repeat steps 1 to 3 multiple times until the resolution of the circuit reaches a preset standard.

[0082] Steps 1 to 3 are a complete quantization process. Here we only take the first case as an example to continue the explanation. The second case is the same and will not be repeated. After the integral capacitor Cint is quantized m1 times by the first quantization device and m2 times by the second quantization device, a complete quantization is completed. The integral capacitor Cint will still have an error charge Δq1. The error current Δq1 will be equal to the charge Q on the integral capacitor Cint during the second complete quantization process. N After the second complete quantization, the error charge Δq2 will still remain on the integration capacitor Cint, and the error charge Δq2 will be quantized together with the charge Q on the integration capacitor Cint during the third complete quantization process. N Quantify together.

[0083] However, no matter how many times the complete quantization is performed, the error charge Δq retained on the integral capacitor Cint is always within a range, and this range is smaller than ΔQ. In this way, after M times of oversampling (that is, M times of complete quantization), the error charge Δq equivalent to the result of one oversampling will be evenly distributed into M parts, so the resolution of the entire circuit will be improved, and the detection accuracy will also be improved.

[0084] Before system detection, the standard resolution can be set to C LSB , and there are:

[0085] ΔQ=Vcm·C LSB ·M

[0086] During detection, ΔQ is fixed, Vcm is fixed, and the standard resolution is preset to C LSB , the total number of quantization times M can be calculated. When M complete quantizations are completed, the standard resolution C will be reached. LSB , at this time, quantization is completed. In the subsequent normal detection, the charge on the capacitor Cs to be measured can be directly detected, and the accuracy of the system detection has been greatly improved.

[0087] Embodiment 2:

[0088] See also Figure 5 , a circuit for mutual capacitance detection, including a capacitance to be measured Cm, a quantization unit, an integrator, a comparator, and a counting unit, wherein the capacitance to be measured Cm is a mutual capacitance. Different from Embodiment 1, the mutual capacitance Cm does not need to be compensated, and after the mutual capacitance Cm is charged by the common mode voltage Vcm, the voltage at the first input terminal of the integrator and the voltage at the second output terminal are equal, both being Vcm.

[0089] The charge Q on the integral capacitor Cint is Cm·Vcm=Q. The charge Q is quantized by the first quantization unit m1 and by the second quantization unit m2. The rest of the contents are the same as those in Embodiment 1 and will not be described again.

[0090] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A circuit for capacitance detection, characterized in that: include: Capacitance to be measured, quantization unit, integrator, comparator, counting unit, wherein, The quantization unit includes a first quantization device and a second quantization device; the first end of the capacitor to be measured is connected to the first quantization device and the second quantization device respectively, and the second end of the capacitor to be measured is connected to the ground; The first quantization device includes a first switch CK_S1 and a first current detector; the first end of the first switch CK_S1 is connected to the first input end of the integrator, the second end of the first switch CK_S1 is connected to the first end of the first current detector, and the second end of the first current detector is connected to the ground; the second quantization device includes a second switch CK_S2 and a second current detector; the first end of the second current detector is connected to the power supply AVDD, the second end of the second current detector is connected to the first end of the second switch CK_S2, and the second end of the second switch CK_S2 is connected to the first input end of the integrator; The integrator comprises an integrating capacitor Cint, a first end of the integrating capacitor Cint is connected to a first input end of the integrator, and a second end of the integrating capacitor Cint is connected to an output end of the integrator; a second input end of the integrator is connected to a voltage Vcm; The first quantization device is used to quantize the charge in the integration capacitor Cint until the charge in the integration capacitor Cint is negative, and the counting unit outputs the quantization times m1 of the first quantization device; the second quantization device is used to quantize the charge in the integration capacitor Cint until the charge in the integration capacitor Cint is positive, and the counting unit outputs the quantization times m2 of the second quantization device; The output end of the integrator is connected to the first input end of the comparator, and the output end of the comparator is connected to the input end of the counting unit; the second input end of the comparator is connected to the voltage Vcm.

2. A circuit for capacitance detection according to claim 1, characterized in that: The first end of the capacitor to be measured is connected to a reference voltage Vref through a third switch CK_CG.

3. A method for capacitance detection, applied to the circuit of any one of claims 1-2, characterized in that: The following steps are involved: Step 1, the remaining charge after the capacitor to be measured is compensated is transferred to the integrating capacitor of the integrator; Step 2, controlling the first quantization device to quantize the charge in the integral capacitor until the charge in the integral capacitor is negative, stopping the quantization of the first quantization device, and recording the quantization times m1 of the first quantization device; Step 3, controlling the second quantization device to continue quantizing the charge in the integration capacitor until the charge in the integration capacitor is positive, stopping the quantization of the second quantization device, and recording the quantization times m2 of the second quantization device; Step 4, repeating steps 1 to 3 multiple times until the resolution of the circuit reaches a preset standard; The resolution of the circuit in step 4 reaches the preset standard: Among them, C LSB Preset standards for resolution; Vcm is the voltage at the second input terminal of the integrator; ∆Q is the amount of charge quantized by the first quantization device or the second quantization device at one time, and the amount of charge quantized by the first quantization device at one time is equal to the amount of charge quantized by the second quantization device at one time; M is the number of complete quantization times, and performing m1 quantization of the first quantization device once and m2 quantization of the second quantization device once represents one complete quantization.

4. A method for capacitance detection according to claim 3, characterized in that: The step 2 of obtaining the quantization order m1 comprises: The first quantization device is controlled to quantize the charge amount in the integral capacitor, where the charge amount in the integral capacitor is the charge amount Q remaining after the capacitor to be measured is compensated N times. N , until the charge amount in the integrating capacitor becomes negative, the quantization of the first quantization device is stopped, and the count value of the counting unit is recorded as the quantization number m1; The first quantization device is used to measure the charge Q on the integral capacitor. N The process of quantization includes: repeatedly closing the first switch CK_S1 for a time period of ∆t and then opening it until the charge on the integration capacitor is negative, and recording the count value of the counting unit as the quantization number m1.

5. A method for capacitance detection according to claim 4, characterized in that: The step 3 of obtaining the quantization number m2 comprises: Control the second quantization unit to continue quantizing the charge in the integration capacitor until the charge in the integration capacitor is positive, stop quantizing the second quantization device, and record the count value of the counting unit as the quantization number m2; The process of quantizing the charge on the integration capacitor by the second quantization device includes: repeatedly closing the second switch CK_S2 for a period of ∆t and then opening it until the charge on the integration capacitor is positive, and recording the count value of the counting unit as the quantization number m2.

6. A method for capacitance detection according to claim 3, characterized in that: After each complete quantization, an error charge ∆q is retained on the integration capacitor Cint. The error charge ∆q is equal to the charge Q on the integration capacitor Cint during the next complete quantization process. N quantified together.

Images