A test method for asymmetric bridging faults

Abstract

The present invention belongs to the field of integrated circuit testing technology, specifically a method for testing asymmetric bridging faults. The present invention refers to the logical state of all test nets at the same moment as a logic vector. If the logical states of all test nets within an integrated circuit are fully controllable and observable, the present invention provides a set of logic vectors that can detect asymmetric bridging faults (dominance faults, dominance and faults, or dominance or faults) between any two test nets. The present invention is easy to automate, highly versatile, and requires a relatively small number of logic vectors, thereby improving testing efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit testing, and in particular relates to a method for testing asymmetric bridging faults, which can be used to detect whether there are asymmetric bridging faults (dominance fault, dominance and fault, dominance or fault) between line networks. Background Art

[0002] In the field of integrated circuit testing, setting the test net to a specific logical state and observing whether it matches a fault-free reference state is a common fault detection method applicable to various IC testing scenarios, such as ASIC testing, FPGA application-related testing, and FPGA application-independent testing. The logical state of all test nets at the same moment is called a logic vector. If the logic states of all test nets within the IC are fully controllable and observable, the goal of the testing method is to detect as many faults as possible using as few logic vectors as possible, and the process of obtaining the logic vectors should be as automated as possible.

[0003] Bridging fault testing has always been an important issue in the field of integrated circuit testing. Reference [1] points out that in addition to symmetrical bridging faults (line-and faults, line-or faults), asymmetrical bridging faults (dominant faults, dominant-and faults, dominant-or faults) may also exist between the lines of an integrated circuit. In this case, the logical state of one line network will be unilaterally affected by the logical state of another line network, causing the integrated circuit to malfunction. Testing asymmetrical bridging faults is more difficult than testing symmetrical bridging faults, and the testing of asymmetrical bridging faults will naturally cover the testing of symmetrical bridging faults and open circuit faults.

[0004] Reference [2] proposes a test method that obtains a logic vector by encoding the line network. If the logic states of all the lines to be tested in the integrated circuit are completely controllable and observable, then the logic vector provided by reference [2] can detect all open circuit faults and all symmetrical bridge faults, but cannot detect all asymmetrical bridge faults.

[0005] References

[0006] 【1】JMEmmert, CEStroud and JRBailey, "A new bridging fault model for more accurate fault behavior," 2000IEEE Autotestcon Proceedings.IEEESystems Readiness Technology Conference.Future Sustainment for MilitaryAerospace(Cat.No.00CH37057),2000,pp.481-485.

[0007] 【2】M.Tahoori, "Application-Dependent Testing of FPGAs," in IEEETransactions on Very Large Scale Integration (VLSI) Systems, vol.14, no.9, pp.1024-1033, Sept.2006. Summary of the Invention

[0008] The object of the present invention is to provide a method for testing asymmetric bridging faults which uses a small number of logic vectors, has high testing efficiency and strong versatility.

[0009] The present invention provides a method for testing asymmetric bridging faults. This method uses concise and clear steps to obtain a set of logic vectors, enabling detection of asymmetric bridging faults that may exist between any two test nets in an integrated circuit. The method also ensures a small number of logic vectors, thereby improving test efficiency. The specific steps are as follows:

[0010] (1) The number of logic vectors N is calculated by the number of lines M to be tested, so that N satisfies a N The smallest positive integer ≥M, where:

[0011]

[0012] floor(N / 2) means rounding down N / 2, and ceil(N / 2) means rounding up N / 2.

[0013] (2) Assign a binary code to each of the test lines. The number of bits of the code is the logic vector N. The number of 1s in each code is floor(N / 2), and the number of 0s is ceil(N / 2), or vice versa. Since floor(N / 2) codes are selected from N bits as 1 (or 0), it is easy to know that there are a total of codes that meet the requirements. M of them can be selected as the codes of all the network to be tested;

[0014] (3) Take the first bit of all the network codes to be tested to form the first logic vector, and so on to obtain all N logic vectors;

[0015] (4) Set the line network to be tested to the logic state indicated by the first logic vector at the same time, and observe whether the logic state is consistent with the reference state without faults; and so on. If the logic state is observed to be consistent with the reference state without faults for all N logic vectors, then there is no asymmetric bridging fault in the circuit.

[0016] The above steps can produce a relatively small number of logic vectors, and all asymmetric bridging faults can be activated and detected for the following reasons. Take any two nets, denoted as Net A and Net B. Since each net has a different encoding, but the number of 1s and 0s is the same, there must be two different bits in the encoding: one bit where Net A has a value of 1 and Net B has a value of 0, and the other bit where Net A has a value of 0 and Net B has a value of 1. This ensures that any asymmetric bridging faults that may exist between any two nets under test will be activated and detected. In the present invention, the number of 0s and 1s in the encoding should be as close as possible, thereby minimizing the number of bits in the encoding and, accordingly, the number of logic vectors.

[0017] The advantages of the present invention mainly include:

[0018] (1) The present invention is easy to automate, the steps are concise and clear, and no expert knowledge is required;

[0019] (2) The present invention is versatile and can be applied to different integrated circuit testing scenarios;

[0020] (3) The present invention can detect asymmetric bridging faults between any two lines to be tested;

[0021] (4) The number of test vectors of the present invention is relatively small. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of asymmetric bridging fault model.

[0023] Figure 2 Schematic diagram of the line network coding and logic vector to be tested.

[0024] Figure 3 The following is a schematic diagram of the network to be tested (taking FPGA application-related tests as an example).

[0025] Figure 4 This is a schematic diagram of the logical state of the line network under test when there is no fault.

[0026] Figure 5 Schematic diagram of the logic state of the line network under test when an asymmetric bridging fault occurs. DETAILED DESCRIPTION

[0027] In order to better illustrate the scheme and advantages of the present invention, the following is a specific description of the FPGA application related test with reference to the accompanying drawings. In this example, the FPGA application circuit is as follows Figure 3 As shown in the figure, the number of network to be tested is 6, which are respectively recorded as network A, B, C, D, E, and F.

[0028] In the first step, based on the number of nets to be tested being 6, the number of logic vectors calculated according to formula (1) is 4.

[0029] In the second step, a 4-bit binary code is assigned to each of the test lines. The number of 1s and 0s in each binary code is 2. It is not difficult to obtain the only 6 codes that meet the requirements: "0011", "0101", "0110", "1001", "1010", and "1100". These codes are used as the binary codes of the 6 test lines, as shown in the following example: Figure 2 shown.

[0030] The third step is to obtain four logical vectors: "000111", "011001", "101010", and "110100".

[0031] The fourth step is to configure the lookup table in the FPGA as a single-term function in order to simultaneously control and observe the logic states of all the lines under test. Taking the first logic vector "000111" as an example, the logic functions of each lookup table are reversed based on the logic states of the six lines under test, A=0, B=0, C=0, D=1, E=1, and F=1. The output line of the lookup table will be in a given logic state only when the input line of the lookup table is in a given logic state. The logic function at this time is called a single-term function, as shown in the following example: Figure 4 As shown, the bold solid line represents the logic state 1, and the dotted line represents the logic state 0. In addition, the initial state of each trigger needs to be configured to be the same as the given logic state of its output network. When all lookup tables and all triggers are configured correctly, all the lines to be tested in the FPGA application circuit can be set to the logic state shown by the logic vector at the same time. Assuming that there is an asymmetric bridging fault of "E dominates or B" in the application circuit, the logic state of line B will change from 0 to 1, causing the logic state of line F to change from 1 to 0, and the wrong logic state will be displayed at the output end, thereby detecting the fault, as shown in FIG. Figure 5 When all four logic vectors are tested, any asymmetric bridging fault between any two test nets can be detected.

[0032] The above description is merely a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that simple modifications and alterations made by those skilled in the art to the above embodiments, without departing from the scope and spirit of the present invention, in accordance with the technical essence of the present invention, fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for testing asymmetric bridging faults, characterized in that: The specific steps are as follows: (1) The number of logic vectors N is calculated by the number of lines M to be tested, so that N satisfies a N The smallest positive integer ≥M, where: floor(N / 2) means rounding down N / 2, and ceil(N / 2) means rounding up N / 2. (2) Assign a binary code to each of the test lines. The number of bits of the code is the logic vector N. The number of 1s in each code is floor(N / 2), and the number of 0s is ceil(N / 2), or vice versa. Since floor(N / 2) codes are selected from N bits as 1 or 0, there are a total of codes that meet the requirements. Therefore, M of them are randomly selected as the codes of all the network to be tested; (3) Take the first bit of all the network codes to be tested to form the first logic vector, and so on to obtain all N logic vectors; (4) Set the line network to be tested to the logic state shown by the first logic vector at the same time, and observe whether the logic state is consistent with the reference state without fault; and so on; if the logic state is observed to be consistent with the reference state without fault for all N logic vectors, then there is no asymmetric bridging fault in the circuit.

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