Circuit systems applied to memristor array weight modulation and image recognition

Abstract

This invention provides a circuit system for memristor array weight modulation and image recognition. The circuit system includes a PC, an FPGA chip, a digital-to-analog converter (DAC), a switching unit, memristor array units, integrator and signal amplification circuits, and an analog-to-digital converter (ADC). This invention allows the PC to select the desired function via specific software, which can be array read / write, weight modulation, or image recognition. Commands or image RGB values ​​acquired by the PC are converted into corresponding grayscale values ​​and sent to the FPGA chip. The FPGA chip, through the DAC and switching units, controls the selection of the memristor array units to be modulated. The PC application program controls the FPGA chip in real time to implement array read / write, weight modulation, and image recognition functions. The results are displayed in real time on the PC via the FPGA chip.

Description

Technical Field

[0001] This invention relates to the field of memristor technology, specifically a circuit system applied to memristor array weight modulation and image recognition. Background Technology

[0002] Over the past few decades, transistor integrated circuits have developed rapidly along Moore's Law, and the performance of electronic computers has improved dramatically. Since the invention of the electronic computer, the von Neumann architecture has been dominant. In the past few decades, the von Neumann architecture has achieved tremendous success. However, with the advent of the Internet of Things, cloud computing, and big data era, the in-depth analysis and processing of massive amounts of unstructured data requires higher computing speeds and energy efficiency. The computing system under the von Neumann architecture is gradually proving inadequate, and the continuation of Moore's Law faces significant challenges. Therefore, finding new high-energy-efficiency computing technologies is an important direction of current research.

[0003] Memristors are novel nanodevices whose resistance is determined by and continuously changes based on their excitation history, exhibiting non-volatility. Their emergence provides a new physical basis for developing energy-efficient, in-memory computing systems. With advantages such as high integration density, fast operating speed, low power consumption, and non-volatility, memristors are considered a strong contender for fundamental in-memory computing devices, offering a practical solution for realizing in-memory computing technology.

[0004] Memristors are typically integrated at high density using a cross-array configuration. When a column voltage vector is applied to one end of the memristor cross-array, the output row current vector at the other end is the product of the applied column voltage vector and the memristor conductance matrix. In other words, based on Ohm's law and Kirchhoff's voltage law, the memristor array can complete vector-matrix multiplication and accumulation operations within one cycle. The multiplication factors are directly stored in the memristor array, eliminating the need for separate storage units and thus bypassing the von Neumann bottleneck. Furthermore, the core unit computational efficiency of this memristor array-based multiplication and accumulation operation is two orders of magnitude higher than that of existing CMOS devices, which is of great significance for intelligent processing tasks involving a large number of multiplication and accumulation operations. Summary of the Invention

[0005] The purpose of this invention is to provide a circuit system for memristor array weight modulation and image recognition, so as to realize memristor array information reading, memristor weight modulation, and image recognition.

[0006] The present invention is implemented as follows: a circuit system for memristor array weight modulation and image recognition, comprising a PC, an FPGA chip, a digital-to-analog converter unit, a switching unit, a memristor array unit, an integrator and signal amplification circuit, and an analog-to-digital converter;

[0007] The PC is connected to the FPGA chip, which is also connected to the digital-to-analog converter and the analog-to-digital converter; the FPGA chip uses an FPGA core board.

[0008] The digital-to-analog converter unit is used to receive the digital signal sent by the FPGA chip, step it down, convert it into a corresponding pulse signal, and output it to the switching unit. The switching unit controls the memristor array unit through selection.

[0009] The switching unit includes two dual-channel 2-to-1 switching units and six 16-to-1 switching units. The input of one dual-channel 2-to-1 switching unit is connected to the output of the digital-to-analog converter unit. This dual-channel 2-to-1 switching unit has two output terminals. One output terminal is connected to the source of the CMOS transistor in the memristor array unit through two 16-to-1 switching units, and the other output terminal is connected to the gate of the CMOS transistor in the memristor array unit through another two 16-to-1 switching units. The drain of the CMOS transistor in the memristor array unit is connected to another dual-channel 2-to-1 switching unit through the remaining two 16-to-1 switching units. One dual-channel 2-to-1 switch unit is connected to the other dual-channel 2-to-1 switch unit, which is connected to the analog-to-digital converter through an integration and signal amplification circuit. This other dual-channel 2-to-1 switch unit is used to control the charging and discharging of the integration circuit, and does not select the output of the 32 outputs of the memristor array unit. Discharging is required after each integration. Therefore, this other dual-channel 2-to-1 switch unit controls the discharge of the integration circuit after each output. Therefore, in this invention, the switch unit is used to control the on / off of the 32×32 signal of the memristor array, that is, to control the on / off of the source, gate, and drain of the CMOS transistor of a single device in the memristor array unit.

[0010] The memristor array unit is used to convert the received pulse signal into a corresponding current signal and output it to the switching unit for selective output;

[0011] The integration and signal amplification circuit is used to convert the current signal output by the memristor array unit into a corresponding voltage signal, and amplify the signal before outputting it to the analog-to-digital converter.

[0012] The analog-to-digital converter is used to convert the analog signal output from the integration and signal amplification circuit into a corresponding digital signal and send it to the FPGA chip.

[0013] The circuit system provided by this invention includes the following functions: read / write functionality for individual devices in a memristor array and read / write functionality for the entire array; weight modulation for individual devices in the memristor array and weight modulation for the entire array; and image recognition functionality. Furthermore, this circuit system can simultaneously control the source and gate of the CMOS transistors in the memristor array cells.

[0014] The dual-channel 2-to-1 switch unit includes a TMUX6136 chip. The 16-to-1 switch unit includes a MUX506 chip.

[0015] The digital-to-analog converter unit includes an AD7847 digital-to-analog converter chip and two AD711 operational amplifiers, which can perform digital-to-analog signal conversion with a maximum resolution of 12 bits as needed, and can amplify the output signal.

[0016] The integrating and signal amplifying circuit includes an integrating circuit and a signal amplifying circuit; the integrating circuit includes an IF356 chip; the signal amplifying circuit includes a first-stage amplifying circuit and a second-stage amplifying circuit; the first-stage amplifying circuit includes a PGA202 chip, and the second-stage amplifying circuit includes a PGA203 chip. The first-stage and second-stage amplifying circuits are each connected to a zero-adjustment circuit, which includes an OPA602 chip.

[0017] The analog-to-digital converter (ADC) includes an AD574 ADC chip and a 74LS373 latch. The ADC converts the signal transmitted from the integration and signal amplification circuits and sends it to the FPGA chip.

[0018] Compared with the prior art, the unique feature of this invention is:

[0019] This invention allows for the selection of desired functions via specific software on a PC, including array read / write, weight modulation, and image recognition. Commands or image RGB values ​​acquired by the PC are converted into corresponding grayscale values ​​and sent to an FPGA chip. The FPGA chip then controls the selection of the memristor array unit to be modulated. Specifically, the FPGA chip controls a digital-to-analog converter (DAC) to step down the voltage and convert it into a 12-bit resolution pulse signal, which is then output to the 32×32-channel memristor array unit. The memristor array unit converts the received pulse signal into a corresponding current signal and sends it to an integration and signal amplification unit via a 16-to-1 switch. The integration and signal amplification unit integrates the received small pulse signal and amplifies it to a certain factor as needed before sending it to an analog-to-digital converter (ADC). The ADC converts the received analog signal into a corresponding digital signal and sends it to the FPGA chip. The FPGA chip then transmits the received information to the PC and matches it with signals in a database to obtain the corresponding results. This enables the reading of information from the memristor array unit, weight modulation, and image recognition. Attached Figure Description

[0020] Figure 1 This is an overall block diagram of the circuit system of the present invention applied to memristor array weight modulation and image recognition.

[0021] Figure 2 This is a circuit diagram of the digital-to-analog converter unit in this invention.

[0022] Figure 3 This is a circuit diagram of the first dual-channel two-to-one switching unit in this invention.

[0023] Figure 4 This is a circuit diagram of the second dual-channel two-to-one switching unit in this invention.

[0024] Figure 5 This is a circuit diagram of the first sixteen-to-one switching unit in this invention.

[0025] Figure 6 This is a circuit diagram of the twenty-sixth selector switch unit in this invention.

[0026] Figure 7 This is a circuit diagram of the thirty-sixth selector switch unit in this invention.

[0027] Figure 8 This is a circuit diagram of the forty-sixth selector switch unit in this invention.

[0028] Figure 9 This is a circuit diagram of the fifty-sixth selector switch unit in this invention.

[0029] Figure 10 This is a circuit diagram of the sixty-sixth selector switch unit in this invention.

[0030] Figure 11 This is a circuit diagram of the first integrator and signal amplifier circuit in this invention.

[0031] Figure 12 This is a circuit diagram of the second integrator and signal amplifier circuit in this invention.

[0032] Figure 13 This is a circuit diagram of the analog-to-digital converter in this invention. Detailed Implementation

[0033] This invention provides a circuit system for memristor array weight modulation and image recognition, also known as a memristor array read / write circuit. The overall framework of this circuit is as follows: Figure 1 As shown, the circuit specifically includes a PC, an FPGA chip, a digital-to-analog converter unit, a switching unit (including two dual-channel 2-to-1 switching units and six 16-to-1 switching units), a memristor array unit, an integrator and signal amplification circuit (including two integrator circuits and two signal amplification circuits), and an analog-to-digital converter.

[0034] The digital-to-analog converter (DAC) is suitable for stepping down the received digital signal and converting it into a corresponding pulse signal, which is then output to one of the dual-channel 2-to-1 switching units in the switching unit. The circuit of the DAC is as follows: Figure 2 As shown.

[0035] The digital-to-analog converter unit includes a digital-to-analog converter chip (AD7847), an operational amplifier circuit, and resistors R1, R2, R3, R4, R5, and R6. The operational amplifier circuit includes a first operational amplifier and a second operational amplifier.

[0036] The 15 input terminals CSA, CSB, WR, and DB0 to DB11 of the digital-to-analog converter chip are connected to the 15 pins of a 15-pin header. The DGND, AGVDB, and AGNDA ports of the digital-to-analog converter chip are grounded. VREFA and VREFB of the digital-to-analog converter chip are connected to a +10V power supply, VDD to a +15V power supply, and VSS to a -15V power supply. VOUTA and VOUTB are connected to an operational amplifier circuit via resistors to amplify the output signal.

[0037] In the operational amplifier circuit, the inverting input (port 2) of the first operational amplifier IC1 (AD711) is connected to port 4 (VOUTA) of the digital-to-analog converter chip via a third resistor R3, and to port 3 (VREFA) of the digital-to-analog converter chip via a second resistor R2. Thirdly, it is connected to port 6 of the first operational amplifier via a first resistor R1. Port 6 of the first operational amplifier serves as the first output terminal (DAC1) of the digital-to-analog converter unit. The non-inverting input (port 3) of the first operational amplifier is coupled to AGND. The +VCC and -VCC ports of the first operational amplifier are connected to the ±15V power supply via filter capacitors, respectively.

[0038] The inverting input (port 2) of the second operational amplifier IC2 (AD711) is connected to port 9 (VOUTB) of the digital-to-analog converter (DAC) chip via resistor R4, and to port 10 (VREFB) via resistor R5. It is also connected to port 6 of the second operational amplifier via resistor R6. Port 6 of the second operational amplifier serves as the second output (DAC2) of the DAC unit. The non-inverting input (port 3) of the second operational amplifier is coupled to AGND. The +VCC and -VCC ports of the second operational amplifier are connected to the ±15V power supply via filter capacitors.

[0039] The digital-to-analog converter is suitable for stepping down the received digital signal and converting it into a corresponding pulse signal using the following formula:

[0040]

[0041] Where VOUT represents the converted pulse signal, and VIN represents the received digital signal. The digital signals and corresponding formulas listed in the table are all terminal values. For any intermediate digital signal, for each increment of 1, the numerator of the corresponding formula is incremented by 1.

[0042] The switching unit is adapted to select the source and gate of the CMOS of the devices in the memristor array unit, input the output pulse signal of the digital-to-analog converter unit to the source and gate of the corresponding devices, and selectively output the drain output. Therefore, the switching unit is connected to the source, gate, and drain of the CMOS of the devices in the memristor array unit.

[0043] like Figure 1 As shown, the switching unit includes two dual-channel 2-to-1 switching units and six 16-to-1 switching units. The output of the digital-to-analog converter is connected to one of the dual-channel 2-to-1 switching units. The two dual-channel 2-to-1 switching units are designated as the first dual-channel 2-to-1 switching unit and the second dual-channel 2-to-1 switching unit, respectively. The six 16-to-1 switching units are designated as the first 16-to-1 switching unit, the second 16-to-1 switching unit, the third 16-to-1 switching unit, the fourth 16-to-1 switching unit, the fifth 16-to-1 switching unit, and the sixth 16-to-1 switching unit. The second dual-channel 2-to-1 switching unit is connected to the third 16-to-1 switching unit and the fourth 16-to-1 switching unit. The second dual-channel 2-to-1 switching unit is also connected to two integrating circuits.

[0044] The memristor array unit is adapted to convert received pulse signals into corresponding current signals and output them to the switching unit for selective output. The memristor array unit is a 32×32-channel memristor array unit. The source port of the 32×32-channel memristor array unit is connected to the first and second 16-to-1 switching units as inputs; the gate port of the 32×32-channel memristor array unit is connected to the fifth and sixth 16-to-1 switching units as inputs; and the drain port of the 32×32-channel memristor array unit is connected to the 36-to-1 and 46-to-1 switching units as outputs.

[0045] The circuit diagrams of the first dual-channel 2-to-1 switch unit and the second dual-channel 2-to-1 switch unit are shown below. Figure 3 and Figure 4 .

[0046] The first dual-channel 2-to-1 multiplexer unit includes a seventh chip U5. The input port D1 of the seventh chip U5 is connected to the first output terminal DAC1 of the digital-to-analog converter unit, and the input port D2 of the seventh chip U5 is connected to the second output terminal DAC2 of the digital-to-analog converter unit. Combined with... Figure 5-10Port S1A of the seventh chip U5 is connected to port D1 of the first chip U6 of the first sixteen-to-one switch unit; port S1B of the seventh chip U5 is connected to port D2 of the second chip U7 of the twenty-sixteen-to-one switch unit; port S2A of the seventh chip U5 is connected to port D6 of the sixth chip U12 of the sixty-sixteen-to-one switch unit; and port S2B of the seventh chip U5 is connected to port D5 of the fifth chip U11 of the fifty-sixteen-to-one switch unit. The VSS port of the seventh chip U5 is connected to the -15V power supply through a filter capacitor, the VDD port is connected to the +15V power supply through a filter capacitor, and the GND port is grounded.

[0047] The second dual-channel 2-to-1 switch unit includes an eighth chip U10. Input port D1 of the eighth chip U10 is connected to port D4 of the fourth chip U9 of the forty-sixth switch unit, and input port D2 of the eighth chip U10 is connected to port D3 of the third chip U8 of the thirty-sixth switch unit. Port S1A of the eighth chip U10 is connected to the IF356_OUT1 port of the first integrating circuit; port S2A of the eighth chip U10 is connected to the IF356_OUT2 port of the second integrating circuit. The VSS port of the eighth chip U10 is connected to the -15V power supply through a filter capacitor, the VDD port is connected to the +15V power supply through a filter capacitor, and the GND port is grounded.

[0048] like Figure 5 As shown, the first sixteen-to-one switch unit includes a first chip U6. The output ports S1A, S2A, S3A, S4A, S5A, S6A, S7A, S8A, S1B, S2B, S3B, S4B, S5B, S6B, S7B, and S8B of the first chip U6 are connected to the upper electrodes R0_ROW1, R1_ROW2, R2_ROW3, ​​R3_ROW4, R4_ROW5, R5_ROW6, R6_ROW7, R7_ROW8, R8_ROW9, R9_ROW10, R10_ROW11, R11_ROW12, R12_ROW13, R13_ROW14, R14_ROW15, and R15_ROW16 of the memristor array unit. The GND port is grounded, and the VDD port is connected to the +15V power supply through a filter capacitor.

[0049] like Figure 6As shown, the 26th selector switch unit includes a second chip U7. The output ports S1A, S2A, S3A, S4A, S5A, S6A, S7A, S8A, S1B, S2B, S3B, S4B, S5B, S6B, S7B, and S8B of the second chip U7 are connected to the upper electrodes R16_ROW17, R17_ROW18, R18_ROW19, R19_ROW20, R20_ROW21, R21_ROW22, R22_ROW23, R23_ROW24, R24_ROW25, R25_ROW26, R26_ROW27, R27_ROW28, R28_ROW29, R29_ROW30, R30_ROW31, and R31_ROW32 of the memristor array unit. The GND port is grounded, and the VDD port is connected to the +15V power supply through a filter capacitor.

[0050] like Figure 7 As shown, the 36th selector switch unit includes a third chip U8. The output ports S1A, S2A, S3A, S4A, S5A, S6A, S7A, S8A, S1B, S2B, S3B, S4B, S5B, S6B, S7B, and S8B of the third chip U8 are connected to the memristor array unit ports SL16_COL17, SL17_COL18, SL18_COL19, SL19_COL20, SL20_COL21, SL21_COL22, SL22_COL23, SL23_COL24, SL24_COL25, SL25_COL26, SL26_COL27, SL27_COL28, SL28_COL29, SL29_COL30, SL30_COL31, and SL31_COL32. The GND port is grounded, and the VDD port is connected to the +15V power supply through a filter capacitor.

[0051] like Figure 8 As shown, the 46th selector switch unit includes a fourth chip U9. The output ports S1A, S2A, S3A, S4A, S5A, S6A, S7A, S8A, S1B, S2B, S3B, S4B, S5B, S6B, S7B, and S8B of the fourth chip U9 are connected to the memristor array unit ports SL0_COL1, SL1_COL2, SL2_COL3, SL3_COL4, SL4_COL5, SL5_COL6, SL6_COL7, SL7_COL8, SL8_COL9, SL9_COL10, SL10_COL11, SL11_COL12, SL12_COL13, SL13_COL14, SL14_COL15, and SL15_COL16. The GND port is grounded, and the VDD port is connected to the +15V power supply through a filter capacitor.

[0052] like Figure 9 As shown, the fifty-sixth selector switch unit includes a fifth chip U11. The output ports S1A, S2A, S3A, S4A, S5A, S6A, S7A, S8A, S1B, S2B, S3B, S4B, S5B, S6B, S7B, and S8B of the fifth chip U11 are connected to the memristor array unit ports AD5532RWL0_T0, AD5532RWL1_T1, AD5532RWL2_T2, AD5532RWL3_T3, and AD5532RWL0_T0. Connect L4_T4, AD5532RWL5_T5, AD5532RWL6_T6, AD5532RWL7_T7, AD5532RWL8_T8, AD5532RWL9_T9, AD5532RWL10_0, AD5532RWL11_T11, AD5532RWL12_T12, AD5532RWL13_T13, AD5532RWL14_T14, and AD5532RWL15_T15. The GND port is grounded, and the VDD port is connected to the +15V power supply through a filter capacitor.

[0053] like Figure 10 As shown, the sixty-sixth selector switch unit includes a sixth chip U12. The output ports S1A, S2A, S3A, S4A, S5A, S6A, S7A, S8A, S1B, S2B, S3B, S4B, S5B, S6B, S7B, and S8B of the sixth chip U12 are connected to the memristor array unit ports AD5532RWL16_T16, AD5532RWL17_T17, AD5532RWL18_T18, AD5532RWL19_T19, and AD5532RWL20. Connect the following pins: _T20, AD5532RWL21_T21, AD5532RWL22_T22, AD5532RWL23_T23, AD5532RWL24_T24, AD5532RWL25_T25, AD5532RWL26_T26, AD5532RWL27_T27, AD5532RWL28_T28, AD5532RWL29_T29, AD5532RWL30_T30, and AD5532RWL31_T31. The GND port is grounded, and the VDD port is connected to the +15V power supply via a filter capacitor.

[0054] The integration and signal amplification circuit is suitable for converting the current signal output by the memristor array unit into the corresponding voltage signal, and then amplifying the signal before outputting it to the analog-to-digital converter.

[0055] The integrator and signal amplifier circuit includes a first integrator and signal amplifier circuit and a second integrator and signal amplifier circuit.

[0056] The first integrating and signal amplifying circuit includes a first integrating circuit and a first signal amplifying circuit.

[0057] like Figure 11 As shown, the first integrating circuit includes an IF356 chip. The non-inverting input terminal 3 of the IF356 chip is grounded, and the inverting input terminal 2 is connected to the output terminal D4 of the fourth chip of the forty-sixth selector switch unit. The inverting input terminal is connected to the output port IF356_OUT1 via capacitor C1 and NPO capacitor 1. Port 4 (V-) is connected to a -15V power supply via coupling capacitor C20. Port 1 of the IF356 chip is connected to the first port of the first potentiometer R17, and port 5 is connected to the second port of the first potentiometer R17. The third control port of the first potentiometer R17 is connected to port 7 (V+), and V+ is connected to a +15V power supply via a coupling capacitor.

[0058] The first signal amplification circuit includes a first-stage amplification circuit and a first-second-stage amplification circuit. The output port IF356_OUT1 of the first integrator circuit is connected to +VIN of the PGA202 chip in the first-stage amplification circuit. The VOSAdjust 9 port of the PGA202 chip is connected to the first port of the second potentiometer R14, the VOS Adjust 6 port is connected to the second port of the second potentiometer R14, and the third control port of the second potentiometer R14 is connected to a +15V power supply. The VREF port of the PGA202 chip in the first-stage amplification circuit is connected to output port 6 of the first zero-adjustment circuit IC5 (OPA602), and the inverting input port -In of the first zero-adjustment circuit IC5 (OPA602) is connected to output port 6. The first port of the first zero-adjustment resistor R12 is connected to GND, the second port of the first zero-adjustment resistor R12 is connected to the first port of the second zero-adjustment resistor R10, and the second port of the second zero-adjustment resistor R10 is connected to the third control port of the third potentiometer R11. The first port of the third potentiometer R11 is connected to the +15V power supply, and the second port of the third potentiometer R11 is connected to the -15V power supply. The positive input port 3 (+In) of the first zero-adjustment circuit IC5 (OPA602) is connected to the second port of the first zero-adjustment resistor R12. Port 1 of the first zero-adjustment circuit IC5 (OPA602) is connected to the first port of the fourth potentiometer R13, and port 5 of the first zero-adjustment circuit IC5 (OPA602) is connected to the second port of the fourth potentiometer R13. The third control port of the fourth potentiometer R13 is connected to the -15V power supply. The -VIN and Digital Common ports of the first stage amplifier circuit are grounded. +VCC is connected to the +15V power supply through a filter capacitor, and -VCC is connected to the -15V power supply through a filter capacitor. Ports A0 and A1 are connected to the 10-pin header ports PGA12 and PGA13. VOUT and VOUT Sense are interconnected as outputs, connected to the +VIN port of the first stage amplifier circuit as the input signal for the first stage amplifier circuit.

[0059] The VOS Adjust 9 port of the PGA203 chip in the first and second stage amplifier circuits is connected to the first port of the fifth potentiometer R20, the VOS Adjust 6 port is connected to the second port of the fifth potentiometer R20, and the third control port of the fifth potentiometer R20 is connected to the +15V power supply. The VREF terminal of the first and second stage amplifier circuits is connected to the output port of the second zero-adjustment circuit IC7 (OPA602) chip (port 6), and the inverting input port -In of the second zero-adjustment circuit IC7 (OPA602) chip (port 2) is connected to the output port 6. The first port of the zero-adjustment third resistor R18 is connected to GND, the second port of the zero-adjustment third resistor R18 is connected to the first port of the zero-adjustment fourth resistor R15, and the second port of the zero-adjustment fourth resistor R15 is connected to the third control port of the sixth potentiometer R16. The first port of the sixth potentiometer R16 is connected to the +15V power supply, and the second port of the sixth potentiometer R16 is connected to the -15V port. The positive input port +In of the second zero-adjustment circuit IC7 (OPA602) is connected to the second port of the zero-adjustment third resistor R18. The first port of the second zero-adjustment circuit IC7 (OPA602) is connected to the first port of the seventh potentiometer R19, and the fifth port of the second zero-adjustment circuit IC7 (OPA602) is connected to the second port of the seventh potentiometer R19. The third control port of the seventh potentiometer R19 is connected to the -15V power supply. The -VIN and Digital Common ports of the PGA203 chip in the first and second stage amplifier circuits are grounded. +VCC is connected to the +15V power supply through a filter capacitor. -VCC is connected to the -15V power supply through a filter capacitor. Ports A0 and A1 are connected to the 10-pin header ports PGA10 and PGA11. VOUT and VOUT Sense are interconnected as outputs, connected to the analog-to-digital converter.

[0060] The second integrator and signal amplifier circuit includes a second integrator circuit and a second signal amplifier circuit.

[0061] like Figure 12 As shown, the second integrating circuit includes an IF356 chip. The non-inverting input port 3 of the IF356 chip is grounded, and the inverting input port 2 is connected to the output terminal D3 of the third chip of the 36-to-1 switch unit. The inverting input port 2 is connected to the output port IF356_OUT2 via capacitor C2 and NPO capacitor 2. The IF356's port 4 (V-) is connected to a -15V power supply via coupling capacitor C22. The IF356's port 1 is connected to the first port of the eighth potentiometer R30, and the IF356's port 5 is connected to the second port of the eighth potentiometer R30. The third control port of the eighth potentiometer R30 is connected to V+, and V+ is connected to a +15V power supply via a coupling capacitor.

[0062] The second signal amplification circuit includes a second-stage amplifier circuit PGA202 and a second-stage amplifier circuit PGA203. IF356_OUT2 is connected to port 8 (+VIN) of the second-stage amplifier circuit PGA202. The VOS Adjust port 9 is connected to the first port of the ninth potentiometer R25. The VOS Adjust port 6 is connected to the second port of the ninth potentiometer R25. The third control port of the ninth potentiometer R25 is connected to the +15V power supply. The VREF port of the second-stage amplifier circuit PGA202 is connected to the output port 6 of the third zeroing circuit IC8 (OPA602). The inverting input port 2 (-In) of the third zeroing circuit IC8 (OPA602) is connected to port 6. The first port of the fifth zeroing resistor R23 is connected to GND. The second port of the fifth zeroing resistor R23 is connected to the first port of the sixth zeroing resistor R21. The second port of the sixth zeroing resistor R21 is connected to the third control port of the tenth potentiometer R22. The first port of the tenth potentiometer R22 is connected to the +15V power supply, and the second port is connected to the -15V port. The positive input port 3 (+In) of the third zeroing circuit IC8 (OPA602) is connected to the second port of the fifth zeroing resistor R23. Port 1 of the third zeroing circuit IC8 (OPA602) is connected to the first port of the eleventh potentiometer R24, and port 5 of the third zeroing circuit IC8 (OPA602) is connected to the second port of the eleventh potentiometer R24. The third control port of the eleventh potentiometer R24 ​​is connected to the -15V power supply. The -VIN and Digital Common ports of the second-stage amplifier circuit PGA202 are grounded. +VCC is connected to the +15V power supply through a filter capacitor, and -VCC is connected to the -15V power supply through a filter capacitor. Ports A0 and A1 are connected to the 10-pin header ports PGA22 and PGA23. VOUT and VOUT Sense are connected as outputs to the PGA203+VIN port of the second stage amplifier circuit, serving as the input signal for the second stage amplifier circuit.

[0063] The VOS Adjust 9 port of the second-stage amplifier circuit PGA203 is connected to the first port of the twelfth potentiometer R31, the VOS Adjust 6 port is connected to the second port of the twelfth potentiometer R31, and the third control port of the twelfth potentiometer R31 is connected to the +15V power supply. The VREF port of the second-stage amplifier circuit PGA203 is connected to the output port of the fourth zero-adjustment circuit IC9 (OPA602), and the inverting input port -In of the fourth zero-adjustment circuit IC9 (OPA602) is connected to port 6. The first port of the seventh zero-adjustment resistor R28 is connected to GND, the second port of the seventh zero-adjustment resistor R28 is connected to the first port of the eighth zero-adjustment resistor R26, and the second port of the eighth zero-adjustment resistor R26 is connected to the third control port of the thirteenth potentiometer R27. The first port of the thirteenth potentiometer R27 is connected to the +15V power supply, and the second port of the thirteenth potentiometer R27 is connected to the -15V port. The positive input port 3 (+In) of the fourth zero-adjustment circuit IC9 (OPA602) is connected to the second port of the seventh zero-adjustment resistor R28. Port 1 of the fourth zero-adjustment circuit IC9 (OPA602) is connected to the first port of the fourteenth potentiometer R29, and port 5 of the fourth zero-adjustment circuit IC9 (OPA602) is connected to the second port of the fourteenth potentiometer R29. The third control port of the fourteenth potentiometer R29 is connected to the -15V power supply. The -VIN and Digital Common ports of the second-stage amplifier circuit PGA203 are grounded. +VCC is connected to the +15V power supply through a filter capacitor. -VCC is connected to the -15V power supply through a filter capacitor. Ports A0 and A1 are connected to the 10-pin header ports PGA20 and PGA11. VOUT and VOUT Sense are connected as outputs to an analog-to-digital converter.

[0064] An analog-to-digital converter (ADC) is used to convert analog signals output from integrators and signal amplifiers into corresponding digital signals and send them to an FPGA chip. The FPGA chip uses an FPGA core board.

[0065] like Figure 13As shown, the analog-to-digital converter (ADC) includes an ADC chip and a latch. The VLOGIC port of the ADC chip (AD574) is connected to a +5V power supply, and the VCC port is connected to a +15V power supply. Both ports are connected to ground via a filter capacitor. The VEE port is connected to -15V and also to the filter capacitor. The AC terminal is connected to AGND, the REF OUT terminal is connected to the first port of the 15th potentiometer R4, and the REF IN terminal is connected to the second port of the 15th potentiometer R4. The third control port of the 15th potentiometer R4 is connected to its second port. The first port of the 15th potentiometer R4 is also connected to the first port of the 16th potentiometer R5. The second and third control ports of the 16th potentiometer R5 are connected and then connected to the BIP OFF port of the AD574. The DB11–DB4 ports of the ADC chip are connected to the 8D–1D ports of the latch (74LS373), and the DB3–DB0 ports are connected to the DB11–DB8 ports, respectively. The D1–D8 ports of the 74LS373 chip are connected to the general-purpose input / output interface of the FPGA core board.

[0066] The circuit system in this invention can realize memristor array reading and writing, weight modulation, and image recognition, which are described below.

[0067] I. Read and write functions include reading and writing individual devices in the array, as well as reading and writing the array as well as user-defined read and write operations.

[0068] 1. Read operations include single device read, array read, configuration read, and array save functions. The parameters that need to be set here are: number of array rows, number of array columns, pulse width, and gate voltage.

[0069] 1) Component selection

[0070] a) Selection of individual devices in the array

[0071] Reading or writing to a single device requires first selecting the device to be operated on. The number of rows and columns is set (within 32×32). After the microcontroller sends a signal, the FPGA chip receives the signal and controls the digital-to-analog converter (DAC). The DAC converts the digital signal sent by the FPGA chip into a corresponding pulse signal, which is then output to the switching unit.

[0072] The FPGA chip controls the array switching units (including two source MUX switches U6 and U7, two drain MUX switches U8 and U9, and two gate MUX switches U11 and U12) to achieve row and column selection of the array. The FPGA chip output signals control units U6 and U7, outputting control signals S1-S32; the FPGA chip output signals control units U8 and U9, outputting thirty-two control signals S33-S64. U6 and U7 control the upper electrode of the memristor array, and U8 and U9 control the drain of the memristor array. The FPGA chip output signals control the output ports M1-M16 of unit U11 and the output ports M17-M32 of unit U12. U11 and U12 control the gate of the CMOS of the memristor array.

[0073] b) Entire array selection

[0074] When reading or writing to the entire array is required, the entire memristor array needs to be selected. Two options are available: The first is parallel input and parallel output. Thirty-two signal sources are connected to the sources of the array, and thirty-two signal sources are connected to the gates of the memristor array. When reading or writing to the entire array, sixty-four channels operate simultaneously, transmitting signals to both the sources and gates of the array at the same time. This scheme allows for parallel input and output, achieving high efficiency. The disadvantage is that sixty-four signal sources are very expensive. The second option is serial input and serial output. Two signal sources are used, one connected to the source of the array and the other to the gate. When operating on the array, individual devices in the array are selected sequentially for operation within a very short time, which can be approximated as parallel input and output. Considering cost and practical requirements, this application chose the second option. When reading or writing to the array, individual devices are read and written sequentially.

[0075] c) User-defined selection

[0076] When operating an array, it is sometimes necessary to read and write to several devices within the array. To do this, select the row and column numbers of the devices to be operated on, set the signals, and then you can operate on those devices.

[0077] 2) Read operation

[0078] After selecting the device to be operated on in the array (this can be a single device, the entire array, or several user-defined devices), based on the characteristics of the materials in the array, the pulse width is specified as 2000µs and the gate voltage as 0.4V. It is important to note that although the signal during a read operation is a single pulse, even a small signal can affect the device, thus impacting the overall read / write accuracy of the system. To reduce errors, positive and negative pulse signals with the same pulse width but opposite gate voltage polarities are used. Data is automatically saved after the read operation is completed.

[0079] 2. Write operations include pulse write, scan write, and custom write operations.

[0080] 1) Pulse writing. Pulse writing can be divided into single-pulse mode and multi-pulse mode. The parameters that need to be set here include: number of rows and columns, high effective pulse width (≤2S), low effective pulse, pulse amplitude (±5V), gate voltage, number of pulses, and number of sampling points;

[0081] a) Select pulse write; pulse write mode is now enabled.

[0082] b) Select the number of rows and columns of the array devices to be operated, as well as the number of pulses required, and set the gate voltage at this time;

[0083] c) Write the pulse, inputting the pulse width, pulse period width, and pulse amplitude;

[0084] d) Select the array to begin the write operation;

[0085] e) Save the data.

[0086] 2) Scan Write. The parameters that need to be set for scan write are: number of rows and columns, effective pulse width (≤2S), pulse width (±5V), gate voltage, number of pulse steps, and number of sampling points.

[0087] 3) Custom Write. Custom write allows users to operate on specific devices in the array according to their own needs. A custom write operation requires first downloading a custom netlist, then performing the custom write operation, and finally reading the result. The custom netlist requires setting the number of rows and columns, custom write direction, number of pulses, and gate voltage.

[0088] II. Weight Modulation. Weight modulation is the process by which the system automatically adjusts the array weights according to the user's target weights. Weight modulation includes single-shot modulation, gate voltage modulation, array modulation, pulse modulation, and pulse width modulation.

[0089] 1) Single-shot modulation. Single-shot modulation is fixed-gate voltage modulation. Only the SET and RESET voltages need to be provided for the gate voltage; other parameters are modulated based on the device performance. The adjustment range is specified to be within ±3V, depending on the device performance.

[0090] 2) Gate voltage modulation. Gate voltage modulation needs to be combined with pulse modulation. The parameters that need to be set are maximum gate voltage, minimum gate voltage, and gate voltage step size.

[0091] 3) Array modulation. Array modulation modulates the weights of the entire array. Array modulation needs to be combined with gate voltage modulation. It requires reading an EXCEL file (containing target parameters), setting the modulation termination (an error within 200Ω is considered acceptable, i.e., successful modulation), setting the number of cycles, and reading the array conductance value.

[0092] 4) Pulse Width Modulation (PWM). PWM consists of pulse width amplitude and pulse width. The pulse width amplitude requires setting an initial positive amplitude value and an initial negative amplitude value, while the pulse width requires setting an initial pulse width, a maximum pulse width, and a pulse width step size.

[0093] III. Image Recognition. Image recognition involves target weight modulation on the array based on weight modulation. The target weights are stored in the image to be recognized, and the image pixel values ​​correspond to conductance values ​​according to a linear relationship. This conductance value is the target conductance value. The system modulates the array weights according to the target value, and modulation is considered complete if it is within the error range. Different input images correspond to different input signals. Different input signals are repeatedly modulated in the array chip until the next-stage integrator circuit sends out the corresponding pulse signal. The signal and amplification circuit amplifies the signal, and it is converted into a digital signal by an analog-to-digital converter and sent to the FPGA chip. The FPGA chip then sends the signal to the PC to display the result.

Claims

1. A circuit system applied to memristor array weight modulation and image recognition, characterized in that, It includes a PC, FPGA chip, digital-to-analog converter unit, switching unit, memristor array unit, integrating and signal amplification circuit, and analog-to-digital converter; The PC is connected to the FPGA chip, and the FPGA chip is also connected to the digital-to-analog converter and the analog-to-digital converter. The digital-to-analog converter unit is used to receive the digital signal sent by the FPGA chip, step it down, and then convert it into a corresponding pulse signal, which is then output to the switching unit. The switching unit includes two dual-channel 2-to-1 switching units and six 16-to-1 switching units. The input of one dual-channel 2-to-1 switching unit is connected to the output of the digital-to-analog converter (DAC). This dual-channel 2-to-1 switching unit has two output terminals. One output terminal is connected to the source of the CMOS transistor in the memristor array unit via two 16-to-1 switching units, and the other output terminal is connected to the gate of the CMOS transistor in the memristor array unit via two 16-to-1 switching units. The drain of the CMOS transistor in the memristor array unit is connected to another dual-channel 2-to-1 switching unit via the other two 16-to-1 switching units. This other dual-channel 2-to-1 switching unit is connected to the DAC via an integration and signal amplification circuit. The switching unit is used to select the source and gate of the CMOS transistor in the memristor array unit, input the pulse signal output from the DAC to the source and gate of the corresponding device, and selectively output the drain output. The memristor array unit is used to convert the received pulse signal into a corresponding current signal and output it to the switching unit for selective output; The integration and signal amplification circuit is used to convert the current signal output by the memristor array unit into a corresponding voltage signal, and amplify the signal before outputting it to the analog-to-digital converter. The analog-to-digital converter is used to convert the analog signal output from the integration and signal amplification circuit into a corresponding digital signal and send it to the FPGA chip.

2. The circuit system for memristor array weight modulation and image recognition according to claim 1, characterized in that, The memristor array unit is a 32×32 channel memristor array unit.

3. The circuit system for memristor array weight modulation and image recognition according to claim 1, characterized in that, The dual-channel 2-to-1 switch unit includes a TMUX6136 chip.

4. The circuit system for memristor array weight modulation and image recognition according to claim 1, characterized in that, The 16-to-1 selector switch unit includes a MUX506 chip.

5. The circuit system for memristor array weight modulation and image recognition according to claim 1, characterized in that, The digital-to-analog conversion unit includes an AD7847 digital-to-analog converter chip and two AD711 operational amplifiers.

6. The circuit system for memristor array weight modulation and image recognition according to claim 1, characterized in that, The integration and signal amplification circuit includes an integration circuit and a signal amplification circuit; the integration circuit includes an IF356 chip; the signal amplification circuit includes a first-stage amplification circuit and a second-stage amplification circuit; the first-stage amplification circuit includes a PGA202 chip, and the second-stage amplification circuit includes a PGA203 chip.

7. The circuit system for memristor array weight modulation and image recognition according to claim 6, characterized in that, The first-stage amplifier circuit and the second-stage amplifier circuit are each connected to a zero-adjustment circuit, which includes an OPA602 chip.

8. The circuit system for memristor array weight modulation and image recognition according to claim 1, characterized in that, The analog-to-digital converter includes an AD574 analog-to-digital converter chip and a 74LS373 latch.

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