Compiling method of expression in canonical sentence, readable storage medium and compiler

Abstract

This invention relates to a method for compiling expressions in normalized statements, a readable storage medium, and a compiler. The computing device of this invention is included in an integrated circuit device, which includes a general interconnect interface and other processing devices. The computing device interacts with the other processing devices to jointly perform user-specified computational operations. The integrated circuit device may also include a storage device connected to both the computing device and the other processing devices for data storage by the computing device and the other processing devices.

Description

Technical Field

[0001] This invention generally relates to the field of neural networks. More specifically, this invention relates to methods for compiling expressions in normalized statements, readable storage media, and compilers. Background Technology

[0002] When implementing operators in neural networks, developers can utilize various computational methods to achieve the same results. Different methods can lead to differences in code locality and parallelism. TVM is an open-source deep learning compiler that generates efficient machine code for different hardware backends by providing graph-level and operator-level optimizations.

[0003] TVM defines operators based on tensor expressions and provides a series of scheduling primitives to perform iterative transformations on the operator code. Operators described using tensor expressions are translated by TVM into TVM intermediate representations (IRs), which are tree-like, high-level representations that easily describe iterative computations. TVM implements a series of optimized passes of analysis and transformations on the intermediate representations, adjusting the operators to ultimately generate efficient code for the target hardware platform.

[0004] Important operators in deep learning applications, such as convolution, matrix multiplication, and vector addition, are often generated by TVM compilers into multi-layered nested loops in their intermediate representations. These programs, after loop transformations, produce complex expressions related to loop iteration variables. Existing non-TVM compilers optimize loop invariant extraction by storing computation results in physical registers to avoid recalculation on each use. However, the high-level intermediate representations of existing TVM compilers are unaware of physical registers. Blindly referencing the loop invariant extraction methods of non-TVM compilers introduces unnecessary register pressure, ultimately degrading operator performance. Therefore, directly applying the loop invariant extraction algorithm from existing non-TVM compilers to TVM compilers does not yield ideal optimization results.

[0005] Secondly, in the process of detecting loop invariants, the order of operands in the expression affects the discovery of invariants. Existing optimization algorithms have limited ability to detect complex nested conditional expressions that frequently appear in deep learning operators; in other words, their optimization level is not good.

[0006] Finally, the operator code generated by the TVM compiler still needs to undergo compilation and optimization by the target platform compiler before it can generate executable code for the target hardware. The target platform compiler may perform other optimizations at lower-level intermediate representations. These two different levels of optimization often conflict, reducing the effectiveness of the loop invariant outfetching algorithm.

[0007] Therefore, a technical solution for normalizing expressions in statements during compilation is urgently needed. Summary of the Invention

[0008] To at least partially solve the technical problems mentioned in the background art, the present invention provides a method for compiling expressions in a normalized statement, a readable storage medium, and a compiler.

[0009] In one aspect, the present invention discloses a method for compiling expressions in a statement that normalizes the description of a neural network operator, comprising: setting the level of each expression according to its type; and sorting each expression based on the levels of all expressions in the statement.

[0010] In another aspect, the present invention discloses a computer-readable storage medium storing computer program code that normalizes expressions in statements describing neural network operators, wherein the aforementioned compilation method is executed when the computer program code is run by a processing device.

[0011] In another aspect, the present invention discloses a compiler for normalizing expressions in a statement, comprising: a setting module and a sorting module. The setting module is used to set the level of each expression according to its type; the sorting module is used to sort each expression based on the level of all expressions in the statement.

[0012] This invention proposes a method to normalize loop expressions by adjusting the operand combination order and transforming the form of the conditional expression before detecting loop invariants, providing a better foundation for loop invariant extraction optimization and other subsequent optimizations. Finally, this invention, combining the characteristics of TVM intermediate representation and the target platform compiler, provides special handling for inner loops with a small number of branches and iterations, resolving optimization conflicts on intermediate representations at different levels. Attached Figure Description

[0013] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts. Wherein:

[0014] Figure 1 This is a structural diagram of a board card according to an embodiment of the present invention;

[0015] Figure 2 This is a structural diagram illustrating an integrated circuit device according to an embodiment of the present invention;

[0016] Figure 3 This illustrates the compilation process of TVM;

[0017] Figure 4 This diagram illustrates the overall architecture and key compilation flowchart of an embodiment of the present invention in TVM;

[0018] Figure 5 It shows the abstract syntax tree corresponding to the exemplary expression during the compilation process;

[0019] Figure 6 It shows the abstract syntax tree corresponding to the rewritten expression;

[0020] Figure 7 This is a flowchart illustrating the expressions in the statements that standardize the description of neural network operators according to embodiments of the present invention;

[0021] Figure 8 This shows the syntax tree corresponding to the example conditional expression;

[0022] Figure 9 It shows the syntax tree corresponding to the merged conditional expression;

[0023] Figure 10 This is a flowchart illustrating an expression in a statement that standardizes the description of a neural network operator according to another embodiment of the present invention;

[0024] Figure 11 This is a flowchart illustrating the optimized description of the loop of the neural network operator according to an embodiment of the present invention; and

[0025] Figure 12 This is a schematic diagram illustrating a compiler according to another embodiment of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be understood that the terms "first," "second," "third," and "fourth," etc., in the claims, specification, and drawings of this invention are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" used in the specification and claims of this invention indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0028] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0029] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection."

[0030] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0031] Controlling AI chips to execute complex neural networks generates a large number of instructions. Developers often cannot meet the requirements of generalization when writing instructions, so compilers are needed to accelerate neural networks. The compiler generates a sequence of hardware-executable instructions based on the graph and operator structures of the neural network. Compilers can be broadly divided into front-end and back-end. The front-end mainly optimizes and transforms the network structure described by deep learning frameworks such as TensorFlow, Caffe, and PyTorch into an intermediate representation. The back-end optimizes and transforms the intermediate representation into a hardware-executable program. The main challenge of the front-end is designing a universal intermediate representation that can interface with different deep learning frameworks. More complex compiler front-ends also include many hardware-independent optimization strategies, such as constant folding and operator fusion. The back-end, on the other hand, is hardware-specific. Different hardware has specific design structures, especially specially designed AI chips. Due to the uniqueness of these chips, the back-end needs to be optimized for these design structures and memory allocations for different networks.

[0032] Figure 1 A schematic diagram of the structure of a board 10 according to an embodiment of the present invention is shown. Figure 1As shown, board 10 includes chip 101, which is a system-on-chip (SoC) integrating one or more combined processing units. These combined processing units are artificial intelligence computing units used to support various deep learning and machine learning algorithms, meeting the intelligent processing needs of complex scenarios in fields such as computer vision, speech, natural language processing, and data mining. In particular, deep learning technology is widely used in cloud intelligence. A significant characteristic of cloud intelligence applications is the large volume of input data, placing high demands on the platform's storage and computing capabilities. Board 10 in this embodiment is suitable for cloud intelligence applications, possessing massive off-chip storage, on-chip storage, and powerful computing capabilities.

[0033] Chip 101 is connected to external device 103 via external interface device 102. External device 103 may be, for example, a server, computer, camera, monitor, mouse, keyboard, network card, or Wi-Fi interface. Data to be processed can be transmitted from external device 103 to chip 101 via external interface device 102. The calculation results from chip 101 can be transmitted back to external device 103 via external interface device 102. Depending on the application scenario, external interface device 102 may have different interface forms, such as a PCIe interface.

[0034] The board 10 also includes a storage device 104 for storing data, which includes one or more memory cells 105. The storage device 104 is connected to and transmits data with the controller 106 and the chip 101 via a bus. The controller 106 in the board 10 is configured to regulate the state of the chip 101. Therefore, in one application scenario, the controller 106 may include a microcontroller (MCU).

[0035] Figure 2 This is a structural diagram illustrating the combined processing device in chip 101 of this embodiment. (As shown) Figure 2 As shown, the combined processing device 20 includes a computing device 201, an interface device 202, a processing device 203, and off-chip memory 204.

[0036] The computing device 201 is configured to perform user-specified operations. It is mainly implemented as a single-core intelligent processor or a multi-core intelligent processor to perform deep learning or machine learning calculations. It can interact with the processing device 203 through the interface device 202 to jointly complete the user-specified operations.

[0037] Interface device 202 is used to transmit data and control commands between computing device 201 and processing device 203. For example, computing device 201 can obtain input data from processing device 203 via interface device 202 and write it to on-chip storage device of computing device 201. Further, computing device 201 can obtain control commands from processing device 203 via interface device 202 and write them to on-chip control cache of computing device 201. Alternatively or optionally, interface device 202 can also read data from storage device of computing device 201 and transmit it to processing device 203.

[0038] The processing device 203, as a general-purpose processing device, performs basic controls including but not limited to data transfer and starting / stopping the computing device 201. Depending on the implementation, the processing device 203 may be one or more types of processors, such as a central processing unit (CPU), a graphics processing unit (GPU), or other general-purpose and / or special-purpose processors. These processors include, but are not limited to, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, the computing device 201 of this invention can be considered as having a single-core structure or a homogeneous multi-core structure. However, when the computing device 201 and the processing device 203 are considered together, they are considered to form a heterogeneous multi-core structure.

[0039] The off-chip memory 204 is used to store data to be processed. It is DDR memory, typically 16G or larger, and is used to store data of computing device 201 and / or processing device 203.

[0040] To effectively utilize the aforementioned hardware, this embodiment optimizes the existing TVM architecture. TVM provides a complete compiler architecture solution, customizing the intermediate representation and abstracting the computation process (including operators, variables, etc.) to generate complete code and execution framework.

[0041] Figure 3The compilation flow of TVM is illustrated. Model 301 refers to the series of code controlling the aforementioned hardware generated after the developer completes the programming. Front-end import 302 is the process by which the front-end component extracts neural networks from various deep learning frameworks, especially tensor expressions, and transforms them into intermediate representations of TVM. The so-called tensor expressions here are domain-specific languages ​​designed by TVM to describe tensor operations based on Halide's idea of ​​separating operator description and scheduling optimization. This language defines the input-output relationships between tensors and provides a series of scheduling primitives such as loop splitting, loop merging, and loop blocking. The combination of these scheduling primitives specifies the specific strategy for computing the output tensor.

[0042] The intermediate representation module 303 generates intermediate representations of relays, which are high-level abstract representations used to construct a data flow graph containing multiple nodes. The intermediate representation of a relay is described by `relay::function`, which describes the entire graph structure, has input and output variables, and internally contains the computation sequence. The intermediate representation module 303 optimizes and transforms the network graph structure based on the relay passes function 304, such as constant folding, useless code elimination, layout transformation, and scale factor folding, to improve hardware operating efficiency.

[0043] The intermediate representation generated at this point mainly includes two types of nodes: expression nodes and statement nodes. Expression nodes contain variables and constants, array data loading, function calls, arithmetic and logical expressions, conditional expressions, etc.; statement nodes contain sequence, loop, branch, assignment, etc. TVM traverses and modifies the nodes using the relay pass function 304. At this point, the front-end task of the TVM compiler is complete.

[0044] Next, the backend program is executed. Primitive-function scheduling 305 calls primitives related to the aforementioned nodes and searches for the optimal optimization space through automatic TVM function 306. Automatic TVM function 306 is an automatic optimization algorithm whose main idea is to achieve network optimization based on reinforcement learning. It collects information from computing device 201 on how to perform the same task in different ways to continuously update optimization variables.

[0045] The intermediate representation module 307, based on the underlying intermediate representation pass (TIR passes) function 308, optimizes and transforms the operator structure, mostly handling dimensionality reduction, such as expanding multidimensional paths into one-dimensional pointer paths and modifying function entry points to be runtime-callable. The underlying intermediate representation pass function 308 is a representation structure closer to the hardware, which can optimize instructions such as tensor computation operators and load / store operations. If developers have custom instructions, they are usually defined in the underlying intermediate representation pass function 308.

[0046] Target translation 309 converts the intermediate representation generated by intermediate representation module 307 into an executable program, which is encapsulated by runtime module 310, making it easier to load, export, and execute in the runtime environment of computing device 201. At this point, the backend tasks of the TVM compiler are complete.

[0047] Specifically, this embodiment incorporates an optimized compiler designed by the developer into the underlying intermediate representation transfer function 308, particularly optimizing the loops describing neural network operators. Under certain conditions, and considering the characteristics of the intermediate representation module 307 and the target platform compiler, this embodiment reduces redundant computations by hoisting loop invariants, thereby improving the runtime performance of the target translation result 309.

[0048] The following example defines a tensor expression describing a fixed-size matrix multiplication operator:

[0049] M=1024; K=1024; N=1024; bn=32

[0050] A=te.placeholder((M,K),name="A")

[0051] B=te.placeholder((K,N),name="B")

[0052] k = te.reduce_axis((0,K),"k")

[0053] C=te.compute((M,N),lambda x,y:te.sum(A[x,k]*B[k,y],axis=k),name="C")

[0054] s = te.create_schedule(C.op)

[0055] Variables A and B are defined as two-dimensional matrices of size 1024×1024, and k is defined as the cyclic axis for summation and reduction during matrix multiplication. Matrix C is calculated from matrices A and B. After the above operator description is compiled by the intermediate representation module 307 of the TVM deep learning compiler, the following intermediate representation code can be obtained:

[0056]

[0057]

[0058] In existing technologies, to implement the innermost loop in the code above, TVM uses functions such as tile, split, and reorder to perform loop-blocking, loop-split, and loop-reordering on the matrix multiplication operator, thereby obtaining the following intermediate representation:

[0059] xo,yo,xi,yi=s[C].tile(C.op.axis[0],C.op.axis[1],bn,bn)

[0060] (k,)=s[C].op.reduce_axis ko,ki=s[C].split(k,factor=32)

[0061] s[C].reorder(xo,yo,ko,ki,xi,yi)

[0062] The transformed operator description, after being translated by Target Translation 309, yields the following intermediate representation code:

[0063]

[0064] After undergoing a loop transformation, operators achieve better parallelism and data locality, and can fully utilize the characteristics of the underlying hardware. However, this transformation changes the array expression from a simple expression to a semantically equivalent but more complex one, adding unnecessary scalar operations. For example, in the intermediate representation code obtained after the loop transformation of the matrix multiplication operator above, for the innermost loop, the loop iteration variable is yi, and its expression xo*32768+xi*1024+yo*32 remains unchanged in each iteration of the innermost loop, making the calculations after the first iteration redundant.

[0065] To address this technical problem, this embodiment modifies the machine learning operator-level optimization module of TVM. This embodiment introduces the concept of normalization, recombining expressions and merging conditional expressions and branches. Then, by moving redundant calculations where the values ​​remain unchanged multiple times in the loop outside the loop, additional redundant operations are reduced, resulting in higher-performance operators. Figure 4 This diagram illustrates the overall architecture and key compilation flowchart of this embodiment in TVM.

[0066] In step 401, the ScheduleOps function is executed to translate the tensor expression of the operator into an intermediate representation. In step 402, the StorageFlattern function is executed to flatten the multidimensional array of tensors into a one-dimensional array. In step 403, the InjectDoubleBuffer function is executed to maximize hardware utilization and optimize the pipeline. In step 404, the StorageRewrite function is executed to calculate memory reuse and optimize memory-related variables. In step 405, the Normalize function is executed, which performs semantic-preserving transformations on statements and expressions, making the normalized statements more conducive to subsequent loop invariant hoisting or optimization by the target platform compiler. In step 406, the LICM (loopinvariant code motion) function is executed, using the loop invariant hoisting algorithm in this embodiment to hoist variables that remain unchanged within the loop to outside the loop. In step 407, the UnrollLoop function is executed to unroll the loop, reducing the number of loops. In step 408, the HoistIfThenElse function is executed to move the inner conditional branch statements to the outer loop as much as possible to reduce the number of calculations.

[0067] When the compiler seeks to identify loop invariants in an expression, the order of operands is crucial. Different operand orders not only affect whether certain loop-invariant expressions can be detected but also determine whether certain branch optimizations in the compiler can be triggered. Therefore, before executing the LICM function, this embodiment normalizes the expression in step 405, using the associativity of operators to perform transformations such as reassociation, so that the updated operand order is conducive to detecting loop-invariant expressions and triggering branch optimizations.

[0068] The most important operations in normalization are expression reassociation and merging of conditional expressions and branches. Expression reassociation refers to using specific algebraic laws, such as associativity, commutativity, and distributivity, to divide an expression into constant parts, loop-invariant parts, and variable parts. Although expression reassociation itself does not improve performance, since whether a subexpression in an expression is a loop-invariant expression largely depends on the order of operations and associativity of the operands, expression reassociation can significantly improve subsequent loop invariant outfetching optimizations.

[0069] To illustrate the normalization process more clearly, the following expression is given as an example:

[0070] ((((3 <i)&&(3<j))&&(i<56))&&(j<56))

[0071] Where i is the loop iteration variable. Based on the execution priority determined by the parentheses in the above expression, the corresponding abstract syntax tree during compilation is as follows: Figure 5 As shown. One task of normalization is to make appropriate adjustments so that the subexpression is as invariant as possible to facilitate its hoisting in subsequent steps. For example, the compiler in this embodiment can rewrite the above expression after normalization as follows:

[0072] (((3 <i)&&(i<56))&&((3<j)&&(j<56)))

[0073] The abstract syntax tree corresponding to the rewritten expression is as follows: Figure 6 As shown. This expression has the same computational result as the unnormalized expression, but from... Figure 6 It can be seen that the normalized expression yields a more ideal loop-invariant expression ((3) <j)&&(j<56))。

[0074] Figure 7 This embodiment shows a flowchart of the expression in the statement that normalizes the description of the neural network operator in step 405.

[0075] In step 701, it is determined whether the statement includes a conditional expression and whether the condition is true or false corresponds to the same return value. Conditional expressions have complex structures, so they are processed first. Each conditional expression produces a corresponding return value for both the true and false conditions. In nested conditional expressions, multiple true or false conditions may correspond to the same return value. In this case, this embodiment merges these conditions with the same return value, making the loop invariants in the transformed expression more complete.

[0076] For example, the following expression is a nested conditional expression, where only i is the loop iteration variable:

[0077] ((3 < i) && (3 < j))? (((i < 56) && (j < 56))? 1 : 0) : 0

[0078] This conditional expression includes two levels of conditional judgments. The first level is: when i < 56 holds and j < 56 holds, the return value is 1, otherwise the return value is 0. The second level is that when 3 < i holds and 3 < j holds, the return value is the return value of the first level, otherwise the return value is 0. The syntax tree corresponding to this conditional expression is as Figure 8 shown. Based on this syntax tree, the candidate loop invariants that the TVM compiler can determine are 3 < j and j < 56.

[0079] Taking the above example, the compiler determines that this statement does indeed include a conditional expression, and when both conditions (i < 56) && (j < 56) and (3 < i) && (3 < j) hold, they correspond to the same return value 1. Moreover, when both conditions (i < 56) && (j < 56) and (3 < i) && (3 < j) do not hold, they also correspond to the same return value 0. Under this premise, step 702 is executed to call the function condCollapse(e) to optimize the expression e that can be used for conditional merging, that is, to merge the conditional judgments with the same return value, and return the optimized result to update the conditional expression. The merged expression is as follows:

[0080] ((((3 < i) && (i < 56)) && ((3 < j) && (j < 56)))? 1 : 0)

[0081] Its corresponding syntax tree is as Figure 9 shown. The merged expression generates a better candidate loop invariant expression ((3 < j) && (j < 56)), and the forms of the two expressions ((3 < i) && (i < 56)) and ((3 < j) && (j < 56)) are more conducive to implementing peephole optimizations related to Boolean expressions. Peephole optimization is a local optimization method. The compiler only focuses on the code that has been generated in the sliding window, and combines the instruction characteristics of the computing device 201 to improve the performance of the code in the sliding window through instruction transformation.

[0082] If the statement in step 701 does not include a conditional expression or the condition (true or false) does not correspond to the same return value, or if step 702 is executed, then step 703 is executed to determine whether the statement satisfies the associativity law. If the statement satisfies the associativity law, it means that moving the relative position of the expression within the statement does not change the result of the statement's operation, and the statement can be normalized. More specifically, this embodiment iterates through the statement to find whether there exists an operator ⊕ that satisfies the associativity law. The operator ⊕ is merely a symbolic designation used to represent all types of operators that satisfy the associativity law.

[0083] If a statement does not satisfy the associativity law, it cannot be normalized. Step 704 is executed to end the normalization process for that statement.

[0084] If the statement satisfies the associativity, then step 705 is executed, setting the level of the expression according to the type of each expression. If the expression has been merged in step 702, then this step sets the level according to the type of the merged conditional expression.

[0085] Specifically, this embodiment calls `deconstruct(e, ⊕)` to convert the expressions connected by the operator `⊕` into an ordered sequence of expressions `L`, assigning a level to each expression. This embodiment divides expressions into three levels based on their type: constants are the highest level, nested loops are the middle level, and other types are the lowest level. Higher levels are more beneficial for subsequently identifying expressions with invariant loops and triggering branch optimizations. Based on the aforementioned rules, this step first determines whether the expression is a constant; if it is, its level is set to level one. If it is not a constant, it further determines whether the expression includes nested loops; if it does, its level is set to level two. If it does not include nested loops, meaning the expression is neither a constant nor contains nested loops, its level is set to level three regardless of its type.

[0086] Because nested loops can have multiple levels, variables in the outer loop are more easily hoisted than those in the inner loop. Therefore, if the expression includes nested loops, and these nested loops contain N loops (N greater than 1), this step, while setting the level of the expression containing nested loops to the second level, further sets the child levels based on the loop hierarchy. Specifically: the child level of the outermost loop is set as the first child level; the child level of the next outermost loop is set as the second child level; and so on, setting the child levels of other loops until the child level of the innermost loop is set as the Nth child level. In other words, the outermost loop has the highest child level, and the innermost loop has the lowest. Similarly, a higher child level is more conducive to subsequently identifying loop-invariant expressions and triggering branch optimizations.

[0087] For example, a statement might contain three expressions: one a constant, another containing a nested loop, and the last of some other type, with three nested loops. This step first determines if the expressions are constants and assigns them a first-level priority. Next, it checks for nested loops and assigns them a second-level priority. Since there are three levels of nested loops, this step further assigns the outermost loop's child to the first-level priority; the second outermost loop's child to the second-level priority; and the innermost loop's child to the third-level priority. Finally, the last expression is assigned a third-level priority.

[0088] In some cases, an expression may include multiple subexpressions, each with a different level. This embodiment sets the level of the expression based on the lowest level among all subexpressions. Specifically, if an expression contains any subexpression that is not a constant and does not contain nested loops, then the expression must contain other types of subexpressions, and this embodiment sets the level of the expression to level three. If all subexpressions in an expression are constants or contain nested loops, this embodiment sets the level of the expression to level two based on the level of the nested loops.

[0089] In step 706, each expression is sorted based on its rank. In this embodiment, the function stableSort(L) is called to sort the sequence of expressions L with rank markings from highest to lowest according to their rank and sub-rank, and the sorted sequence L is returned.

[0090] The sorting method is as follows: all expressions in the statement are arranged in the order of their level 1, level 2, and level 3, and all expressions in the level 2 are arranged in the order of their child level 1, level 2, and so on up to level N.

[0091] In the example above, the priority order of the expressions is: constant (level 1) > outermost loop (level 2, first sub-level) > second outermost loop (level 2, second sub-level) > innermost loop (level 2, third sub-level) > others (level 3). Based on the priority order of the expressions, this embodiment can further consider reorganizing these levels and sub-levels to obtain a more intuitive sorting method and facilitate recording the priority order. For example, the expression for constant can be adjusted to level 0, the expression for outermost loop to level 1, the expression for second outermost loop to level 2, the expression for innermost loop to level 3, and the other expressions to level 4. In this way, the sorting can be intuitively performed according to the level number.

[0092] In step 707, expressions with the same level or sublevel are concatenated using operators to generate sibling expressions. This embodiment calls the function `groupExpressions(L, ⊕)` to concatenate expressions with the same level or sublevel in the sorted sequence `L` using the operator `⊕` to form a new expression, and returns the transformed sequence `L`. For example, if a statement contains multiple constant expressions, since the level of these constant expressions is all set to first level, these constant expressions will be concatenated together using the operator `⊕` to form a new expression.

[0093] In step 708, all sibling expressions are concatenated using operators based on hierarchical or child order to return the updated statement. This embodiment calls the function `construct(L, ⊕)`, which uses the operator `⊕` to sequentially concatenate all expressions in sequence `L` and returns the transformed final result `e`. Since normalization is performed under associative conditions, the transformed final result `e` has an equivalent computational result to the original sequence `L`.

[0094] Figure 10 This embodiment shows a flowchart of the expression in another normalized statement describing the neural network operator in step 405.

[0095] In step 1001, it is determined whether the statement includes a conditional expression and whether the condition is true or false corresponds to the same return value. Conditional expressions have complex structures, so they are processed first. Each conditional expression produces a corresponding return value for both the truth and falsehood of the condition. In nested conditional expressions, multiple conditions may have the same return value. In this case, this embodiment merges these conditions with the same return value, making the loop invariants in the transformed expression more complete.

[0096] If the statement includes a conditional expression and the true / false conditions correspond to the same return value, then step 1002 is executed, calling the function condCollapse(e) to optimize the expression e that can be merged for conditional merging, i.e., merging conditional statements with the same return value, and returning the optimized result to update the conditional expression. If the statement in step 1001 does not include a conditional expression or the true / false conditions do not correspond to the same return value, or if step 1002 has been executed, then step 1003 is executed next, setting the level of the expression according to its type. If the expression has been merged in step 1002, then this step sets the level according to the type of the merged conditional expression. The merging method is as described in step 705 and will not be repeated here.

[0097] In step 1004, it is determined whether the statement satisfies the associativity law. If the statement satisfies the associativity law, it means that moving the relative positions of the expressions within the statement will not change the result of the operation, and the statement can be normalized. More specifically, this embodiment iterates through the statement to find whether there exists an operator ⊕ that satisfies the associativity law. The operator ⊕ is merely a symbolic designation used to represent all types of operators that satisfy the associativity law.

[0098] If a statement does not satisfy the associativity law, it cannot be normalized. Execute step 1005 to end the normalization process for that statement.

[0099] If the statement satisfies the associative law, then proceed to step 1006, which sorts each expression based on its rank. The sorting method is as described in step 706 and will not be repeated here.

[0100] In step 1007, expressions with the same level or sublevel are concatenated using operators to generate sibling expressions. This embodiment calls the function `groupExpressions(L, ⊕)` to concatenate expressions with the same level or sublevel in the sorted sequence `L` using the operator `⊕` to form a new expression, and returns the transformed sequence `L`. For example, if a statement contains multiple constant expressions, since the level of these constant expressions is all set to first level, these constant expressions will be concatenated together using the operator `⊕` to form a new expression.

[0101] In step 1008, all sibling expressions are concatenated using operators based on hierarchical or child order to return the updated statement. This embodiment calls the function `construct(L, ⊕)`, which uses the operator `⊕` to sequentially concatenate all expressions in sequence `L` and returns the transformed final result `e`. Since normalization is performed under associative conditions, the transformed final result `e` has an equivalent computational result to the original sequence `L`.

[0102] Regardless of the use Figure 7 or Figure 10 The normalized operation in this embodiment places the optimization of memory read and write related operations on a lower-level intermediate representation. The normalization in this embodiment focuses on specific transformations of different variables and conditional expressions, which is beneficial to the subsequent implementation of loop invariant extraction optimization and control flow optimization.

[0103] Step 406 is a key operation for optimizing the loop. The loop nodes in the intermediate representation of TVM contain the nested loop relationship and the corresponding iteration variables. In this embodiment, based on the normalized statement, it recursively determines whether a certain expression remains unchanged in the loop. If so, it means that the expression has redundant calculations in the loop. Therefore, the expression is taken out of the loop and only executed once outside the loop. Figure 11The flowchart of the loop describing the neural network operator in step 406 of this embodiment is further shown.

[0104] In step 1101, the underlying intermediate representation transfer function 308 is used to traverse all statements in the program, classifying and discussing them according to their possible syntactic forms, and determining whether the expression of each statement is loop-invariant. These expressions are all associated with variables. For ease of distinction, the variables before loop optimization are called initial variables, and the variables after loop optimization are called hoisted variables. Apart from the difference in name, they are essentially the same intermediate representation variables and have no difference.

[0105] In this embodiment, an expression is considered cyclically invariant if the value constituting the expression satisfies any of the following criteria: the initial variable is a constant, including immutable program parameters or immediate values; the assignment of the variable in the expression occurs outside the loop; and the variable is used to only one fixed value, and the expression for that fixed value is also cyclically invariant. In other words, this step determines whether the value constituting the expression satisfies any of the above criteria.

[0106] If the expression is not loop-invariant, it means that the initial variable associated with the expression will change within the loop and cannot be extracted from the loop. In this case, step 1102 is executed, marking the expression as "cannot be extracted." Specifically, this embodiment identifies invariant expressions within the loop and marks those expressions whose calculation results may change in multiple iterations of the loop. The remaining unmarked expressions are the loop invariants. This embodiment does not mark or process loop-invariant expressions at this stage.

[0107] In other cases, in step 1101, when it is determined that the statement is an assignment to an initial variable through an expression, such as initial variable x = e, and the expression e is marked as "not to be moved out", the initial variable x is not a loop invariant, that is, the initial variable x defined by the assignment statement is regarded as "not to be moved out", then in step 1102, the initial variable x in the expression is marked as "not to be moved out".

[0108] In other cases, in step 1101, when the judgment statement is a loop statement and the expression is not a loop invariant, then in step 1102, the initial variable in the expression is marked as "cannot be moved out".

[0109] Regardless of whether the expression is a loop that does not change, step 1103 is executed to determine whether the iteration has been completed. If not, the process returns to step 1101 to evaluate the next expression.

[0110] After traversing all statements, step 1104 is then executed, replacing each expression not marked as "non-promotable" with a different hoisted variable. This embodiment generates hoisted variables, rewrites the loop-invariant expressions in the statements using hoisted variables, and adds the hoisted variables of all identified loop invariants to the loop invariant set for subsequent processing.

[0111] In step 1105, a cost function is invoked to calculate the cost of each expression not marked as "non-promotable". In this embodiment, the cost function cost(e) is invoked to calculate the cost of outsourcing expression e. The cost function cost(e) takes expression e as input, calculates and returns the outsourcing cost of e. The reason for introducing the cost function cost(e) in this embodiment is that the high-level operator code generated by TVM needs to be compiled by the target platform compiler to generate an executable program on computing device 201. Since the target platform compiler will also perform a series of optimizations on the program at a lower-level intermediate representation, in order to avoid interference between the two different levels of optimization, the cost function cost(e) is used to calculate and select more efficient loop invariants for outsourcing.

[0112] The cost function cost(e) can be defined as follows:

[0113]

[0114] When e is a constant or variable, its cost is defined as 0; when e is a compound expression, its cost is recursively defined on its various subexpressions a, plus the cost of its operator ⊕.

[0115] In expression For example, according to its definition, its cost function for:

[0116]

[0117] Different operators ⊕ have different costs based on their required clock cycles. Generally, the addition instruction requires fewer clock cycles, so in this example, cost(+) = 1. The division instruction requires more clock cycles, so in this example, cost(÷) = 3. Since x, 1124, and y are constants or variables, cost(x), cost(1124), and cost(y) are all 0. The cost function can be obtained in this step.

[0118] It is important to note that the cost function cost(e) can be adjusted arbitrarily to match the actual situation of different hardware platforms. For example, for GPUs, the compiler on the platform usually chooses to expand loops with a very small iteration range and perform other optimizations on this basis. Based on this characteristic, the cost value of the expression in the loop with a very small iteration range can be set to 0, thereby avoiding interference between two different levels of optimization.

[0119] In step 1106, it is determined whether the cost value is greater than or equal to a threshold. In this embodiment, the threshold is set to 1, which means whether the cost value is greater than or equal to 1. By comparing it with the preset threshold, it is evaluated whether extracting the expression produces a sufficiently large benefit.

[0120] If the cost is not greater than or equal to the threshold, it indicates insufficient benefit and is not worthwhile to extract the expression. Therefore, step 1107 is executed to abandon the extraction attempt, remove the extracted variable from the set of loop invariants, restore the replaced expression, and mark the expression as "cannot be extracted". For example, although the constant is also loop invariant, its cost is zero, which is less than the threshold. Extracting the constant would not be beneficial, so the constant will not be extracted in this step.

[0121] If the cost is greater than or equal to the threshold, the compiler considers it a sufficient benefit, and if expression hoisting has no side effects, the expression can be hoisted. In this case, step 1108 is executed, inserting the assignment statements for all hoisted variables before the loop. For example... The cost is 4, which is greater than the threshold of 1. It is beneficial to hoist the expression, so the assignment statement of its hoisted variable is inserted before the loop.

[0122] In step 1109, the hoisted expressions are deleted. Since expressions not marked as "non-hoisted" have been rewritten as hoisted variables and inserted before the loop, the corresponding expressions in the loop are deleted to avoid duplicate execution.

[0123] In step 1110, an intermediate representation is generated based on the assignment statements of all hoisted variables. The intermediate representation module 307 generates an intermediate representation based on the assignment statements of all hoisted variables and other statements.

[0124] In step 1111, a translation is performed based on the intermediate representation. Target translator 309 translates the intermediate representation generated in step 1110 to generate an executable program for computing device 201.

[0125] In step 1112, the runtime module 311 encapsulates the executable program.

[0126] Since the loop invariant has been moved outside the loop, when the computing device 201 performs deep learning tasks according to the encapsulated executable program, such as performing intelligent needs in fields like computer vision, speech, natural language processing, and data mining, it will no longer repeatedly execute the loop-invariant expression in the loop, thus completing the task more efficiently.

[0127] Another embodiment of the present invention is a compiler for normalizing expressions in statements, used to implement, for example... Figure 7 or Figure 10 The method shown is a normalized description of expressions in statements that describe neural network operators. Figure 12 The diagram shows a compiler for this embodiment. The compiler includes a judgment module 1201, a merging module 1202, a setting module 1203, a sorting module 1204, and a connection module 1205. Each module transmits information through a bus 1206.

[0128] The judgment module 1201 is used to determine whether a statement includes a conditional expression and whether the condition is true or false corresponds to the same return value. A conditional expression produces a corresponding return value for both the truth and falsehood of the judgment condition. In nested conditional expressions, multiple judgment conditions may correspond to the same return value.

[0129] The merging module 1202 is used to merge judgment conditions with the same return value and return the optimized result to update the condition expression.

[0130] Next, the judgment module 1201 further determines whether the statement satisfies the associativity law. If the statement satisfies the associativity law, it means that moving the relative positions of the expressions within the statement will not change the result of the statement's operation, and the statement can be normalized. More specifically, the judgment module 1201 traverses the statement to find whether there exists an operator ⊕ that satisfies the associativity law. If the expression has been merged by the merging module 1202, the judgment module 1201 will determine whether the statement satisfies the associativity law based on the type of the merged conditional expression.

[0131] If a statement does not satisfy the associativity law, normalization cannot be performed, and the normalization process for that statement ends. If a statement satisfies the associativity law, the setting module 1203 sets the level of each expression according to its type. Specifically, the setting module 1203 converts expressions connected by the operator ⊕ into an ordered sequence of expressions L, and assigns a level to each expression. In this embodiment, the setting module 1203 divides expressions into three levels according to their type: constants are the highest level, nested loops are the middle level, and other types are the lowest level. A higher level is more conducive to subsequently discovering expressions with invariant loops and triggering branch optimizations.

[0132] Because nested loops can have multiple levels, variables in the outer loop are more easily hoisted than those in the inner loop. Therefore, if the expression includes nested loops, and these nested loops contain N loops (N greater than 1), then module 1203, while setting the level of the expression containing nested loops to the second level, will further set the child levels according to the loop hierarchy. Specifically, the child level of the outermost loop is set as the first child level; the child level of the next outermost loop is set as the second child level; and so on, setting the child levels of other loops until the child level of the innermost loop is set as the Nth child level.

[0133] In some cases, an expression may include multiple subexpressions, each with a different level. The setting module 1203 sets the lowest level among all subexpressions to the level of the expression. Specifically, if an expression contains any subexpression that is not a constant and does not contain nested loops, then the expression must contain other types of subexpressions, and the setting module 1203 sets the level of that expression to level three. If all subexpressions in an expression are constants or contain nested loops, the setting module 1203 sets the level of the expression to level two, based on the level of the nested loops.

[0134] In another implementation, the setting module 1203 can first set the level of the expression according to the type of each expression, and then the judgment module 1201 can determine whether the statement satisfies the associative law. Those skilled in the art can understand and implement this technical solution without creative effort, so it will not be described in detail here.

[0135] The sorting module 1204 sorts each expression based on its level in the statement, sorts the sequence of expressions L with marked levels from highest to lowest, and returns the sorted sequence L.

[0136] The sorting method is as follows: all expressions in the statement are arranged in the order of their level 1, level 2, and level 3, and all expressions in the level 2 are arranged in the order of their child level 1, level 2, and so on up to level N.

[0137] The joiner module 1205 is used to connect expressions of the same level or sublevel using operators to generate sibling expressions. More specifically, the joiner module 1205 connects expressions of the same level or sublevel in a sorted sequence L using the operator ⊕ to form a new expression and returns the transformed sequence L. The joiner module 1205 also connects all sibling expressions based on their level or sublevel order using operators to return an updated statement; that is, it sequentially connects all expressions in sequence L using the operator ⊕ and returns the final transformed result e.

[0138] Since normalization is performed under the associative law, the transformed final result e has an equivalent operational result to the original sequence L. At this point, the normalization operation in this embodiment has been completed.

[0139] Another embodiment of the present invention is a computer-readable storage medium storing computer program code that normalizes expressions in statements describing neural network operators. When the computer program code is run by a processor, it executes... Figure 7 or Figure 10 The method described above. In some implementation scenarios, the integrated unit described above can be implemented as a software program module. If implemented as a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable storage memory. Based on this, when the solution of the present invention is embodied in the form of a software product (e.g., a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to cause a computer device (e.g., a personal computer, a server, or a network device, etc.) to execute some or all of the steps of the method described in the embodiments of the present invention. The aforementioned memory may include, but is not limited to, various media capable of storing program code, such as USB flash drives, flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0140] This invention reduces redundant computations by moving redundant calculations that keep the value constant within a loop outside the loop, thereby generating higher-performance operators. Currently, a typical characteristic of various AI-specific processors is that many components are designed for running computationally intensive programs, exhibiting high computational parallelism. To fully utilize these hardware characteristics, the target platform compiler of this invention chooses to unroll inner loops. The latency of some computations is compensated for by the instruction pipeline; therefore, the redundant computations of unrolling inner loops do not affect runtime but rather reduce physical register pressure. Since AI-specific processors focus on parallel computing, branch optimization tasks need to be handled by the compiler. Therefore, the outsourcing of Boolean expressions and conditional branch statements requires careful handling, and the form of conditional expressions may be transformed when necessary to make the generated code more conducive to optimization by the underlying compiler.

[0141] In summary, this invention proposes a scheme for standardizing expressions in statements describing neural network operators, targeting deep learning compilers. This standardization focuses on specific transformations of different variables and conditional expressions, which is beneficial for subsequent loop invariant extraction optimization and control flow optimization.

[0142] Depending on the application scenario, the electronic devices or apparatus of the present invention may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, dashcams, navigators, sensors, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, autonomous driving terminals, vehicles, home appliances, and / or medical devices. The vehicles include airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs. The electronic devices or apparatus of the present invention can also be applied in fields such as the Internet, IoT, data centers, energy, transportation, public management, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and healthcare. Furthermore, the electronic devices or apparatus of the present invention can also be used in application scenarios related to artificial intelligence, big data, and / or cloud computing, such as cloud computing, edge computing, and terminal computing. In one or more embodiments, the high-computing-power electronic devices or apparatuses according to the present invention can be applied to cloud devices (e.g., cloud servers), while the low-power electronic devices or apparatuses can be applied to terminal devices and / or edge devices (e.g., smartphones or cameras). In one or more embodiments, the hardware information of the cloud devices and the hardware information of the terminal devices and / or edge devices are compatible with each other, so that suitable hardware resources can be matched from the hardware resources of the cloud devices to simulate the hardware resources of the terminal devices and / or edge devices based on the hardware information of the terminal devices and / or edge devices, so as to complete the unified management, scheduling and collaborative work of end-to-cloud or cloud-edge-end integration.

[0143] It should be noted that, for the sake of brevity, this invention describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solution of this invention is not limited to the order of the described actions. Therefore, based on the disclosure or teachings of this invention, those skilled in the art will understand that some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this invention can be considered as optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions of this invention. In addition, depending on the solution, the description of some embodiments of this invention also has different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this invention can also refer to the relevant descriptions of other embodiments.

[0144] In terms of specific implementation, based on the disclosure and teachings of this invention, those skilled in the art will understand that the several embodiments disclosed herein can also be implemented in other ways not disclosed herein. For example, regarding the various units in the electronic device or device embodiments described above, this document has divided them based on logical functions, but in actual implementation, there may be other ways of division. As another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. Regarding the connection relationship between different units or components, the connection discussed above in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection utilizing an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

[0145] In this invention, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same position or distributed across multiple network units. Furthermore, depending on actual needs, some or all of the units can be selected to achieve the purpose of the solution described in the embodiments of this invention. Additionally, in some scenarios, multiple units in the embodiments of this invention may be integrated into one unit or each unit may exist physically independently.

[0146] In other implementation scenarios, the integrated units described above can also be implemented in hardware, i.e., as specific hardware circuits, which may include digital circuits and / or analog circuits. The physical implementation of the circuit's hardware structure may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors. Therefore, the various devices described herein (e.g., computing devices or other processing devices) can be implemented using appropriate hardware processors, such as central processing units, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage units or storage devices can be any suitable storage medium (including magnetic storage media or magneto-optical storage media), such as resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), ROM, and RAM.

[0147] The foregoing can be better understood in accordance with the following terms:

[0148] Clause A1. A method for compiling expressions in a statement that normalizes a neural network operator, comprising: setting the level of each expression according to its type; and sorting each expression based on the levels of all expressions in the statement.

[0149] Clause A2, the compilation method according to Clause A1 further includes: determining whether the statement satisfies the associativity law; wherein, if the statement satisfies the associativity law, the setting step is executed.

[0150] Clause A3, the compilation method according to Clause A1 further includes: determining whether the statement satisfies the associative law; wherein, if the statement satisfies the associative law, the sorting step is executed.

[0151] Clause A4, the compilation method according to Clause A1 further includes: determining whether the statement is a conditional statement and whether the condition is true or false corresponds to the same return value; and if the statement is a conditional statement and whether the condition is true or false corresponds to the same return value, merging the judgment conditions with the same return value to update the conditional statement; wherein, the setting step sets the level according to the type of the updated conditional statement.

[0152] Clause A5, the compilation method according to Clause A2 or 3, wherein the setting step includes: determining whether the expression is a constant; and if the expression is a constant, setting the level to level one.

[0153] Clause A6, the compilation method according to Clause A5, wherein the setting step includes: determining whether the expression contains nested loops; and if the expression contains nested loops, setting the level to level two.

[0154] Clause A7. The compilation method according to Clause A6, wherein the nested loop includes N loops, and the step of setting the level to the second level includes: setting the sub-level of the outermost loop to the first sub-level; setting the sub-level of the next outermost loop to the second sub-level; and setting the sub-levels of the other loops in this manner until the sub-level of the innermost loop is set to the Nth sub-level.

[0155] Clause A8, the compilation method according to Clause A7, wherein the setting step includes: setting the level to level three if the expression is not a constant and does not contain nested loops.

[0156] Clause A9, the compilation method according to Clause A8, wherein the expression includes multiple sub-expressions, and the setting step includes: if any sub-expression is not a constant and does not contain nested loops, setting the level to level three.

[0157] Clause A10, the compilation method according to Clause A8, wherein the expression comprises multiple sub-expressions, and the setting step comprises: if all sub-expressions are constants and include one of nested loops, and any sub-expression includes a nested loop, setting the level to level two.

[0158] Clause A11, the compilation method according to Clause A8, wherein in the sorting step, all expressions in the statement are arranged in the order of the first level, the second level, and the third level.

[0159] Clause A12, the compilation method according to Clause A11, wherein in the sorting step, all expressions of the second level are arranged in the order of the first sub-level, the second sub-level to the Nth sub-level.

[0160] Clause A13, the compilation method described in Clause A12, further includes: concatenating expressions of the same level or sublevel with operators to generate sibling expressions; concatenating all sibling expressions with operators based on the order of level or sublevel to return an updated statement; and compiling based on the updated statement.

[0161] Clause A14. A computer-readable storage medium having stored thereon computer program code of expressions in statements that normalize descriptions of neural network operators, which, when run by a processing device, executes the compilation method described in any one of Clauses A1 to A13.

[0162] Clause A15, a compiler for normalizing expressions in a statement, comprising: a setting module for setting the rank of each expression according to its type; and a sorting module for sorting each expression based on the rank of all expressions in the statement.

[0163] The embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for compiling expressions in statements that standardize descriptions of neural network operators, comprising: Merge expressions in statements describing neural network operators; Based on the type of each expression, the level of the expression is set, wherein the level of the expression includes a first level for constant expressions, a second level for expressions representing nested loops, and a third level for expressions representing other expressions, wherein when the level of the expression for a nested loop is second level, the sub-level is set according to the loop hierarchy; and Based on the level of all expressions in the statement, each expression is sorted to connect expressions with the same level or sub-level with operators to generate sibling expressions. All sibling expressions are concatenated with operators based on rank or subrank order to return an updated statement that has the same effect as the original statement in the neural network operator. The updated statement is used to discover expressions that are invariant to cycles.

2. The compilation method according to claim 1 further includes: Determine whether the statement satisfies the associative law; If the statement satisfies the associative law, the setting steps are executed.

3. The compilation method according to claim 1 further includes: Determine whether the statement satisfies the associative law; If the statement satisfies the associative law, the sorting step is executed.

4. The compilation method according to claim 1 further includes: Determine whether the statement is a conditional statement and whether the condition is true or false corresponds to the same return value; as well as If the statement is a conditional statement and the condition is true or false, the same return value is returned. Conditions with the same return value are merged to update the conditional statement. The setting step sets the level according to the type of the updated conditional statement.

5. The compilation method according to claim 2 or 3, wherein the setting step includes: Determine whether the expression is a constant; as well as If the expression is a constant, the level is set to level one.

6. The compilation method according to claim 5, wherein the setting step includes: Determine whether the expression contains nested loops; as well as If the expression includes nested loops, the level is set to level two.

7. The compilation method according to claim 6, wherein the nested loop includes N loops, and the step of setting the level to the second level includes: Set the child level of the outermost loop to the first child level; Set the child level of the outermost loop to the second child level; as well as Set the sub-levels of other loops in this way until the sub-level of the innermost loop is set to the Nth sub-level.

8. The compilation method according to claim 7, wherein the setting step includes: If the expression is not a constant and does not contain nested loops, the level is set to level three.

9. The compilation method according to claim 8, wherein the expression includes multiple sub-expressions, and the setting step includes: If any subexpression is not a constant and does not contain nested loops, the level is set to level three.

10. The compilation method according to claim 8, wherein the expression includes multiple sub-expressions, and the setting step includes: If all subexpressions are constants and include one of nested loops, and any subexpression includes a nested loop, then the level is set to Level 2.

11. The compilation method according to claim 8, wherein in the sorting step, all expressions in the statement are arranged in the order of the first level, the second level, and the third level.

12. The compilation method according to claim 11, wherein in the sorting step, all expressions of the second level are arranged in the order of the first sub-level, the second sub-level to the Nth sub-level.

13. The compilation method according to claim 12, further comprising: Based on the updated statement, recursively determine whether the expression remains unchanged in the loop. If so, the expression is determined to be a loop-invariant expression.

14. The compilation method according to claim 13, further comprising: The expression is determined to be a loop-invariant expression when it satisfies any of the following conditions: The initial variables in the expression are constants; The assignment of values ​​to the variables in the expression is outside the loop; The variable is used to have only one constant value, and the expression for that constant value is also cyclically invariant.

15. A computer-readable storage medium storing computer program code on which expressions in statements that normalize descriptions of neural network operators are stored, wherein when the computer program code is run by a processing device, the compilation method according to any one of claims 1 to 14 is executed.

16. A compiler for normalizing expressions in a statement, comprising: The judgment module is used to determine whether a statement can be normalized, so as to perform a merging operation on the expressions in the statement describing the neural network operator; A setting module is used to set the level of each expression according to its type, wherein the levels of the expressions include a first level for constant expressions, a second level for expressions representing nested loops, and a third level for expressions representing other expressions, wherein when the level of a nested loop expression is second level, the sub-level is set according to the loop hierarchy; and A sorting module is used to sort each expression based on the level of all expressions in the statement, to connect expressions with the same level or sub-level with operators to generate sibling expressions; and to connect all sibling expressions with operators based on the order of level or sub-level to return an updated statement, which has an equivalent effect to the original statement in the neural network operator, and is used to discover expressions that are invariant to cycles.

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