Key generation device and key generation method

Abstract

A key storage device includes a first key unit and a second key unit. The first key unit, for outputting a first logic value through a first terminal, includes a first setting circuit for outputting a first setting voltage and a first inverter including a first output transistor having a first threshold voltage for receiving the first setting voltage and generating the first logic value. The second key unit, for outputting a second logic value through a second terminal, includes a second setting circuit for outputting a second setting voltage and a second inverter including a second output transistor having a second threshold voltage for receiving the second setting voltage and generating the second logic value. An absolute value of the first threshold voltage is lower than an absolute value of the second threshold voltage. The first setting voltage is higher than the second setting voltage.

Description

Technical Field

[0001] This invention relates to a key generation apparatus and a key generation method, and more particularly to a key generation apparatus and a key generation method that can provide keys for electronic devices or circuits. Background Technology

[0002] With the advancement of technology in recent years, integrated circuits (ICs) have become increasingly important for various electronic devices. Semiconductor manufacturers often invest significant resources in IC design research and development. However, IC reverse engineering poses a serious threat to semiconductor manufacturers because it can be used by attackers to steal or copy circuit designs. Attackers who successfully reverse engineer ICs can manufacture and sell similar ICs, illegally sell IC designs, or leak IC designs. This reverse engineering can also be applied to on-chip devices.

[0003] Therefore, a mechanism is needed to provide a key for preventing reverse engineering. Summary of the Invention

[0004] One objective of this invention is to disclose a key storage device that can provide a key.

[0005] Another object of the present invention is to disclose a key generation method that can provide a key.

[0006] An embodiment of the present invention discloses a key storage device, characterized in that it includes a first key unit and a second key unit. The first key unit, used to output a first logic value through a first terminal, includes: a first setting circuit for outputting a first setting voltage; and a first inverter including a first output transistor having a first threshold voltage for receiving the first setting voltage and generating the first logic value. The second key unit, used to output a second logic value through a second terminal, includes: a second setting circuit for outputting a second setting voltage; and a second inverter including a second output transistor having a second threshold voltage for receiving the second setting voltage and generating the second logic value. The absolute value of the first threshold voltage is lower than the absolute value of the second threshold voltage. The first setting voltage is higher than the second setting voltage.

[0007] Another embodiment of the present invention discloses a key generation method, characterized by comprising: generating a first setting voltage using a first setting circuit; transmitting the first setting voltage to a first output transistor in a first inverter to generate a first logic value, wherein the first output transistor has a first threshold voltage; generating a second setting voltage using a second setting circuit; and transmitting the second setting voltage to a second output transistor in a second inverter to generate a second logic value, wherein the second output transistor has a second threshold voltage. The absolute value of the first threshold voltage is lower than the absolute value of the second threshold voltage. The first setting voltage is higher than the second setting voltage.

[0008] According to the above embodiments, a mechanism for preventing reverse engineering of keys is disclosed. Such keys can be further used in other applications. Attached Figure Description

[0009] Figure 1 A block diagram of a key storage device according to an embodiment of the present invention is shown.

[0010] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 as well as Figure 9 The diagram shows a key storage device according to different embodiments of the present invention.

[0011] Figure 10 A flowchart illustrating a key generation method according to an embodiment of the present invention is provided.

[0012] The reference numerals in the attached figures are explained as follows:

[0013] 100 Key Storage Device

[0014] 901 comparator

[0015] C1 is the first capacitor, and C2 is the second capacitor.

[0016] C3 (third capacitor) C4 (fourth capacitor)

[0017] CL_1 First control line; CL_2 Second control line

[0018] IV_1 First inverter IV_2 Second inverter

[0019] IN_1 First input endpoint IN_2 Second input endpoint

[0020] KU_1 First Key Unit KU_2 Second Key Unit

[0021] L_tl First transmission line L_t2 Second transmission line

[0022] LV_1 First logical value; LV_2 Second logical value

[0023] ND_1 First endpoint ND_2 Second endpoint

[0024] ND_3 Third endpoint ND_4 Fourth endpoint

[0025] SCK_1 First setting circuit; SCK_2 Second setting circuit

[0026] T_N1 is the first setting transistor; T_N2 is the second setting transistor.

[0027] T_N3 Third NMOS T_N4 Fourth NMOS

[0028] T_P3 Third PMOS T_P4 Fourth PMOS

[0029] T_1 First transistor; T_2 Second transistor

[0030] T_3 is the third transistor, and T_4 is the fourth transistor.

[0031] T_S1 First setting transistor; T_S2 Second setting transistor

[0032] T_S3 is the third setting transistor, and T_S4 is the fourth setting transistor.

[0033] T_O1 First output transistor; T_O2 Second output transistor

[0034] T_O3 is the third output transistor, and T_O4 is the fourth output transistor.

[0035] V_S1 First set voltage V_S2 Second set voltage

[0036] V_th1 First critical voltage V_th2 Second critical voltage

[0037] V_th3 Third critical voltage V_th4 Fourth critical voltage

[0038] V_P Predetermined voltage

[0039] V_a1 voltage

[0040] V1 First Voltage

[0041] V2 Second Voltage

[0042] VDD First Supply Voltage Detailed Implementation

[0043] The present invention will be described below with reference to several embodiments. It should be noted that the elements in each embodiment can be implemented by hardware (e.g., devices or circuits) or firmware (e.g., at least one program written in a microprocessor). Furthermore, the terms "first," "second," and similar descriptions in the following description are only used to define different elements, parameters, data, signals, or steps, and are not intended to limit their order. For example, the first device and the second device can be devices with the same structure but different from each other.

[0044] Furthermore, the circuits in the following embodiments include transistors, and NMOS and PMOS are used as examples. Please note that in the following embodiments, the description of "first threshold voltage is lower than second threshold voltage" for NMOS or transistors with similar polarity means "first threshold voltage is lower than second threshold voltage" and "the absolute value of the first threshold voltage is lower than the absolute value of the second threshold voltage." However, for PMOS or transistors with similar polarity, "first threshold voltage is lower than second threshold voltage" means "the absolute value of the first threshold voltage is lower than the absolute value of the second threshold voltage." The definition of transistor threshold voltage is well known to those skilled in the art and will not be elaborated upon here.

[0045] Furthermore, the “key” described below can be set in an IC or chip and can be used to prevent reverse engineering. However, the key can be used in any other type of electronic device and can have other applications, such as, but not limited to, authentication, encoding data, or decoding data. Figure 1 A block diagram of a key storage device 100 according to an embodiment of the present invention is shown. Figure 1 As shown, the key storage device 100 includes a first key unit KU_1 and a second key unit KU_2. Note that the key storage device disclosed in this invention may include other numbers of key units, and is not limited to two. These key units can be implemented using circuitry.

[0046] The first key unit KU_1 outputs a first logic value LV_1 through a first terminal ND_1 and includes a first setting circuit SCK_1 and a first inverter IV_1. The first setting circuit SCK_1 is used to output a first setting voltage V_S1. The first inverter IV_1 is used to receive the first setting voltage V_S1 and generate the first logic value LV_1. In one embodiment, the first inverter IV_1 includes a first output transistor having a first threshold voltage. The first output transistor is used to receive the first setting voltage V_S1 and generate the first logic value LV_1. Details of the first output transistor will be described later.

[0047] Similarly, the second key unit KU_2 outputs a second logic value LV_2 through a second terminal ND_2 and includes a second setting circuit SCK_2 and a second inverter IV_2. The first logic value LV_1 and the second logic value LV_2 can be used to generate the aforementioned "key". The second setting circuit SCK_2 outputs a second setting voltage V_S2. The second inverter IV_2 receives the second setting voltage V_S2 and generates the second logic value LV_2. In one embodiment, the second inverter IV_2 includes a second output transistor with a second threshold voltage. The second output transistor receives the second setting voltage V_S2 and generates the second logic value LV_2. Details regarding the second output transistor will be described later. The aforementioned first and second output transistors can be NMOS or PMOS.

[0048] The first critical voltage is lower than the second critical voltage. Furthermore, in Figure 2 and Figure 3 In one embodiment, the first set voltage V_S1 is higher than the second set voltage V_S2.

[0049] In the following description, several embodiments are disclosed to explain the concept of the invention. It should also be noted that, for simplicity, some ends or endpoints are not shown in the corresponding figures in the following description, but they can be clearly identified from the drawings and related descriptions. Furthermore, in the following embodiments, except... Figure 4 In addition to the embodiments described above, the first logic value LV_1 is low (e.g., 0) and the second logic value LV_2 is high (e.g., 1).

[0050] Figure 2 The illustrated embodiment is Figure 1 An example of the detailed circuitry for the first key unit KU_1 in the example. Figure 2The first setting circuit SCK_1 includes at least one setting stage (two setting stages in this embodiment). Each setting stage includes a control terminal that receives a predetermined voltage V_P and generates a first setting voltage V_S1 based on the predetermined voltage V_P. For example, the first setting transistor T_S1 in the first setting circuit SCK_1 serves as a setting stage, and its control terminal (gate) receives the predetermined voltage V_P. Furthermore, in this example, the predetermined voltage V_P is reduced by a first threshold voltage V_th1 through the first setting transistor T_S1 to generate voltage V_a1. Additionally, voltage V_a1 is reduced by the first threshold voltage V_th1 through the third setting transistor T_S3 in the first setting circuit SCK_1 to generate the first setting voltage V_S1. However, the first setting circuit SCK_1 may include only one setting stage, for example, without the third setting transistor T_S3. In this example, the first setting transistor T_S1 has a control terminal (gate) that receives the predetermined voltage V_P and generates voltage V_a1 as the first setting voltage V_S1. In one embodiment, the predetermined voltage V_P is equal to the first supply voltage VDD.

[0051] Figure 3 The illustrated embodiment is Figure 1 An example of the detailed circuitry for the second key unit KU_2 in the example. Figure 3 The second key unit KU_2 in the middle has the same as Figure 2 The circuit is similar to the first key unit KU_1 in the example. More specifically, Figure 3 The second setting circuit SCK_2 includes at least one setting stage. The setting stage includes a control terminal and receives a predetermined voltage V_P and generates a second setting voltage V_S2 based on the predetermined voltage V_P. For example, in... Figure 3 In this embodiment, the second setting transistor T_S2 in the second setting voltage V_S2 serves as the setting stage, and its control terminal (gate) receives the predetermined voltage V_P. Furthermore, in this example, the predetermined voltage V_P is reduced by a second threshold voltage V_th2 through the second setting transistor T_S2 to generate voltage V_a2. Additionally, the voltage V_a2 is reduced by a second threshold voltage V_th2 through the fourth setting transistor T_S4 in the second setting circuit SCK_2 to generate the second setting voltage V_S2. However, the second setting circuit SCK_2 may include only one setting stage, such as... Figure 2 As described in the description.

[0052] Please note that the number of setting stages in the first setting circuit SCK_1 is not limited to 1 or 2. Therefore, according to the above description, the first setting circuit SCK_1 and the second setting circuit SCK_2 can each include multiple setting stages, where each setting stage includes a setting transistor. The setting transistor of the first stage in the setting stage (e.g., Figure 2The gate of the first setting transistor (T_S1) receives a predetermined voltage V_P, and the source of the first-stage setting transistor is coupled to the gate of the next-stage setting transistor (e.g., Figure 2 The third setting transistor T_S3 in the middle. The last stage setting transistor (e.g., Figure 2 The gate of the third setting transistor (T_S3) is coupled to the setting transistor of the previous stage (e.g., Figure 2 The source of the first setting transistor T_S1 in the circuit is used to output either the first setting voltage V_S1 or the second setting voltage V_S2. The second setting circuit SCK_2 follows the same rule.

[0053] exist Figure 2 In this circuit, the first inverter IV_1 includes the aforementioned first output transistor T_O1 and third output transistor T_O3. Furthermore, in... Figure 3 In this circuit, the second inverter IV_2 further includes the aforementioned second output transistor T_O2 and fourth output transistor T_O4. The third output transistor T_O3 has a third threshold voltage V_th3 and includes a first terminal coupled to the first supply voltage VDD, a second terminal coupled to the first terminal ND_1, and a control terminal for receiving a first set voltage V_S1. The fourth output transistor T_O4 has a fourth threshold voltage V_th4 and includes a first terminal coupled to the first supply voltage VDD, a second terminal coupled to the second terminal ND_2, and a control terminal for receiving a second set voltage V_S2.

[0054] In one embodiment, the third critical voltage V_th3 is equal to or higher than the fourth critical voltage V_th4. In another embodiment, the third critical voltage V_th3 is equal to or higher than the first critical voltage V_th1, and the fourth critical voltage V_th4 is equal to or lower than the second critical voltage V_th2. The voltage levels of the critical voltages can be set using various methods. In one embodiment, the voltage levels of the critical voltages are set by providing different doping concentrations of ions to different transistors. Because doping concentrations are difficult to analyze through reverse engineering, attackers attempting to pirate circuit designs may see that the circuitry in an IC has the same physical circuit architecture and layout, but cannot know the doping concentrations, and therefore they still cannot successfully replicate the IC.

[0055] Please refer to this again. Figure 2 and Figure 3The first output transistor T_O1 includes a first terminal coupled to a first endpoint ND_1, a second terminal coupled to a second supply voltage (ground potential in this example), and a control terminal for receiving a first set voltage V_S1. The second output transistor T_O2 includes a first terminal coupled to a second endpoint ND_2, a second terminal coupled to a second supply voltage (ground potential in this example), and a control terminal for receiving a second set voltage V_S2.

[0056] exist Figure 2 In this embodiment, since the first setting circuit SCK_1 has a lower first threshold voltage V_th1, the first setting voltage V_S1 is high. Furthermore, the first output transistor T_O1 is an NMOS, and the third output transistor T_O3 is a PMOS. The Vsg of the third output transistor T_O3 is equal to the first voltage difference between the first supply voltage VDD and the first setting voltage V_S1. Furthermore, the Vgs of the first output transistor T_O1 is equal to the second voltage difference between the first setting voltage V_S1 and the second supply voltage GND. Therefore, since the first setting voltage V_S1 is high, the second voltage difference is greater than the first voltage difference. In this case, because the absolute value of the third threshold voltage V_th3 is equal to or higher than the first threshold voltage V_th1, the difference between the absolute values ​​of the first voltage difference and the third threshold voltage V_th3 is less than the difference between the second voltage difference and the first threshold voltage V_th1 (i.e., (VDD-V_S1)-|V_th3|<(V_S1-0)-Vth1). Therefore, in the non-steady state, the first output transistor T_O1 will output a larger current, while the third output transistor T_O3 will output a smaller current. When the first key unit KU_1 enters the steady state, the current flowing through the first output transistor T_O1 and the third output transistor T_O3 will become the same.

[0057] The differences between the first voltage difference and the third critical voltage V_th3, and the differences between the second voltage difference and the first critical voltage V_th1, correspond to the resistances of the first output transistor T_O1 and the third output transistor T_O3. Therefore, Figure 2 The embodiment can be represented as follows: Since the first threshold voltage V_th1 of the first setting circuit SCK_1 is low, the first setting voltage V_S1 is high, therefore the third output transistor T_O3 has a high resistance and the first output transistor T_O1 has a low resistance. Thus, the first logic value LV_1 will be low because the voltage VDD is divided by the first output transistor T_O1 and the third output transistor T_O3.

[0058] Figure 3 The second inverter IV_2 in the circuit has the opposite operation. Figure 3In this embodiment, since the second setting circuit SCK_2 has a higher second threshold voltage V_th2, the second setting voltage V_S2 is low. Furthermore, the second output transistor T_O2 is an NMOS, and the fourth output transistor T_O4 is a PMOS. The Vsg of the fourth output transistor T_O4 is equal to the third voltage difference between the first supply voltage VDD and the second setting voltage V_S2, while the Vgs of the second output transistor T_O2 is equal to the fourth voltage difference between the second setting voltage V_S2 and the second supply voltage GND. Therefore, since the second setting voltage V_S2 is low, the fourth voltage difference is less than the third voltage difference. In this case, because the fourth threshold voltage V_th4 is equal to or lower than the second threshold voltage V_th2, the difference between the third voltage difference and the fourth threshold voltage V_th4 is greater than the difference between the fourth voltage difference and the second threshold voltage V_th2 (i.e., (VDD-V_S2)-|V_th4|>(V_S2-0))-Vth2). Therefore, in the non-steady state, the fourth output transistor T_O4 outputs a larger current, while the second output transistor T_O2 outputs a smaller current. When the second key unit KU_2 enters the steady state, the current flowing through the second output transistor T_O2 and the current flowing through the fourth output transistor T_O4 will become the same.

[0059] The differences between the third voltage difference and the fourth critical voltage V_th4, and between the fourth voltage difference and the second critical voltage V_th2, correspond to the resistances of the second output transistor T_O2 and the fourth output transistor T_O4. Therefore, Figure 3 The embodiment can be described as follows: Because the second threshold voltage V_th2 of the second setting circuit SCK_2 is high, and the second setting voltage V_S2 is low, the fourth output transistor T_O4 has a low resistance, and the second output transistor T_O1 has a high resistance. Thus, the second logic value LV_2 will be high due to the voltage division operation of the second output transistor T_O2 and the fourth output transistor T_O4 on the voltage VDD. Furthermore, in Figure 2 and Figure 3 In one embodiment, the resistance (first resistance) of the first output transistor T_O1 is lower than the resistance (second resistance) of the second output transistor T_O2.

[0060] As mentioned above, in Figure 2 , Figure 3 In this embodiment, the setting transistors in the first setting circuit SCK_1 and the second setting circuit SCK_2 are NMOS. Therefore, the setting stages of the first setting circuit SCK_1 and the second setting circuit SCK_2 will progressively decrease the predetermined voltage V_P. Therefore, according to Figure 2 and Figure 3As shown in the rules, the first set voltage V_S1 is high, the second set voltage V_S2 is low, the first logic value LV_1 is low, and the second logic value LV_2 is high.

[0061] However, in another embodiment, the setting transistor in the setting phase can be replaced by a PMOS. Figure 4 This is a circuit diagram of a key storage device according to another embodiment of the present invention. Figure 4 As shown, the first setting transistor T_S1 and the third setting transistor T_S3 are PMOS transistors with a first threshold voltage V_th1, the first output transistor T_O1 is a PMOS transistor with a first threshold voltage V_th1, and the third output transistor T_O3 is an NMOS transistor with a third threshold voltage V_th3. Furthermore, Figure 4 The connection of the first setting transistor T_S1 and the third setting transistor T_S3 in the middle Figure 2 The differences.

[0062] Figure 3 The second setting transistor T_S2 and the fourth setting transistor T_S4 of the second key unit KU_2 can also be configured according to... Figure 4 The rules shown are replaced with PMOS. However, in such an example, the second setting transistor T_S2 and the fourth setting transistor T_S4 have a fourth threshold voltage V_th4, the second output transistor T_O2 is a PMOS with a second threshold voltage V_th2, and the fourth output transistor T_O4 is an NMOS with a fourth threshold voltage V_th4. In the embodiment where the setting transistors are replaced with PMOS, the setting stages of the first setting circuit SCK_1 and the second setting circuit SCK_2 increase by a predetermined voltage step by step. As mentioned above, the first threshold voltage V_th1 is lower than the second threshold voltage V_th2. Thus, in the embodiment where the setting transistors and output transistors are replaced with PMOS, the first setting voltage V_S1 is lower, while the second setting voltage V_S2 is higher. Therefore, according to Figure 2 and Figure 3 As shown in the rule, the first logical value LV_1 is high, and the second logical value LV_2 is low.

[0063] As mentioned above, Figure 2 , Figure 3 and Figure 4 In one embodiment, the first terminal ND_1 and the second terminal ND_2 are pulled up or pulled down by the current difference flowing through the first inverter IV_1 or the second inverter IV_2. In another embodiment, an inverter may also be present at the first terminal ND_1 or the second terminal ND_2 to enhance the voltage transition at the first terminal ND_1 and the second terminal ND_2. In other words, the voltage difference between logic high and logic low can be increased.

[0064] Figure 1 The first setting circuit SCK_1 and the second setting circuit SCK_2 can have other circuits, and are not limited to them. Figure 2 , Figure 3 and Figure 4 The circuit shown. Figure 5 and Figure 6 This is a circuit diagram of a key storage device according to different embodiments of the present invention. Figure 5 and Figure 6 The circuitry in this structure can be called an SRAM-like (static random access) structure. Figure 5 In the circuit, the first setting circuit SCK_1 is the third inverter IV_3. Additionally, in... Figure 6 In this circuit, the second setting circuit SCK_2 is the fourth inverter IV_4. The third inverter IV3 includes a first setting transistor T_N1 having a second threshold voltage V_th2, and includes a first input terminal IN_1 coupled to the first terminal ND_1. The third inverter IV3 is used to output a first setting voltage V_S1, which is higher than half of the first supply voltage VDD, to the first inverter IV_1 through the third terminal ND_3. The fourth inverter IV4 includes a second setting transistor T_N2 having a first threshold voltage V_th1, and includes a second input terminal IN_2 coupled to the second terminal ND_2. The fourth inverter IV4 is used to output a second setting voltage V_S2, which is lower than half of the first supply voltage VDD, to the second inverter IV2 through the fourth terminal ND_4. Figure 5 , Figure 6 In this embodiment, the first setting transistor T_N1 and the second setting transistor TN_2 are NMOS. Figure 5 In one embodiment, the third output transistor T_O3 is a first PMOS having a third threshold voltage V_th3, including a drain coupled to the first terminal ND_1 and a gate coupled to the third terminal ND_3. In the same embodiment, the third inverter IV_3 further includes a third PMOS T_P3 having a fourth threshold voltage V_th4, including a drain coupled to the third terminal ND_3 and a gate coupled to the first input terminal ND_1.

[0065] In addition, Figure 6In one embodiment, the fourth output transistor T_O4 is a second PMOS having a fourth threshold voltage V_th4, including a drain coupled to the second terminal ND_2 and a gate coupled to the fourth terminal ND_4. In the same embodiment, the fourth output transistor T_O4 includes a fourth PMOS T_P4 having a third threshold voltage V_th3, including a drain coupled to the fourth terminal ND_4 and a gate coupled to the second input terminal ND_2. The absolute value of the fourth threshold voltage V_th4 is lower than the absolute value of the third threshold voltage V_th3. That is, the threshold voltage of the third PMOS T_P3 is lower than the threshold voltage of the fourth PMOS T_P4. Furthermore, in one embodiment, the third threshold voltage V_th3 is equal to or higher than the first threshold voltage V_th1, the fourth threshold voltage V_th4 is equal to or lower than the second threshold voltage V_th2, and the first threshold voltage V_th1 is lower than the second threshold voltage V_th2.

[0066] Figure 7 and Figure 8 These are circuit diagrams of key storage devices according to different embodiments of the present invention. Figure 7 In the embodiment, the circuitry and threshold voltage of the first inverter IV_1 are related to... Figure 2 The first inverter IV_1 is the same as described above, and will not be repeated here. In the same embodiment, the first setting circuit SCK_1 includes a third NMOS T_N3 and a third PMOS T_P3. The third NMOS T_N3 has a second threshold voltage V_th2 and includes a drain that outputs the first setting voltage V_S1 through the third terminal ND_3. The third PMOS T_P3 has a fourth threshold voltage V_th4. The drain and gate of the third NMOS T_N3 are short-circuited with the drain and gate of the third PMOS T_P3. In other words, the first input terminal IN_1 of the first inverter IV_1 is connected to the third terminal ND_3.

[0067] In addition, Figure 8 In the embodiment, the circuitry and threshold voltage of the second inverter IV_2 are related to... Figure 3 The second inverter IV_2 is the same as that described above, and will not be repeated here. In the same embodiment, the second setting circuit SCK_2 includes a fourth NMOS T_N4 and a fourth PMOS T_TP4. The fourth NMOS T_N4 has a first threshold voltage V_th1 and includes a drain that outputs a second setting voltage V_S2. The fourth PMOS T_P4 has a third threshold voltage V_th3. The drain and gate of the fourth NMOS T_N4 are short-circuited with the drain and gate of the fourth PMOS T_P4. That is, the second input terminal IN_2 of the second inverter IV_2 is connected to the fourth terminal ND_4.

[0068] The absolute value of the fourth threshold voltage V_th4 is lower than the absolute value of the third threshold voltage V_th3. That is, the threshold voltage of the fourth PMOS T_P4 is lower than the threshold voltage of the third PMOS T_P3. Furthermore, in one embodiment, the third threshold voltage V_th3 is equal to or higher than the first threshold voltage V_th1, the fourth threshold voltage V_th4 is equal to or lower than the second threshold voltage V_th2, and the first threshold voltage V_th1 is lower than the second threshold voltage V_th2.

[0069] exist Figure 2 , Figure 3 , Figure 4 In this embodiment, the predetermined voltage level V_P input to the control terminal of the setting transistor is a constant value that does not change even after a period of time. Furthermore, Figure 5 , Figure 6 , Figure 7 and Figure 8 The control terminal of the transistor in the transistor does not receive any variable signals from the outside. Therefore, in the above embodiment, after the first key unit KU_1 and the second key unit KU_2 enter a stable state, the voltage at each terminal of the components of the first key unit KU_1 and the second key unit KU_2 is a fixed value. The key unit disclosed in this invention is not limited to including... Figure 1 The setting circuit and flip-flop are shown. The key unit can be implemented by other circuitry. Figure 9 This is a circuit diagram of a key storage device according to another embodiment of the present invention. Figure 9 The circuit shown can be called a DRAM-like structure.

[0070] like Figure 9 As shown, the first key unit KU_1 includes a first transistor T_1, a second transistor T_2, a first capacitor C1, and a second capacitor C2. The first transistor T_1 and the second transistor T_2 each include a first terminal, a second terminal, and a control terminal. The first terminal is coupled to one end of the first capacitor C1 and the second capacitor C2, respectively. The second terminal is coupled to the first transmission line L_t1 and the second transmission line L_t2, respectively. The control terminal is coupled to the first control line CL_1. The other ends of the first capacitor C1 and the second capacitor C2 are coupled to ground. The first transmission line L_t1 and the second transmission line L_t2 can be referred to as bit lines. The first transistor T_1, having a first threshold voltage V_th1, is used to charge the first capacitor C1 in a first mode according to the control voltage provided by the first control line CL_1 and the first charging voltage provided by the first transmission line L_t1. The first mode can be referred to as the pre-charge mode. The second transistor T_2, having a second threshold voltage V_th2, is used to charge the second capacitor C2 in the first mode according to the control voltage provided by the first control line CL_1 and the second charging voltage provided by the second transmission line L_t2.

[0071] Comparator 901 is used to compare the first voltage V1 of the first capacitor C1 and the second voltage V2 of the second capacitor C2 via the first transmission line L_t1 and the second transmission line L_t2, and output the comparison result in a second mode. The second mode can be called the readout mode.

[0072] In one embodiment, after pre-charging the first capacitor C1 and the second capacitor C2 in the first mode, the first key unit KU_1 will further operate in a third mode, which follows the first mode and precedes the second mode. The third mode can be referred to as the idle mode.

[0073] In one embodiment, the first transmission line L_t1 and the second transmission line L_t2 provide the supply voltage VDD in the first mode, and the first transmission line L_t1 and the second transmission line L_t2 provide 0 voltage (i.e., ground) in the third mode. Furthermore, in the second mode, the first transmission line L_t1 and the second transmission line L_t2 do not provide voltage. In this case, the voltage of the first transmission line L_t1 corresponds to the voltage of the first capacitor C1 and the third capacitor C3, and the voltage of the second transmission line L_t2 corresponds to the voltage of the second capacitor C2 and the fourth capacitor C4.

[0074] Furthermore, in one embodiment, the voltage provided by the first control line CL_1 and the second control line CL_2 in the first and second modes is the supply voltage VDD, and the voltage provided by the first transmission line L_tl and the second transmission line L_t2 in the third mode is 0 (i.e., grounded).

[0075] In the third mode, the control voltage is set to the turn-off voltage of the first transistor T_1 and the second transistor T_2. However, in the third mode, the first transistor T_1 may still have leakage current flowing from the first capacitor C1 to the first transmission line L_t1. Similarly, the second transistor T_2 may still have leakage current flowing from the second capacitor C2 to the second transmission line L_t2.

[0076] As described in the above embodiment, the first threshold voltage V_th1 is lower than the second threshold voltage V_th2, so the leakage current of the first transistor T_1 is greater than the leakage current of the second transistor T_2. Therefore, in the third mode, the first voltage V1 is lower than the second voltage V2, causing the comparator 901 to output a first logic value (0 in this embodiment).

[0077] In addition, Figure 9In this embodiment, the second key unit KU_2 includes a third transistor T_3, a fourth transistor T_4, a third capacitor C3, and a fourth capacitor C4. The circuit connection and operation of the second key unit KU_2 are similar to those of the first key unit KU_1. However, the third transistor T_3 has a third threshold voltage V_th3, and the fourth transistor T_4 has a fourth threshold voltage V_th4, which is lower than the third threshold voltage V_th3. Therefore, the leakage current of the third transistor T_3 is less than the leakage current of the fourth transistor T_4. Thus, when the comparator reads the capacitors in the second key unit KU_2 in the third mode, the first voltage V1 transmitted by the third capacitor C3 is greater than the second voltage V2 transmitted by the fourth capacitor C4, causing the comparator 901 to output a second logic value (1 in this embodiment). In one embodiment, the first threshold voltage V_th1 is equal to the fourth threshold voltage V_th4, and the second threshold voltage V_th2 is equal to the third threshold voltage V_th3.

[0078] In one embodiment, the first key unit KU_1 and the second key unit KU_2 switch to the second mode instead of the third mode after the first mode is completed. That is, the first key unit KU_1 and the second key unit KU_2 are read after being pre-charged, instead of entering idle mode. In this case, because the first transistor T_1 has a lower threshold voltage, the current from the first transistor T_1 is greater than the current from the second transistor T_2. Thus, the first voltage V1 increases faster than the second voltage V2, so the first voltage V1 will be higher than the second voltage V2. Therefore, in such an embodiment, the comparator 901 will output a second logic value (1 in this embodiment) in the third mode. Following the same rule, when the comparator 901 reads the voltage of the third capacitor C3 and the fourth capacitor C4 in the third mode, it will output a first logic value (0 in this embodiment).

[0079] Please note that, for ease of explanation, Figure 9 In the embodiments described, the first transmission line L_t1 and the second transmission line L_t2 are adjacent, and the first control line CL_1 and the second control line CL_2 are adjacent. However, this does not limit the scope of the invention to such a configuration. The transmission lines can be configured as the first transmission line L_t1 and the second transmission line L_t2 by providing a voltage to them. That is, at least one transmission line or any other wire may exist between the first transmission line L_t1 and the second transmission line L_t2. Similarly, at least one transmission line or any other wire may exist between the first control line CL_1 and the second control line CL_2.

[0080] Please note that the above embodiments can be used in combination. For example, Figure 2 , Figure 3 and Figure 5The illustrated embodiment can be applied as a key unit in an IC. Furthermore, according to the above embodiment, the first key unit KU_1 and the second key unit KU_2 have the same physical circuit architecture, but because the transistors in the first key unit KU_1 and the second key unit KU_2 have different threshold voltages, the first key unit KU_1 and the second key unit KU_2 will output different logic values ​​when operating under the same supply voltages VDD and GND. For example, in Figure 2 and Figure 3 In this configuration, the first key unit KU_1 and the second key unit KU_2 have the same physical circuit architecture. Both the first key unit KU_1 and the second key unit KU_2 receive a predetermined voltage V_P and operate under a first supply voltage VDD and a second supply voltage GND. However, due to the different threshold voltages of the transistors, the first key unit KU_1 outputs a logic value of 0 while the second key unit KU_2 outputs a logic value of 1.

[0081] In one embodiment, an error detection mechanism can be provided to improve the stability of the key stored in the key unit. For example, the BCH (Bose Chaudhuri Hocquenghem) code can be used for key error detection. Furthermore, a majority voting mechanism can also be used to improve key stability.

[0082] Based on the foregoing embodiments, a key generation method can be obtained. Figure 10 This is a flowchart of a key generation method according to an embodiment of the present invention, corresponding to... Figure 1 The illustrated embodiment includes the following steps:

[0083] Step 1001

[0084] The first setting voltage V_S1 is generated by the first setting circuit SCK_1.

[0085] Step 1003

[0086] A first set voltage V_Sl is transmitted to the first output transistor in the first inverter IV_l to generate a first logic value LV_l, wherein the first output transistor has a first threshold voltage V_thl.

[0087] Step 1005

[0088] The second setting voltage V_S2 is generated by the second setting circuit SCK_2.

[0089] Step 1007

[0090] The second set voltage V_S2 is transmitted to the second output transistor in the second inverter IV_2 to generate the second logic value LV_2, wherein the second output transistor has a second threshold voltage V_th2.

[0091] The first critical voltage V_th1 is lower than the second critical voltage V_th2, and the first set voltage V_S1 is higher than the second set voltage V_S2. Other detailed steps can be found in the above description and will not be repeated here.

[0092] According to the above embodiments, a mechanism for preventing reverse engineering of keys is disclosed. Such keys can be further used in other applications.

[0093] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A key storage device, characterized by, include: The first key unit, used to output a first logical value through a first endpoint, includes: A first setting circuit is used to output a first setting voltage; and A first inverter includes a first output transistor having a first threshold voltage for receiving the first set voltage and generating the first logic value; and The second key unit, used to output a second logical value through a second endpoint, includes: A second setting circuit is used to output a second setting voltage; and The second inverter includes a second output transistor having a second threshold voltage for receiving the second set voltage and generating the second logic value. The absolute value of the first critical voltage is lower than the absolute value of the second critical voltage; Wherein the first set voltage is higher than the second set voltage; The first setting circuit and the second setting circuit each include a setting level; The setting stage includes a control terminal for receiving a predetermined voltage, and the setting stage is used to generate the first setting voltage and the second setting voltage according to the predetermined voltage; The setting stage of the first setting circuit includes a first setting transistor having the first threshold voltage, and the setting stage of the second setting circuit includes a second setting transistor having the second threshold voltage. The first inverter further includes a third output transistor having a third threshold voltage, and includes a first terminal coupled to a first supply voltage, a second terminal coupled to the first terminal, and a control terminal receiving the first set voltage. The second inverter further includes a fourth output transistor having a fourth threshold voltage, and includes a first terminal coupled to the first supply voltage, a second terminal coupled to the second terminal, and a control terminal receiving the second set voltage. The first output transistor includes a first terminal coupled to the first endpoint, a second terminal coupled to the second supply voltage, and a control terminal that receives the first set voltage. The difference between the first supply voltage and the first set voltage is the first voltage difference, and the difference between the second supply voltage and the first set voltage is the second voltage difference; The difference between the absolute values ​​of the first voltage difference and the third critical voltage is smaller than the difference between the absolute values ​​of the second voltage difference and the first critical voltage.

2. The key storage device as described in claim 1, characterized in that, The first resistance value of the first output transistor is lower than the second resistance value of the second output transistor.

3. The key storage device as described in claim 1, characterized in that, The second output transistor includes a first terminal coupled to the second endpoint, a second terminal coupled to the second supply voltage, and a control terminal that receives the second set voltage. The difference between the first supply voltage and the second set voltage is the third voltage difference, and the difference between the second supply voltage and the second set voltage is the fourth voltage difference; The difference between the absolute values ​​of the third voltage difference and the fourth critical voltage is greater than the difference between the absolute values ​​of the fourth voltage difference and the second critical voltage.

4. The key storage device as described in claim 1, characterized in that, The absolute value of the third critical voltage is equal to or higher than the absolute value of the fourth critical voltage.

5. The key storage device as described in claim 1, characterized in that, The absolute value of the third critical voltage is equal to or higher than the absolute value of the first critical voltage, and the absolute value of the fourth critical voltage is equal to or lower than the absolute value of the second critical voltage.

6. The key storage device as claimed in claim 1, characterized in that, The first setting transistor, the second setting transistor, the first output transistor, and the second output transistor are all NMOS transistors. The predetermined voltage is progressively reduced in the setting stage of the first setting circuit and the setting stage of the second setting circuit. The first logic value is low and the second logic value is high.

7. The key storage device as claimed in claim 1, characterized in that, The first setting transistor, the second setting transistor, the first output transistor, and the second output transistor are all NMOS transistors. The predetermined voltage is increased step by step in the setting stage of the first setting circuit and the setting stage of the second setting circuit. The first logic value is high and the second logic value is low.

8. The key storage device as claimed in claim 1, characterized in that, The first output transistor and the second output transistor are NMOS, the first inverter further includes a first PMOS having a third threshold voltage, and the second inverter includes a second PMOS having a fourth threshold voltage. The first setting circuit includes: A third NMOS, having the second threshold voltage, includes a drain for outputting the first set voltage; and The third PMOS has this fourth threshold voltage; The drain and gate of the third NMOS are short-circuited with the drain and gate of the third PMOS; the second setting circuit includes: A fourth NMOS, having the first threshold voltage, includes a drain for outputting the second set voltage; and The fourth PMOS has this third threshold voltage; The drain and gate of the fourth NMOS are short-circuited with the drain and gate of the fourth PMOS; and the absolute value of the fourth threshold voltage is lower than the absolute value of the third threshold voltage.

9. The key storage device as claimed in claim 1, characterized in that, The voltage at each end of the components of the first key unit and the second key unit is a fixed value.

10. The key storage device as claimed in claim 1, characterized in that, The first key unit and the second key unit have the same physical circuit architecture.

11. A key generation method, characterized in that, include: The first set voltage is generated by the first set circuit; as well as The first set voltage is transmitted to the first output transistor in the first inverter to generate a first logic value, wherein the first output transistor has a first threshold voltage; The second setting circuit generates the second setting voltage; as well as The second set voltage is transmitted to the second output transistor in the second inverter to generate a second logic value, wherein the second output transistor has a second threshold voltage; The absolute value of the first critical voltage is lower than the absolute value of the second critical voltage; Wherein the first set voltage is higher than the second set voltage; Where the first logic value is low and the second logic value is high; The first setting circuit and the second setting circuit each include a setting level; The key generation method includes: The setting stage progressively decreases the predetermined voltage to generate the first setting voltage and the second setting voltage, respectively.

12. A key storage device, characterized in that, include: The first key unit, used to output a first logical value through a first endpoint, includes: A first setting circuit is used to output a first setting voltage; and A first inverter includes a first output transistor having a first threshold voltage for receiving the first set voltage and generating the first logic value; and The second key unit, used to output a second logical value through a second endpoint, includes: A second setting circuit is used to output a second setting voltage; and The second inverter includes a second output transistor having a second threshold voltage for receiving the second set voltage and generating the second logic value. The absolute value of the first critical voltage is lower than the absolute value of the second critical voltage; Wherein the first set voltage is higher than the second set voltage; The first output transistor and the second output transistor are NMOS, the first inverter further includes a first PMOS having a third threshold voltage, and the second inverter includes a second PMOS having a fourth threshold voltage. The first setting circuit includes: A third NMOS, having the second threshold voltage, includes a drain for outputting the first set voltage; and The third PMOS has this fourth threshold voltage; The drain and gate of the third NMOS are short-circuited with the drain and gate of the third PMOS; the second setting circuit includes: A fourth NMOS, having the first threshold voltage, includes a drain for outputting the second set voltage; and The fourth PMOS has this third threshold voltage; The drain and gate of the fourth NMOS are short-circuited with the drain and gate of the fourth PMOS; and the absolute value of the fourth threshold voltage is lower than the absolute value of the third threshold voltage.

13. A key generation method, characterized in that, include: The first set voltage is generated by the first set circuit; as well as The first set voltage is transmitted to the first output transistor in the first inverter to generate a first logic value, wherein the first output transistor has a first threshold voltage; The second setting circuit generates the second setting voltage; as well as The second set voltage is transmitted to the second output transistor in the second inverter to generate a second logic value, wherein the second output transistor has a second threshold voltage; The absolute value of the first critical voltage is lower than the absolute value of the second critical voltage; Wherein the first set voltage is higher than the second set voltage; Where the first logic value is high and the second logic value is low; The first setting circuit and the second setting circuit each include a setting level; The key generation method includes: The setting level increases the predetermined voltage step by step to generate the first setting voltage and the second setting voltage, respectively.

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