Chip module testing apparatus and method

Abstract

Disclosed are a chip module testing device and method. The device comprises: a storage module for storing test instructions, the test instructions comprising a plurality of test parameters, each test parameter being used to implement a different test item; a testing module for connecting a chip module and testing the chip module; a main control module connected to the storage module and the testing module, used to read the test instructions from the storage module and send the test instructions to the testing module to implement a plurality of test items, and obtain a plurality of test results corresponding to the plurality of test items; and an analysis module connected to the main control module, used to analyze the plurality of test results. The chip module testing device and method provided by the application consider multiple stages before, during and after testing, thereby providing a multi-element fault-tolerant chip module testing device.

Description

Technical Field

[0001] This invention relates to the field of chip module testing technology, and in particular to a chip module testing device and method based on multi-factor fault-tolerant processing. Background Technology

[0002] With the development of technology, chips are being used more and more widely in the field of electronic circuit technology. However, in order to achieve the expected results in chip applications, testing of chip modules has become an essential part of chip production and use.

[0003] Currently, chip module manufacturers have time-sensitive requirements for production testing systems. First-pass yield significantly impacts costs, affecting labor costs, product waste, and schedule control. The goal is to design a stable and efficient production testing system that accurately provides test results and avoids repeated testing and related problems caused by hardware changes, environmental differences, and improper operation. Summary of the Invention

[0004] In view of the above problems, the purpose of the present invention is to provide a chip module testing device and method, which takes into account multiple stages before testing, during testing and after testing, thereby providing a multi-factor fault-tolerant chip module testing device.

[0005] According to one aspect of the present invention, a chip module testing apparatus is provided, comprising: a storage module for storing test instructions, the test instructions including multiple test parameters, each test parameter being used to implement different test items; a test module for connecting to a chip module and testing the chip module; a main control module connected to the storage module and the test module, for reading test instructions from the storage module and sending them to the test module to perform multiple test items, and obtaining multiple test results corresponding to the multiple test items; and an analysis module connected to the main control module for analyzing the multiple test results, wherein, when the analysis module determines that a certain test result has an error, the main control module sends a retry signal to the test module, and the test module re-performs the test; when the analysis module determines that the number of times a certain test result has an error exceeds a threshold, the main control module sends a stop signal to the test module, suspending the test by the test module; when the test module suspends the test, the main control module sends a repair signal to the test module, and the test module performs self-repair according to the repair signal and then restarts the test.

[0006] Optionally, the storage module is connected to the analysis module and is used to store multiple test results corresponding to multiple test items, as well as the analysis results of the analysis module on the multiple test results.

[0007] Optionally, the analysis module analyzes the test results, including performing checksum verification on the test results.

[0008] Optionally, the analysis module analyzes the test results, including performing protocol checks on the test results.

[0009] Optionally, a test parameter may include multiple test data. When the analysis module determines that a certain test data is incorrect, the test module returns the first test data for testing.

[0010] Optionally, the test module includes: at least one test board connected to the chip module; and at least one control unit connected to the test board and the main control module, for receiving test parameters and signals sent by the main control module, wherein the test board performs tests according to the test parameters and signals received by the control unit.

[0011] Optionally, the test module can separate multiple chip modules into different threads based on their index numbers for testing.

[0012] Optionally, the analysis module acquires multiple test parameters before testing and determines whether its own analysis unit corresponds to the multiple test parameters. When the analysis module determines that its own analysis unit does not correspond to the multiple test parameters, the analysis module is upgraded.

[0013] Optionally, it further includes: a configuration module, connected to the storage module and the main control module, for inputting test commands to the storage module.

[0014] Optionally, the storage module records communication logs for the entire process, and the analysis module analyzes and categorizes the communication logs.

[0015] Optionally, the communication log includes descriptive information such as the date and time of the test, the test index, stage information, and the location of the failure.

[0016] Optionally, the storage module records communication data throughout the entire process, and the analysis module analyzes and categorizes the communication data.

[0017] Optionally, the main control module periodically sends monitoring signals to the chip module to determine the connection status between the chip module and the test board.

[0018] According to another aspect of the present invention, a chip module testing method is provided, comprising: connecting a testing device to at least one chip module; acquiring a test instruction and testing the chip module according to the test instruction, the test instruction including multiple test parameters, each test parameter being used to implement different test items; acquiring and analyzing test data of the chip module, wherein, when it is determined that an error has occurred in a certain test data, the chip module is retested according to a retry signal; when it is determined that the number of times a certain test data has occurred exceeds a threshold, the testing of the chip module is paused; after the testing is paused, self-repair is performed and the testing is restarted.

[0019] Optionally, the test data can be analyzed, including checking the test data for checksums.

[0020] Optionally, the test data may be analyzed, including performing protocol checks on the test data.

[0021] Optionally, a test parameter may include multiple test data. When a certain test data is determined to be incorrect, the first test data of that test parameter is returned for testing.

[0022] Optionally, when testing multiple chip modules simultaneously, the multiple chip modules can be separated into different threads for testing according to their index numbers.

[0023] Optionally, communication logs for the entire process are recorded, and the communication logs are analyzed and categorized.

[0024] Optionally, the communication log includes descriptive information such as the date and time of the test, the test index, stage information, and the location of the failure.

[0025] Optionally, the communication data for the entire process can be recorded, and the communication data can be analyzed and categorized.

[0026] Optionally, monitoring signals are periodically sent to the chip module to determine the connection status between the chip module and the test board.

[0027] The chip module testing device and method provided by this invention considers multiple stages before, during and after testing, thereby providing a multi-factor fault-tolerant chip module testing device that can reduce the low first-pass yield caused by factors other than the chip module itself, and reduce the cost of manpower, time and material resources.

[0028] The chip module testing apparatus and method provided by this invention, before testing, on the one hand, reduces the problem of low test pass rate caused by module connection errors through status monitoring; on the other hand, it reduces the problem of low test pass rate caused by different versions using the same testing method through version management.

[0029] The chip module testing device and method provided by this invention reduce the problem of low test pass rate caused by factors other than the module itself through functions such as data verification, circuit breaking mechanism, retry logic, protocol check, test rollback, self-repair and partition mode.

[0030] The chip module testing device and method provided by this invention, after testing, records the problems encountered in the module testing through functions such as log analysis, data statistics, and fault caching. After classification, the problems are upgraded and optimized to reduce the problem of low test pass rate caused by factors other than the module itself when using the module testing device in the future.

[0031] The chip module testing device and method provided by this invention perform log recording and heartbeat monitoring throughout the entire testing phase in order to record problems encountered during module testing and carry out targeted upgrades and improvements. Attached Figure Description

[0032] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0033] Figure 1 A structural diagram of a chip module testing apparatus according to an embodiment of the present invention is shown;

[0034] Figure 2 A structural diagram of a test module in a chip module testing apparatus according to an embodiment of the present invention is shown;

[0035] Figure 3 The test content of each stage of the chip module testing method according to an embodiment of the present invention is shown. Detailed Implementation

[0036] Various exemplary embodiments, features, and aspects of the present invention will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0037] In the description of this invention, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0038] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0039] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0040] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0041] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0042] Furthermore, to better illustrate the present invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the present invention can be practiced without certain specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order to highlight the spirit of the invention.

[0043] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0044] The manufacturing process of integrated circuit chips is complex and requires precision, which inevitably leads to defects. For chips with stringent reliability requirements, testing is typically required before shipment to prevent failures in circuits. However, environmental factors such as noise and temperature can interfere with the chip module during testing, resulting in a low first-pass yield.

[0045] Figure 1 A structural diagram of a chip module testing apparatus according to an embodiment of the present invention is shown; Figure 2 A structural diagram of a test module in a chip module testing apparatus according to an embodiment of the present invention is shown; Figure 3 The test contents of each stage of the chip module testing apparatus according to an embodiment of the present invention are shown.

[0046] refer to Figure 1 The chip module testing device 100 of this application includes: a main control module 110, a configuration module 120, an analysis module 130, a testing module 140, and a storage module 150. The main control module is connected to the configuration module 120, the analysis module 130, the testing module 140, and the storage module 150, respectively. The storage module 150 is also connected to the configuration module 120 and the analysis module 130, respectively.

[0047] In this embodiment, the configuration module 120 is used to input test instructions. Each test instruction includes multiple test parameters, each used to implement different test items, and each test parameter includes multiple test data. Furthermore, for different versions of the chip module, the test instructions can be modified via the configuration module. For example, when the chip module is a touch chip, the test items may include open / short circuit tests, touch sensing tests, etc.

[0048] Storage module 150 is used to store various information such as test instructions, test results, test data, communication logs, communication data, and analysis content.

[0049] Test module 140 is used to connect to the test module and perform multiple tests on the chip module according to test commands and signals. The structure of test module 140 is as follows: Figure 2 As shown, it includes multiple test boards 141, each test board 141 including a control unit 143 and a chip module area 142 connected to at least one chip module.

[0050] The main control module 110 is used to read test instructions from the storage module 150 and send them to the test module 140, obtain test results corresponding to multiple test items of the test module 140, and send different signals to the test module 140 according to the analysis results of the analysis module 130.

[0051] The analysis module 130 is used to analyze the test results corresponding to multiple test items obtained by the main control module 110 and return the analysis results to the main control module 110.

[0052] Furthermore, before testing, the chip module testing device 100 provided in this application also includes: inputting test instructions into the storage module 150 via the configuration module 120; the analysis module 130 acquiring and analyzing the test instructions before testing; determining whether its own analysis unit corresponds to multiple test parameters of the test instructions; and upgrading the version of the analysis module 130 when the analysis module 130 determines that its own analysis unit does not correspond to multiple test parameters.

[0053] In this embodiment, the upgrade analysis module 130 includes two aspects. Firstly, due to compatibility considerations during use, the version of the chip module testing device 100 may be upgraded and modified. Therefore, before using the chip module testing device 100, it is necessary to check to ensure that its version is up-to-date, thereby reducing usage limitations. Secondly, when using the chip module testing device 100 to test chip modules, if the same chip module testing device 100 can test different chip modules or chip modules from the same series, then before using the chip module testing device 100, it is necessary to configure it through the configuration module 120 to ensure that the testing process matches the corresponding chip modules.

[0054] Furthermore, before testing, the main control module 110 sends a test signal to the test module 140, and the analysis module 130 analyzes the data returned by the test module 140 to determine whether the connection between the test module 140 and the chip module is normal. On the one hand, data analysis can be used to preliminarily determine whether there are defects in the chip module; on the other hand, the acquired data can also be used to determine whether the chip module is connected correctly.

[0055] Furthermore, during testing, the analysis module 130 analyzes the test data acquired by the main control module 110, such as for check code verification, to determine the accuracy of the data.

[0056] When the test module 140 tests the chip module according to the test parameters, if the test result returned by a certain test data in the test parameters is determined to be a test failure after analysis by the analysis module 130, the main control module 110 sends a retry signal to the test module 140, and the test module 140 retests the test data according to the retry signal.

[0057] When the test module 140 returns test results after retrying multiple times based on a certain test data, and the analysis module 130 determines that all of them are test failures, the main control module 110 sends a stop signal to the test module 140 to suspend the test module 140's test of the test data.

[0058] When test module 140 pauses testing the test data, main control module 110 sends a repair signal to test module 140. Test module 140 performs forced repair according to the repair signal, and after repair, restarts testing the test data, or starts testing from the beginning. In this embodiment, the forced repair performed by test module 140 may be, for example, forced initialization, forced power-off, or forced power-on.

[0059] In addition, during the test, the analysis module 130 also performs protocol checks based on the test results obtained by the main control module 110. Specifically, the analysis module 130 performs data sequence checks, content representation checks, and data length checks based on a specific piece of data in the test results.

[0060] Furthermore, when the test module 140 performs tests according to the test parameters, if a certain test data in a certain test parameter fails, the test needs to be rolled back to the first test data and restarted. In this embodiment, since one test parameter represents one test item, the multiple test data in that test parameter may have dependencies in terms of order, timing, or test results during testing. Therefore, if subsequent test data fails, it is necessary to roll back to the first test and retest.

[0061] Furthermore, the test module 140 includes multiple test boards 141, each test board 141 including a control unit 143 and a chip module area 142 connected to at least one chip module. When testing multiple chip modules simultaneously, the test module 140 can separate the multiple chip modules into different threads for testing according to the index number and thread ID of the test board 141, so as to avoid the impact of one chip module failing on other chip modules.

[0062] Throughout the entire testing process, the storage module 150 recorded all communication logs and data for each stage. Simultaneously, the main control module 110 periodically sent test signals to the test module 140 to determine the connection status between the chip module and the test module 140, ensuring normal communication during testing.

[0063] After testing, the analysis module 130 analyzes the communication logs throughout the entire process to determine the causes of failures and categorize them for future upgrades of the testing device. Furthermore, by analyzing the communication logs throughout the entire process, the analysis module 130 can also determine whether the same failure items exist in the same batch of chip modules, thus enabling chip module upgrades. The analysis module 130 also analyzes the communication data throughout the entire process, especially focusing on non-module factors such as noise and electrical signals, and categorizes these data for further upgrades of the testing device.

[0064] Further, refer to Figure 3 The chip module testing device 100 of this application takes into account the pre-test, during-test, and post-test processes, thereby providing a stable and efficient testing device that accurately provides test results and avoids repeated testing and related problems caused by factors such as hardware changes, environmental differences, and improper operation.

[0065] In this embodiment, the fault tolerance considerations for the entire testing process include the following:

[0066] Before testing, two aspects are involved: status monitoring and version management.

[0067] Status monitoring is used to determine whether the chip under test (DUT) is connected correctly by sending test signals and obtaining test results after the DUT is connected to the test module 140. If the obtained test results are found to be incorrect or no test results are obtained, it is necessary to check whether the connection between the DUT and the test module 140 is correct.

[0068] Version management is used to check whether the chip module testing device 100 is up-to-date and to manage the version of the chip module under test. On one hand, when using the chip module testing device 100, due to compatibility issues, version upgrades, and changes, a check is necessary before testing; if a new version is available, an upgrade should be performed to reduce usage limitations. On the other hand, after the chip module under test is connected to the testing module 140, it needs to be managed according to the version of the chip module under test to facilitate subsequent testing.

[0069] The testing process includes multiple aspects such as data validation, retry logic, circuit breaking mechanism, protocol checking, test rollback, self-healing, and partition mode.

[0070] Data verification is performed when the chip module communicates with the test board 141, verifying the communication data. This includes CRC (Cyclic Redundancy Check) and parity check. CRC is used to detect or verify errors that may occur after data transmission or storage, while parity check is used to verify the correctness of code transmission.

[0071] The retry logic performs a second test when the chip module's test result fails, in order to avoid communication errors caused by factors other than the chip module itself. During communication between the chip module and the test board 141, environmental interference such as noise may cause errors in the test results, leading to failure during data verification. Therefore, multiple retries are necessary when communication errors occur to reduce the impact of accidental environmental factors such as noise.

[0072] The circuit breaker mechanism stops communication between the chip module and the test board 141 when the number of test failures reaches a predetermined value. If communication errors between the chip module and the test board 141 continue to occur, it may be due to factors within the chip module itself, not factors outside the chip module. In such cases, multiple communication retries will not succeed. Therefore, communication between the chip module under test and the test board 141 can be stopped when the cumulative number of communication failures reaches the predetermined value.

[0073] Protocol check: Check whether the communication protocol between the chip module and test board 141 is valid.

[0074] Test rollback is used in a specific test item of a chip module where subsequent tests depend on earlier tests. When a later test fails, it's necessary to roll back to the earlier tests and re-perform the test. In this embodiment, even if only the later test fails, the cause of the failure might lie in an earlier test. Therefore, rolling back to the earlier tests and restarting the test minimizes the impact of non-chip module factors.

[0075] Self-repair: When the chip module test is halfway through and multiple measures fail to perform normal testing, it will enter forced mode for self-repair before continuing the subsequent tests.

[0076] In the partition mode, when a test board is connected to multiple chip modules, one chip module can be isolated into a single thread. This ensures that if one chip module fails, the others can continue operating. Furthermore, if the chip module testing device 100 is connected to various types of chip modules under test, the same type of chip module can be isolated into a single thread. This also ensures that if one type of chip module fails, the others can continue operating.

[0077] The testing process also includes log analysis, data statistics, and fault caching, among other things.

[0078] Log analysis involves analyzing communication logs recorded throughout the entire process to determine the cause of failure and categorize them into relevant system content, so that subsequent upgrades and optimizations can be carried out based on the cause of failure.

[0079] Data statistics and analysis of communication data during the testing process, especially noise, electrical signals and other data related to the system, can be used to upgrade and optimize the chip module testing device 100 based on relevant influencing factors.

[0080] Fault caching allows for the analysis and categorization of failed test items during the testing process, enabling workflow optimization to reduce the failure rate of subsequent tests.

[0081] In addition, the entire testing process also includes logging and heartbeat monitoring.

[0082] Log recording is used to record descriptive information such as test items, test time, test index, stage information, failure location, and number of tests throughout the entire testing process, which facilitates log analysis after the test.

[0083] Heartbeat monitoring is used to periodically check the connection status between the chip module under test and the test board to ensure normal communication services during the testing process.

[0084] The chip module testing device provided by this invention considers multiple stages before, during and after testing, thereby providing a multi-factor fault-tolerant chip module testing device that can reduce the low first-pass yield caused by factors other than the chip module itself, and reduce the cost of manpower, time and material resources.

[0085] The chip module testing device provided by this invention, before testing, reduces the problem of low test pass rate caused by module connection errors through status monitoring; and reduces the problem of low test pass rate caused by different versions using the same testing method through version management.

[0086] The chip module testing device provided by this invention reduces the problem of low test pass rate caused by factors other than the module itself through functions such as data verification, circuit breaking mechanism, retry logic, protocol check, test rollback, self-repair and partition mode.

[0087] The chip module testing device provided by this invention records the problems encountered during module testing through functions such as log analysis, data statistics, and fault caching. After classification, the problems are upgraded and optimized to reduce the problem of low test pass rate caused by factors other than the module itself when using the module testing device in the future.

[0088] The chip module testing device provided by this invention performs log recording and heartbeat monitoring throughout the entire testing phase in order to record problems encountered during module testing and carry out targeted upgrades and improvements.

[0089] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A chip module testing device, comprising: A storage module is used to store test instructions, which include multiple test parameters, each of which is used to implement different test items. The test module is used to connect to the chip module and to test the chip module. The main control module, connected to the storage module and the test module, is used to read test instructions from the storage module, send them to the test module to perform multiple test items, and obtain multiple test results corresponding to the multiple test items; The analysis module, connected to the main control module, is used to analyze multiple test results. Specifically, when the analysis module determines that a test result is incorrect, the main control module sends a retry signal to the test module, and the test module re-performs the test; when the analysis module determines that the number of times a test result is incorrect exceeds a threshold, the main control module sends a stop signal to the test module, pausing the test; after the test module pauses the test, the main control module sends a repair signal to the test module, and the test module performs self-repair based on the repair signal and then restarts the test. One of the test parameters includes multiple test data, and the multiple test data have dependencies in order, timing or test results. When the analysis module determines that a certain test result is incorrect, the test module returns the first test data for testing. The storage module records communication logs for the entire process, and the analysis module analyzes and categorizes the communication logs; the storage module also records communication data for the entire process, and the analysis module analyzes and categorizes the communication data.

2. The chip module testing apparatus according to claim 1, wherein, The storage module is connected to the analysis module and is used to store multiple test results corresponding to multiple test items, as well as the analysis results of the analysis module on the multiple test results.

3. The chip module testing apparatus according to claim 2, wherein, The analysis module analyzes the test results, including verifying the test results with a checksum.

4. The chip module testing apparatus according to claim 2, wherein, The analysis module analyzes the test results, including performing protocol checks on the test results.

5. The chip module testing apparatus according to claim 2, wherein, The testing module includes: At least one test board is connected to the chip module; At least one control unit, connected to the test board and the main control module, is used to receive test parameters and signals sent by the main control module. The test board performs tests based on the test parameters and signals received by the control unit.

6. The chip module testing apparatus according to claim 5, wherein, The testing module separates multiple chip modules into different threads based on their index numbers for chip module testing.

7. The chip module testing apparatus according to claim 1, wherein, Before testing, the analysis module acquires multiple test parameters and determines whether its own analysis unit corresponds to these parameters. When the analysis module determines that its analysis unit does not correspond to multiple test parameters, the analysis module is upgraded.

8. The chip module testing apparatus according to claim 1, wherein, Also includes: The configuration module, connected to the storage module and the main control module, is used to input test commands to the storage module.

9. The chip module testing apparatus according to claim 1, wherein, The communication log includes: the date and time of the test, the test index, the stage information, and a description of the failure location.

10. The chip module testing apparatus according to claim 1, wherein, The main control module periodically sends monitoring signals to the chip module to determine the connection status between the chip module and the test board.

11. A chip module testing method, comprising: Connect the test device to at least one chip module; The chip module is tested according to the test instructions. The test instructions include multiple test parameters, each of which is used to implement different test items. Acquire and analyze the test data of the chip module. Specifically, when an error is detected in a certain test data, the chip module is retested based on the retry signal; when the number of errors in a certain test data exceeds a threshold, the chip module test is paused; after the test is paused, it performs self-repair and then restarts the test. One of the test parameters includes multiple test data, and the multiple test data are dependent on each other in terms of order, timing or test results. When it is determined that an error has occurred in a certain test result, the first test data of the test parameter is returned for testing. Record communication logs for the entire process, analyze and categorize the communication logs; and record communication data for the entire process, analyze and categorize the communication data.

12. The chip module testing method according to claim 11, wherein, The test data is analyzed, including the verification of the test data using checksums.

13. The chip module testing method according to claim 11, wherein, Analyze the test data, including performing protocol checks on the test data.

14. The chip module testing method according to claim 11, wherein, When testing multiple chip modules simultaneously, the chip modules are separated into different threads for testing based on their index numbers.

15. The chip module testing method according to claim 11, wherein, The communication log includes: the date and time of the test, the test index, the stage information, and a description of the failure location.

16. The chip module testing method according to claim 11, wherein, Monitoring signals are periodically sent to the chip module to determine the connection status between the chip module and the test board.

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