NMOS super source follower low dropout regulator

Abstract

The present disclosure relates to NMOS super source follower low dropout regulators. Embodiments disclosed herein relate to a low dropout regulator, and more particularly to improving the power supply rejection ratio (PSRR) of the low dropout regulator. Low dropout regulators can be used to generate various voltages for integrated circuits of electronic devices. In some cases, a P-type metal-oxide-semiconductor (PMOS) low dropout (LDO) regulator can be used. However, a PMOS LDO can not provide sufficient PSRR or reduction of power supply noise. To address these issues, an N-type metal-oxide-semiconductor (NMOS) LDO regulator with an NMOS pass transistor can be used. An NMOS LDO can provide lower impedance than a PMOS LDO. Furthermore, an NMOS LDO can provide increased bandwidth and consume less physical area than a PMOS LDO.

Description

Technical Field

[0001] This disclosure relates in general to wireless communication, and more specifically to voltage regulators in wireless communication devices. Background Technology

[0002] Wireless communication devices may include multiple different integrated circuits, such as amplifiers, mixers, transceivers, data converters, etc. The voltage input level of each integrated circuit can vary based on the function performed by the various integrated circuits. A voltage regulator can be used to generate each of these voltage levels. In some cases, low-dropout regulators can be used to generate various voltage levels. For example, a P-type metal-oxide-semiconductor (PMOS) low-dropout (LDO) regulator can be used. PMOS LDOs can be used in any suitable part of an electronic device, such as amplifiers, mixers, transceivers, data converters, low-noise amplifiers, etc. However, in some cases, PMOS LDOs may not provide sufficient power supply rejection ratio (PSRR) or reduce the power supply noise of the electronic device. Summary of the Invention

[0003] The following outlines some of the embodiments disclosed herein. It should be understood that these aspects are presented merely to provide the reader with a concise overview of these particular embodiments, and are not intended to limit the scope of this disclosure. In fact, this disclosure may cover many aspects not set forth below.

[0004] As described above, P-type metal-oxide-semiconductor (PMOS) low-dropout (LDO) regulators can be used to generate various voltage levels for a variety of functions performed by various integrated circuits in electronic devices. However, in some cases, PMOS LDOs may not provide sufficient power supply rejection ratio (PSRR) or reduce power supply noise. PMOS LDOs (e.g., secondary transistors) can also consume relatively large physical areas on various integrated circuits in electronic devices.

[0005] In the currently disclosed embodiments, an N-type metal-oxide-semiconductor (NMOS) LDO regulator with an N-type transfer transistor can be used. The topology of an NMOS LDO can be similar to that of a PMOS LDO. However, the differences between NMOS LDOs and PMOS LDOs are discussed herein. Advantageously, NMOS LDOs can provide improved (e.g., increased) PSRR, increased bandwidth, and improved suppression of power supply noise. Furthermore, the physical size of an NMOS LDO can be smaller than that of a PMOS LDO, thus saving physical space in electronic devices.

[0006] In one embodiment, a low-dropout regulator is presented, comprising a current source and an n-type transistor. The gate of the n-type transistor is coupled to the current source, and a first source of the n-type transistor is coupled to a second source of the p-type transistor. The p-type transistor includes a drain coupled to the gate of the n-type transistor. The low-dropout regulator also includes a compensation capacitor coupled to the current source, the gate of the n-type transistor, and the drain of the p-type transistor.

[0007] In another embodiment, a low-dropout regulator is presented. The low-dropout regulator includes a first current source and a compensation capacitor coupled to the first current source. A buffer transistor of the low-dropout regulator has a first gate, a first source, and a first drain. The first gate of the buffer transistor is coupled to the compensation capacitor. The low-dropout regulator also includes a second current source coupled to the first source of the buffer transistor. The low-dropout regulator further includes an n-type transistor having a second gate, a second source, and a second drain. The second gate of the n-type transistor is coupled to the second current source and the first source of the buffer transistor. The second source of the n-type transistor is coupled to the output terminal of the low-dropout regulator. The low-dropout regulator also includes a p-type transistor having a third source coupled to the output terminal of the low-dropout regulator and a third drain coupled to the first gate of the buffer transistor.

[0008] In another embodiment, an electronic device is presented. The electronic device includes a primary low-dropout regulator. The primary low-dropout regulator includes a first current source and an n-type transistor having a first gate coupled to the first current source. The first source of the n-type transistor is coupled to the output of the primary low-dropout regulator. The primary low-dropout regulator also includes a p-type transistor having a second source coupled to the first source of the n-type transistor. The first drain of the p-type transistor is coupled to the first gate of the n-type transistor. The electronic device further includes a secondary low-dropout regulator coupled to the primary low-dropout regulator via a resistor and a second current source. The second current source is configured to control the input voltage of the secondary low-dropout regulator from the primary low-dropout regulator.

[0009] Various modifications to the above-described features may exist with respect to various aspects of the invention. Other features may also be incorporated into these aspects. These modifications and additional features may exist individually or in any combination. For example, various features discussed below relating to one or more illustrated embodiments may be incorporated individually or in any combination into any of the above aspects of the invention. The brief summary presented above is intended only to familiarize the reader with specific aspects and context of the embodiments disclosed herein and does not limit the claimed subject matter. Attached Figure Description

[0010] Various aspects of this disclosure can be better understood by reading the following detailed description and referring to the accompanying drawings, wherein similar figures refer to similar parts.

[0011] Figure 1 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0012] Figure 2 It is based on the implementation scheme of this disclosure. Figure 1 Functional diagram of electronic devices.

[0013] Figure 3 It is based on the implementation scheme of this disclosure. Figure 1 A circuit diagram of an exemplary primary-secondary architecture for an N-type metal-oxide-semiconductor (NMOS) low-dropout (LDO) regulator in an electronic device.

[0014] Figure 4A It is based on the implementation scheme of this disclosure. Figure 1 A circuit diagram of an exemplary P-type metal-oxide-semiconductor (PMOS) low-dropout (LDO) regulator for an electronic device.

[0015] Figure 4B It is based on the implementation scheme of this disclosure. Figure 3 Circuit diagram of an N-type metal-oxide-semiconductor (NMOS) low-dropout (LDO).

[0016] Figure 5 This illustrates an embodiment according to this disclosure. Figure 4A PMOS LDO and Figure 4B A graph comparing the power supply rejection ratio (PSRR) of NMOS LDOs.

[0017] Figure 6 It is a source follower according to an embodiment of this disclosure. Figure 4B Circuit diagram of an NMOS LDO.

[0018] Figure 7 This illustrates an embodiment according to this disclosure. Figure 4B NMOS LDO and Figure 6 A graph comparing the power supply rejection ratio (PSRR) of NMOS LDOs with source followers.

[0019] Figure 8 It is for use in accordance with the embodiments of this disclosure Figure 4B Independent control of the primary NMOS LDO Figure 4B A circuit diagram of an exemplary architecture of multiple secondary NMOS LDOs. Detailed Implementation

[0020] One or more specific implementations will be described below. To provide a brief description of these implementations, not all characteristics of the actual implementations are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, decisions must be made specific to many implementations to achieve the developer's specific objectives, such as compliance with system-related and business-related constraints that may vary from one implementation to another. Furthermore, it should be understood that such development work can be complex and time-consuming, but will still be routine work of design, fabrication, and manufacturing for those skilled in the art who benefit from this disclosure.

[0021] When describing elements of various embodiments of this disclosure, the articles “an” and “the” are intended to refer to one or more of the elements present. The terms “comprising,” “including,” and “having” are intended to be included and to indicate the presence of additional elements besides those listed. Additionally, it should be understood that reference to “an embodiment” or “an embodiment” of this disclosure is not intended to be construed as excluding the existence of additional embodiments also incorporating the cited features. Furthermore, specific features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. The use of the terms “generally,” “approximately,” “about,” “close to,” and / or “substantially” should be understood to mean including close to the target (e.g., design, value, quantity), such as within limits of any suitable or conceivable error (e.g., within 0.1% of the target, within 1% of the target, within 5% of the target, within 10% of the target, within 25% of the target, etc.).

[0022] This disclosure relates to improving power supply rejection ratio (PSRR), providing increased bandwidth, and improving power supply noise suppression for low-dropout (LDO) regulators in electronic devices. Furthermore, embodiments herein provide LDOs with reduced physical size to maintain or reduce the overall physical size of electronic devices. To this end, embodiments herein provide N-type (e.g., conductive) metal-oxide-semiconductor (NMOS) low-dropout (LDO) regulators with NMOS transfer transistors. The impedance of an NMOS LDO can be reduced compared to that of a P-type (e.g., conductive) metal-oxide-semiconductor (PMOS) low-dropout (LDO) regulator. Specifically, an NMOS LDO can be used in any suitable part of an electronic device to support improved power supply rejection ratio (PSRR), improved noise suppression, and improved bandwidth. For example, the NMOS LDO discussed herein can be incorporated into amplifiers, mixers, transceivers, data converters, low-noise amplifiers, etc. It should be understood that one or more transistors discussed herein can operate as switches and therefore can represent switches.

[0023] Furthermore, the compensation capacitor for an NMOS LDO can be smaller than that for a PMOS LDO. The size of the compensation capacitor for an NMOS LDO can be reduced because the dominant pole of an NMOS LDO can be larger than that of a PMOS LDO. In other words, a smaller compensation capacitor can be used because the dominant pole of an NMOS LDO can be increased due to the N-type transfer transistor. Due to the smaller compensation capacitor, the bandwidth of an NMOS LDO increases compared to a PMOS LDO. The bandwidth of an NMOS LDO can also be increased due to the lower impedance compared to a PMOS LDO.

[0024] Figure 1 This is a block diagram of an electronic device 10 according to an embodiment of the present disclosure. Among other things, the electronic device 10 may include one or more processors 12 (collectively referred to herein as a single processor, which may be implemented in any suitable form of processing circuitry), memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface (e.g., wireless interface) 26, and power supply 29. Figure 1 The various functional blocks shown may include hardware elements (including circuitry), software elements (including machine-executable instructions), or combinations of hardware and software elements (which may be referred to as logic). Processor 12, memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network and / or wireless interface 26, and / or power supply 29 may each be directly or indirectly communicatively coupled to each other (e.g., via another component, communication bus, wireless connection, network) to transmit and / or receive data between them. It should be noted that... Figure 1 This is merely one example of a specific implementation and is intended to illustrate the types of components that may exist in electronic device 10.

[0025] For example, electronic device 10 may include any suitable computing device, including desktop computers or laptops (e.g., those available from Apple Inc., Cupertino, California). Pro, MacBook mini or Mac (in the form of) portable electronic devices or handheld electronic devices such as wireless electronic devices or smartphones (e.g., available from Apple Inc. in Cupertino, California). (Model form), tablet computers (for example, those available from Apple in Cupertino, California) (in the form of a model), wearable electronic devices (e.g., Apple products available from Apple Inc. in Cupertino, California) (in the form of) and other similar devices. It should be noted that, Figure 1 The processor 12 and other related items herein may be generally referred to as "data processing circuitry". This data processing circuitry may be embodied wholly or partially in software, hardware, or both. Furthermore, the processor 12 and... Figure 1 Other related items may be a single, independent processing module, or may be incorporated, wholly or partially, into any of the other elements within the electronic device 10. Processor 12 may be implemented using a combination of a general-purpose microprocessor, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic device (PLD), controller, state machine, gated logic, discrete hardware components, dedicated hardware finite state machine, or any other suitable entity capable of performing computations or other manipulations of information. Processor 12 may perform the various functions described herein.

[0026] exist Figure 1 In the electronic device 10, a processor 12 may be operatively coupled to a memory 14 and a non-volatile storage device 16 to execute various algorithms. Such programs or instructions executed by the processor 12 may be stored in any suitable article of writing comprising one or more tangible computer-readable media. The tangible computer-readable media may include the memory 14 and / or the non-volatile storage device 16, individually or jointly, to store instructions or routines. The memory 14 and the non-volatile storage device 16 may include any suitable article of writing for storing data and executable instructions, such as random access memory, read-only memory, rewritable flash memory, hard disk drive, and optical disk. Furthermore, programs (e.g., operating systems) encoded on such computer program products may also include instructions executable by the processor 12 to enable the electronic device 10 to provide various functions.

[0027] In some embodiments, display 18 may facilitate a user's viewing of images generated on electronic device 10. In some embodiments, display 18 may include a touchscreen that facilitates user interaction with the user interface of electronic device 10. Furthermore, it should be understood that in some embodiments, display 18 may include one or more liquid crystal displays (LCDs), light-emitting diode (LED) displays, organic light-emitting diode (OLED) displays, active-matrix organic light-emitting diode (AMOLED) displays, or some combination of these and / or other display technologies.

[0028] The input structure 22 of the electronic device 10 allows a user to interact with the electronic device 10 (e.g., press a button to increase or decrease the volume level). Like the network and / or wireless interface 26, the I / O interface 24 enables the electronic device 10 to interact with a variety of other electronic devices. In some embodiments, the I / O interface 24 may include I / O ports for hardwired connections for charging and / or content manipulation using standard connectors and protocols such as the Lightning connector supplied by Apple Inc. of Cupertino, California, Universal Serial Bus (USB), or other similar connectors and protocols. The network and / or wireless interface 26 may include, for example, one or more interfaces for personal area networks (PANs) such as… Networks, local area networks (LANs), or wireless local area networks (WLANs) such as those employing a protocol from the IEEE 802.11x family of protocols (e.g., Networks and / or wide area networks (WANs) such as any standards related to the 3rd Generation Partnership Project (3GPP), including, for example, third-generation (3G) cellular networks, Universal Mobile Telecommunications System (UMTS), fourth-generation (4G) cellular networks, Long Term Evolution (LTE) Cellular networks, Long Term Evolution License Auxiliary Access (LTE-LAA) cellular networks, fifth-generation (5G) cellular networks and / or New Radio (NR) cellular networks, satellite networks, etc. Specifically, network interface 26 may include, for example, one or more interfaces for using Release-15 cellular communication standards that include millimeter-wave (mmWave) frequency ranges (e.g., 24.25-300 GHz). Network interface 26 of electronic device 10 may allow communication via the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, etc.).

[0029] Network and / or wireless interface 26 may also include one or more interfaces, for example, for a broadband fixed wireless access network (e.g., Mobile broadband wireless network (mobile) Asynchronous digital subscriber lines (e.g., ADSL, VDSL) and digital video terrestrial broadcasting Network and its extensions DVB handheld Networks, ultra-wideband (UWB) networks, AC power lines, etc.

[0030] As shown, the network and / or wireless interface 26 may include a transceiver 30. In some embodiments, all or part of the transceiver 30 may be located within the processor 12. The transceiver 30 may support the transmission and reception of various wireless signals via one or more antennas. Therefore, the transceiver may include both a transmitter and a receiver. The power supply 29 of the electronic device 10 may include any suitable power source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter. In some embodiments, the electronic device 10 may take the form of a computer, a portable electronic device, a wearable electronic device, or other types of electronic devices.

[0031] Figure 2 It is based on the implementation scheme of this disclosure. Figure 1 Functional diagram of electronic device 10. As shown, processor 12, memory 14, transceiver 30, transmitter 52, receiver 54 and / or antenna 55 (shown as 55A-55N, collectively referred to as antenna 55) may be directly or indirectly communicatively coupled to each other (e.g., through or via another component, communication bus, network) to transmit and / or receive data between each other.

[0032] Electronic device 10 may include transmitter 52 and / or receiver 54, which respectively enable the transmission and reception of data between electronic device 10 and external devices via, for example, a network (e.g., including a base station) or a direct connection. As shown, transmitter 52 and receiver 54 may be combined into transceiver 30. Electronic device 10 may also have one or more antennas 55A to 55N electrically coupled to transceiver 30. Antennas 55A-55N may be configured in an omnidirectional or directional configuration, a single-beam, dual-beam, or multi-beam arrangement, etc. Each antenna 55 may be associated with one or more beams and various configurations. In some embodiments, multiple antennas in antennas 55A-55N of an antenna group or module may be communicatively coupled to a respective transceiver 30 and each transmits radio frequency signals that can be advantageously and / or destructively combined to form a beam.

[0033] As shown in the figure, various components of electronic device 10 can be coupled together via bus system 56. Bus system 56 may include, for example, a data bus, as well as power buses, control signal buses, and status signal buses in addition to the data bus. Components of electronic device 10 can be coupled together or use some other mechanism to accept or provide input to each other.

[0034] Although Figure 1 and Figure 2While transceivers have been described, it should be understood that the N-type metal-oxide-semiconductor (NMOS) low-dropout (LDO) regulators discussed herein can be part of any suitable part of an electronic device, such as a processor 12, memory 14, storage device 16, display 18, input structure 22, I / O interface 24, power supply 29, etc. Specifically, NMOS LDOs can be used in any suitable part of an electronic device to support improved power supply rejection ratio (PSRR), improved noise suppression, and improved bandwidth. For example, the NMOS LDOs discussed herein can be incorporated into amplifiers, mixers, transceivers, data converters, low-noise amplifiers, etc.

[0035] Figure 3 It is based on the implementation scheme of this disclosure. Figure 1 A circuit diagram of an exemplary primary-secondary architecture 100 for an N-type metal-oxide-semiconductor (NMOS) low-dropout (LDO) regulator in an electronic device. Architecture 100 can be used in any suitable component of electronic device 10, such as as part of processor 12, network interface 26, transceiver 30, transmitter 52, receiver 54, and / or power supply 29, as... Figure 1 and / or Figure 2 As shown. In other or alternative embodiments, architecture 100 may be included in any suitable integrated circuit, DSP, general-purpose microprocessor, microcontroller, FPGA, PLD, and / or controller of electronic device 10. As shown, architecture 100 includes a primary NMOS LDO 102 and a secondary NMOS LDO 104. The secondary NMOS LDO 104 may be substantially similar to the primary NMOS LDO 102. It should be understood that architecture 100 is merely an example, and many other architectures are possible. For example, the architecture may include multiple secondary NMOS LDOs 104 coupled to the primary NMOS LDO 102.

[0036] Architecture 100 includes an operational amplifier 106 coupled to a primary NMOS LDO 102 and a secondary NMOS LDO 104. Operational amplifier 106 can provide a reference voltage (V) to the primary NMOS LDO 102 and the secondary NMOS LDO 104. ref The primary NMOS LDO 102 may include multiple N-type transistors 114, 120, 122 and P-type transistor 118. Operational amplifier 106 may provide a reference voltage (V) to the gate of transistor 118. refCurrent source 110 is coupled to the gate of transistor 114 and the drain of transistor 120. The gate of transistor 114 is also coupled to the drain of transistor 120. The source of transistor 114 is coupled to the source of transistor 118 and, via node 128 disposed between resistors 124 and 126, to one or more resistors 124 and 126 in the feedback loop. The drain of transistor 118 may be coupled to the drain and gate of transistor 122. The drain of transistor 118 may also be coupled to the gate of transistor 120. The sources of transistor 120 and transistor 122 may be coupled to ground. It should be noted that architecture 100 is merely an example, and different arrangements of transistors with different conduction types (e.g., n-type and p-type) are possible.

[0037] Transistor 114 can selectively couple one or more resistors 124, 126 of the feedback loop to low voltage (LV) 108 based on high voltage (HV) 112 and current source 110. Resistors 124, 126 can form a resistive voltage divider and can be used to determine the output voltage of the primary NMOS LDO 102. Transistor 118 can be based on a reference voltage V from operational amplifier 106. ref Transistors 120 and 122 are selectively coupled to low voltage 108.

[0038] The secondary NMOS LDO 104 may include multiple N-type transistors 138, 140, and 142 and a P-type transistor 136. The operational amplifier 106 can provide a reference voltage (V) to the gate of transistor 136. ref Current source 134 is coupled to the gate of transistor 138 and the drain of transistor 140. The gate of transistor 138 is also coupled to the drain of transistor 140. The source of transistor 138 is coupled to the source of transistor 136. The drain of transistor 136 can be coupled to the drain and gate of transistor 142. The drain of transistor 136 can also be coupled to the gate of transistor 140. The sources of transistor 140 and transistor 142 can be coupled to ground. The output 146 of the secondary NMOS LDO 104 can be measured between the sources of transistors 138 and 136.

[0039] Architecture 100 may include a noise filter 154. The noise filter 154 may include a resistor 130 disposed between the primary NMOS LDO 102 and the secondary NMOS LDO 104. The noise filter 154 may also include a capacitor 132 coupled to the resistor 130. Combined, the resistor 130 and the capacitor 132 may filter the reference voltage V from the operational amplifier 106. ref The noise. It should be understood that other noise filtering technologies and devices can be used to filter noise from the reference voltage V. ref The noise.

[0040] The primary NMOS LDO 102 includes a compensation capacitor 116 disposed between and coupled to the current source 110 and the transistor 114. The compensation capacitor 116 can generate the dominant pole of the primary NMOS LDO 102. The dominant pole can refer to a frequency where the slope of the magnitude curve of the NMOS LDO decreases by approximately 20 dB for every tenfold increase in frequency (e.g., for every tenfold increase in frequency, the voltage gain decreases tenfold (to one-tenth of its previous value)). The size of the compensation capacitor 116 can be small (e.g., relative to the compensation capacitor of a PMOS LDO discussed below), and thus can provide an increased bandwidth for the NMOS LDO 102. The secondary NMOS LDO 104 may also include a compensation capacitor 150 disposed between and coupled to the respective current source 134 and the transistor 138 of the secondary NMOS LDO 104. The operation of the compensation capacitor 150 of the secondary NMOS LDO 104 is essentially the same as that of the compensation capacitor 116 of the primary NMOS LDO 102.

[0041] The current 152 flowing through transistor 138 can be equal to the load current I. L and static current I Q The sum of . Static current I Q This can explain the difference between the input current and the output current of the NMOS LDO 104. In some cases, the load current can be greater than the quiescent current I. Q The magnitude is a multiple in the range of approximately 10 to 100, for example, approximately 80 times. Advantageously, the NMOS transfer transistor 138 provides low impedance with high suppression of power supply noise. Furthermore, the NMOS transfer transistor 138 can be affected by the load current I... L It features low output impedance. The high gain of the NMOS transfer transistor 138 can be used to achieve high PSRR of the LDO without wasting (e.g., consuming excessive) power.

[0042] Figure 4A It is based on the implementation scheme of this disclosure. Figure 1A circuit diagram of an exemplary P-type metal-oxide-semiconductor (PMOS) low-dropout (LDO) regulator 170 for an electronic device is shown. As illustrated, the PMOS LDO 170 includes a plurality of P-type transistors 138, 136. A first transistor 138 can selectively couple the output 172 of the PMOS LDO 170 to a low voltage LV 108, at least partially based on a high voltage 112. A parasitic capacitance 176 can exist between the drain and gate of the first transistor 138. Additionally, a capacitive load 144 can exist at the output 172. A second transistor 136 can selectively couple a feedback loop to the low voltage LV 108 via a third transistor 174 based on the input of the PMOS LDO 170.

[0043] As shown in the figure, the gate of transistor 178 is coupled to current source 134 and the drain of transistor 178. The source of transistor 178 can be coupled to the gate of transistor 178 via parasitic capacitance 176. The drain of transistor 178 is coupled to the source of transistor 136. The drain of transistor 136 and the source of transistor 174 are coupled to ground. The output 172 of PMOS LDO 170 can be measured between the drain of transistor 178 and the source of transistor 136.

[0044] The PSRR of a PMOS LDO 170 can be determined differently based on the frequency of the input signal. For example, if the frequency is equal to or less than the frequency of the dominant pole, the PSRR of the PMOS LDO can be determined by the first transfer function:

[0045]

[0046] Where V out It is the voltage supplied to the load at 180V, V s This is the power supply voltage of the PMOS LDO 170, g mp It is the gain across the P-type transistor 178, and R out This is the output resistance of the PMOS LDO 170. If the frequency is greater than the dominant pole, the PSRR of the PMOS LDO can be determined by the second transfer function:

[0047]

[0048] Where r ds It is the "drain-source on-resistance" or the total resistance between the drain and source of transistor 178. The non-master poles of the PMOS LDO170 can be determined by the quiescent current I. Q Sure.

[0049] In operation, transistor 138 can provide output current to load 144. In some implementations, the load current can be between approximately 2 mA and approximately 25 mA, such as approximately 10 mA. Transistor 136 can provide low impedance and generate loop gain to suppress power supply noise at the input of the PMOS LDO 170. In doing so, transistor 136 can consume approximately 0.5 mA. However, the PMOS LDO 170 may not provide sufficient power supply rejection ratio (PSRR) or power supply noise reduction. Power supply rejection ratio (PSRR) can refer to the ability of an LDO to suppress input power variations. The PMOS LDO 170 can also consume a relatively large physical area on various integrated circuits of the electronic device 10.

[0050] Figure 4B It is based on the implementation scheme of this disclosure. Figure 3 Circuit diagrams of N-type metal-oxide-semiconductor (NMOS) low-dropout (LDO) circuits 102 and 104. NMOS LDOs 102 and 104 can be similar to... Figure 4A The PMOS LDO 170. However, the NMOS LDOs 102 and 104 include N-type transistors 138, 140, and 142 and a compensation capacitor 150. The NMOS LDO may also include a P-type transistor 136 disposed between and coupled to transistors 138 and 142. Transistor 138 may optionally provide a similar... Figure 4A The load current of transistor 178 in the PMOS LDO 170 is considered. However, compared to transistor 178 in the PMOS LDO 170, transistor 138 can have a lower output impedance. Therefore, the impedance of NMOS LDOs 102 and 104 can be less than that of transistor 138. Figure 4A The impedance of the PMOS LDO 170. Advantageously, the lower impedance of the NMOS LDO 102 and 104 can lead to an increase in bandwidth.

[0051] As mentioned above Figure 3 The current source 134 is coupled to the gate of transistor 138 and the drain of transistor 140. The gate of transistor 138 is also coupled to the drain of transistor 140. The source of transistor 138 is coupled to the source of transistor 136. The drain of transistor 136 can be coupled to the drain and gate of transistor 142. The drain of transistor 136 can also be coupled to the gate of transistor 140. The gate of transistor 140 can be coupled to the gate of transistor 142. The sources of transistor 140 and transistor 142 can be coupled to ground. The output 192 of NMOS LDOs 102 and 104 can correspond to... Figure 3 The output is 146, and it can be measured between the source of transistor 138 and the source of transistor 136.

[0052] As described above, the compensation capacitor 150 can generate the dominant poles of the NMOS LDOs 102 and 104. Furthermore, with... Figure 4A Compared to the PMOS LDO 170, the compensation capacitor 150 can increase the physical size of the NMOS LDOs 102 and 104. However, when the dominant poles of the NMOS LDOs 102 and 104 are smaller than the dominant pole of the PMOS LDO 170, the capacitance and therefore the physical size of the compensation capacitor 150 can be reduced.

[0053] Such as about Figure 4A The PSRR of NMOS LDOs 102 and 104, as discussed with the PMOS LDO 170, can be calculated differently based on the frequency of the input signal. For example, if the frequency is less than the dominant pole of the NMOS LDO 102 or 104, the PSRR of the NMOS LDO 102 or 104 can be calculated using the transfer function:

[0054]

[0055] Where g mn It is the gain across the N-type transistor 138, g mp It is the gain across the P-type transistor 136, r ds It is the "drain-source on-resistance" or the total resistance between the drain and source of transistor 178, and R out This refers to the output resistance of NMOS LDOs 102 and 104. Therefore, at frequencies below the dominant pole, the PSRR of NMOS LDOs 102 and 104 is increased by g compared to the PSRR of PMOS LDO 170 (as shown in Equation 1 above). mn r ds This factor allows NMOS LDOs 102 and 104 to achieve higher power supply rejection within a 3dB bandwidth.

[0056] If the frequency is greater than the dominant pole, the PSRR of the NMOS LDO 104 can be determined by the transfer function:

[0057]

[0058] Therefore, at frequencies above the dominant pole, the PSRR of NMOS LDOs 102 and 104 is increased by g compared to the PSRR of PMOS LDO 170 (as shown in Equation 4 above). mn / g mp The factors of.

[0059] The non-dominant poles of NMOS LDOs 102 and 104 can be connected to the load current I. LThis is determined by the load current I. In other words, NMOS LDO102 and 104 can be used to determine this. L (Instead of the quiescent current I of the PMOS LDO 170) Q This improves the closed-loop bandwidth and suppresses power supply noise at higher frequencies (e.g., frequencies above the dominant pole). Furthermore, power supply noise in NMOS LDOs 102 and 104 modulates the drain of N-type transfer transistor 138, while power supply noise in PMOS LDO 170 modulates the source of P-type transfer transistor 178.

[0060] Advantageously, the impedance of the NMOS LDO 104 can be less than that of the PMOS LDO 170. Therefore, the bandwidth of the NMOS LDO 104 can be improved relative to the bandwidth of the PMOS LDO 170. The bandwidth of the NMOS LDO 104 can be further improved due to the smaller compensation capacitor 150. In some cases, the compensation capacitor 150 of the NMOS LDO 102, 104 can be three to five times smaller than that of the PMOS LDO 170.

[0061] At certain operating frequencies, the noise suppression of NMOS LDOs 102 and 104 can be improved to be superior to that of PMOS LDO 170. For example, NMOS LDOs 102 and 104 can provide improved noise suppression by approximately 25% to approximately 50% compared to PMOS LDO 170. At certain operating frequencies, the noise suppression of NMOS LDOs 102 and 104 can be similar to that of PMOS LDO 170. In other words, NMOS LDOs 102 and 104 can at least maintain noise suppression compared to PMOS LDO 170.

[0062] Figure 5 This illustrates an embodiment according to this disclosure. Figure 4A PMOS LDO 170 and Figure 4B The power supply rejection ratio (PSRR) of the NMOS LDO104 is compared in graph 200. As shown in the figure, graph 200 illustrates... Figure 4A The PMOS LDO170 has a power supply rejection ratio (PSRR) of 202 and Figure 4BThe PSRR of the NMOS LDO 104 is 204. As an example, the dominant poles of the PMOS LDO 170 and NMOS LDO 104 can be at a first frequency f1. Therefore, the PSRR of the PMOS LDO 170 and NMOS LDOs 102 and 104 can differ for frequencies below the dominant pole (206) and frequencies above the dominant pole (208). In some cases, the first frequency f1 can be approximately 100 kHz. The second frequency f2 of the second pole of the PMOS LDO 170 and NMOS LDO 104 can be approximately 1 MHz.

[0063] Graph 200 depicts that the PSRR 204 of the NMOS LDO 104 is lower than the PSRR 202 of the PMOS LDO 170 because the PSRR value is negative. Therefore, even though the PSRR 204 of the NMOS LDO 104 is lower than the PSRR 202 of the PMOS LDO 170, the suppression is increased because PSRR 204 provides additional suppression. Thus, for frequencies below the dominant pole (e.g., less than the first frequency f1), the PSRR 204 of the NMOS LDO is improved by approximately 30 dB compared to the PSRR 202 of the PMOS LDO 170. For frequencies above the dominant pole (e.g., greater than the first frequency f1), the PSRR 204 of the NMOS LDO is improved by approximately 20 dB compared to the PSRR 202 of the PMOS LDO 170.

[0064] Figure 6 It is a source follower 234 according to an embodiment of this disclosure. Figure 4B Circuit diagram 220 shows NMOS LDOs 102 and 104. NMOS LDOs 102 and 104 with source follower 234 are shown relative to... Figure 4B The NMOS LDOs 102 and 104 further improved PSRR. However, compared with... Figure 4B Compared to NMOS LDOs 102 and 104, Figure 6 The NMOS LDOs 102 and 104 with source follower 234 can consume more power. Therefore, when a higher PSRR is required, Figure 6 The NMOS LDOs 102 and 104 with source follower 234 shown can be used in limited applications.

[0065] Source follower 234 (e.g., a buffer) includes a current source 222 coupled to buffer transistor 224. The drain of buffer transistor 224 is coupled to ground, and the source of buffer transistor 224 is coupled to the gate of transistor 138 and the current source 222. The gate of buffer transistor 224 is coupled to the current source 134 and the drain of transistor 140. The current source is also coupled to the gate of transistor 138. The source of transistor 138 is coupled to the source of transistor 136 and the output terminal 228 of NMOS LDO 220. The drain of transistor 136 is coupled to the drain and gate of transistor 142. The drain of transistor 136 is also coupled to the gate of transistor 140. The sources of transistor 140 and transistor 142 are coupled to ground. As shown, buffer transistor 224 is a P-type transistor.

[0066] As shown in the figure, current source 222 and buffer transistor 224 are disposed between N-type transistor 138 and compensation capacitor 226. Thus, the current source 222 and buffer transistor 224 of source follower 234 reduce the power supply noise at node 230 coupled to the gate of transistor 138 by approximately 1 / g. m Factors of g, where g m The gain of the N-type transfer transistor 138. The noise at node 230 can be determined by the following:

[0067]

[0068] Where C p It is the capacitance across the parasitic capacitance of transistor 138. In other words, Figure 6 The source follower 234 reduces the impedance at the gate of transistor 138, which in turn reduces the parasitic capacitance C to the output terminal 228 of NMOS LDOs 102 and 104. p Noise coupling. In some cases, Figure 6 The source follower 234 of the NMOS LDO102 and 104 reduces the PSRR of the NMOS LDO102 and 104 by about 10dB.

[0069] Figure 7 This illustrates an embodiment according to this disclosure. Figure 4B NMOS LDOs 102, 104 and Figure 6 A graph 250 compares the power supply rejection ratio (PSRR) of NMOS LDOs 102 and 104 with source followers 234. As shown in the figure, graph 250 illustrates... Figure 4B NMOS LDOs 102 and 104, PSRR 204 and Figure 6The PSRR 254 consists of NMOS LDOs 102 and 104 with source followers 234. As an example, the dominant poles of the NMOS LDOs 102 and 104 can be at a first frequency f1. In some cases, the first frequency f1 can be approximately 100 kHz. The non-dominant poles can be at, for example, a second frequency f2 of approximately 1 MHz.

[0070] As shown in graph 250 Figure 6 The NMOS LDO with source follower 234, the PSRR 254 with source follower 102, and the PSRR 104 are compared to Figure 4B The PSRR of NMOS LDOs 102 and 104 is approximately 10 dB lower than that of NMOS LDO 204. In other words, the PSRR of NMOS LDOs 102 and 104 with source follower 234 is 254 lower than that of NMOS LDOs 102 and 104. Figure 4B The PSRR of NMOS LDOs 102 and 104 is improved by approximately 10 dB. In some cases, due to... Figure 6 The peak PSRR frequency of the NMOS LDOs 102 and 104 can be increased by about 1.5 times by the addition of the source follower 234.

[0071] Figure 8 This is an embodiment of the present disclosure for use with a primary NMOS LDO 282 (such as...). Figure 3 and Figure 4B The NMOS LDOs 102 and 104 independently control multiple secondary NMOS LDOs 284 (such as...). Figure 3 and Figure 4B A circuit diagram of an exemplary architecture 280 for NMOS LDOs 102 and 104 is shown. As illustrated, the primary NMOS LDO 282 is coupled to multiple secondary NMOS LDOs 284. In some cases, architecture 280 can be substantially similar to... Figure 3 The architecture is 100. The secondary NMOS LDOs (e.g., secondary 1, 2, ... N) 284 can be essentially similar to... Figure 3 and Figure 4B The NMOS LDOs 102 and 104 are shown. However, the primary NMOS LDO 282 includes a resistor 288 and a current source 290 coupled to the output of operational amplifier 106. As shown, resistor 288 is coupled to the output of operational amplifier 106 and the gate of transistor 118. The input of the secondary NMOS LDO 286 can be connected between resistor 288 and current source 290.

[0072] Another secondary NMOS LDO (e.g., secondary N+1) 286 can be substantially similar to Figure 3 and Figure 4BThe NMOS LDOs 102 and 104 are examples. However, an additional secondary NMOS LDO 286 includes a resistor 292 and a capacitor 294 coupled to the drain of transistor 138. Resistor 292 and capacitor 294 can act as power supply filters to reduce noise from the input voltage of the primary NMOS LDO 282.

[0073] An additional secondary NMOS LDO 286 is coupled to the primary NMOS LDO 282 between resistor 288 and current source 290. A noise filter 154, including resistor 130 and capacitor 132, can be provided between the primary NMOS LDO 282 and the additional secondary NMOS LDO 286. The input voltage of the additional secondary NMOS LDO 286 can be the voltage output of operational amplifier 106 (e.g., V). b The voltage is determined by subtracting the resistance from resistor 288 and the current supplied by current source 290. In other words, the primary NMOS LDO 282 can supply different input voltages to various secondary NMOS LDOs 284 and 286 by adjusting the resistors and current used to couple the secondary NMOS LDOs 284 and 286 to the primary NMOS LDO 282. Thus, the input voltages of the secondary NMOS LDOs 284 and 286 can be independently controlled by adjusting the current through the corresponding current source coupled to the primary NMOS LDO 282.

[0074] Furthermore, the input of each secondary NMOS LDO 284, 286 can have individual noise filtering via a noise filter 154 including resistors and capacitors such as resistor 130 and capacitor 132. The input voltage of another secondary NMOS LDO 286 can also control the output voltage 296 of another secondary NMOS LDO 286. Therefore, by reducing the input voltage to another secondary NMOS LDO 286, the primary NMOS LDO 282 can reduce the output voltage 296 of the other secondary NMOS LDO 286. Thus, the primary NMOS LDO 282 can support multiple output voltage levels of the secondary NMOS LDOs 284, 286.

[0075] The specific embodiments described above have been illustrated by way of example, and it should be understood that various modifications and alternatives are permissible. It should also be understood that the claims are not intended to limit us to the specific forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the substance and scope of this disclosure.

[0076] The techniques described herein and protected by the claims are referenced and applied to specific examples of physical and practical nature, which significantly improve the technical field and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [function]..." or "steps for [performing] [function]...", those elements shall be interpreted in accordance with 35U.SC112(f). However, for any claim containing elements designated in any other manner, those elements shall not be interpreted in accordance with 35U.SC112(f).

[0077] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

Claims

1. A low-dropout voltage regulator, comprising: Current source; A first n-type transistor has a first gate and a first source, the first gate being coupled to the current source, and the first source being coupled to the second source of a p-type transistor; The p-type transistor has a first drain, which is coupled to the second gate of the second n-type transistor. and A compensation capacitor is coupled to the current source, the first gate of the first n-type transistor, and the second drain of the second n-type transistor.

2. The low-dropout regulator of claim 1, further comprising an additional transistor having a third drain coupled to the first drain of the p-type transistor.

3. The low-dropout regulator according to claim 2, wherein the p-type transistor and the additional transistor provide a feedback loop for the current of the low-dropout regulator.

4. The low-dropout voltage regulator according to claim 1, comprising: Additional current source; and A buffer transistor having a third source coupled to the first gate of the first n-type transistor and the additional current source, and a third drain coupled to ground.

5. The low-dropout regulator of claim 4, wherein the additional current source and the buffer transistor improve the power supply rejection ratio of the low-dropout regulator.

6. The low-dropout regulator of claim 1, comprising a resistor coupled to the third gate of the p-type transistor and an additional current source.

7. The low-dropout regulator of claim 6, wherein the resistor and the additional current source are configured to provide a reduced output voltage to the secondary low-dropout regulator.

8. The low dropout regulator according to claim 1, comprising a noise filter coupled to the third gate of the p-type transistor, the noise filter comprising a resistor-capacitor filter.

9. The low-dropout regulator according to claim 1, wherein the first drain of the p-type transistor is directly coupled to the second gate of the second n-type transistor.

10. A low-dropout voltage regulator, comprising: First current source; A compensation capacitor, wherein the compensation capacitor is coupled to the first current source; A buffer transistor having a first gate, a first source, and a first drain, wherein the first gate is coupled to the compensation capacitor; A second current source is coupled to the first source. An n-type transistor having a second gate, a second source, and a second drain, wherein the second gate is coupled to a second current source and the first source of the buffer transistor, and the second source is coupled to an output terminal; and The p-type transistor has a third source that is coupled to the output terminal and the second source of the n-type transistor.

11. The low dropout regulator of claim 10, wherein the buffer transistor and the second current source comprise a source follower.

12. The low dropout regulator of claim 11, wherein the source follower improves the power supply rejection ratio of the low dropout regulator.

13. The low-dropout regulator of claim 10, further comprising an additional n-type transistor having a fourth drain coupled to a third drain of the p-type transistor.

14. The low-dropout regulator of claim 13, wherein the p-type transistor and the additional n-type transistor provide a feedback loop for the current of the low-dropout regulator via the buffer transistor.

15. An electronic device comprising: Primary low-dropout regulator, the primary low-dropout regulator includes First current source An n-type transistor, the n-type transistor having a first gate and a first source, the first gate being coupled to a first current source, and the first source being coupled to an output terminal. The p-type transistor has a second source and a first drain, the second source being coupled to the first source of the n-type transistor, and the first drain being coupled to the second gate of the second n-type transistor. as well as A secondary low-dropout regulator is coupled to the primary low-dropout regulator via a resistor and a second current source configured to control the input voltage of the secondary low-dropout regulator from the primary low-dropout regulator.

16. The electronic device of claim 15, wherein the primary low-dropout regulator includes a compensation capacitor coupled to the first current source, the first gate of the n-type transistor, and the second drain of the second n-type transistor.

17. The electronic device of claim 16, wherein the secondary low-dropout regulator comprises Third current source An additional n-type transistor, the additional n-type transistor having a third gate and a third source, the third gate being coupled to the third current source, and the third source being coupled to an additional output terminal, and An additional p-type transistor having a fourth source and a third drain, the fourth source being coupled to the third source of the additional n-type transistor, and the third drain being coupled to the fourth gate of the second additional n-type transistor.

18. The electronic device of claim 15, wherein the resistor and the second current source are configured to reduce the input voltage of the secondary low-dropout regulator.

19. The electronic device of claim 15, further comprising: An additional resistor, coupled to the third gate of the p-type transistor, and A capacitor coupled to the additional resistor, wherein the additional resistor and the capacitor include an input filter for the secondary low-dropout regulator.

20. The electronic device of claim 15, further comprising an additional low-dropout regulator coupled to the primary low-dropout regulator via the resistor and the second current source, the second current source being configured to control the input voltage of the additional low-dropout regulator from the primary low-dropout regulator.

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