A method, system, device, and medium for improving the computational efficiency of delayed computing blocks.

Abstract

This invention discloses a method, system, device, and medium for improving the computation efficiency of delayed computing blocks. It belongs to the fields of artificial intelligence, in-memory computing, and delayed computing technologies, and includes: using an 8-bit unsigned number as the common-mode weight value W. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM The method converts an 8-bit unsigned number into an 8-bit signed number to obtain the binary code of the true value. Based on this binary code, a memory-based delayed computation circuit is used to perform delayed computation, completing the inner product calculation within one computation clock cycle. This invention's delayed computation block efficiency improvement method utilizes the concept of differential-mode and common-mode computation, converting an 8-bit unsigned number into an 8-bit signed number and converting weights into differential-mode and common-mode weights for delayed computation; within the delayed computation block, it restores the accumulated delay value corresponding to the differential-mode weight to the accumulated delay value corresponding to the common-mode weight.

Description

Technical Field

[0001] This invention relates to the fields of artificial intelligence, in-memory computing, and delayed computing technologies, specifically to a method, system, device, and medium for improving the computing efficiency of delayed computing blocks. Background Technology

[0002] Artificial intelligence neural networks are being used more and more widely across various industries. As research deepens, different applications are placing higher computational demands on artificial intelligence neural networks. Due to the separation of storage and computing units, the traditional von Neumann architecture can no longer meet the ever-increasing computational needs. In order to break down the "memory wall" between storage and computing units, researchers have proposed a new "in-memory computing" architecture to meet the current computational requirements of artificial intelligence neural networks.

[0003] To achieve an "in-memory computing" architecture, researchers have proposed various circuit structures. Recent studies show that delay computing blocks based on static random access memory (SRAM) and delay units can efficiently perform neural network computations in the time domain through delay accumulation. Since SRAM fabrication using CMOS technology is quite mature, and delay units can be implemented using CMOS circuit structures, delay computing blocks are simpler to implement than other circuit structures because they do not rely on novel memory devices and can be deployed to practical applications more quickly.

[0004] In applications where the input data is unsigned, due to circuit structure limitations and the irreversible nature of time, the delay computation block can only complete the computation of a neural network with unsigned weights within one computation clock cycle. However, most practical neural network applications involve signed weights, thus requiring a solution to this problem. A common solution is to sacrifice computation speed to complete the computation of a neural network with signed weights. Specifically, this involves calculating the neural network with only positive weights and the neural network with only the absolute values ​​of negative weights separately within two computation clock cycles. After obtaining the cumulative time-domain delay value, the cumulative delay value corresponding to the positive weights is subtracted from the cumulative delay value corresponding to the negative weights, thereby completing the computation of the neural network with signed weights. Summary of the Invention

[0005] To address the aforementioned shortcomings, the present invention aims to provide a method, system, device, and medium for improving the computational efficiency of delayed computation blocks. The present invention can complete the computation of neural networks with signed weights within one computation clock cycle, thereby further improving the computational efficiency of delayed computation blocks.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A method for improving the computational efficiency of delayed computation blocks, used for delayed computation blocks, includes:

[0008] Use an 8-bit unsigned number as the common-mode weight value W. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM Convert an 8-bit unsigned number into an 8-bit signed number to obtain the binary code of the actual value.

[0009] Based on the binary code, a memory-based delay calculation circuit is used to perform delay calculation, and the inner product calculation is completed within one calculation clock cycle.

[0010] As a further improvement of the present invention, the 8-bit unsigned number is used as the common-mode weight value W. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM ,include:

[0011]

[0012] In the formula, Y, Y DM, and Y DM These represent the calculated output of MWDCB weights without differential common-mode coding, the output of MWDCB weights after differential common-mode coding, and U, respectively. DM, The output related to the intermediate mode weight; IN i Let W be the input vector of MWDCB, where i represents the i-th channel of MWDCB; i W DM, W CMi W DMi W DM, [7] and W DM, [6:0] represents the weight vector without differential common-mode encoding, the weight vector after differential common-mode encoding, the common-mode weight vector, the differential-mode weight vector, and W, respectively. DMi The highest bit vector and W DMi A 0- to 6-bit vector, where a and b represent two functions.

[0013] As a further improvement of the present invention, the delayed calculation block is further included with a 23-bit two's complement method:

[0014] Invert the first digit of the common modulus weight;

[0015] After the delay accumulation value generated by the DCB corresponding to the first bit of the differential common mode weight is restored to a 15-bit digital signal by shifting and adding, it should be bitwise inverted, and 1 bit data "1" should be appended before the first bit as the sign bit, and 7 bits data "1111111" should be appended after the last bit as the shift weight corresponding to the highest bit. Finally, the addition operation is completed in the summing circuit.

[0016] The delay accumulation value generated by the delay calculation block corresponding to the lower 7 bits of the differential common mode weight should be converted into a 23-bit signed number after shifting and adding to restore it to a digital signal. The sign bit should be set to "0", and then summed with the two's complement to obtain a 23-bit signed number result.

[0017] As a further improvement of the present invention, it also includes replacing the RELU activation function by judging the sign bit of the 23-bit result.

[0018] As a further improvement of the present invention, the delay calculation block is a multi-bit delay calculation block, and one multi-bit delay calculation block includes 8 delay calculation blocks. One delay calculation block includes 64 delay calculation units. Each delay calculation unit includes one SRAM storage unit storing 1 bit weight and 4 edge delay units. The 4 edge delays are controlled by every 2 bits of an 8-bit input from high to low and 1 bit of the weight at a time.

[0019] The present invention also provides a circuit for improving the computational efficiency of a delay computation block, comprising:

[0020] The common-mode weighting module is used to take an 8-bit unsigned number as the common-mode weight value W. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM Convert an 8-bit unsigned number into an 8-bit signed number to obtain the binary code of the actual value.

[0021] Based on the binary code, a memory-based delay calculation circuit is used to perform delay calculation, and the inner product calculation is completed within one calculation clock cycle.

[0022] As a further improvement of the present invention, in the differential common-mode weighting module, the 8-bit unsigned number is used as the common-mode weight value W. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM ,include:

[0023]

[0024] In the formula, Y, Y DM, and Y DM These represent the calculated output of MWDCB weights without differential common-mode coding, the output of MWDCB weights after differential common-mode coding, and Y, respectively. DM, The output related to the intermediate mode weight; IN i Let W be the input vector of MWDCB, where i represents the i-th channel of MWDCB; i W DM, W CMi W DMi WDM, [7] and W DM, [6:0] represents the weight vector without differential common-mode encoding, the weight vector after differential common-mode encoding, the common-mode weight vector, the differential-mode weight vector, and W, respectively. DMi The highest bit vector and W DMi A 0- to 6-bit vector, where a and b represent two functions.

[0025] As a further improvement of the present invention, a 23-bit two's complement circuit is also included, used for:

[0026] Invert the first digit of the common modulus weight;

[0027] After the delay accumulation value generated by the DCB corresponding to the first bit of the differential common mode weight is restored to a 15-bit digital signal by shifting and adding, it should be bitwise inverted, and 1 bit data "1" should be appended before the first bit as the sign bit, and 7 bits data "1111111" should be appended after the last bit as the shift weight corresponding to the highest bit. Finally, the addition operation is completed in the summing circuit.

[0028] The delay accumulation value generated by the delay calculation block corresponding to the lower 7 bits of the differential common mode weight should be converted into a 23-bit signed number after shifting and adding to restore it to a digital signal. The sign bit should be set to "0", and then summed with the two's complement to obtain a 23-bit signed number result.

[0029] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method for improving the computational efficiency of the delayed computation block.

[0030] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method for improving the computational efficiency of a delayed computation block.

[0031] Compared with the prior art, the present invention has the following advantages:

[0032] This invention provides a method for improving the computation efficiency of delayed computation blocks. It utilizes the concept of differential-mode and common-mode to convert 8-bit unsigned numbers into 8-bit signed numbers and convert weights into differential-mode and common-mode weights for delayed computation. Under the delayed computation block, it also provides a method for restoring the cumulative delay value corresponding to the differential-mode weight to the cumulative delay value corresponding to the differential-mode weight. Attached Figure Description

[0033] Figure 1 This is the schematic diagram of the DCU circuit.

[0034] Figure 2 For MWDCB diagram;

[0035] Figure 3 This is a conceptual diagram of the differential common-mode weighting of this invention;

[0036] Figure 4 This is a schematic diagram illustrating the implementation principle of the differential common-mode weighting of this invention.

[0037] Figure 5 This is a flowchart of a method for improving the computational efficiency of a delayed computation block according to the present invention;

[0038] Figure 6 This is a schematic diagram of an electronic device. Detailed Implementation

[0039] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] Terminology Explanation:

[0042] The present invention will be described in detail below with reference to specific embodiments.

[0043] MWDCB (Multi-bit Delayed Computation Block);

[0044] DCB Delayed Calculation Block;

[0045] DCU Delay Computation Unit;

[0046] EDC edge delay unit;

[0047] TDC Time-to-Digital Converter.

[0048] The technical content of this application will be described in detail below with reference to specific embodiments.

[0049] like Figure 1 As shown, in the EDC, P4 operates in the linear region, and its equivalent resistance is determined by the MID point voltage. The higher the MID point voltage, the larger the equivalent resistance of P4, and the longer the charging time of the drain terminal of P4. That is, the higher the MID point voltage, the longer the delay time from the rising edge from EIN10 to EOUT10. Therefore, four sets of VIN10 voltages are set so that the delay time value has a linear relationship with the VIN10 voltage value, as shown in the first four cases in Table 1. Furthermore, the weight value stored in SRAM is used as the enable signal for the EDC. That is, when the SRAM stores "0", the EDC does not work, and the delay time is the circuit's inherent delay time t0. When the SRAM stores "1", the EDC works, and the delay time is controlled by VIN10. From the above, it can be seen that one EDC can complete a multiplication of a 1-bit number (weight) and a 2-bit number (input). Each DCU has 4 EDCs, which can complete a multiplication of a 1-bit number (weight) and an 8-bit number (input).

[0050] Table 1. Correspondence between delay values ​​and input voltages

[0051]

[0052] By leveraging the cumulative property of delay time, cascading 64 DCUs to form a DCB allows for the multiplication and addition operation (vector inner product) of 64 1-bit numbers (weights) and 64 8-bit numbers (inputs). Furthermore, a DCB composed of 8 DCBs can be used... Figure 2 The MWDCB shown can perform multiplication and addition operations on 64 8-bit numbers (weights) and 64 8-bit numbers (inputs). The result is reflected in the delay value. To use this result in digital calculations, the delay value needs to be converted into a digital signal using a time-to-digital converter (TDC). Since the MWDCB performs multiplication and addition operations bit by bit, the results obtained for each bit need to be shifted before summing to obtain the correct result. This summation is performed by a digital adder.

[0053] As can be seen from the above, this circuit structure cannot directly perform neural network calculations with signed weights. The presence of TDC and digital arithmetic circuits restricts binary two's complement arithmetic (22-bit output, 8-bit two's complement arithmetic will produce erroneous carry). Therefore, neural network calculations with signed weights cannot be performed within one calculation clock cycle.

[0054] To solve the above problems, such as Figure 5 As shown, this invention proposes a method for improving the computational efficiency of delayed computation blocks, comprising:

[0055] Use an 8-bit unsigned number as the common-mode weight value W. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM Convert an 8-bit unsigned number into an 8-bit signed number to obtain the binary code of the actual value.

[0056] Based on the binary code, a memory-based delay calculation circuit is used to perform delay calculation, and the inner product calculation is completed within one calculation clock cycle.

[0057] This invention utilizes the concept of differential mode and common mode to convert an 8-bit unsigned number into an 8-bit signed number. The conversion principle is as follows: the 8-bit unsigned number (10000000)2 is used as the common mode weight value W. CM Based on this, add or subtract an 8-bit unsigned differential weight value W, where the highest bit is 0. DM .

[0058] For example, a weight value of -3 is represented as (01111101)2, and a weight value of +3 is represented as (10000011)2. Subtracting (10000000)2 from these representations yields the binary code of the actual value. In practical circuits, this would be as follows: Figure 3 As shown.

[0059] The mathematical model of MWDCB is shown in equation (1). Applying the above differential mode and common mode concepts to MWDCB requires MWDCB. CM-DM and MWDCB CM Only then can the calculation be completed, including MWDCB. CM-DM The mathematical operation represented by equation (2) yields a result that includes both the cumulative delay value corresponding to the common mode weight and the cumulative delay value corresponding to the differential mode weight. However, the actual operation result is only related to the cumulative delay value corresponding to the differential mode weight. Therefore, MWDCB CM-DM The result needs to be subtracted from the cumulative delay value corresponding to the common mode weight, which is determined by MWDCB. CM The calculation is given, and the mathematical process is given by equation (3). The specific process is as follows:

[0060]

[0061]

[0062]

[0063]

[0064] In the formula, Y, Y DM, and Y DMThese represent the calculated output of MWDCB weights without differential common-mode coding, the output of MWDCB weights after differential common-mode coding, and Y, respectively. DM, The output related to the intermediate mode weight; IN i Let be the input vector of MWDCB, where i = 1, 2, 3... represents the i-th channel of MWDCB; W i W DM, W CMi W Dmi W DM, [7] and W DM, [6:0] represents the weight vector without differential common-mode encoding, the weight vector after differential common-mode encoding, the common-mode weight vector, the differential-mode weight vector, and W, respectively. DMi The highest bit vector and W DMi A vector of 0 to 6 bits.

[0065] The above principles impose the following three requirements on circuit implementation:

[0066] 1) Invert the first digit of the common modulus weight;

[0067] 2) After the delay accumulation value generated by the DCB corresponding to the first bit of the differential common-mode weight is restored to a 15-bit digital signal through shifting and addition, it should be bitwise inverted, and a 1-bit data "1" should be appended before the first bit as the sign bit, and a 7-bit data "1111111" should be appended after the last bit as the shift weight corresponding to the highest bit. Finally, the addition operation is completed in the summing circuit. The above circuit corresponds to the complement and shift operation of item a in equation (4). The specific principle is as follows: Figure 4 As shown;

[0068] 3) The accumulated delay value generated by the DCB corresponding to the lower 7 bits of the differential common-mode weight, after being shifted and added back to the digital signal, should be converted into a 23-bit signed number, with its sign bit set to "0". Then, it should be summed with the two's complement result from step 2 to obtain the 23-bit signed number result. The corresponding principle is as follows: Figure 4 As shown.

[0069] Furthermore, in an optional embodiment of the present invention, the sign bit of the 23-bit result obtained in step 3 can be used to replace the ReLU activation function, thereby reducing circuit complexity.

[0070] Equation (4) shows that by re-encoding the weights and adding a 23-bit complement circuit to the digital processing circuit, the present invention enables the delay calculation circuit structure to complete the calculation of a neural network with signed weights in one calculation cycle with relatively small hardware resources. Under the premise that the calculation density remains basically unchanged, the calculation efficiency is improved. In the calculation of a neural network with the activation function ReLU, the present invention has a greater advantage.

[0071] Example

[0072] With the development of artificial intelligence in the power sector, the YOLOv3-Tiny algorithm has been widely used in outdoor power image detection. To reduce the power consumption of IoT edge devices, it is necessary to reduce the resource overhead of the YOLOv3-Tiny algorithm on dedicated computing chips while maintaining accuracy. This places new demands on dedicated chips. Delayed computation blocks, due to their high energy efficiency, are designed into dedicated chips to meet these new requirements. However, due to circuit structure limitations, they cannot complete the computation of neural networks containing signed weights within a single computation cycle. Using the method of this invention, the computation of neural networks containing signed weights can be completed within a single computation cycle without increasing hardware resources. Compared to traditional methods, this doubles the energy efficiency and reduces circuit complexity.

[0073] The present invention also provides a system for improving the computational efficiency of delayed computation blocks, comprising:

[0074] The common-mode weighting module is used to take an 8-bit unsigned number as the common-mode weight value W. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM Convert an 8-bit unsigned number into an 8-bit signed number to obtain the binary code of the actual value.

[0075] The delay calculation module is used to perform delay calculation based on the binary code using an in-memory delay calculation circuit, and complete the inner product calculation within one calculation clock cycle.

[0076] It also includes a 23-bit two's complement circuit, used for:

[0077] Invert the first digit of the common modulus weight;

[0078] After the delay accumulation value generated by the DCB corresponding to the first bit of the differential common mode weight is restored to a 15-bit digital signal by shifting and adding, it should be bitwise inverted, and 1 bit data "1" should be appended before the first bit as the sign bit, and 7 bits data "1111111" should be appended after the last bit as the shift weight corresponding to the highest bit. Finally, the addition operation is completed in the summing circuit.

[0079] The delay accumulation value generated by the delay calculation block corresponding to the lower 7 bits of the differential common mode weight should be converted into a 23-bit signed number after shifting and adding to restore it to a digital signal, and its sign bit should be set to "0". Then it should be summed with the two's complement.

[0080] The result is a 23-bit signed number.

[0081] like Figure 6As shown, the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method for improving the computational efficiency of the delayed computation block.

[0082] The method for improving the computational efficiency of the delayed computation block includes the following steps:

[0083] Use an 8-bit unsigned number as the common-mode weight value W. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM This converts an 8-bit unsigned number into an 8-bit signed number, obtaining the binary code of the actual value.

[0084] The present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the method for improving the computational efficiency of the delayed computation block.

[0085] The method for improving the computational efficiency of the delayed computation block includes the following steps:

[0086] Use an 8-bit unsigned number as the common-mode weight value W. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM Convert an 8-bit unsigned number into an 8-bit signed number to obtain the binary code of the actual value.

[0087] Based on the binary code, a memory-based delay calculation circuit is used to perform delay calculation, and the inner product calculation is completed within one calculation clock cycle.

[0088] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0089] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0090] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0091] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for improving the computational efficiency of delayed computation blocks, characterized in that, include: Use an 8-bit unsigned number as the common-mode weight value W. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM Convert an 8-bit unsigned number into an 8-bit signed number to obtain the binary code of the actual value. Based on the binary code, a memory-based delay calculation circuit is used to perform delay calculation, and the inner product calculation is completed within one calculation clock cycle. The 8-bit unsigned number is used as the common-mode weight value W. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM ,include: In the formula, , and These are the calculated outputs of MWDCB weights without differential common-mode coding, the outputs of MWDCB weights after differential common-mode coding, and... Output related to the intermediate difference modulus weights; For the input vector of MWDCB, i Represented as the MWDCB of the i aisle; 、 、 、 、 and These represent the weight vector without differential common-mode encoding, the weight vector after differential common-mode encoding, the common-mode weight vector, and the differential-mode weight vector, respectively. The highest bit vector and A 0- to 6-bit vector, where a and b represent two functions; After obtaining the binary code of the true value, a 23-bit two's complement method is also included: Invert the first digit of the common modulus weight; After the delay accumulation value generated by the DCB corresponding to the first bit of the differential common mode weight is restored to a 15-bit digital signal by shifting and adding, it should be bitwise inverted, and 1 bit data "1" should be appended before the first bit as the sign bit, and 7 bits data "1111111" should be appended after the last bit as the shift weight corresponding to the most significant bit. Finally, the addition operation is completed in the summing circuit. The delay accumulation value generated by the delay calculation block corresponding to the lower 7 bits of the differential common mode weight should be converted into a 23-bit signed number after shifting and adding to restore it to a digital signal. The sign bit should be set to "0", and then summed with the two's complement to obtain a 23-bit signed number result.

2. The method for improving the computational efficiency of delayed computation blocks according to claim 1, characterized in that, It also includes replacing the ReLU activation function by judging the sign bit of the 23-bit result.

3. A circuit for improving the computational efficiency of a delay calculation block, characterized in that, include: The differential common-mode weighting module is used to use an 8-bit unsigned number as the common-mode weight value W within one computation clock cycle. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM Convert an 8-bit unsigned number into an 8-bit signed number to obtain the binary code of the actual value. The delay calculation module is used to perform delay calculation based on the binary code using an in-memory delay calculation circuit, and complete the inner product calculation within one calculation clock cycle; The 8-bit unsigned number is used as the common-mode weight value W. CM Add or subtract an 8-bit unsigned differential weight value W with the highest bit set to 0. DM ,include: In the formula, , and These are the calculated outputs of MWDCB weights without differential common-mode coding, the outputs of MWDCB weights after differential common-mode coding, and... Output related to the intermediate difference modulus weights; For the input vector of MWDCB, i Represented as the MWDCB of the i aisle; 、 、 、 、 and These represent the weight vector without differential common-mode encoding, the weight vector after differential common-mode encoding, the common-mode weight vector, and the differential-mode weight vector, respectively. The highest bit vector and A 0- to 6-bit vector, where a and b represent two functions; It also includes a 23-bit two's complement circuit, used for: Invert the first digit of the common modulus weight; After the delay accumulation value generated by the DCB corresponding to the first bit of the differential common mode weight is restored to a 15-bit digital signal by shifting and adding, it should be bitwise inverted, and 1 bit data "1" should be appended before the first bit as the sign bit, and 7 bits data "1111111" should be appended after the last bit as the shift weight corresponding to the most significant bit. Finally, the addition operation is completed in the summing circuit. The delay accumulation value generated by the delay calculation block corresponding to the lower 7 bits of the differential common mode weight should be converted into a 23-bit signed number after shifting and adding to restore it to a digital signal. The sign bit should be set to "0", and then summed with the two's complement to obtain a 23-bit signed number result.

4. The circuit for improving the computational efficiency of a delay calculation block according to claim 3, characterized in that, The delay calculation block is a multi-bit delay calculation block. One multi-bit delay calculation block includes 8 delay calculation blocks. One delay calculation block includes 64 delay calculation units. Each delay calculation unit includes one SRAM storage unit that stores 1 bit of weight and 4 edge delay units. The 4 edge delays are controlled by every 2 bits of an 8-bit input from high to low and 1 bit of the weight.

5. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the delayed computing block computation efficiency improvement method according to any one of claims 1-2.

6. A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the delayed computing block computation efficiency improvement method according to any one of claims 1-2.

Images