Three-dimensional memory devices and methods for enhanced page register reset

Abstract

A method of programming a memory device having planes includes receiving a program command, obtaining an address associated with the program command, determining a first plane of the planes based on the address, and resetting a page register of the first plane without resetting one or more page registers of one or more remaining planes of the planes.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202180001070.7, filed on March 30, 2021, entitled "Three-dimensional storage device and method for enhanced page register reset". Technical Field

[0002] This application relates to the field of semiconductor technology, and more particularly to a method for resetting three-dimensional (3D) memory devices and page registers. Background Technology

[0003] NAND flash memory is a non-volatile type of memory that does not require power to retain the stored data. The ever-growing demands of consumer electronics, cloud computing, and big data have created a sustained need for larger capacity, higher performance NAND memory. As conventional two-dimensional (2D) NAND memory approaches its physical limits, three-dimensional (3D) NAND memory is now playing a crucial role. 3D NAND memory uses multiple stacked layers on a single die to achieve higher density, higher capacity, faster performance, lower power consumption, and better cost efficiency.

[0004] Before data is written to the 3D NAND storage device, multiple page registers are reset or cleared. This register reset process can cause an increase in peak power, total power, and power noise. The disclosed method addresses one or more of the problems described above, as well as others. Summary of the Invention

[0005] In one aspect of this disclosure, a method for programming a surfaced storage device includes: receiving a programming command for the storage device; obtaining an address associated with the programming command; determining a first surface in the surface based on the address; and resetting a page register of the first surface without resetting one or more page registers of one or more other surfaces in the surface.

[0006] In another aspect of this disclosure, a storage device includes: one or more logic units (LUNs) including faces; page registers respectively corresponding to the faces; and a controller for executing commands. The controller is configured to: receive programming commands for the storage device; obtain an address associated with the programming commands; determine a first face in the faces based on the address; and reset the page registers in the page registers corresponding to the first face without resetting one or more of the remaining page registers in the page registers.

[0007] In another aspect of this disclosure, a method for a surface-based storage device includes: receiving a programming command for the storage device; obtaining an address associated with the programming command; determining a first surface in the surface for register reset based on the address; and maintaining the state of one or more page registers of one or more remaining surfaces in the surface.

[0008] In another aspect of this disclosure, a storage device includes a surface and a reset circuit for resetting the surface. The reset circuit is configured to receive a first address-based control signal for resetting the surface, and, according to the first control signal, reset the page register of a first surface in the surface without resetting one or more page registers of one or more other surfaces in the surface.

[0009] Other aspects of this disclosure will be understood by those skilled in the art based on the specification, claims and drawings. Attached Figure Description

[0010] Figure 1 Cross-sectional views of exemplary three-dimensional (3D) storage devices according to various embodiments of the present disclosure are shown;

[0011] Figure 2 Block diagrams of 3D storage devices according to various embodiments of the present disclosure are shown;

[0012] Figure 3 A top view of the construction of a 3D array device according to various embodiments of the present disclosure is shown;

[0013] Figure 4 and Figure 5 This illustrates specific stages in an exemplary manufacturing process according to various embodiments of the present disclosure. Figure 3 Top view and cross-sectional view of a portion of the 3D array device shown;

[0014] Figure 6 and Figure 7 This illustrates specific stages in an exemplary manufacturing process according to various embodiments of the present disclosure. Figure 4 and Figure 5 A cross-sectional view of a portion of the 3D array device shown;

[0015] Figure 8 Cross-sectional views of exemplary peripheral devices according to various embodiments of the present disclosure are shown;

[0016] Figure 9 Various embodiments according to this disclosure are shown. Figure 6 The 3D array device shown is Figure 7 A cross-sectional view of an exemplary 3D memory device after the peripheral devices are attached;

[0017] Figure 10Various embodiments according to this disclosure are shown. Figure 9 The diagram shows the organization of the 3D storage device.

[0018] Figure 11 Various embodiments according to this disclosure are shown. Figure 10 Timing diagram of write operations for the 3D storage device shown;

[0019] Figure 12 A schematic flowchart illustrating a method for resetting a page register at a 3D memory device according to various aspects of this disclosure is shown;

[0020] Figure 13A and 13B Exemplary implementation block diagrams according to various aspects of this disclosure are shown; and

[0021] Figure 14 A timing diagram of page register reset according to various aspects of this disclosure is shown. Detailed Implementation

[0022] The technical solutions in the embodiments of this disclosure will be described below with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used in all drawings to indicate the same or similar parts. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Features in the various embodiments can be exchanged and / or combined. Other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort will fall within the scope of this disclosure.

[0023] Figure 1 A cross-sectional view of an exemplary 3D storage device 100 according to an embodiment of the present disclosure is schematically shown. The 3D storage device 100 may be a discrete storage device that operates independently. The 3D storage device 100 may also be part of a storage system having multiple storage devices 100. In some embodiments, the 3D storage device 100 may be coupled to a host device (not shown) or embedded in a host device. In such cases, the 3D storage device 100 may be controlled by a controller of the host device. The host device may include computing devices or electronic devices, such as mobile phones, smartphones, smartwatches, tablets, laptops, personal computers, data servers, workstations, and other host devices.

[0024] Optionally, the 3D storage device 100 may include a storage array device 110 and peripheral devices 120. The storage array device 110 may include storage cells forming one or more 3D arrays. The peripheral devices 120 may include circuitry as a controller to control the operation of the 3D storage device 100. In some embodiments, the storage array device 110 and peripheral devices 120 may be fabricated separately and then joined together to form a stacked structure, such as... Figure 1 As shown in the diagram. Alternatively, the memory array device 110 and the peripheral device 120 can be integrated into a single device. For example, the peripheral device 120 can be fabricated first, and then the memory array device 110 can be fabricated on top of the peripheral device 120, using the peripheral device 120 as a substrate. In some other embodiments, the memory array device 110 and the peripheral device 120 can be fabricated separately and then mounted side-by-side on a printed circuit board (PCB).

[0025] Figure 2A block diagram of a 3D memory device 200 according to an embodiment of the present disclosure is shown. The 3D memory device 200 may include a memory array 210 and circuitry 220. The memory array 210 may include a 3D array of memory cells (not shown). The circuitry 220 may include control circuitry 222, an input / output (I / O) interface 224, a page register 226, a row decoder 228, and a column decoder 230. The row decoder and column decoder may also be referred to as an X decoder and a Y decoder, respectively. Furthermore, the circuitry 220 may include Y-path circuitry (not shown). The Y-path circuitry is connected to the column decoder 230 (i.e., the Y decoder) and is arranged to allocate bitline paths based on the output transmitted from the column decoder 230. The control circuitry 222 may act as a controller implementing various functions of the 3D memory device 200. For example, the control circuitry 222 may implement read operations, write operations, and erase operations. I / O interface 224 may include I / O circuitry to receive command signals, address signals, and data signals from the 3D storage device 200 and to transmit data signals and status information from the 3D storage device 200 to an external device (e.g., a host device). Row decoder 228 may select one or more word lines of storage array 210, and column decoder 230 may select one or more bit lines of storage array 210. Row decoder 228 and column decoder 230 may also receive different voltages from voltage generator circuitry (not shown) and pass the received voltages to the selected word lines and the selected bit lines. Page register 226 may include one or more page registers and temporarily stores incoming or outgoing data when data is transferred between I / O interface 224 and storage array 210 during write or read operations. Optionally, page register 226 may include sensing devices or sense amplifiers (not shown) to sense the data status of the memory cells of storage array 210. For example, the data state of a memory cell can be detected by sensing the state of the bit lines connected to the memory cell. As used herein, the term "connected" refers to an electrical connection.

[0026] 3D NAND storage devices can logically comprise one or more NAND targets. A NAND target can contain one or more logical units (LUNs). A LUN can contain one or more faces. A face can contain one or more blocks. A block can contain multiple pages. A page, containing several bytes or words, is the smallest addressable unit for read and write operations. A LUN can be the smallest unit capable of independently executing commands and reporting status. NAND storage cells within a block can be reset together during a block erase operation.

[0027] One or more page registers (also known as page buffers) can be configured to be used for and connected to each face. Data passed to and from the page can be temporarily stored in the page registers. For example, a page register can store a portion of data while another portion of that data is written to the page. In some cases, when a write operation, also known as a programming operation, is performed at the NAND target, the page registers of all faces of the LUNs on the NAND target are cleared or reset. In other cases, when a write operation is performed at the NAND target, the page registers of all faces of the selected LUNs on the target are reset. In the above cases, the page registers in the face, whose page data remains unchanged, are reset, which increases the number of registers undergoing the reset process. Therefore, peak power, total power, and power noise may be unnecessarily increased during the write operation.

[0028] Figure 3 A top view schematically illustrating the construction of a 3D array device 300 according to various embodiments of the present disclosure is shown. This top view is taken along the XY plane from above a 3D memory die 301 of the 3D array device 300. The 3D memory die 301 can be divided into faces. For example, four faces can form a LUN. One or more LUNs can form a NAND target of the 3D array device 300. As an example, the 3D array device 300 may include a NAND target containing two LUNs, such as LUN 0 and LUN 1. Reference Figure 3 Each LUN may have, for example, faces 0-3, and each face may also be divided into blocks, for example, blocks 0-3. Furthermore, each block may contain pages (not shown) where NAND storage cells are arranged. The number of targets, LUNs, faces, and blocks described above is exemplary and for illustrative purposes only. According to various embodiments of this disclosure, other numbers of targets, LUNs, faces, and blocks larger or smaller than those described above may be used in the disclosed 3D array device 300.

[0029] Figure 4 and Figure 5 A schematic top view and schematic cross-sectional view of a portion 400 of a 3D array device 300 at a specific stage in an exemplary fabrication process according to an embodiment of the present disclosure are shown. Reference Figure 3 Part 400 can represent a portion of block 2 of face 1 of LUN 1. For example... Figure 4 As shown, the top view is in the XY plane, and the cross-sectional view is in the YZ plane. Figure 5 The cross-sectional view shown is along Figure 4 The line AA' is intercepted. For example... Figure 5As shown, a portion 400 or 3D array device 300 may include a substrate 410, a doped region 420, and a semiconductor layer 430. The substrate 410 may include a semiconductor material, such as single-crystal silicon. In some embodiments, the top portion of the substrate 410 may be doped with an n-type dopant via ion implantation and / or diffusion to form the doped region 420. The semiconductor layer 430 may be formed on the doped region 420 and may comprise, for example, n-type doped polycrystalline silicon (polysilicon). A layer stack 440 may be fabricated on the semiconductor layer 430. The layer stack 440 may include dielectric layers 441 and conductor layers 442 alternately stacked on top of each other. The dielectric layer 441 may comprise a dielectric material (e.g., silicon oxide), and the conductor layer 442 may comprise a conductive material (e.g., tungsten (W)). The term "conductive" as used herein refers to electrical conductivity. The layer stack may include 64 pairs, 128 pairs, or more than 128 pairs of dielectric layers 441 and conductor layers 442.

[0030] refer to Figure 4 and Figure 5 The channel vias 450 are arranged to extend in the Z direction and form an array of predetermined patterns in the XY plane. The channel vias 450 may be cylindrical or columnar, extending through the layer stack 440, the semiconductor layer 430, and partially penetrating the doped region 420. In this disclosure... Figure 4 and Figure 5 The number, size, and arrangement of the channel holes 450 shown in the other figures are exemplary and for illustrative purposes; however, any suitable number, size, and arrangement may be used for the disclosed 3D array device 300 according to various embodiments of the present disclosure.

[0031] A functional layer 451 may be deposited within the channel via 450. The functional layer 451 may include a barrier layer 452 on the sidewalls and bottom of the channel via for preventing charge outflow, a charge trapping layer 453 on the surface of the barrier layer 452 for storing charge during operation of the 3D array device 300, and a tunneling insulating layer 454 on the surface of the charge trapping layer 453. In some embodiments, the functional layer 451 may have an oxide-nitride-oxide (ONO) structure. That is, the barrier layer 452 may be a silicon oxide layer deposited on the sidewalls of the channel via 450, the charge trapping layer 453 may be a silicon nitride layer deposited on the barrier layer 452, and the tunneling insulating layer 454 may be another silicon oxide layer deposited on the charge trapping layer 453.

[0032] A channel layer 455 may be deposited on top of the tunneling insulating layer 454. The channel layer 455 is also referred to as a "semiconductor channel" and in some embodiments may include polysilicon. Similar to the channel via, the channel layer 455 extends through the layer stack 440 and into the doped region 420. A semiconductor layer 430 may be formed on the doped region 420 and on certain sidewalls or side portions of the channel layer 455, and may be connected to the doped region 420 and the channel layer 455. In some embodiments, the semiconductor layer 430 may serve as an array common source. After the channel layer 455 is formed, the channel via 450 may be filled with an oxide material 456. The functional layer 451 and the channel layer 455 formed in the channel via 450 can be considered as a channel structure.

[0033] like Figure 5 As shown, a portion of each functional layer 451 in the via 450 may be located between a portion of the conductor layer 442 and a portion of the channel layer 455. Each conductor layer 442 may connect to a NAND memory cell in the XY plane and is configured as a word line of the 3D array device 300. The channel layer 455 formed in the via 450 may be configured to connect a string of NAND memory cells along the Z direction. One end of the channel layer 455 may be connected to a bit line of the 3D array device 300. Accordingly, the portion of the functional layer 451 in the XY plane of the via 450, as part of the NAND memory cell, may be arranged between the conductor layer 442 and the channel layer 455, i.e., between the word line and the channel layer connected to the bit line. The NAND memory cell (including the portion of the conductor layer 442 surrounding a portion of the via 450) may be considered as a field-effect transistor having a control gate, a source, and a drain. The portion of the conductor layer 442 surrounding a portion of the via 450 may serve as a control gate for the transistor. The 3D array device 300 can be viewed as a 2D array comprising strings of NAND memory cells (such strings are also referred to as "NAND strings"). Each NAND string may contain multiple NAND memory cells and extends vertically toward the substrate 410. The NAND strings can form a 3D array of NAND memory cells. A NAND string may correspond to a transistor string containing multiple field-effect transistors connected in series along the channel layer 455 in the Z direction. Accordingly, the transistor strings can form a 3D array of field-effect transistors.

[0034] Figure 6 and Figure 7 A schematic cross-sectional view of a portion 400 of a 3D array device 300 at a specific stage in an exemplary fabrication process according to an embodiment of the present disclosure is shown. Figure 6As shown, a dielectric layer 457 can be deposited over the layer stack 440 and the via 450. Furthermore, vias 460 and 461, and a conductive layer 462, can be formed for interconnects within the dielectric layer 457. For example, some of the vias 460 can be connected to the channel layer 455. A dielectric material can then be deposited to thicken the dielectric layer 457, and connection pads 463 can be formed over the vias 461 and connected to the vias 461. Some of the connection pads 463 can be connected to the channel layer 455 through the vias 460-461 and the conductive layer 462. The vias 460-461, the conductive layer 462, and the connection pads 463 can be fabricated using a conductive material (e.g., W).

[0035] Figure 6 The channel structure and conductor layer 442 shown in the cross-sectional view can be represented in part 480 of the same block as part 400 (i.e., block 2 of face 1 of LUN 1 of 3D array device 300). Figure 6 The portion 480, whose boundary is depicted by dashed lines, can contain multiple NAND strings or transistor strings. Figure 7 The diagram schematically illustrates a portion of the field-effect transistor and circuitry at 480, where the circuit diagram replaces a schematic representation of the channel structure and layer stack 440. (See diagram for reference.) Figure 7 As shown, each NAND memory cell is replaced by a field-effect transistor. Channel layers 455 are connected to bit lines BL1-BL8 (e.g., vias 460). Field-effect transistors with their drains connected to the bit lines can be configured as select transistors and are referred to as top select gates (TSGs). Field-effect transistors with their sources connected to the array's common source can also be configured as select transistors and are referred to as bottom select gates (BSGs). The control gate of the TSG can be connected to a select line (e.g., conductor layer 442), while the control gate of the BSG can be connected to another select line (e.g., another conductor layer 442). Word lines WL1-WLn can correspond to conductor layers 442 between the TSGs and BSGs.

[0036] NAND memory cells (or field-effect transistors) connected to conductor layer 442 (i.e., word lines) via control gates can form pages. Thus, there can be n pages connected to word lines WL1-WLn respectively. NAND memory cells (or field-effect transistors) connected to channel layer 455, which is connected to bit lines, can form NAND strings or transistor strings. For example... Figure 7 As shown, transistor strings S1-S8 are connected to bit lines BL1-BL8, respectively. In some embodiments, a page can be considered a row, and a NAND string can be considered a column. The address of the NAND memory can include row addresses and column addresses. The row address indicates the page, block, or LUN to be accessed, while the column address indicates the byte or word within the page to be accessed.

[0037] Figure 8 A schematic cross-sectional view of a portion 470 of a peripheral device according to an embodiment of the present disclosure is shown. The peripheral device may include a semiconductor substrate 471, such as monocrystalline silicon. Control circuitry (e.g., reference...) Figure 2 The control circuitry 222 can be fabricated on the substrate 471 and is used to facilitate the operation of the 3D memory device. A dielectric layer 472 can be deposited over the substrate 471 and the control circuitry. Connection pads, such as connection pads 473, and vias can be formed in the dielectric layer 472. The connection pads 473 can be configured to connect to the 3D array device 300 and can contain a conductive material, such as W.

[0038] Figure 9 A portion 490 of an exemplary 3D storage device at a specific manufacturing stage, according to an embodiment of the present disclosure, is illustrated schematically. The 3D storage device may include... Figure 6 The 3D array device 300 shown and Figure 8 The peripheral devices shown are configured as control array device 300 or 3D memory device.

[0039] A 3D array device 300 and peripheral devices can be bonded using a flip-chip bonding method to form a 3D memory device, such as... Figure 9 The diagram is schematic. For the 3D array device 300 and peripheral devices, the bottom surface of the substrate 410 or 471 can be referred to as the back surface, and the side with the bonding pads 463 or 473 can be referred to as the front surface or the front side. After the flip-chip bonding process, the bonding pads 463 are bonded to the bonding pads 473 respectively. That is, the 3D array device 300 and peripheral devices are bonded face-to-face and electrically communicated.

[0040] Then, other manufacturing steps or processes can be performed to complete the fabrication of the 3D storage device. For simplicity, details of these other manufacturing steps or processes have been omitted.

[0041] Figure 10 Various embodiments according to this disclosure are shown. Figure 3-9 A schematic organization diagram 500 of a 3D memory device is shown in the middle. As illustrated above, the 3D memory device may exemplary have NAND targets (e.g., NAND target 510) including LUN 0 and LUN 1. The LUNs may be connected to a controller 520, for example, the controller 520 may have a reference... Figure 2 The control circuit 222 functions similarly. Each LUN can, for example, contain four faces, such as faces 0-3. Each face can, for example, contain four blocks, such as blocks 0-3. Each block can, for example, contain several pages. Furthermore, as... Figure 10As shown, page registers can be connected to faces LUN 0 and LUN 1, respectively. In some embodiments, one page register can be connected to one face. Optionally, in some cases, more than one page register can be connected to faces LUN 0 and LUN 1. When a page register is allocated and connected to a face, it can be assumed that the page register works for that face, and that the face includes the page register.

[0042] In some embodiments, certain write operations can be represented by page programming operations, and write commands can be replaced by page programming commands. For example, page programming operations can be arranged to program data to the memory array, and the memory array can be programmed by pages. Optionally, partial page programming can also be implemented. After the controller 520 receives a page programming command, there are two possible scenarios. In the first scenario, after the controller 520 receives a page programming command for the NAND target 510, the controller 520 can reset or clear the page registers of all LUNs of the NAND target. Reference Figure 10 The page registers of all LUNs in NAND target 510 refer to all page registers of faces 0-3 of LUN 0 and LUN 1. Therefore, in the first scheme, after receiving the page programming command, all page registers of faces 0-3 of LUN 0 and LUN 1 are reset. In the second scheme, after controller 520 receives the page programming command for NAND target 510, all page registers of the selected LUN of NAND target 510 are cleared. (See reference...) Figure 10 The page registers of the selected LUN of NAND target 510 indicate all page registers of face 0-face 3 of LUN 0 or LUN 1. For example, in the second scenario, if LUN 0 is selected, the controller 520 resets all page registers of face 0-face 3 of LUN 0 after receiving the page programming command. In the second scenario, if LUN 1 is selected, the controller resets all page registers of face 0-face 3 of LUN 1 after receiving the page programming command.

[0043] However, in many cases, it is not necessary to reprogram all faces of the LUN, and some faces can retain the stored data unchanged during page programming operations. Figure 10 Take LUN 0 as an example. Page programming commands may require page programming actions (i.e., write actions) for one, two, or three faces instead of four. Accordingly, when fewer than four faces require page programming actions, it is not necessary to reset all page registers for faces 0-3. Resetting all faces of all LUNs (e.g., the first scenario) or all faces of a single LUN (e.g., the second scenario) increases the number of page registers cleared by controller 520, and may therefore increase the peak power, total power, and power noise of the 3D memory device during the page reset process.

[0044] Figure 11 Various embodiments according to this disclosure are shown. Figure 10 A schematic timing diagram 1100 illustrates page programming operations for the 3D memory device shown. Timing diagram 1100 schematically presents commands and instructions along a timeline. When dealing with a single face, 80h can represent the first cycle of page programming commands, and 10h can represent the second cycle of page programming commands. When dealing with multiple faces, 80h can represent the first cycle of multi-faceted page programming commands, and 11h can represent the second cycle of multi-faceted page programming commands. In some embodiments of multi-faceted page programming operations, two (or more) pages from different faces can have the same address and can be programmed in parallel (e.g., simultaneously or within the same time period). Alternatively, two (or more) pages from different faces can also be reset in parallel (e.g., simultaneously or within the same time period). Faces in a multi-faceted page programming operation can originate from the same LUN. Alternatively, faces in a multi-faceted page programming operation can originate from different LUNs.

[0045] like Figure 11As shown, after the controller 520 receives the first page programming command, it can check the address, for example, a 6-byte address, and execute a first loop 80h. The controller 520 can determine the face indicated in the address, for example, face 0. The controller 520 can then reset only the page register of the face indicated in the address. If the face indicated in the address has a single page register, only that single page register is reset. If the face indicated in the address has multiple page registers, only those multiple page registers are reset. Accordingly, the controller 520 does not reset the page registers of the other faces of the NAND target 510 and can leave the page registers of the other faces of the NAND target 510 unchanged. Furthermore, the controller 520 can execute a data input command to obtain data signals for the page programming operation, followed by the execution of a second loop of page programming commands (e.g., command 10h). The controller 520 can then receive a second page programming command as multi-faceted page programming. Multi-faceted page programming involves writing to multiple faces, which in various embodiments may originate from LUN 0 and / or LUN 1. The controller 520 can check the address, for example, a 6-byte address, and execute the first loop 80h of the multi-faceted page programming command. The controller 520 can determine the face indicated in the address, for example, face 2. Then, the controller 520 can reset only the page registers of the face indicated in the address (e.g., face 2 from LUN 0 and LUN 1). Therefore, the controller 520 does not reset the page registers of other faces of the NAND target 510 not indicated in the address, and can leave the page registers of other faces of the NAND target 510 unchanged. Furthermore, another data input command is executed to obtain data signals for the multi-faceted page programming operation, and the controller 520 executes the second loop of the page programming command (e.g., command 11h). Therefore, only one or more page registers of one or more faces indicated in the page programming command are reset. Compared to clearing all page registers of all LUNs or clearing all page registers of a selected LUN, the peak power and total power during the page register reset process can be reduced. Furthermore, the power noise of the 3D memory device can be improved.

[0046] Figure 12 A schematic flowchart 1200 is shown for performing page programming operations at a 3D memory device according to an embodiment of the present disclosure. It is assumed that the 3D memory device has one or more NAND targets, and each NAND target includes one or more faces. Each face contains a block of pages having NAND memory cells. Each face also includes one or more page registers.

[0047] At 1210, the controller of the 3D storage device receives a page programming command for page programming operations at the NAND target and begins checking or detecting the page programming command. The page programming command may be a set of commands including multiple commands and communication entries. At 1220, the controller detects the page programming command and obtains the address from it. This address may be, for example, a six-byte address, which provides the location for the page programming operation. The controller checks or detects the address after obtaining it. At 1230, the controller identifies or determines the face indicated in the address. The indicated face represents the location where page programming will be performed.

[0048] At address 1240, the controller clears the page registers of the face indicated in the address during reset. If the face indicated in the address has multiple page registers, multiple page registers can be reset. If the NAND target has a single LUN, the page register(s) of the face(s) indicated in the address are cleared, or only the page register(s) of the face(s) are cleared, while the page registers of the other faces (or remaining faces) of the single LUN are not cleared and remain unchanged. That is, the controller retains the state of the page registers of the other faces of the single LUN (or NAND target) not indicated in the address. If the NAND target has multiple LUNs, the page register(s) of the face(s) indicated in the address are cleared, or only the page register(s) of the face(s) are cleared, while the page registers of the other faces (or remaining faces) of the multiple LUNs (or NAND target) are not cleared and remain unchanged. That is, the controller retains the state of the page registers of the other faces of the NAND target not indicated in the address.

[0049] If the controller receives a multi-page programming command for multi-page programming operations at 1210, it checks or detects the multi-page programming command. At 1220, the controller detects the multi-page programming command and obtains the address from the multi-page programming command. The controller then checks or detects this address. At 1230, the controller identifies or determines the face indicated in that address. The indicated face represents the location where multi-page programming will be performed.

[0050] At address 1240, the controller clears the page registers of the face indicated in the address during reset. If the NAND target has a single LUN, the page registers of the face indicated in the address are cleared, or only the page registers of that face are cleared, while the page registers of the other faces of the single LUN (or the other faces of the NAND target) are not cleared and remain unchanged. That is, the controller retains the state of the page registers of the other faces of the NAND target not indicated in the address. If the NAND target has multiple LUNs, the page registers of the face indicated in the address are cleared, or only the page registers of that face are cleared, while the page registers of the other faces of the multiple LUNs (or the other faces of the NAND target) are not cleared and remain unchanged. That is, the controller retains the state of the page registers of the other faces of the NAND target not indicated in the address.

[0051] Figure 13A Block diagram 1300 illustrates an exemplary implementation of a storage device consistent with the disclosed embodiments. This storage device may include a controller (not shown), for example, regarding... Figure 2 The control circuit 222. For example... Figure 13A As shown, the implementation may include input and output control circuitry IO_CTRL1302, page buffer control circuitry PB_CTRL1304 for each face, and facility circuitry 1306. Other circuitry may also be included.

[0052] IO_CTRL 1302 can be a single instance, while PB_CTRL 1304 can be provided for each face. The controller can send commands to PB_CTRL 1304. IO_CTRL 1302 can receive the "80h_setcache" signal from the command and can generate or enable signals, and transmit these signals to PB_CTRL 1304. PB_CTRL 1304 may include reset circuitry for resetting the page register based on control signals from IO_CTRL 1302. Furthermore, facility circuitry 1306 can provide facility functionality between IO_CTRL 1302 and PB_CTRL 1304.

[0053] Furthermore, the input and output control circuit IO_CTRL 1302 can be located in the data path of the storage device (e.g., the controller), and the facility circuit 1306 can be located in the Y path of the storage device. That is, the facility circuit 1306 can be located in the Y path circuit of the storage device, and the IO_CTRL 1302 can be located in the data path circuit of the storage device.

[0054] Specifically, facility circuit 1306 can receive address information from a controller or address register (not shown) and can generate a control signal or enable signal addr_plane_dp for an individual plane and transmit the control signal or enable signal addr_plane_dp to the reset circuit of PB_CTRL 1304. Therefore, the reset circuit can combine the control signal or enable signal addr_plane_dp from facility circuit 1306 with the control signal / enable signal from IO_CTRL 1302 to generate appropriate control signals / enable signals for all individual planes. For example, a page register reset in PB_CTRL 1304 for a specific plane based on the address information can be enabled by its corresponding addr_plane_dp signal, while a page register reset in PB_CTRL 1304 for any other plane is not enabled by the corresponding addr_plane_dp signal. Therefore, a page register reset can be performed only on one or more page registers of a selected plane based on the address-information-based addr_plane_dp signal.

[0055] Figure 13B It shows Figure 13A The embodiment block diagram 1300 shown is an example of a simplified reset circuit in PB_CTRL 1304. (As...) Figure 13B As shown, an enable signal (e.g., row_en[5:0]) for an individual plane can be generated by the PB_CTRL circuit, thus enabling the individual plane for page register reset. Simultaneously, the enable signal can be combined with the addr_plane_dp signal to generate the final page register reset signal, thereby enabling a specific plane based on address information. The addr_plane_dp signal can be enabled / disabled using a bitmap, or it can be enabled / disabled using a single on / off signal.

[0056] For example, for a single 16KB face and a configuration with four faces (4 × 16KB), after receiving the six-byte address of the page programming command (80h), the controller can reset only the page registers of that single face (whose address is indicated by the address). Furthermore, for multi-faceted page programming, the controller will continue to reset only the page registers indicated by the six-byte address while executing command 80h or 81h. Therefore, the peak power during the page register reset of command 80h or 81h can be reduced, as can the total power consumption when programming fewer than four faces, and / or power noise that might affect background page register programming can also be reduced.

[0057] In addition, the controller can send a switching signal c_vsc_pc_multi to facility circuit 1306 to enable or disable the facilitation functions of facility circuit 1306. This switching signal, also known as a "trim" bit signal, controls whether control signals or enable signals for individual faces can be passed to the face's PB_CTRL 1304. The trim bit signal can be used by the controller to enable / disable facility functions and / or maintain backward compatibility with other page programming standards.

[0058] For example, such as Figure 13B As shown, when c_vsc_pc_multi is "0", the addr_plane_dp signal is not propagated to the plane's PB_CTRL 1304. In this case, only control signals from IO_CTRL1302 are propagated to the plane's PB_CTRL 1304. In the four-plane (4×16KB) example above, even if a page programming command is applied to only a single plane (16KB), all page registers in the four planes (4×16KB) can be reset. Other reset mechanisms can also be used.

[0059] Figure 14 A timing diagram 1400 illustrating page register reset of a 3D memory device according to various embodiments of the present disclosure is shown. It is assumed that the 3D memory device has a NAND target comprising four LUNs (e.g., LUN 0-LUN 3). Each LUN of the 3D memory device has four faces (e.g., face 0-face 3), which are respectively connected to page registers 0-3.

[0060] At time t1, the controller of the 3D memory device receives a command and an address signal. The received command includes a page programming command 80h. The address signal includes, for example, a 6-byte address. The controller detects that this 6-byte address indicates face 0 of LUN 3. After determining that face 0 of LUN 3 is indicated in the address signal, the controller activates page register 0 of LUN 3 corresponding to face 0 of LUN 3 (i.e., before time t2). Figure 14 The latched page registers are reset. Accordingly, the controller does not reset the remaining page registers of LUN 0-LUN 3 (i.e., all page registers of the NAND target except page register 0 of LUN 3), and maintains or preserves the state of the remaining page registers.

[0061] At time t2, the controller receives a multi-faceted page programming command 80h and the command's address signal. The controller detects that the address signal contains, for example, a 6-byte address indicating face 2 of LUN 0-LUN 3. Upon determining that face 2 of LUN 0-LUN 3 is indicated in the address signal, the controller causes page register 2 of LUN 0-LUN 3 (i.e., after time t2) to open. Figure 14The latched page registers are reset. The four reset page registers correspond to face 2 of LUN 0-LUN 3 respectively. Therefore, the controller does not reset the remaining page registers of LUN0-LUN 3 (i.e., all page registers of the NAND target except for page register 2 of each LUN) and keeps or maintains the state of the remaining page registers unchanged.

[0062] Therefore, embodiments of this disclosure allow for the implementation of page programming and multi-faceted page programming operations of 3D memory devices with lower power consumption. In page programming, only one or more page registers of one or more faces of the NAND target indicated in the page programming command are reset. In multi-faceted page programming, only the page registers of the faces of the NAND target indicated in the multi-faceted page programming command are reset. In both page programming and multi-faceted page programming operations, page registers of faces of the NAND target not indicated in the command are not unnecessarily cleared and remain unchanged. Thus, lower peak power and lower total power consumption can be achieved during the page register reset process compared to clearing all page registers of all LUNs of the NAND target or clearing all page registers of selected LUNs of the NAND target. Furthermore, power noise of the 3D memory device can be improved.

[0063] Although the principles and implementation methods of this disclosure have been described in this specification using specific examples, the foregoing description of the embodiments is only intended to aid in understanding this disclosure. Furthermore, features of the foregoing different embodiments can be combined to form additional embodiments. Those skilled in the art can make modifications to the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A programming method for a storage device having multiple surfaces, comprising: Receive programming commands for the storage device; Obtain the address associated with the programming command; The first and second faces among the plurality of faces are determined based on the address; as well as The page registers of the first face determined by the address are cleared, and the page registers of the second face determined by the address are cleared, while one or more page registers of one or more of the remaining faces are retained, wherein clearing the page registers of the first face determined by the address and clearing the page registers of the second face determined by the address are performed in parallel.

2. The method according to claim 1, further comprising: Maintain the state of the one or more page registers of the remaining one or more of the plurality of faces.

3. The method according to claim 1, wherein: The first surface and the second surface are derived from the same logical unit (LUN) of the memory device or from multiple LUNs of the memory device.

4. The method according to claim 1, wherein: The first face comes from the first logic unit (LNU) of the storage device, and one or more of the remaining faces come from the second LNU of the storage device.

5. The method according to claim 1, wherein: The first surface and one or more of the remaining surfaces originate from the same logical unit (LUN) of the storage device.

6. A storage device, comprising: One or more logical units (LUNs), each LUN comprising multiple faces; Multiple page registers, each page register corresponding to one of the multiple faces; as well as A controller, configured to execute commands, wherein the controller is configured to: Receive programming commands for the storage device; Obtain the address associated with the programming command; Determine the first and second faces among the plurality of faces based on the address; and The page register corresponding to the first face in the plurality of page registers is cleared, and another page register corresponding to the second face in the plurality of page registers is cleared, while one or more of the remaining page registers in the plurality of page registers are retained, wherein clearing the page register corresponding to the first face in the plurality of page registers and clearing the other page register corresponding to the second face in the plurality of page registers are performed in parallel.

7. The storage device according to claim 6, wherein, The controller is also configured to: Maintain the state of one or more of the remaining page registers among the plurality of page registers.

8. The storage device according to claim 6, wherein: The first face and the second face are from the same LUN or from different LUNs.

9. The storage device according to claim 6, wherein: The first face of the plurality of faces comes from the first LUN of the plurality of LUNs, and one or more of the remaining faces of the plurality of faces come from the second LUN of the plurality of LUNs.

10. The storage device according to claim 6, wherein: The first face of the plurality of faces and one or more of the remaining faces of the plurality of faces come from the same LUN of the plurality of LUNs.

11. The storage device according to claim 6, further comprising: Three-dimensional (3D) NAND storage devices.

12. A method for a storage device having multiple surfaces, comprising: Receive programming commands for the storage device; Obtain the address associated with the programming command; The first and second faces among the plurality of faces are determined according to the address, so as to clear the page register of the first face determined according to the address and clear the page register of the second face determined according to the address, wherein clearing the page register of the first face determined according to the address and clearing the page register of the second face determined according to the address are parallel operations; as well as Maintain the state of one or more page registers of one or more of the remaining faces among the plurality of faces.

13. The method according to claim 12, wherein: The first surface and the second surface are derived from the same logical unit (LUN) of the memory device or from multiple LUNs of the memory device.

14. The method according to claim 12, wherein: The first face comes from the first logic unit (LNU) of the storage device, and one or more of the remaining faces come from the second LNU of the storage device.

15. The method according to claim 12, wherein: The first surface and one or more of the remaining surfaces originate from the same logical unit (LUN) of the storage device.

16. A storage device comprising: Multiple faces; as well as A reset circuit, wherein the reset circuit is configured to clear the plurality of surfaces, and the reset circuit is configured to: Based on the address, a first control signal for clearing the first and second faces of the plurality of faces is obtained; and The page registers of the first face and the second face are cleared according to the first control signal, while one or more page registers of one or more of the remaining faces are retained, wherein clearing the page registers of the first face and clearing the page registers of the second face are performed in parallel.

17. The storage device according to claim 16, wherein, The reset circuit is also configured to: Maintain the state of the one or more page registers of the remaining one or more of the plurality of faces.

18. The storage device of claim 16, further comprising: A facility circuit configured to transmit the first control signal to the reset circuit based on the address; as well as A controller configured to transmit the address to the facility circuitry.

19. The storage device of claim 18, further comprising: An input / output (I / O) circuit is configured to transmit a second control signal to the reset circuit after receiving a programming command from the controller.

20. The storage device according to claim 18, wherein: The facility circuit is located in the Y-path circuit of the storage device.

21. The storage device according to claim 18, wherein, The controller is also configured to: A switch signal is transmitted to the facility circuitry to control the emptying.

22. The storage device according to claim 21, wherein: The transmission of the first control signal from the facility circuit to the reset circuit is controlled by the switch signal.

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