High-performance TFT array substrate and manufacturing method thereof

Abstract

The application relates to the technical field of liquid crystal display screens, and provides a high-performance TFT array substrate and a manufacturing method thereof, which comprises the following steps: a glass substrate; a first metal layer fixedly arranged on the upper surface of the glass substrate and forming a gate electrode; a gate insulation layer fixedly arranged on the upper surface of the first metal layer and the glass substrate; a left active layer fixedly arranged on the upper surface of the gate insulation layer; a right active layer fixedly arranged on the upper surface of the gate insulation layer; a bridging layer with the left and right ends connected with the left active layer and the right active layer; a second metal layer fixedly arranged on the upper surface of the gate insulation layer and connected with the left active layer to form a source electrode; and a third metal layer fixedly arranged on the upper surface of the gate insulation layer and connected with the right active layer to form a drain electrode. The application has the advantages that the channel length of the active layer is shortened without shortening the distance between the source electrode and the drain electrode of the TFT device, and the TFT array substrate has the advantages of quick response, large on-state current, small threshold voltage and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of liquid crystal display screens, and in particular to a high-performance TFT array substrate and a manufacturing method thereof. Background Art

[0002] With the rapid development of artificial intelligence, TFT-LCD screen technology has also been continuously improved. High definition, fast speed, and low power consumption will become the development trend of TFT-LCD screens.

[0003] To achieve high-performance displays, manufacturers currently miniaturize TFT devices by shortening the active layer channel length. This shortened active layer channel length offers advantages such as higher on-state current, faster device response, and lower threshold voltage. However, the design of the active layer channel length is limited by the distance between the source and drain electrodes of TFT devices, primarily due to the risk of short circuits if the source and drain electrodes are too close. After years of technological development, the source and drain spacing of current thin-film transistors (TFTs) is typically kept to a safe minimum distance, generally 5-6μm.

[0004] See Figure 1 , which is a schematic diagram of the structure of a traditional TFT device. The active layer is a semiconductor, and the active layer channel length refers to the length of the semiconductor from the source to the drain.

[0005] Therefore, how to shorten the active layer channel length without shortening the source-drain distance of the TFT device is a technical problem that needs to be solved urgently in this field. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a high-performance TFT array substrate and a manufacturing method thereof, which can shorten the active layer channel length without shortening the source-drain distance of the TFT device.

[0007] The present invention is implemented as follows: a high-performance TFT array substrate, comprising:

[0008] glass substrate;

[0009] A first metal layer is fixedly disposed on the upper surface of the glass substrate to form a gate;

[0010] a gate insulating layer fixedly disposed on the upper surfaces of the first metal layer and the glass substrate;

[0011] a left active layer, fixedly disposed on the upper surface of the gate insulating layer and also located above the left end of the first metal layer;

[0012] A right active layer is fixedly arranged on the upper surface of the gate insulating layer and above the right end of the first metal layer;

[0013] A bridge layer is fixedly arranged on the upper surface of the gate insulating layer and connected with the left active layer and the right active layer at the left end and the right end respectively;

[0014] A second metal layer is fixedly arranged on the upper surface of the gate insulating layer and connected with the left active layer to form a source electrode;

[0015] A third metal layer is fixedly arranged on the upper surface of the gate insulating layer and connected with the right active layer to form a drain electrode.

[0016] Further, the display panel further comprises:

[0017] A pixel electrode is fixedly arranged on the upper surface of the gate insulating layer and connected with the third metal layer;

[0018] A conductive layer is fixedly arranged on the upper surface of the gate insulating layer and located beside the pixel electrode;

[0019] A passivation layer is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left active layer, the right active layer, the bridge layer, the gate insulating layer, the pixel electrode and the conductive layer, and the passivation layer is provided with a through hole;

[0020] A common electrode is fixedly arranged on the upper surface of the passivation layer and connected with the conductive layer through the through hole.

[0021] Further, the display panel further comprises:

[0022] A conductive layer is fixedly arranged on the upper surface of the gate insulating layer;

[0023] A common electrode is fixedly arranged on the upper surface of the gate insulating layer and connected with the conductive layer;

[0024] A passivation layer is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left active layer, the right active layer, the bridge layer, the gate insulating layer, the common electrode and the conductive layer, and the passivation layer is provided with a through hole;

[0025] A pixel electrode is fixedly arranged on the upper surface of the passivation layer and connected with the third metal layer through the through hole.

[0026] Further, the first metal layer, the second metal layer, the third metal layer and the conductive layer are any one of an MO single-layer structure, a Ti single-layer structure, an MO / AL / MO three-layer structure, a Ti / AL / Ti three-layer structure, an AL / MO double-layer structure and an AL / Ti double-layer structure.

[0027] Further, the left active layer and the right active layer are both IGZO material, and the bridge layer, the pixel electrode and the common electrode are all ITO material.

[0028] Further, the gate insulation layer is a single-layer structure of SiOx or a double-layer structure of SiNx / SiOx, and the passivation layer is SiOx or SiNO or SiNx material.

[0029] Further, the through hole is an inverted cone shape.

[0030] A manufacturing method of a high-performance TFT array substrate comprises the following steps.

[0031] S1, plating a first metal layer on the upper surface of a glass substrate to form a gate electrode;

[0032] S2, plating a gate insulation layer on the upper surface of the glass substrate and the first metal layer;

[0033] S3, plating a bridge layer on the upper surface of the gate insulation layer, the bridge layer being above the first metal layer;

[0034] S4, plating a left active layer and a right active layer on the upper surface of the gate insulation layer, the left active layer and the right active layer being above the first metal layer and being connected to the left and right ends of the bridge layer respectively;

[0035] S5, plating a second metal layer on the upper surface of the gate insulation layer, the second metal layer being further connected to the left active layer to form a source electrode;

[0036] S6, plating a third metal layer on the upper surface of the gate insulation layer, the third metal layer being further connected to the right active layer to form a drain electrode.

[0037] Further, a pixel electrode is plated on the upper surface of the gate insulation layer, the pixel electrode being beside the bridge layer;

[0038] The S5 further comprises that the third metal layer is further connected to the pixel electrode; and a conductive layer is plated on the upper surface of the gate insulation layer, the conductive layer being beside the pixel electrode.

[0039] Further, it further comprises:

[0040] S6, plating a passivation layer on the upper surface of the second metal layer, the third metal layer, the left active layer, the right active layer, the bridge layer, the pixel electrode, the conductive layer and the gate insulation layer, the passivation layer being provided with a through hole, and the conductive layer being exposed to the through hole.

[0041] S7, plating a common electrode on the passivation layer, the common electrode being further connected to the conductive layer through the through hole.

[0042] The advantages of the present application are: 1. Different from the traditional TFT device, the present application replaces a section in the middle of the active layer with a bridge layer, the bridge layer is a conductor and the active layer is a semiconductor, so that the overall channel length of the active layer is shortened, but the distance between the source and the drain remains unchanged, ensuring the safety of the device; that is, under the premise of not shortening the distance between the source and the drain of the TFT device, the channel length of the active layer is shortened, the TFT array substrate of the present application has the advantages of fast response, large on-state current, small threshold voltage, etc., and improves the performance of the display screen after practical application. 2. Since the ITO material has excellent conductivity and light transmission characteristics, the materials of the bridge layer and the pixel electrode of the TFT device of the present application are both ITO, the film formation of the bridge layer and the pixel electrode under this structure is carried out in the same process, which simplifies the structure of the array substrate, improves production, and reduces cost. BRIEF DESCRIPTION OF DRAWINGS

[0043] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0044] Figure 1 is a schematic diagram of the structure of the traditional TFT device in the background art.

[0045] Figure 2 is the manufacturing process of the high-performance TFT array substrate of the present application Figure 1 .

[0046] Figure 3 is the manufacturing process of the high-performance TFT array substrate of the present application Figure 2 .

[0047] Figure 4 is the manufacturing process of the high-performance TFT array substrate of the present application Figure 3 .

[0048] Figure 5 is the manufacturing process of the high-performance TFT array substrate of the present application Figure 4 .

[0049] Figure 6 is the manufacturing process of the high-performance TFT array substrate of the present application Figure 5 .

[0050] Figure 7 is the manufacturing process of the high-performance TFT array substrate of the present application Figure 6 .

[0051] Figure 8 is the manufacturing process of the high-performance TFT array substrate of the present application Figure 7 .

[0052] Figure 9 is to Figure 8Fig. 2 is a schematic diagram of the pixel electrode and the common electrode after their positions are interchanged in Fig. 1.

[0053] Reference numerals: glass substrate 1; gate 2; gate insulating layer 3; active layer 4; left active layer 41; right active layer 42; bridging layer 5; source 6; drain 7; pixel electrode 8; conductive layer 9; passivation layer 10; via 101; common electrode 20. DETAILED DESCRIPTION

[0054] The embodiment of the present application provides a high-performance TFT array substrate and a manufacturing method thereof, solves the design limitation of the channel length of the active layer on the distance between the source and the drain of the TFT device in the background art, and shortens the channel length of the active layer without shortening the distance between the source and the drain of the TFT device.

[0055] The technical solution in the embodiment of the present application is as follows to solve the above-mentioned shortcomings:

[0056] Different from the traditional TFT device, the TFT device of the present application replaces a section of the active layer with a bridging layer, the bridging layer is a conductor, the active layer is a semiconductor, so that the overall channel length of the active layer is shortened, that is, the length of the semiconductor is shortened, but the distance between the source and the drain remains unchanged, ensuring the safety of the device.

[0057] The channel length of the active layer has a significant influence on the gate characteristics of the thin film transistor (TFT), and the general trend is that the shorter the channel, the greater the on-state current, and the longer the channel, the smaller the on-state current. DS This can be attributed to the fact that as the channel length increases, the probability of carrier capture during the drift process increases, and the decrease in carrier density also causes the threshold voltage to increase, which also causes the source-drain current I to grow slowly, causing the subthreshold swing to increase, that is, the response speed of the device will decrease.

[0058] In order to better understand the above technical solution, the above technical solution will be described in detail in combination with the drawings of the specification and the specific embodiments.

[0059] Reference Figures 1 to 9 to the preferred embodiment of the present application.

[0060] In combination Figure 8 , a high-performance TFT array substrate comprises:

[0061] A glass substrate 1;

[0062] A first metal layer is fixedly arranged on the upper surface of the glass substrate 1 to form a gate 2;

[0063] A gate insulation layer 3 is fixedly arranged on the upper surface of the first metal layer and the glass substrate 1;

[0064] A left active layer 41 is fixedly arranged on the upper surface of the gate insulation layer 3 and above the left end of the first metal layer;

[0065] A right active layer 42 is fixedly arranged on the upper surface of the gate insulation layer 3 and above the right end of the first metal layer;

[0066] A bridge layer 5 is fixedly arranged on the upper surface of the gate insulation layer 3 and connected with the left active layer 41 and the right active layer 42 at the left and right ends respectively;

[0067] A second metal layer is fixedly arranged on the upper surface of the gate insulation layer 3 and connected with the left active layer 41 to form a source 6;

[0068] A third metal layer is fixedly arranged on the upper surface of the gate insulation layer 3 and connected with the right active layer 42 to form a drain 7.

[0069] Different from the conventional TFT device, the TFT device of the present application replaces a section of the active layer with a bridge layer 5, the bridge layer 5 is a conductor, and the left active layer 41 and the right active layer 42 are both semiconductors, so that the overall active layer channel length is shortened, i.e. the length of the semiconductor is shortened, but the distance between the source 6 and the drain 7 remains unchanged, ensuring the safety of the device; that is, under the premise of not shortening the distance between the source 6 and the drain 7 of the TFT device, the active layer channel length is shortened, the TFT array substrate of the present application has the advantages of fast response, large on-state current, small threshold voltage and the like, and improves the performance of the display screen after practical application.

[0070] Further comprising: a pixel electrode 8 fixedly arranged on the upper surface of the gate insulation layer 3 and connected with the third metal layer;

[0071] A conductive layer 9 is fixedly arranged on the upper surface of the gate insulation layer 3 and located at the side of the pixel electrode 8;

[0072] A passivation layer 10 is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left active layer 41, the right active layer 42, the bridge layer 5, the gate insulation layer 3, the pixel electrode 8 and the conductive layer 9, and the passivation layer 10 is provided with a through hole 101;

[0073] A common electrode 20 is fixedly arranged on the upper surface of the passivation layer 10 and connected with the conductive layer 9 through the through hole 101.

[0074] The first metal layer (gate 2), the second metal layer (source 6), the third metal layer (drain 7) and the conductive layer 9 are any one of MO single-layer structure, Ti single-layer structure, MO / AL / MO three-layer structure, Ti / AL / Ti three-layer structure, AL / MO double-layer structure and AL / Ti double-layer structure.

[0075] The left active layer 41 and the right active layer 42 are both IGZO material, and the bridge layer 5, the pixel electrode 8 and the common electrode 20 are all ITO material.

[0076] The gate insulating layer 3 is SiOx single-layer structure or SiNx / SiOx double-layer structure, and the passivation layer 10 is SiOx, SiNO or SiNx material.

[0077] The through hole 101 is inverted conical shape, which is convenient for depositing and fixing materials in the hole position.

[0078] In combination Figures 2 to 8 , the manufacturing method of the high-performance TFT array substrate includes the following steps:

[0079] S1, a first metal layer is plated on the upper surface of a glass substrate 1 to form a gate 2; the gate 2 functions to transmit a gate signal to turn on and off a TFT device, and the material can be any one of MO single-layer structure, Ti single-layer structure, MO / AL / MO three-layer structure, Ti / AL / Ti three-layer structure, AL / MO double-layer structure and AL / Ti double-layer structure, PVD film forming is adopted, and acid liquid wet etching is used.

[0080] S2, a gate insulating layer 3 is plated on the upper surface of the first metal layer and the glass substrate 1; the gate insulating layer 3 functions as an insulating medium and also as a capacitive medium between the gate 2 and the active layer, and the material is SiOx single-layer structure or SiNx / SiOx double-layer structure, CVD film forming is adopted, and dry etching is used.

[0081] Considering the current requirements of TFT device is fast response, low power consumption, which is achieved by reducing the TFT device, in order to achieve the miniaturization of the gate insulating layer needs to select the appropriate high K material (such as HfO2), but considering the interface of HfO2 there are more defects, if directly with the active layer or the gate metal contact may affect the stability of the device, so can consider the use of interface is good SiOx or SiNx (SiNx can only be used as a contact film layer with the gate metal layer, if as a contact surface with IGZO, H in the SiNx film layer residual film forming process will destroy the IGZO characteristics) as a contact surface, such as SiOx / HfO2 / SiOx three layer structure as GI insulating layer, in order to ensure the advantages of high K material, HfO2 in the three layer structure in the thickness of SiOx needs to be larger.

[0082] S3, plating a bridge layer 5 on the upper surface of the gate insulating layer 3, the bridge layer 5 is located above the first metal layer;

[0083] Plating a pixel electrode 8 on the upper surface of the gate insulating layer 3, the pixel electrode 8 is located on the side of the bridge layer 5;

[0084] The bridge layer 5 is to connect the left and right active layers together, and the pixel electrode 8 is to serve as an electrode for providing an electric field for liquid crystal molecules. Both are made of ITO and are formed by PVD together and wet etched by acid.

[0085] S4, plating a left active layer 41 and a right active layer 42 on the upper surface of the gate insulating layer 3, the left active layer 41 and the right active layer 42 are located above the first metal layer and are connected to the left and right ends of the bridge layer 5 respectively; the left active layer 41 and the right active layer 42 serve as semiconductor layers and provide carrier channels or close carrier channels under the action of the gate 2 voltage. The material is selected from metal oxide semiconductors such as IGZO, PVD film forming, and wet etching by acid.

[0086] S5, plating a second metal layer on the upper surface of the gate insulating layer 3, the second metal layer is also connected to the left active layer 41 to form a source electrode 6;

[0087] Plating a third metal layer on the upper surface of the gate insulating layer 3, the third metal layer is also connected to the right active layer 42 and the pixel electrode 8 to form a drain electrode 7;

[0088] Plating a conductive layer 9 on the upper surface of the gate insulating layer 3, the conductive layer 9 is located on the side of the pixel electrode 8;

[0089] The source electrode 6, the drain electrode 7 and the conductive layer 9 are used to provide signals to the pixel electrode 8 and the common electrode 20, and are formed by PVD magnetron sputtering, and the material can be selected from any one of MO single-layer structure, Ti single-layer structure, MO / AL / MO three-layer structure, Ti / AL / Ti three-layer structure, AL / MO double-layer structure and AL / Ti double-layer structure, and the etching method is acid wet etching.

[0090] S6, the passivation layer 10 is plated on the upper surface of the second metal layer, the third metal layer, the left active layer 41, the right active layer 42, the bridging layer 5, the pixel electrode 8, the conductive layer 9 and the gate insulating layer 3, the passivation layer 10 is provided with a through hole 101, and the conductive layer 9 is exposed to the through hole 101;

[0091] The passivation layer 10 is used to protect the TFT device and act as a capacitor medium between the pixel electrode 8 and the common electrode 20, and the material can be selected from insulating materials such as SiOx, SiNO or SiNx, and is formed by CVD and dry etching. The purpose of punching above the conductive layer 9 is to transmit the signal of the conductive layer 9 to the common electrode 20.

[0092] S7, the common electrode 20 is plated on the passivation layer 10, and the common electrode 20 is also connected with the conductive layer 9 through the through hole 101.

[0093] The common electrode 20 is used as an electrode for providing an electric field for liquid crystal molecules, and the material is ITO, which is formed by PVD and wet etched by acid.

[0094] In combination Figure 9 In the present application, the positions of the common electrode 20 and the pixel electrode 8 can be interchanged, that is:

[0095] The conductive layer 9 is fixedly arranged on the upper surface of the gate insulating layer 3;

[0096] The common electrode 20 is fixedly arranged on the upper surface of the gate insulating layer 3 and is also connected with the conductive layer 9;

[0097] The passivation layer 10 is fixedly arranged on the upper surface of the second metal layer, the third metal layer, the left active layer 41, the right active layer 42, the bridging layer 5, the gate insulating layer 3, the common electrode 20 and the conductive layer 9, and the passivation layer 10 is provided with a through hole 101;

[0098] The pixel electrode 8 is fixedly arranged on the upper surface of the passivation layer 10 and is also connected with the third metal layer through the through hole 101.

[0099] Since the ITO material has excellent conductivity and light transmission characteristics, the material of the bridge layer 5 and the pixel electrode 8 of the TFT array substrate of the present application is ITO, the film forming of the bridge layer 5 and the pixel electrode 8 under the structure is performed in the same process, so that the structure of the array substrate can be simplified, the production capacity is improved, and the cost is reduced.

[0100] Although the specific embodiments of the present application have been described above, it should be understood by those skilled in the art that the specific embodiments described are only illustrative and are not intended to limit the scope of the present application, and equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.

Claims

1. A high-performance TFT array substrate, characterized in that: include: glass substrate; A first metal layer is fixedly disposed on the upper surface of the glass substrate to form a gate; a gate insulating layer fixedly disposed on the upper surfaces of the first metal layer and the glass substrate; a left active layer, fixedly disposed on the upper surface of the gate insulating layer and also located above the left end of the first metal layer; a right active layer, fixedly disposed on the upper surface of the gate insulating layer and also located above the right end of the first metal layer; a bridging layer, fixedly disposed on the upper surface of the gate insulating layer, with left and right ends respectively connected to the left active layer and the right active layer; a second metal layer, fixedly disposed on the upper surface of the gate insulating layer and connected to the left active layer to form a source electrode; a third metal layer, fixedly disposed on the upper surface of the gate insulating layer and connected to the right active layer to form a drain; a pixel electrode, fixedly disposed on the upper surface of the gate insulating layer and connected to the third metal layer; a conductive layer fixedly disposed on the upper surface of the gate insulating layer and also located on the side of the pixel electrode; a passivation layer fixedly disposed on the upper surfaces of the second metal layer, the third metal layer, the left active layer, the right active layer, the bridge layer, the gate insulating layer, the pixel electrode, and the conductive layer, wherein the passivation layer is provided with a through hole; a common electrode, fixedly disposed on the upper surface of the passivation layer and connected to the conductive layer through the through hole; The first metal layer, the second metal layer, the third metal layer, and the conductive layer are any one of a MO single-layer structure, a Ti single-layer structure, a MO / AL / MO three-layer structure, a Ti / AL / Ti three-layer structure, an AL / MO double-layer structure, and an AL / Ti double-layer structure; The left active layer and the right active layer are both made of IGZO material, and the bridge layer, pixel electrode, and common electrode are all made of ITO material.

2. The high-performance TFT array substrate according to claim 1, characterized in that: Also includes: a conductive layer, fixedly disposed on the upper surface of the gate insulating layer; a common electrode, fixedly disposed on the upper surface of the gate insulating layer and connected to the conductive layer; a passivation layer fixedly disposed on the upper surfaces of the second metal layer, the third metal layer, the left active layer, the right active layer, the bridge layer, the gate insulating layer, the common electrode, and the conductive layer, wherein the passivation layer is provided with a through hole; The pixel electrode is fixedly arranged on the upper surface of the passivation layer and is connected to the third metal layer through the through hole.

3. The high-performance TFT array substrate according to claim 1, characterized in that: The gate insulating layer is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, and the passivation layer is made of SiOx, SiNO or SiNx.

4. The high-performance TFT array substrate according to claim 1, characterized in that: The through hole is in an inverted tapered shape.

5. A method for manufacturing a high-performance TFT array substrate, characterized in that: The following steps are involved: S1, plating a first metal layer on the upper surface of the glass substrate to form a gate; S2, coating a gate insulating layer on the upper surface of the first metal layer and the glass substrate; S3, plating a bridge layer on the upper surface of the gate insulating layer, wherein the bridge layer is located above the first metal layer; S4, plating a left active layer and a right active layer on the upper surface of the gate insulating layer, wherein the left active layer and the right active layer are located above the first metal layer and are respectively connected to the left and right ends of the bridge layer; S5, plating a second metal layer on the upper surface of the gate insulating layer, wherein the second metal layer is also connected to the left active layer to form a source electrode; Plating a third metal layer on the upper surface of the gate insulating layer, wherein the third metal layer is also connected to the right active layer to form a drain; The left active layer and the right active layer are both made of IGZO material, and the bridge layer is made of ITO material.

6. The method for manufacturing a high-performance TFT array substrate according to claim 5, wherein: The S3 further includes: plating a pixel electrode on the upper surface of the gate insulating layer, wherein the pixel electrode is located on the side of the bridge layer; The step S5 further includes: the third metal layer is further connected to the pixel electrode; and a conductive layer is plated on the upper surface of the gate insulating layer, wherein the conductive layer is located on the side of the pixel electrode.

7. The method for manufacturing a high-performance TFT array substrate according to claim 6, wherein: Also includes: S6. Coating a passivation layer on the upper surfaces of the second metal layer, the third metal layer, the left active layer, the right active layer, the bridge layer, the pixel electrode, the conductive layer, and the gate insulating layer, wherein the passivation layer is provided with a through hole, and the conductive layer is exposed through the through hole; S7. Plating a common electrode on the passivation layer, wherein the common electrode is connected to the conductive layer through the through hole.

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