A power factor correction (PFC) circuit, a switching power supply and a computing device

Abstract

Embodiments of the present application disclose a power factor correction (PFC) circuit, a switching power supply and a computing device. The PFC circuit comprises a controller configured to: obtain a first inductor current; determine a first count value of a first pulse width modulation (PWM) signal counter based on the first inductor current, wherein the first count value is a time length of one cycle of a PWM signal of a first switch tube, and the PWM signal of the first switch tube is used to control an operating state of the first switch tube; obtain a second inductor current; determine a second count value of the first PWM signal counter based on the second inductor current; and adjust a maintaining time length of a conduction control signal in a PWM signal of a third switch tube based on the first count value and the second count value, wherein the conduction control signal in the PWM signal of the third switch tube is used to control the third switch tube to be in a conduction state. By using the embodiments of the present application, switching loss can be reduced, and the working efficiency of the PFC current is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a power factor correction (PFC) circuit, a switching power supply, and a computing device. Background Technology

[0002] With the advancement of power electronics technology, the power consumption of Internet Technology (IT) devices is increasing, and the power requirements of the power supplies providing power to these devices are also growing. Traditional single-phase boost power factor correction (PFC) circuits are no longer suitable for the rectifier circuits at the front end of high-power power supplies. In high-power applications, multi-parallel boost PFC circuits are commonly used. Because interleaved multi-parallel boost PFC circuits have advantages such as low output ripple current and small branch power ratings, they are widely used in medium and high-power power supplies.

[0003] Existing multiphase interleaved parallel circuits use a fixed switching frequency. However, due to differences in the components of the circuit itself, the zero-crossing times of the current of the interleaved parallel power devices are not exactly the same. If the conduction time of the switch in the first phase boost branch is controlled, and the PWM of the other phases is output at a fixed interval, the switch in the other phase boost branches will not be conducting at zero voltage, resulting in high switching losses. Summary of the Invention

[0004] This application provides a power factor correction (PFC) circuit, a switching power supply, and a computing device, which can reduce switching losses and improve the operating efficiency of the PFC current.

[0005] In a first aspect, embodiments of this application provide a power factor correction (PFC) circuit. The PFC circuit includes a first-phase boost branch, a second-phase boost branch, and a controller. The first-phase boost branch includes a first inductor, a first switching transistor, and a second switching transistor. The first terminal of the first inductor is coupled to the positive terminal of the AC power supply. The second terminal of the first inductor, the first terminal of the first switching transistor, and the second terminal of the second switching transistor are electrically connected. The second terminal of the first switching transistor is electrically connected to the negative terminal of the AC current. The first terminal of the second switching transistor is electrically connected to the load.

[0006] The second-phase boost branch includes a second inductor, a third switch, and a fourth switch; the first terminal of the second inductor is coupled to the positive terminal of the AC power supply; the second terminal of the second inductor, the first terminal of the third switch, and the second terminal of the fourth switch are electrically connected; the second terminal of the third switch is electrically connected to the negative terminal of the AC current; and the first terminal of the fourth switch is electrically connected to the load.

[0007] The control terminals of the first, second, third, and fourth switching transistors are electrically connected to the four control terminals of the controller, respectively. The controller is used to control the control terminals of the first, second, third, and fourth switching transistors to output pulse width modulation signals and control the operating state of each switching transistor.

[0008] The controller is also used for:

[0009] Obtain the first inductor current;

[0010] Based on the first inductor current, a first count value of the first pulse width modulation signal counter is determined, wherein the first count value is the duration of one cycle of the pulse width modulation signal of the first switch transistor; the pulse width modulation signal of the first switch transistor is used to control the operating state of the first switch transistor.

[0011] Obtain the second inductor current;

[0012] Based on the second inductor current, the second count value of the first pulse width modulation signal counter is determined, wherein the pulse width modulation signal of the third switch is used to control the operating state of the third switch.

[0013] Based on the first count value and the second count value, the duration of the conduction control signal in the pulse width modulation signal of the third switch is adjusted, wherein the conduction control signal in the pulse width modulation signal of the third switch is used to control the third switch to be in the conduction state.

[0014] In one possible design, when the switching transistor in the PFC circuit is an NMOS transistor, the above-mentioned turn-on control level is high; when the switching transistor in the PFC circuit is a PMOS transistor, the above-mentioned turn-on control level is low.

[0015] The controller determines the adjustment value of the PWM signal turn-on control signal for the i-th phase boost branch by using the actual count difference between the start time of the high level of the PWM signal of the i-th phase boost branch and the start time of the high level of the PWM signal of the first phase boost branch, and the fixed count difference between the PWM signals of the i-th phase boost branch and the first phase boost branch. Based on this adjustment value, the controller adjusts the duration of the turn-on control signal for the i-th phase boost branch, changing the charging and discharging duration of the inductor in the i-th phase boost branch. This adjusts the zero-crossing time of the inductor current to be close to or equal to the start time of the turn-on control signal of the PWM signal of the i-th phase boost branch, which is also the turn-on time of the switching transistor in the i-th phase boost branch. This ensures that the switching transistor in the i-th phase boost branch turns on at the zero-crossing time of the inductor current in the i-th phase boost branch, reducing switching losses and improving the operating efficiency of the PFC current.

[0016] In another possible design, the controller is used for:

[0017] Based on the first count value, a fixed count difference is determined between the start time of the conduction control signal of the pulse width modulation signal of the third switch and the start time of the conduction control signal of the pulse width modulation signal of the first switch.

[0018] The adjustment value is determined based on the second count value and the fixed count difference;

[0019] Based on the adjustment value, the duration of the conduction control signal in the pulse width modulation signal of the third switching transistor is adjusted.

[0020] By calculating adjustment values, the duration of the PWM control signal for the i-th phase boost branch is adjusted accordingly. This changes the charging and discharging duration of the inductor in the i-th phase boost branch, bringing the zero-crossing moment of the inductor current close to or equal to the turn-on moment of the switch in the i-th phase boost branch. This ensures that the switch in the i-th phase boost branch turns on at the zero-crossing moment of the inductor current, reducing switching losses and improving the operating efficiency of the PFC current.

[0021] In another possible design, the controller is used for:

[0022] Calculate the first difference between the second count value and the fixed count difference;

[0023] The adjustment value is calculated based on the first difference and the adjustment coefficient; wherein the adjustment value is the first difference multiplied by the adjustment coefficient, and the adjustment coefficient is determined based on the AC input voltage, the PFC output voltage and the duration of the conduction control signal in the pulse width modulation signal of the third switch in the current cycle.

[0024] In another possible design, the controller is also used for:

[0025] Determine whether the first difference exceeds the preset threshold;

[0026] If the first difference exceeds the preset threshold, the adjustment value is determined.

[0027] By adjusting the duration of the conduction control signal in the pulse width modulation signal of the third switch when the first difference exceeds a preset threshold, the number of compensations is reduced, thereby improving the working efficiency of the PFC circuit.

[0028] In another possible design, the controller is used to: determine a first count value of the first pulse width modulation signal counter based on the first inductor current, including:

[0029] The controller is used for:

[0030] The zero-crossing time of the first inductor current is determined based on the first inductor current;

[0031] At the zero-crossing moment of the first inductor current, the first count value of the first pulse width modulation signal counter is obtained.

[0032] By obtaining the first count value of the first pulse width modulation signal counter at the zero-crossing moment of the first inductor current, the accuracy of obtaining the period of the pulse width modulation signal of the first switch is improved.

[0033] In another possible design, the controller is used for:

[0034] The zero-crossing time of the second inductor current is determined based on the second inductor current;

[0035] At the zero-crossing moment of the second inductor current, the second count value of the first pulse width modulation signal counter is obtained.

[0036] By obtaining the second count value of the first pulse width modulation signal counter at the zero-crossing moment of the second inductor current, the accuracy of obtaining the actual count difference between the start time of the high level of the PWM signal of the third switch of the i-th phase boost branch and the start time of the high level of the PWM signal of the first switch of the first phase boost branch is improved.

[0037] In another possible design, the PFC circuit also includes a rectifier circuit, the input of which is electrically connected to the positive terminal of the AC power supply; the output of which is electrically connected to the first terminal of the first inductor and the second inductor.

[0038] In another possible design, the PFC circuit also includes a fifth switch and a sixth switch. The negative terminal of the AC power supply is electrically connected to the first terminal of the fifth switch and the second terminal of the sixth switch, respectively. The second terminals of the fifth switch, the first switch, and the third switch are electrically connected. The first terminals of the sixth switch, the second switch, and the fourth switch are electrically connected. The control terminals of the fifth and sixth switches are electrically connected to the other two output terminals of the controller, respectively.

[0039] In another possible design, the controller is also used for:

[0040] During the positive half-cycle of the AC power input, the duration of the conduction control signal in the pulse width modulation signal of the third switch is adjusted based on the first and second count values.

[0041] When the AC power input is in the negative half-cycle, obtain the first inductor current;

[0042] Based on the first inductor current, the third count value of the first pulse width modulation signal counter is determined, wherein the third count value is the duration of one cycle of the pulse width modulation signal of the second switch; the pulse width modulation signal of the second switch is used to control the operating state of the second switch.

[0043] Obtain the second inductor current;

[0044] Based on the second inductor current, the fourth count value of the first pulse width modulation signal counter is determined, wherein the pulse width modulation signal of the fourth switch is used to control the operating state of the fourth switch.

[0045] Based on the third and fourth count values, the duration of the conduction control signal in the pulse width modulation signal of the fourth switch is adjusted. The conduction control signal in the pulse width modulation signal of the fourth switch is used to control the fourth switch to be in the conduction state.

[0046] The phase of different main switches is adjusted during the positive and negative half-cycles of the AC input, and corresponding adjustment values ​​are assigned to different main switches to improve the accuracy of phase adjustment of the PFC circuit.

[0047] Secondly, embodiments of this application provide a switching power supply, which includes a PFC circuit in any possible implementation of the first aspect described above.

[0048] Thirdly, embodiments of this application provide a computing device, which includes the switching power supply described in the second aspect. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0050] Figure 1 This is a schematic diagram of a PFC circuit;

[0051] Figure 2 This is a schematic diagram of another PFC circuit;

[0052] Figure 3 This is a waveform diagram of a PFC circuit;

[0053] Figure 4 This is a schematic diagram showing the phase difference between the PWM signals of each phase boost branch;

[0054] Figure 5 This is a waveform diagram of another PFC circuit;

[0055] Figure 6 This is a schematic flowchart of a phase adjustment method provided in an embodiment of this application;

[0056] Figure 7 This is a waveform diagram of a PFC circuit provided in an embodiment of this application;

[0057] Figure 8 This is a schematic diagram of a phase adjustment provided in an embodiment of this application;

[0058] Figure 9 This application provides a schematic diagram of the structure of a computing device. Detailed Implementation

[0059] The embodiments of this application are described below with reference to the accompanying drawings.

[0060] like Figure 1 As shown, Figure 1 This is a schematic diagram of a PFC circuit. The PFC circuit may include a bridge rectifier circuit 101, a boost circuit 102, a controller 103, and a driver 104. Wherein:

[0061] The bridge rectifier circuit 101 receives the AC input voltage Vin and provides the output voltage V1. The bridge rectifier circuit 101 converts AC power into unidirectional pulsating DC power. The circuit structure and principle of the bridge rectifier circuit can be found in existing descriptions and will not be repeated here.

[0062] The boost circuit 102 includes N-phase boost branches and a capacitor C. The N-phase boost branches are connected in parallel and then connected to the capacitor C, where N is a positive integer greater than or equal to 2. In the boost circuit 102, a two-phase boost branch will be used as an example for explanation. Figure 1 Only two-phase boost branches (boost branch 1 and boost branch 2) are shown. It is understood that the boost circuit 102 can have three or more phases. This application does not limit this.

[0063] The first-phase boost branch includes an inductor L1 and a first switch Q1 and a second switch Q2. The first terminal of inductor L1 is connected to the output terminal of the bridge rectifier circuit 101. The other two terminals of inductor L1 are connected to the first electrode of the first switch and the second electrode of the second switch. The first electrode of the second switch is connected to one end of a capacitor C. The second electrode of the first switch and the other end of capacitor C are grounded. The third electrode (control electrode) of both the first and second switches is connected to the driver 104.

[0064] The second-phase boost branch includes inductor L2, a third switch Q3, and a fourth switch Q4. The first terminal of inductor L2 is connected to the output terminal of bridge rectifier circuit 101. The second terminal of inductor L2, the first electrode of the third switch, and the second electrode of the fourth switch are connected together. The first electrode of the fourth switch is connected to one end of capacitor C. The second electrode of the third switch and the other end of capacitor C are grounded. The third electrode (control electrode) of both the third and fourth switches are connected to driver 104.

[0065] The boost circuit 102 is used to receive the output voltage V1 of the bridge rectifier circuit 101 and provide the output voltage V0 to the subsequent circuit (e.g., load) based on the drive signal of the driver 104.

[0066] The controller 103 is connected to one end of the inductor in each phase boost branch via a current sampling circuit. It samples the current of the inductor in each phase boost branch and outputs a pulse width modulation (PWM) signal based on the current of the inductor in each phase boost branch. The controller can be a microcontroller unit (MCU).

[0067] The driver 104, connected to the controller 103, is used to amplify the PWM signal output by the controller 103 and drive the switching transistors in each phase boost branch of the boost circuit 102 to turn on or off.

[0068] The control principle of boost circuit 102 is as follows: Taking the first phase boost circuit as an example, firstly, controller 103 outputs a high-level PWM1 signal and a low-level PWM2 signal. Driver 104 amplifies the above control signals and outputs them, controlling the switching transistor Q1 in boost branch 1 to turn on and the switching transistor Q2 to turn off. At this time, inductor L1 is charged. Then, after a time interval t1, controller 103 outputs a low-level PWM1 signal and a high-level PWM2 signal. Driver 104 amplifies the above control signals and outputs them, controlling the switching transistor Q1 in boost branch 1 to turn off and the switching transistor Q2 to turn on. At this time, inductor L1 is discharged. After a time interval t2, when inductor L1 has finished discharging, controller 103 can sample that the current of inductor L1 is 0. At this time, the previous cycle ends and the next cycle begins. The control principle of boost branch 2 is similar and will not be described in detail here.

[0069] like Figure 2 As shown, Figure 2 This is a schematic diagram of another PFC circuit. This PFC circuit may include a bridgeless rectifier circuit 201, a boost circuit 202, a controller 203, and a driver 204. Wherein:

[0070] The bridgeless rectifier circuit 201 includes a first synchronous rectifier switch (switch Q5) and a second synchronous rectifier switch (switch Q6). The first terminal of switch Q5 is connected to the second terminal of switch Q6. The third terminals (control terminals) of switch Q5 and switch Q6 are respectively connected to the corresponding drive signal output terminals of the driver. When the AC power supply is operating in the positive half-cycle, switch Q5 is turned on and switch Q6 is turned off. When the AC power supply is operating in the negative half-cycle, switch Q5 is turned off and switch Q6 is turned on.

[0071] The boost circuit 202 includes N-phase boost branches and a capacitor C. The N-phase boost branches are connected in parallel and then connected to the capacitor C, where N is a positive integer greater than or equal to 2. The boost circuit 202 will be explained using a 2-phase boost branch as an example. Figure 2 A two-phase boost circuit (boost circuit 1 and boost circuit 2) is given. It is understood that the boost circuit 202 can have three or more phases. This application does not limit this.

[0072] The first-phase boost branch includes an inductor L1 and a first switch Q1 and a second switch Q2. The first terminal of inductor L1 is connected to the positive terminal of the AC power supply. The other two terminals of inductor L1 are connected to the first electrode of the first switch and the second electrode of the second switch. The first electrode of the second switch, the first terminal of the second synchronous rectifier switch, and one end of capacitor C are connected. The second electrode of the first switch and the other end of capacitor C are grounded. The third electrode (control electrode) of both the first and second switches is connected to the driver 104.

[0073] The second-phase boost branch includes inductor L2, a third switch Q3, and a fourth switch Q4. The first terminal of inductor L2 is connected to the positive terminal of the AC power supply. The second terminal of inductor L2, the first terminal of the third switch, and the second terminal of the fourth switch are connected together. The first terminal of the fourth switch is connected to one end of capacitor C. The second terminal of the third switch and the other end of capacitor C are grounded. The third terminal (control terminal) of both the third and fourth switches are connected to driver 104.

[0074] The boost circuit 202 is used to receive the output voltage V1 of the AC power supply and, based on the drive signal of the driver 204, provide the output voltage V0 to the subsequent circuit (e.g., the load).

[0075] The controller 203 is connected to one end of the inductor in each phase boost branch through a current sampling circuit. It is used to sample the current of the inductor in each phase boost branch and output a PWM signal based on the current of the inductor in each phase boost branch.

[0076] The driver 204, connected to the controller 203, is used to amplify the PWM signal output by the controller 203 and drive the switching transistors in each phase boost branch of the boost circuit 202 to turn on or off.

[0077] The control principle of the boost circuit 202 is as follows: taking the first phase containing switching transistors Q3 and Q4 as an example.

[0078] During the positive half-cycle of the AC input, when switch Q5 is turned on and switch Q6 is turned off, controller 203 outputs a high-level PWM1 signal and a low-level PWM2 signal to driver 204, respectively. Driver 204 amplifies the high-level PWM1 signal and the low-level PWM2 signal, and then outputs them to the control terminals (third terminals) of switches Q1 and Q2 in boost branch 1, respectively, controlling switch Q1 to turn on and switch Q2 to turn off. At this time, inductor L1 is charged. Then, after a time t1, controller 203 outputs a low-level PWM1 signal and a high-level PWM2 signal. Driver 204 amplifies the low-level PWM1 signal and the high-level PWM2 signal, and then outputs them to the control terminals of switches Q1 and Q2, respectively, controlling switch Q1 to turn off and switch Q2 to turn on in boost branch 1, at which time inductor L1 is discharged. After a period of time t2, when the inductor L1 has finished discharging, the controller 203 can sample the current of the inductor L1 and find that it is 0.

[0079] During the negative half-cycle of the AC input, when switch Q5 is off and switch Q6 is on, controller 203 outputs a low-level PWM1 signal and a high-level PWM2 signal to driver 204. Driver 204 amplifies the high-level PWM1 signal and the low-level PWM2 signal, and then outputs them to the control terminals of switches Q1 and Q2 in boost branch 1, respectively, controlling switch Q1 to turn off and switch Q2 to turn on. At this time, inductor L1 is charged. Then, after time t3, controller 203 outputs a high-level PWM1 signal and a low-level PWM2 signal. Driver 204 amplifies the high-level PWM1 signal and the low-level PWM2 signal, and outputs them to the control terminals of switches Q1 and Q2, respectively, controlling switch Q1 to turn on and switch Q2 to turn off in boost branch 1. At this time, inductor L1 is discharged. After time t4, when inductor L1 has finished discharging, controller 203 can sample that the current of inductor L1 is 0.

[0080] The control principle of boost branch 2 is similar, and will not be described in detail here.

[0081] for Figure 1 and Figure 2In the PFC circuit shown, the period T1 of the PWM1 signal of the switch Q1 in boost branch 1 is from the start of charging in inductor L1 to the end of discharging in inductor L1. The period T2 of the PWM3 signal of the switch Q3 in boost branch 2 is from the start of charging in inductor L2 to the end of discharging inductor L2. This allows us to obtain the zero-crossing time of the inductor current in each phase of the boost branch, and determine the period of the PWM signal of the switch in each phase of the boost branch based on the zero-crossing time of the inductor current.

[0082] The PWM signals of the switching transistors in each phase boost branch are controlled by a PWM counter (timer) to output the controller. The PWM counter uses an up-counting method. That is, at the start of a cycle, it counts from 0, and the controller starts outputting a PWM signal for one cycle. When the count reaches its maximum value, one cycle of the PWM signal ends, and the next cycle begins, restarting from 0. The PWM counter can also use a down-counting method, with a similar principle, which will not be elaborated here.

[0083] The PWM counter in this embodiment can be a software counter that runs in the controller, or it can be a hardware counter. This application does not limit the choice between the two.

[0084] For example, such as Figure 3 As shown, Figure 3 This is a waveform diagram of a PFC circuit. First, the PWM1 counter triggers the controller to output a high-level PWM1 signal and a low-level PWM2 signal. During the counting period c1, the switching transistors Q1 and Q2 in boost branch 1 are turned on and off, charging inductor L1. After counting period c1, the counter controls the controller to output a low-level PWM1 signal. During the counting period c2, the switching transistor Q1 in boost branch 1 is turned off, discharging inductor L1. After counting period c2, one cycle of the PWM1 counter ends, and one cycle of the PWM1 signal also ends, with inductor L1 discharging completely (current in inductor L1 is 0). The PWM1 counter begins its next cycle, and the PWM1 signal also begins its next cycle. The operation of boost branch 2 is similar and will not be described further here.

[0085] It can be seen that within one cycle, the start time of the PWM counter of the switching transistor Q1 is the start time of the high level of the PWM signal, the turn-on time of the switching transistor in each phase boost branch, and the zero-crossing time of the current of the inductor in each phase boost branch.

[0086] For interleaved parallel multiphase boost branches, the phase difference between the PWM signals of two adjacent boost branches is 360 / N, where N is the number of phases in the parallel boost branches. If the period of the PWM signal of the switching transistor in each boost branch of the PFC circuit is a count C, then the fixed time difference between the start times of the high level in the PWM signals of two adjacent boost branches is C / N, and the fixed time difference between the start time of the high level in the PWM signal of the i-th boost branch and the start time of the high level in the PWM signal of the first boost branch is (i-1)C / N. Here, N is an integer greater than or equal to 2, and i is an integer greater than 1 and less than or equal to N.

[0087] like Figure 4 As shown, Figure 4 This is a schematic diagram illustrating the phase difference between the PWM signals of each phase boost branch. For Figure 1 and Figure 2 The PFC circuit shown has a PWM counter period of C for each phase boost branch switch transistor. The PWM1 counter triggers the controller to output a value for the first switch transistor of the first phase boost branch. Figure 1 and Figure 2 The PWM1 signal of the switching transistor Q1 in the second phase is used to trigger the controller to output a signal for the third switching transistor (Q1) in the second phase boost branch via the PWM2 counter. Figure 1 and Figure 2 The PWM3 signal of the switch (Q3) shown is given. The time difference between the start of the high level in the PWM3 signal of the second-phase boost branch and the start of the high level in the PWM1 signal of the first-phase boost branch is fixed at C / 2. It can be understood that for the i-th phase boost branch, the switch (Q3)... Figure 1 and Figure 2 The fixed time difference between the start time of the high level in the drive signal of Q1) and the start time of the high level in the PWM1 signal of the first phase boost branch is C / 2.

[0088] For interleaved parallel multi-phase boost branches, the controller uses a fixed time difference to output PWM signals for each phase boost branch. Specifically, the sampling signal at the zero-crossing moment of the inductor current in the first phase boost branch triggers the start of the high-level PWM signal of the first switch (switch Q1) in the first phase boost branch. The high-level PWM signals of the switches at the same position in the other phase boost branches are output with a fixed time difference from the high-level PWM signal of the first phase boost branch. For example, the high-level PWM3 signal of switch Q3 in the second phase boost branch starts to be output T / 2 after the start of the high-level PWM1 signal of switch Q1.

[0089] Ideally, when the controller outputs PWM signals for each phase boost branch using a fixed time difference, the start time of the high level of the PWM signal for the first phase boost branch is the zero-crossing moment of the current in the inductor in the first phase boost branch, and the start time of the high level of the PWM signal for the other phase boost branches is also the zero-crossing moment of the current in the inductor in the other phase boost branches. That is, at the zero-crossing moment of the current in the inductor in the other phase boost branches, the controller outputs a high level of the PWM signal for the other phase boost branches.

[0090] However, due to differences in the components within each phase of the boost circuit, such as differences in inductor inductance, drive delay, or inductor current sampling delay, the charging and discharging times of the inductors in the N-phase boost circuit differ. If the PWM signals of the other phase boost circuits are output with a fixed time difference, instead of being triggered by the sampling signal at the zero-crossing moment of the inductor current of the other phase boost circuits to start the high level of the PWM signals, the switching transistors in the other phase boost circuits may not turn on at the zero-crossing moment of the inductor current, increasing switching losses.

[0091] like Figure 5 As shown, Figure 5 This is a waveform diagram of another PFC circuit. For Figure 1 The PFC circuit shown initially outputs a high-level PWM1 signal for the first switch (Q1) and a low-level PWM2 signal for the second switch (Q2) in the first-phase boost branch. During a count of c1, Q1 is turned on and Q2 is turned off, while inductor L1 in the first-phase boost branch charges. After a count of c1, the controller outputs a low-level PWM1 signal and a low-level PWM2 signal for the first-phase boost branch. During a count of c2, Q1 is turned off and Q2 is turned on, while inductor L1 in the first-phase boost branch discharges. The periods of the PWM1 and PWM2 signals are C, where C = c1 + c2.

[0092] Then, after C / 2, the controller begins to output a signal to the third switch in the second-phase boost branch. Figure 1 The high level of the PWM3 signal of the fourth switch (Q3) and the fourth switch (Q3) Figure 1During the counting period c3, when the PWM4 signal of the switching transistor Q4 in the second-phase boost branch is low, switching transistor Q3 in the second-phase boost branch is turned on and switching transistor Q4 is turned off, and inductor L2 in the second-phase boost branch is charged. After the counting period c3, the controller starts outputting the low-level PWM3 signal and the low-level PWM4 signal for the second-phase boost branch. During the counting period c4, switching transistor Q3 in the second-phase boost branch is turned off and switching transistor Q4 is turned on, and inductor L2 in the second-phase boost branch is discharged.

[0093] When the device parameters of the two-phase boost circuit are exactly the same, the switching periods of the transistors in the two-phase boost circuit are the same, c1 + c2 = c3 + c4. Because the devices in the second-phase boost branch differ from those in the first-phase boost branch, after counting for c4 seconds, the inductor L2 in the second-phase boost branch has not finished discharging, and the current in inductor L2 is not zero. At this time, the PWM2 counter triggers the controller to start outputting a high level of the PWM3 signal for transistor Q3 and a low level of the PWM4 signal for transistor Q4 in the second-phase boost branch, causing transistor Q3 to turn on and transistor Q4 to turn off, charging inductor L2. However, transistor Q3 in the second-phase boost branch does not turn on at the zero-crossing moment of the current inductor L2, thus increasing switching losses and reducing the efficiency of the PFC circuit.

[0094] To address the aforementioned technical problems, embodiments of this application provide the following solution. This solution ensures that the switches of the corresponding branches conduct at the zero-crossing point of the current, reducing switching losses and thereby improving the efficiency of the PFC circuit.

[0095] like Figure 6 As shown, Figure 6 This is a flowchart illustrating a phase adjustment method provided in an embodiment of this application. The method is applied to a PFC circuit, which includes N-phase boost branches connected in parallel, where N is a positive integer greater than or equal to 2. For example, using... Figure 1 The phase adjustment method is described using an example. It should be understood that this phase adjustment method can be executed by the controller in the PFC circuit. The method includes the following steps:

[0096] S601, obtain the first inductor current.

[0097] S602, based on the first inductor current, determine the first count value of the first pulse width modulation signal counter, wherein the first count value is the duration of one cycle of the pulse width modulation signal of the first switch.

[0098] In this phase adjustment method, for a two-phase boost PFC circuit, one phase of the boost circuit can be selected as the reference phase, and the other phase can be used as the adjustment phase.

[0099] In one implementation, the PFC circuit further includes a first inductor current sampling circuit connected in series with inductor L1 to acquire the current value of inductor L1. The first inductor current sampling circuit is electrically connected to the current sampling input terminal of the controller. The controller acquires the current flowing through inductor L1 through the inductor current sampling circuit, and determines the zero-crossing time of the current in inductor L1 based on the acquired current value.

[0100] The inductor current sampling circuit can be a resistor sampling circuit, a mutual inductance sampling circuit, or any other sampling circuit capable of acquiring inductor current; this application does not limit it in this regard.

[0101] During inductor current sampling, the controller first outputs a high-level PWM1 signal (count value c1) and a low-level PWM2 signal (count value c1) to the first switch (Q1) and the second switch (Q2), respectively, controlling the first switch (Q1) to turn on and the second switch (Q2) to turn off in the first-phase boost branch, charging inductor L1. Then, the controller outputs a low-level PWM1 signal and a high-level PWM2 signal to the first switch (Q1) and the second switch (Q2), respectively, controlling the first switch (Q1) to turn off and the second switch (Q2) to turn on in the first-phase boost branch, discharging inductor L1. After a period of time (count value c2), when inductor L2 has finished discharging, the current in inductor L1 is zero, and the PWM1 counter in the first-phase boost branch reaches its maximum value.

[0102] For inductor L1, the zero-crossing times of the current include the start of charging and the end of discharging. At the start of charging inductor L1, the count value of PWM1 counter is 0, and at the end of discharging inductor L1, the count value of PWM1 counter reaches its maximum value. The maximum count value C1 from the start of charging to the end of discharging inductor L1 is used as the first count value of the PWM signal of the first switching transistor. This count value is actually one cycle of the PWM signal of the first switching transistor.

[0103] Understandable, Figure 1 During the operation of the PFC circuit shown, the first switch in the first phase and the third switch in the second phase are both main switches in their respective boost branches, while the second switch in the first phase and the fourth switch in the second phase are both freewheeling diodes.

[0104] S603, obtain the second inductor current.

[0105] S604, based on the second inductor current, determine the second count value of the first pulse width modulation signal counter, wherein the pulse width modulation signal of the third switch is used to control the operating state of the third switch.

[0106] The second count value is the actual count difference between the start time of the high level of the PWM signal of the third switch in the second phase boost branch and the start time of the high level of the PWM signal of the first switch in the first phase boost branch.

[0107] In the same control cycle satisfying the alternating conduction of the first and second phases, the controller first outputs a high-level PWM3 signal (count value c1) and a low-level PWM4 signal (count value c1) to the third switch (Q3) and the fourth switch (Q4), respectively, controlling the third switch (Q3) to turn on and the fourth switch (Q4) to turn off in the second-phase boost branch, charging inductor L2. Then, the controller outputs a low-level PWM3 signal and a high-level PWM4 signal to the third switch (Q3) and the fourth switch (Q4), respectively, controlling the first switch (Q3) to turn off and the second switch (Q4) to turn on in the first-phase boost branch, discharging inductor L1. After a period of time (count value c3), when inductor L2 has finished discharging, the current in inductor L1 is zero, and the PWM1 counter in the second-phase boost branch reaches its maximum value.

[0108] For inductor L2, the zero-crossing moments of the current include the start of charging and the end of discharging. At the start of charging in inductor L2, the count value of the PWM2 counter is 0; at the end of discharging inductor L1, the count value of the PWM2 counter reaches its maximum value. The maximum count value of the PWM2 counter from the start of charging to the end of discharging inductor L2 is used as the period of the PWM signal for the first switching transistor.

[0109] At the zero-crossing moment of the current in inductor L2, the count value C2 of the PWM1 counter is obtained, and this count value C2 is used as the duration of the pulse width modulation signal of the third switch in one cycle of the PWM1 counter.

[0110] For example, such as Figure 7 As shown, Figure 7 This is a waveform diagram of a PFC circuit provided in an embodiment of this application. For Figure 1 In the PFC circuit shown, the zero-crossing moment of the current of inductor L2 in the second-phase boost branch is the moment when the count of the second-phase counter (PWM2 counter) in the second-phase boost branch is at its maximum. At the moment when the count of the PWM2 counter in the second-phase boost branch is at its maximum (the beginning of the high level of the PWM2 signal in the second-phase boost branch), the count C2 of the PWM1 counter in the second cycle is obtained.

[0111] It should be noted that, under ideal conditions, when the two-phase PFC circuit is operating stably, the PWM signal output to the second-phase boost branch is based on a fixed phase difference of C1 / 2. The fixed count difference between the start time of the high level of the PWM3 signal of the switch Q3 of the second-phase boost branch and the start time of the high level of the PWM1 signal of the switch Q1 of the first-phase boost branch is C1 / 2.

[0112] S605, based on the first count value and the second count value, adjust the duration of the conduction control signal in the pulse width modulation signal of the third switch transistor. The conduction control signal in the pulse width modulation signal of the third switch transistor is used to control the third switch transistor to be in the conduction state.

[0113] The second pulse width modulation signal PWM2 counter is a counter for the pulse width modulation signal of the third switch in the second phase boost branch; by adjusting the count of this counter, the duration of the conduction control signal in the pulse width modulation signal of the third switch can be adjusted.

[0114] Understandably, when the switching transistor is an NMOS transistor, the turn-on control signal can be high; when the switching transistor is a PMOS transistor, the turn-on control signal can be low.

[0115] In an N-phase PFC circuit, for the i-th phase, the fixed counting difference is Cnt_1_i, where Cnt_1_i = (i-1)Cnt_N_1 / N, and 2 ≤ i ≤ N. The count value Cnt_N_1 is the count value of the period duration of the PWM signal of the main switch in the first-phase boost branch. Then, based on the second count value of the main switch in the i-th phase boost branch at the PWM1 counter and the fixed counting difference, the adjustment value of the turn-on control signal of the PWM signal of the i-th phase main switch is determined. The fixed counting difference is the phase difference between the start time of the high level of the PWM signal of the i-th phase boost branch and the start time of the high level of the PWM signal of the main switch in the first-phase boost branch under interleaved conditions. Based on the adjustment value, the duration of the turn-on control signal of the PWM signal of the i-th phase boost branch is adjusted.

[0116] Specifically, for a two-phase PFC circuit, the fixed count difference Cnt_1_2 between the PWM signal of switch Q3 and the PWM signal of switch Q1 can be determined as C1 / 2 based on the first count value C1. Under ideal interleaving conditions, the second count value C2 = C1 / 2. Therefore, the conduction time of the PWM signal of switch Q3 can be determined based on the second count value and the fixed count difference to see if adjustment is needed.

[0117] Furthermore, the first difference can be calculated by subtracting the fixed count difference Cnt_1_2 from the second count value C2. The first difference is then multiplied by an adjustment coefficient to calculate the adjustment value. Finally, the adjustment value is added to or subtracted from the duration of the PWM signal's on-state control signal in the i-th phase boost branch to obtain the adjusted duration of the on-state control signal.

[0118] Optionally, it is determined whether the first difference exceeds a preset threshold. If the first difference exceeds the preset threshold, the duration of the conduction level in the pulse width modulation signal of the third switch (main switch) in the second-phase boost branch is adjusted based on the first difference. If the first difference does not exceed the preset threshold, no conduction level adjustment is performed.

[0119] For example, the first difference is Err_i, the fixed count difference is Cnt_1_i, and the first count value of the first phase PWM counter is Cnt_N_1; the second count value of the i-th phase in the first phase PWM counter is Cnt_N_i, and Err_1_i = Cnt_N_i - Cnt_1_i = Cnt_N_i - (i-1)Cnt_N_1 / N. The adjustment value of the PWM signal control signal for the i-th phase boost branch is Q_1_i = μ*Err_1_i, where μ is the adjustment coefficient, which can be determined based on the input voltage Vin of the boost circuit, the output voltage Vout of the boost circuit, and the on-time Ton of the switch before adjustment.

[0120] The adjustment of the PWM signal's on-state level in the i-th phase boost branch includes either reducing or increasing the duration of the on-state control signal. If the count value Cnt_N_i in the i-th cycle is greater than a fixed count difference, the adjusted value can be subtracted from the on-state control signal's duration to obtain the adjusted duration. If the count value Cnt_N_i in the i-th cycle is less than a fixed count difference, the adjusted value can be added to the on-state control signal's duration to obtain the adjusted duration.

[0121] like Figure 8 As shown, Figure 8This is a schematic diagram of phase adjustment provided in an embodiment of this application. In the first cycle, the switch Q3 in the second-phase boost branch does not turn on at the zero-crossing moment of the current in inductor L2. Before inductor L2 has fully discharged, the PWM3 signal of switch Q3 switches to a high level for the next cycle, causing switch Q3 to turn on. In the second cycle, by reducing the duration of the high level in the PWM3 signal of switch Q3, the charging time of inductor L2 in the second-phase boost branch is reduced, and the discharging time of inductor L2 is increased. This ensures that when the PWM3 signal switches to a high level at the end of the second cycle, the current in inductor L2 is 0. That is, switch Q2 in the second-phase boost branch turns on at the zero-crossing moment of the current inductor L2, thereby reducing the switching losses of switch Q3.

[0122] Optionally, a first adjustment value is determined based on the first and second count values ​​acquired within one cycle. It can be understood that the first and second count values ​​are the counts of the first-phase PWM signal and the second-phase PWM signal on the PWM1 counter, respectively. In subsequent cycles, the duration of the conduction control signal of the PWM signal of the i-th phase boost branch can be adjusted according to the first adjustment value. Then, the first and second count values ​​can be acquired again to determine a second adjustment value, and the duration of the conduction control signal of the PWM signal of the i-th phase boost branch can be adjusted according to the second adjustment value. This dynamically adjusts the duration of the conduction control signal of the PWM signal of the i-th phase boost branch.

[0123] It should be understood that the PWM turn-on control signal is a level signal that controls the switch to turn on. For example, for an NMOS transistor, the PWM turn-on control signal is a high-level signal, and for a PMOS transistor, the PWM turn-on control signal is a low-level signal.

[0124] for Figure 2 In the PFC circuit shown, during the positive half-cycle of the AC voltage input, the first switch (Q1) in the first-phase boost circuit and the third switch (Q3) in the second-phase boost circuit act as the main switch. The current of the first inductor (L1) in the first-phase boost circuit can be obtained, and the first count value of the PWM1 counter is determined based on the inductor L1 current. The first count value is the duration of one cycle of the PWM1 signal of switch Q1. Then, the current of the second inductor (L2) in the second-phase boost circuit is obtained; the second count value of the PWM1 counter is determined based on the inductor L2 current; and the duration of the on-control signal in the PWM3 signal of switch Q3 is adjusted based on the first and second count values.

[0125] During the negative half-cycle of the AC voltage input, the second switch (Q2) in the first-phase boost circuit acts as the main switch; the fourth switch (Q4) in the second-phase boost circuit also acts as the main switch. The current of the first inductor (L1) in the first-phase boost circuit can be obtained. Based on the current of inductor L1, the third count value of the PWM1 counter is determined. This third count value represents the duration of one cycle of the PWM2 signal from switch Q2. Then, the current of inductor L2 is obtained. Based on the current of inductor L2, the fourth count value of the PWM1 counter is determined. Based on the third and fourth count values, the duration of the on-control signal in the PWM4 signal from switch Q4 is adjusted.

[0126] Therefore, during the positive half-cycle of the AC input, the first switch (switch Q1) and the third switch (switch Q3) are used as follows: Figure 6 The phase adjustment method shown; during the negative half-cycle of the AC input, the second switch (switch Q2) and the fourth switch (switch Q4) are adjusted as follows: Figure 6 The phase adjustment method shown is as follows: Phase adjustment is performed on different main switching transistors during the positive and negative half-cycles of the AC input, assigning corresponding adjustment values ​​to different main switching transistors to improve the accuracy of phase adjustment in the PFC circuit.

[0127] In this embodiment, the controller determines the adjustment value of the turn-on control signal of the PWM signal of the i-th phase boost branch by using the actual count difference between the start time of the high level of the PWM signal of the i-th phase boost branch and the start time of the high level of the PWM signal of the first phase boost branch, and the fixed count difference between the PWM signal of the i-th phase boost branch and the PWM signal of the first phase boost branch. The controller then adjusts the duration of the turn-on control signal of the PWM signal of the i-th phase boost branch according to the adjustment value, thereby changing the charging duration and discharging duration of the inductor in the i-th phase boost branch. This adjusts the zero-crossing time of the inductor current to be close to or equal to the start time of the turn-on control signal of the PWM signal of the i-th phase boost branch, which is also the turn-on time of the switch in the i-th phase boost branch. This ensures that the switch in the i-th phase boost branch turns on at the zero-crossing time of the inductor current in the i-th phase boost branch. This reduces switching losses and improves the operating efficiency of the PFC current.

[0128] It is understood that the steps in the compensation method of this application embodiment can be adjusted, merged, or deleted according to actual needs.

[0129] like Figure 9 As shown, Figure 9 This application provides a schematic diagram of the structure of a computing device. The computing device can be an electronic device such as a server, switch, or computer; the computing device includes a switching power supply, which may include… Figure 1or Figure 2 Any of the PFC circuits shown, the controller in the PFC circuit can be used to perform the above. Figure 6 The phase adjustment method shown.

[0130] The computing device may also include a processor, memory, and a transceiver. The processor, memory, transceiver, and switching power supply can communicate with each other via internal connections to transmit control and / or data signals. The memory stores computer programs, and the processor retrieves and runs these programs from the memory to control the transceiver's signal transmission and reception. The processor executes the program code stored in the memory to achieve the above functions. In practice, the memory may be integrated into the processor or independent of it. The transceiver may also be called a transceiver unit or transceiver module. The transceiver may include a receiver (or receiving circuit) and a transmitter (or transmitting circuit). The receiver receives signals, and the transmitter transmits signals. The transceiver is used to communicate with other devices.

[0131] It should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this application, and are not intended to limit them. Although the embodiments of this application have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A power factor correction (PFC) circuit, characterized in that, The PFC circuit includes a first-phase boost branch, a second-phase boost branch, and a controller; the first-phase boost branch includes a first inductor, a first switching transistor, and a second switching transistor; the first terminal of the first inductor is coupled to the positive terminal of the AC power supply; the second terminal of the first inductor, the first terminal of the first switching transistor, and the second terminal of the second switching transistor are electrically connected; the second terminal of the first switching transistor is electrically connected to the negative terminal of the AC current; the first terminal of the second switching transistor is electrically connected to the load. The second phase boost branch includes a second inductor, a third switch, and a fourth switch; the first terminal of the second inductor is coupled to the positive terminal of the AC power supply; the second terminal of the second inductor, the first terminal of the third switch, and the second terminal of the fourth switch are electrically connected; the second terminal of the third switch is electrically connected to the negative terminal of the AC current; and the first terminal of the fourth switch is electrically connected to the load. The control terminals of the first switch, the second switch, the third switch, and the fourth switch are electrically connected to the four control terminals of the controller, respectively. The controller is used to control the control terminals of the first switch, the second switch, the third switch, and the fourth switch to output pulse width modulation signals to control the operating state of each switch. The controller is also used for: Obtain the current of the first inductor; Based on the first inductor current, a first count value of the first pulse width modulation signal counter is determined, wherein the first count value is the duration of one cycle of the pulse width modulation signal of the first switch transistor; the pulse width modulation signal of the first switch transistor is used to control the operating state of the first switch transistor. Obtain the second inductor current; Based on the second inductor current, a second count value of the first pulse width modulation signal counter is determined, wherein the pulse width modulation signal of the third switch is used to control the operating state of the third switch. Based on the first count value and the second count value, the duration of the conduction control signal in the pulse width modulation signal of the third switch is adjusted, wherein the conduction control signal in the pulse width modulation signal of the third switch is used to control the third switch to be in the conduction state.

2. The PFC circuit as described in claim 1, characterized in that, The controller is used to: adjust the duration of the conduction control signal in the pulse width modulation signal of the third switch transistor according to the first count value and the second count value, including: The controller is used for: Based on the first count value, a fixed count difference is determined between the start time of the conduction control signal of the pulse width modulation signal of the third switch and the start time of the conduction control signal of the pulse width modulation signal of the first switch. The adjustment value is determined based on the second count value and the fixed count difference; Based on the adjustment value, the duration of the conduction control signal in the pulse width modulation signal of the third switch is adjusted.

3. The PFC circuit as described in claim 2, characterized in that, The controller is configured to: determine an adjustment value based on the second count value and the fixed count difference, including: The controller is used for: Calculate the first difference between the second count value and the fixed count difference; The adjustment value is calculated based on the first difference and the adjustment coefficient; wherein the adjustment value is the first difference multiplied by the adjustment coefficient, and the adjustment coefficient is determined based on the AC input voltage, the output voltage of the PFC, and the duration of the conduction control signal in the pulse width modulation signal of the third switch in the current cycle.

4. The PFC circuit as described in claim 3, characterized in that, Before calculating the adjustment value based on the first difference, the controller is further configured to: Determine whether the first difference exceeds a preset threshold; If the first difference exceeds the preset threshold, the adjustment value is determined.

5. The PFC circuit as described in any one of claims 1-4, characterized in that, The controller is configured to: determine a first count value of the first pulse width modulation signal counter based on the first inductor current, including: The controller is used for: The zero-crossing time of the first inductor current is determined based on the first inductor current; At the zero-crossing moment of the first inductor current, the first count value of the first pulse width modulation signal counter is obtained.

6. The PFC circuit according to any one of claims 1-4, characterized in that, The controller is configured to: determine a second count value of the first pulse width modulation signal counter based on the second inductor current, including: The controller is used for: The zero-crossing time of the second inductor current is determined based on the second inductor current; At the zero-crossing moment of the second inductor current, the second count value of the first pulse width modulation signal counter is obtained.

7. The PFC circuit according to any one of claims 1-4, characterized in that, The PFC circuit further includes a rectifier circuit, the input terminal of which is electrically connected to the positive terminal of the AC power supply; the output terminal of which is electrically connected to the first terminal of the first inductor and the second inductor.

8. The PFC circuit according to any one of claims 1-4, characterized in that, The PFC circuit further includes a fifth switch and a sixth switch. The negative terminal of the AC power supply is electrically connected to the first terminal of the fifth switch and the second terminal of the sixth switch, respectively. The second terminal of the fifth switch, the second terminal of the first switch, and the second terminal of the third switch are electrically connected. The first terminal of the sixth switch, the first terminal of the second switch, and the first terminal of the fourth switch are electrically connected. The control terminals of the fifth switch and the sixth switch are electrically connected to the other two output terminals of the controller, respectively.

9. The PFC circuit as described in claim 8, characterized in that, The controller is also used for: During the positive half-cycle of the AC power input, based on the first count value and the second count value, the duration of the conduction control signal in the pulse width modulation signal of the third switch is adjusted. When the AC power input is in the negative half-cycle, obtain the first inductor current; Based on the first inductor current, a third count value of the first pulse width modulation signal counter is determined, wherein the third count value is the duration of one cycle of the pulse width modulation signal of the second switch; the pulse width modulation signal of the second switch is used to control the operating state of the second switch. Obtain the second inductor current; Based on the second inductor current, a fourth count value of the first pulse width modulation signal counter is determined, wherein the pulse width modulation signal of the fourth switch is used to control the operating state of the fourth switch. Based on the third count value and the fourth count value, the duration of the conduction control signal in the pulse width modulation signal of the fourth switch is adjusted, wherein the conduction control signal in the pulse width modulation signal of the fourth switch is used to control the fourth switch to be in the conduction state.

10. A switching power supply, characterized in that, The switching power supply includes the PFC circuit according to any one of claims 1-9.

11. A computing device, characterized in that, The computing device includes the switching power supply as described in claim 10.

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